1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
34 #include "freedreno_state.h"
35 #include "freedreno_context.h"
36 #include "freedreno_zsa.h"
37 #include "freedreno_rasterizer.h"
38 #include "freedreno_blend.h"
39 #include "freedreno_program.h"
40 #include "freedreno_resource.h"
41 #include "freedreno_texture.h"
42 #include "freedreno_gmem.h"
43 #include "freedreno_util.h"
46 fd_set_blend_color(struct pipe_context
*pctx
,
47 const struct pipe_blend_color
*blend_color
)
49 struct fd_context
*ctx
= fd_context(pctx
);
50 ctx
->blend_color
= *blend_color
;
51 ctx
->dirty
|= FD_DIRTY_BLEND_COLOR
;
55 fd_set_stencil_ref(struct pipe_context
*pctx
,
56 const struct pipe_stencil_ref
*stencil_ref
)
58 struct fd_context
*ctx
= fd_context(pctx
);
59 ctx
->stencil_ref
=* stencil_ref
;
60 ctx
->dirty
|= FD_DIRTY_STENCIL_REF
;
64 fd_set_clip_state(struct pipe_context
*pctx
,
65 const struct pipe_clip_state
*clip
)
71 fd_set_sample_mask(struct pipe_context
*pctx
, unsigned sample_mask
)
73 struct fd_context
*ctx
= fd_context(pctx
);
74 ctx
->sample_mask
= (uint16_t)sample_mask
;
75 ctx
->dirty
|= FD_DIRTY_SAMPLE_MASK
;
78 /* notes from calim on #dri-devel:
79 * index==0 will be non-UBO (ie. glUniformXYZ()) all packed together padded
81 * I should be able to consider that I own the user_ptr until the next
82 * set_constant_buffer() call, at which point I don't really care about the
84 * index>0 will be UBO's.. well, I'll worry about that later
87 fd_set_constant_buffer(struct pipe_context
*pctx
, uint shader
, uint index
,
88 struct pipe_constant_buffer
*cb
)
90 struct fd_context
*ctx
= fd_context(pctx
);
91 struct fd_constbuf_stateobj
*so
= &ctx
->constbuf
[shader
];
93 /* Note that the state tracker can unbind constant buffers by
97 so
->enabled_mask
&= ~(1 << index
);
98 so
->dirty_mask
&= ~(1 << index
);
99 pipe_resource_reference(&so
->cb
[index
].buffer
, NULL
);
103 pipe_resource_reference(&so
->cb
[index
].buffer
, cb
->buffer
);
104 so
->cb
[index
].buffer_offset
= cb
->buffer_offset
;
105 so
->cb
[index
].buffer_size
= cb
->buffer_size
;
106 so
->cb
[index
].user_buffer
= cb
->user_buffer
;
108 so
->enabled_mask
|= 1 << index
;
109 so
->dirty_mask
|= 1 << index
;
110 ctx
->dirty
|= FD_DIRTY_CONSTBUF
;
114 fd_set_framebuffer_state(struct pipe_context
*pctx
,
115 const struct pipe_framebuffer_state
*framebuffer
)
117 struct fd_context
*ctx
= fd_context(pctx
);
118 struct pipe_framebuffer_state
*cso
= &ctx
->framebuffer
;
121 DBG("%d: cbufs[0]=%p, zsbuf=%p", ctx
->needs_flush
,
122 cso
->cbufs
[0], cso
->zsbuf
);
124 fd_context_render(pctx
);
126 for (i
= 0; i
< framebuffer
->nr_cbufs
; i
++)
127 pipe_surface_reference(&cso
->cbufs
[i
], framebuffer
->cbufs
[i
]);
128 for (; i
< ctx
->framebuffer
.nr_cbufs
; i
++)
129 pipe_surface_reference(&cso
->cbufs
[i
], NULL
);
131 cso
->nr_cbufs
= framebuffer
->nr_cbufs
;
132 cso
->width
= framebuffer
->width
;
133 cso
->height
= framebuffer
->height
;
135 pipe_surface_reference(&cso
->zsbuf
, framebuffer
->zsbuf
);
137 ctx
->dirty
|= FD_DIRTY_FRAMEBUFFER
;
139 /* also need to reset the scissor.. mesa/gl state tracker
140 * does this for us, but u_blitter doesn't and other
141 * state trackers might not..
143 ctx
->scissor
.minx
= 0;
144 ctx
->scissor
.miny
= 0;
145 ctx
->scissor
.maxx
= cso
->width
;
146 ctx
->scissor
.maxy
= cso
->height
;
148 ctx
->dirty
|= FD_DIRTY_SCISSOR
;
152 fd_set_polygon_stipple(struct pipe_context
*pctx
,
153 const struct pipe_poly_stipple
*stipple
)
155 struct fd_context
*ctx
= fd_context(pctx
);
156 ctx
->stipple
= *stipple
;
157 ctx
->dirty
|= FD_DIRTY_STIPPLE
;
161 fd_set_scissor_states(struct pipe_context
*pctx
,
163 unsigned num_scissors
,
164 const struct pipe_scissor_state
*scissor
)
166 struct fd_context
*ctx
= fd_context(pctx
);
168 ctx
->scissor
= *scissor
;
169 ctx
->dirty
|= FD_DIRTY_SCISSOR
;
173 fd_set_viewport_states(struct pipe_context
*pctx
,
175 unsigned num_viewports
,
176 const struct pipe_viewport_state
*viewport
)
178 struct fd_context
*ctx
= fd_context(pctx
);
179 ctx
->viewport
= *viewport
;
180 ctx
->dirty
|= FD_DIRTY_VIEWPORT
;
184 fd_set_vertex_buffers(struct pipe_context
*pctx
,
185 unsigned start_slot
, unsigned count
,
186 const struct pipe_vertex_buffer
*vb
)
188 struct fd_context
*ctx
= fd_context(pctx
);
189 struct fd_vertexbuf_stateobj
*so
= &ctx
->vertexbuf
;
192 /* on a2xx, pitch is encoded in the vtx fetch instruction, so
193 * we need to mark VTXSTATE as dirty as well to trigger patching
194 * and re-emitting the vtx shader:
196 for (i
= 0; i
< count
; i
++) {
197 bool new_enabled
= vb
&& (vb
[i
].buffer
|| vb
[i
].user_buffer
);
198 bool old_enabled
= so
->vb
[i
].buffer
|| so
->vb
[i
].user_buffer
;
199 uint32_t new_stride
= vb
? vb
[i
].stride
: 0;
200 uint32_t old_stride
= so
->vb
[i
].stride
;
201 if ((new_enabled
!= old_enabled
) || (new_stride
!= old_stride
)) {
202 ctx
->dirty
|= FD_DIRTY_VTXSTATE
;
207 util_set_vertex_buffers_mask(so
->vb
, &so
->enabled_mask
, vb
, start_slot
, count
);
208 so
->count
= util_last_bit(so
->enabled_mask
);
210 ctx
->dirty
|= FD_DIRTY_VTXBUF
;
214 fd_set_index_buffer(struct pipe_context
*pctx
,
215 const struct pipe_index_buffer
*ib
)
217 struct fd_context
*ctx
= fd_context(pctx
);
220 pipe_resource_reference(&ctx
->indexbuf
.buffer
, ib
->buffer
);
221 ctx
->indexbuf
.index_size
= ib
->index_size
;
222 ctx
->indexbuf
.offset
= ib
->offset
;
223 ctx
->indexbuf
.user_buffer
= ib
->user_buffer
;
225 pipe_resource_reference(&ctx
->indexbuf
.buffer
, NULL
);
228 ctx
->dirty
|= FD_DIRTY_INDEXBUF
;
232 fd_state_init(struct pipe_context
*pctx
)
234 pctx
->set_blend_color
= fd_set_blend_color
;
235 pctx
->set_stencil_ref
= fd_set_stencil_ref
;
236 pctx
->set_clip_state
= fd_set_clip_state
;
237 pctx
->set_sample_mask
= fd_set_sample_mask
;
238 pctx
->set_constant_buffer
= fd_set_constant_buffer
;
239 pctx
->set_framebuffer_state
= fd_set_framebuffer_state
;
240 pctx
->set_polygon_stipple
= fd_set_polygon_stipple
;
241 pctx
->set_scissor_states
= fd_set_scissor_states
;
242 pctx
->set_viewport_states
= fd_set_viewport_states
;
244 pctx
->set_vertex_buffers
= fd_set_vertex_buffers
;
245 pctx
->set_index_buffer
= fd_set_index_buffer
;
248 /* NOTE: just define the position for const regs statically.. the blob
249 * driver doesn't seem to change these dynamically, and I can't really
250 * think of a good reason to so..
252 #define VS_CONST_BASE 0x20
253 #define PS_CONST_BASE 0x120
256 emit_constants(struct fd_ringbuffer
*ring
, uint32_t base
,
257 struct fd_constbuf_stateobj
*constbuf
,
258 struct fd_shader_stateobj
*shader
)
260 uint32_t enabled_mask
= constbuf
->enabled_mask
;
261 uint32_t start_base
= base
;
264 // XXX TODO only emit dirty consts.. but we need to keep track if
265 // they are clobbered by a clear, gmem2mem, or mem2gmem..
266 constbuf
->dirty_mask
= enabled_mask
;
268 /* emit user constants: */
269 while (enabled_mask
) {
270 unsigned index
= ffs(enabled_mask
) - 1;
271 struct pipe_constant_buffer
*cb
= &constbuf
->cb
[index
];
272 unsigned size
= align(cb
->buffer_size
, 4) / 4; /* size in dwords */
274 // I expect that size should be a multiple of vec4's:
275 assert(size
== align(size
, 4));
277 /* hmm, sometimes we still seem to end up with consts bound,
278 * even if shader isn't using them, which ends up overwriting
279 * const reg's used for immediates.. this is a hack to work
282 if (shader
&& ((base
- start_base
) >= (shader
->first_immediate
* 4)))
285 if (constbuf
->dirty_mask
& (1 << index
)) {
286 const uint32_t *dwords
;
288 if (cb
->user_buffer
) {
289 dwords
= cb
->user_buffer
;
291 struct fd_resource
*rsc
= fd_resource(cb
->buffer
);
292 dwords
= fd_bo_map(rsc
->bo
);
295 dwords
= (uint32_t *)(((uint8_t *)dwords
) + cb
->buffer_offset
);
297 OUT_PKT3(ring
, CP_SET_CONSTANT
, size
+ 1);
298 OUT_RING(ring
, base
);
299 for (i
= 0; i
< size
; i
++)
300 OUT_RING(ring
, *(dwords
++));
302 constbuf
->dirty_mask
&= ~(1 << index
);
306 enabled_mask
&= ~(1 << index
);
309 /* emit shader immediates: */
311 for (i
= 0; i
< shader
->num_immediates
; i
++) {
312 OUT_PKT3(ring
, CP_SET_CONSTANT
, 5);
313 OUT_RING(ring
, start_base
+ (4 * (shader
->first_immediate
+ i
)));
314 OUT_RING(ring
, shader
->immediates
[i
].val
[0]);
315 OUT_RING(ring
, shader
->immediates
[i
].val
[1]);
316 OUT_RING(ring
, shader
->immediates
[i
].val
[2]);
317 OUT_RING(ring
, shader
->immediates
[i
].val
[3]);
323 /* this works at least for a220 and earlier.. if later gpu's gain more than
324 * 32 texture units, might need to bump this up to uint64_t
326 typedef uint32_t texmask
;
329 emit_texture(struct fd_ringbuffer
*ring
, struct fd_context
*ctx
,
330 struct fd_texture_stateobj
*tex
, unsigned samp_id
, texmask emitted
)
332 unsigned const_idx
= fd_get_const_idx(ctx
, tex
, samp_id
);
333 struct fd_sampler_stateobj
*sampler
;
334 struct fd_pipe_sampler_view
*view
;
336 if (emitted
& (1 << const_idx
))
339 sampler
= tex
->samplers
[samp_id
];
340 view
= fd_pipe_sampler_view(tex
->textures
[samp_id
]);
342 OUT_PKT3(ring
, CP_SET_CONSTANT
, 7);
343 OUT_RING(ring
, 0x00010000 + (0x6 * const_idx
));
345 OUT_RING(ring
, sampler
->tex0
| view
->tex0
);
346 OUT_RELOC(ring
, view
->tex_resource
->bo
, 0, view
->fmt
);
347 OUT_RING(ring
, view
->tex2
);
348 OUT_RING(ring
, sampler
->tex3
| view
->tex3
);
349 OUT_RING(ring
, sampler
->tex4
);
350 OUT_RING(ring
, sampler
->tex5
);
352 return (1 << const_idx
);
356 emit_textures(struct fd_ringbuffer
*ring
, struct fd_context
*ctx
)
361 for (i
= 0; i
< ctx
->verttex
.num_samplers
; i
++)
362 if (ctx
->verttex
.samplers
[i
])
363 emitted
|= emit_texture(ring
, ctx
, &ctx
->verttex
, i
, emitted
);
365 for (i
= 0; i
< ctx
->fragtex
.num_samplers
; i
++)
366 if (ctx
->fragtex
.samplers
[i
])
367 emitted
|= emit_texture(ring
, ctx
, &ctx
->fragtex
, i
, emitted
);
371 fd_emit_vertex_bufs(struct fd_ringbuffer
*ring
, uint32_t val
,
372 struct fd_vertex_buf
*vbufs
, uint32_t n
)
376 OUT_PKT3(ring
, CP_SET_CONSTANT
, 1 + (2 * n
));
377 OUT_RING(ring
, (0x1 << 16) | (val
& 0xffff));
378 for (i
= 0; i
< n
; i
++) {
379 struct fd_resource
*rsc
= fd_resource(vbufs
[i
].prsc
);
380 OUT_RELOC(ring
, rsc
->bo
, vbufs
[i
].offset
, 3);
381 OUT_RING (ring
, vbufs
[i
].size
);
386 fd_state_emit(struct pipe_context
*pctx
, uint32_t dirty
)
388 struct fd_context
*ctx
= fd_context(pctx
);
389 struct fd_ringbuffer
*ring
= ctx
->ring
;
391 /* NOTE: we probably want to eventually refactor this so each state
392 * object handles emitting it's own state.. although the mapping of
393 * state to registers is not always orthogonal, sometimes a single
394 * register contains bitfields coming from multiple state objects,
395 * so not sure the best way to deal with that yet.
398 if (dirty
& FD_DIRTY_SAMPLE_MASK
) {
399 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
400 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SC_AA_MASK
));
401 OUT_RING(ring
, ctx
->sample_mask
);
404 if (dirty
& FD_DIRTY_ZSA
) {
405 struct pipe_stencil_ref
*sr
= &ctx
->stencil_ref
;
407 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
408 OUT_RING(ring
, CP_REG(REG_A2XX_RB_DEPTHCONTROL
));
409 OUT_RING(ring
, ctx
->zsa
->rb_depthcontrol
);
411 OUT_PKT3(ring
, CP_SET_CONSTANT
, 4);
412 OUT_RING(ring
, CP_REG(REG_A2XX_RB_STENCILREFMASK_BF
));
413 OUT_RING(ring
, ctx
->zsa
->rb_stencilrefmask_bf
|
414 A2XX_RB_STENCILREFMASK_STENCILREF(sr
->ref_value
[1]));
415 OUT_RING(ring
, ctx
->zsa
->rb_stencilrefmask
|
416 A2XX_RB_STENCILREFMASK_STENCILREF(sr
->ref_value
[0]));
417 OUT_RING(ring
, ctx
->zsa
->rb_alpha_ref
);
420 if (dirty
& (FD_DIRTY_RASTERIZER
| FD_DIRTY_FRAMEBUFFER
)) {
421 OUT_PKT3(ring
, CP_SET_CONSTANT
, 3);
422 OUT_RING(ring
, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL
));
423 OUT_RING(ring
, ctx
->rasterizer
->pa_cl_clip_cntl
);
424 OUT_RING(ring
, ctx
->rasterizer
->pa_su_sc_mode_cntl
|
425 A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE
);
427 OUT_PKT3(ring
, CP_SET_CONSTANT
, 5);
428 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SU_POINT_SIZE
));
429 OUT_RING(ring
, ctx
->rasterizer
->pa_su_point_size
);
430 OUT_RING(ring
, ctx
->rasterizer
->pa_su_point_minmax
);
431 OUT_RING(ring
, ctx
->rasterizer
->pa_su_line_cntl
);
432 OUT_RING(ring
, ctx
->rasterizer
->pa_sc_line_stipple
);
434 OUT_PKT3(ring
, CP_SET_CONSTANT
, 6);
435 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SU_VTX_CNTL
));
436 OUT_RING(ring
, ctx
->rasterizer
->pa_su_vtx_cntl
);
437 OUT_RING(ring
, fui(1.0)); /* PA_CL_GB_VERT_CLIP_ADJ */
438 OUT_RING(ring
, fui(1.0)); /* PA_CL_GB_VERT_DISC_ADJ */
439 OUT_RING(ring
, fui(1.0)); /* PA_CL_GB_HORZ_CLIP_ADJ */
440 OUT_RING(ring
, fui(1.0)); /* PA_CL_GB_HORZ_DISC_ADJ */
443 if (dirty
& FD_DIRTY_SCISSOR
) {
444 OUT_PKT3(ring
, CP_SET_CONSTANT
, 3);
445 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL
));
446 OUT_RING(ring
, xy2d(ctx
->scissor
.minx
, /* PA_SC_WINDOW_SCISSOR_TL */
448 OUT_RING(ring
, xy2d(ctx
->scissor
.maxx
, /* PA_SC_WINDOW_SCISSOR_BR */
451 ctx
->max_scissor
.minx
= MIN2(ctx
->max_scissor
.minx
, ctx
->scissor
.minx
);
452 ctx
->max_scissor
.miny
= MIN2(ctx
->max_scissor
.miny
, ctx
->scissor
.miny
);
453 ctx
->max_scissor
.maxx
= MAX2(ctx
->max_scissor
.maxx
, ctx
->scissor
.maxx
);
454 ctx
->max_scissor
.maxy
= MAX2(ctx
->max_scissor
.maxy
, ctx
->scissor
.maxy
);
457 if (dirty
& FD_DIRTY_VIEWPORT
) {
458 OUT_PKT3(ring
, CP_SET_CONSTANT
, 7);
459 OUT_RING(ring
, CP_REG(REG_A2XX_PA_CL_VPORT_XSCALE
));
460 OUT_RING(ring
, fui(ctx
->viewport
.scale
[0])); /* PA_CL_VPORT_XSCALE */
461 OUT_RING(ring
, fui(ctx
->viewport
.translate
[0])); /* PA_CL_VPORT_XOFFSET */
462 OUT_RING(ring
, fui(ctx
->viewport
.scale
[1])); /* PA_CL_VPORT_YSCALE */
463 OUT_RING(ring
, fui(ctx
->viewport
.translate
[1])); /* PA_CL_VPORT_YOFFSET */
464 OUT_RING(ring
, fui(ctx
->viewport
.scale
[2])); /* PA_CL_VPORT_ZSCALE */
465 OUT_RING(ring
, fui(ctx
->viewport
.translate
[2])); /* PA_CL_VPORT_ZOFFSET */
467 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
468 OUT_RING(ring
, CP_REG(REG_A2XX_PA_CL_VTE_CNTL
));
469 OUT_RING(ring
, A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT
|
470 A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA
|
471 A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA
|
472 A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA
|
473 A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA
|
474 A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA
|
475 A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA
);
478 if (dirty
& (FD_DIRTY_PROG
| FD_DIRTY_VTXSTATE
| FD_DIRTY_TEXSTATE
)) {
479 fd_program_validate(ctx
);
480 fd_program_emit(ring
, &ctx
->prog
);
483 if (dirty
& (FD_DIRTY_PROG
| FD_DIRTY_CONSTBUF
)) {
484 emit_constants(ring
, VS_CONST_BASE
* 4,
485 &ctx
->constbuf
[PIPE_SHADER_VERTEX
],
486 (dirty
& FD_DIRTY_PROG
) ? ctx
->prog
.vp
: NULL
);
487 emit_constants(ring
, PS_CONST_BASE
* 4,
488 &ctx
->constbuf
[PIPE_SHADER_FRAGMENT
],
489 (dirty
& FD_DIRTY_PROG
) ? ctx
->prog
.fp
: NULL
);
492 if (dirty
& (FD_DIRTY_BLEND
| FD_DIRTY_ZSA
)) {
493 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
494 OUT_RING(ring
, CP_REG(REG_A2XX_RB_COLORCONTROL
));
495 OUT_RING(ring
, ctx
->zsa
->rb_colorcontrol
| ctx
->blend
->rb_colorcontrol
);
498 if (dirty
& FD_DIRTY_BLEND
) {
499 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
500 OUT_RING(ring
, CP_REG(REG_A2XX_RB_BLEND_CONTROL
));
501 OUT_RING(ring
, ctx
->blend
->rb_blendcontrol
);
503 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
504 OUT_RING(ring
, CP_REG(REG_A2XX_RB_COLOR_MASK
));
505 OUT_RING(ring
, ctx
->blend
->rb_colormask
);
508 if (dirty
& (FD_DIRTY_VERTTEX
| FD_DIRTY_FRAGTEX
| FD_DIRTY_PROG
))
509 emit_textures(ring
, ctx
);
511 ctx
->dirty
&= ~dirty
;
514 /* emit per-context initialization:
517 fd_state_emit_setup(struct pipe_context
*pctx
)
519 struct fd_context
*ctx
= fd_context(pctx
);
520 struct fd_ringbuffer
*ring
= ctx
->ring
;
522 OUT_PKT0(ring
, REG_A2XX_TP0_CHICKEN
, 1);
523 OUT_RING(ring
, 0x00000002);
525 OUT_PKT3(ring
, CP_INVALIDATE_STATE
, 1);
526 OUT_RING(ring
, 0x00007fff);
528 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
529 OUT_RING(ring
, CP_REG(REG_A2XX_SQ_VS_CONST
));
530 OUT_RING(ring
, A2XX_SQ_VS_CONST_BASE(VS_CONST_BASE
) |
531 A2XX_SQ_VS_CONST_SIZE(0x100));
533 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
534 OUT_RING(ring
, CP_REG(REG_A2XX_SQ_PS_CONST
));
535 OUT_RING(ring
, A2XX_SQ_PS_CONST_BASE(PS_CONST_BASE
) |
536 A2XX_SQ_PS_CONST_SIZE(0xe0));
538 OUT_PKT3(ring
, CP_SET_CONSTANT
, 3);
539 OUT_RING(ring
, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX
));
540 OUT_RING(ring
, 0xffffffff); /* VGT_MAX_VTX_INDX */
541 OUT_RING(ring
, 0x00000000); /* VGT_MIN_VTX_INDX */
543 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
544 OUT_RING(ring
, CP_REG(REG_A2XX_VGT_INDX_OFFSET
));
545 OUT_RING(ring
, 0x00000000);
547 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
548 OUT_RING(ring
, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL
));
549 OUT_RING(ring
, 0x0000003b);
551 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
552 OUT_RING(ring
, CP_REG(REG_A2XX_SQ_CONTEXT_MISC
));
553 OUT_RING(ring
, A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(CENTERS_ONLY
));
555 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
556 OUT_RING(ring
, CP_REG(REG_A2XX_SQ_INTERPOLATOR_CNTL
));
557 OUT_RING(ring
, 0xffffffff);
559 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
560 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SC_AA_CONFIG
));
561 OUT_RING(ring
, 0x00000000);
563 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
564 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SC_LINE_CNTL
));
565 OUT_RING(ring
, 0x00000000);
567 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
568 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET
));
569 OUT_RING(ring
, 0x00000000);
571 // XXX we change this dynamically for draw/clear.. vs gmem<->mem..
572 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
573 OUT_RING(ring
, CP_REG(REG_A2XX_RB_MODECONTROL
));
574 OUT_RING(ring
, A2XX_RB_MODECONTROL_EDRAM_MODE(COLOR_DEPTH
));
576 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
577 OUT_RING(ring
, CP_REG(REG_A2XX_RB_SAMPLE_POS
));
578 OUT_RING(ring
, 0x88888888);
580 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
581 OUT_RING(ring
, CP_REG(REG_A2XX_RB_COLOR_DEST_MASK
));
582 OUT_RING(ring
, 0xffffffff);
584 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
585 OUT_RING(ring
, CP_REG(REG_A2XX_RB_COPY_DEST_INFO
));
586 OUT_RING(ring
, A2XX_RB_COPY_DEST_INFO_FORMAT(COLORX_4_4_4_4
) |
587 A2XX_RB_COPY_DEST_INFO_WRITE_RED
|
588 A2XX_RB_COPY_DEST_INFO_WRITE_GREEN
|
589 A2XX_RB_COPY_DEST_INFO_WRITE_BLUE
|
590 A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA
);
592 OUT_PKT3(ring
, CP_SET_CONSTANT
, 3);
593 OUT_RING(ring
, CP_REG(REG_A2XX_SQ_WRAPPING_0
));
594 OUT_RING(ring
, 0x00000000); /* SQ_WRAPPING_0 */
595 OUT_RING(ring
, 0x00000000); /* SQ_WRAPPING_1 */
597 OUT_PKT3(ring
, CP_SET_DRAW_INIT_FLAGS
, 1);
598 OUT_RING(ring
, 0x00000000);
600 OUT_PKT3(ring
, CP_WAIT_REG_EQ
, 4);
601 OUT_RING(ring
, 0x000005d0);
602 OUT_RING(ring
, 0x00000000);
603 OUT_RING(ring
, 0x5f601000);
604 OUT_RING(ring
, 0x00000001);
606 OUT_PKT0(ring
, REG_A2XX_SQ_INST_STORE_MANAGMENT
, 1);
607 OUT_RING(ring
, 0x00000180);
609 OUT_PKT3(ring
, CP_INVALIDATE_STATE
, 1);
610 OUT_RING(ring
, 0x00000300);
612 OUT_PKT3(ring
, CP_SET_SHADER_BASES
, 1);
613 OUT_RING(ring
, 0x80000180);
615 /* not sure what this form of CP_SET_CONSTANT is.. */
616 OUT_PKT3(ring
, CP_SET_CONSTANT
, 13);
617 OUT_RING(ring
, 0x00000000);
618 OUT_RING(ring
, 0x00000000);
619 OUT_RING(ring
, 0x00000000);
620 OUT_RING(ring
, 0x00000000);
621 OUT_RING(ring
, 0x00000000);
622 OUT_RING(ring
, 0x469c4000);
623 OUT_RING(ring
, 0x3f800000);
624 OUT_RING(ring
, 0x3f000000);
625 OUT_RING(ring
, 0x00000000);
626 OUT_RING(ring
, 0x40000000);
627 OUT_RING(ring
, 0x3f400000);
628 OUT_RING(ring
, 0x3ec00000);
629 OUT_RING(ring
, 0x3e800000);
631 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
632 OUT_RING(ring
, CP_REG(REG_A2XX_RB_COLOR_MASK
));
633 OUT_RING(ring
, A2XX_RB_COLOR_MASK_WRITE_RED
|
634 A2XX_RB_COLOR_MASK_WRITE_GREEN
|
635 A2XX_RB_COLOR_MASK_WRITE_BLUE
|
636 A2XX_RB_COLOR_MASK_WRITE_ALPHA
);
638 OUT_PKT3(ring
, CP_SET_CONSTANT
, 5);
639 OUT_RING(ring
, CP_REG(REG_A2XX_RB_BLEND_RED
));
640 OUT_RING(ring
, 0x00000000); /* RB_BLEND_RED */
641 OUT_RING(ring
, 0x00000000); /* RB_BLEND_GREEN */
642 OUT_RING(ring
, 0x00000000); /* RB_BLEND_BLUE */
643 OUT_RING(ring
, 0x000000ff); /* RB_BLEND_ALPHA */
645 fd_ringbuffer_flush(ring
);
646 fd_ringmarker_mark(ctx
->draw_start
);