src/gallium/drivers/freedreno/freedreno_state.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_helpers.h"
  33
  34 #include "freedreno_state.h"
  35 #include "freedreno_context.h"
  36 #include "freedreno_zsa.h"
  37 #include "freedreno_rasterizer.h"
  38 #include "freedreno_blend.h"
  39 #include "freedreno_program.h"
  40 #include "freedreno_resource.h"
  41 #include "freedreno_texture.h"
  42 #include "freedreno_gmem.h"
  43 #include "freedreno_util.h"
  44
  45 static void
  46 fd_set_blend_color(struct pipe_context *pctx,
  47                 const struct pipe_blend_color *blend_color)
  48 {
  49         struct fd_context *ctx = fd_context(pctx);
  50         ctx->blend_color = *blend_color;
  51         ctx->dirty |= FD_DIRTY_BLEND_COLOR;
  52 }
  53
  54 static void
  55 fd_set_stencil_ref(struct pipe_context *pctx,
  56                 const struct pipe_stencil_ref *stencil_ref)
  57 {
  58         struct fd_context *ctx = fd_context(pctx);
  59         ctx->stencil_ref =* stencil_ref;
  60         ctx->dirty |= FD_DIRTY_STENCIL_REF;
  61 }
  62
  63 static void
  64 fd_set_clip_state(struct pipe_context *pctx,
  65                 const struct pipe_clip_state *clip)
  66 {
  67         DBG("TODO: ");
  68 }
  69
  70 static void
  71 fd_set_sample_mask(struct pipe_context *pctx, unsigned sample_mask)
  72 {
  73         struct fd_context *ctx = fd_context(pctx);
  74         ctx->sample_mask = (uint16_t)sample_mask;
  75         ctx->dirty |= FD_DIRTY_SAMPLE_MASK;
  76 }
  77
  78 /* notes from calim on #dri-devel:
  79  * index==0 will be non-UBO (ie. glUniformXYZ()) all packed together padded
  80  * out to vec4's
  81  * I should be able to consider that I own the user_ptr until the next
  82  * set_constant_buffer() call, at which point I don't really care about the
  83  * previous values.
  84  * index>0 will be UBO's.. well, I'll worry about that later
  85  */
  86 static void
  87 fd_set_constant_buffer(struct pipe_context *pctx, uint shader, uint index,
  88                 struct pipe_constant_buffer *cb)
  89 {
  90         struct fd_context *ctx = fd_context(pctx);
  91         struct fd_constbuf_stateobj *so = &ctx->constbuf[shader];
  92
  93         /* Note that the state tracker can unbind constant buffers by
  94          * passing NULL here.
  95          */
  96         if (unlikely(!cb)) {
  97                 so->enabled_mask &= ~(1 << index);
  98                 so->dirty_mask &= ~(1 << index);
  99                 pipe_resource_reference(&so->cb[index].buffer, NULL);
 100                 return;
 101         }
 102
 103         pipe_resource_reference(&so->cb[index].buffer, cb->buffer);
 104         so->cb[index].buffer_offset = cb->buffer_offset;
 105         so->cb[index].buffer_size   = cb->buffer_size;
 106         so->cb[index].user_buffer   = cb->user_buffer;
 107
 108         so->enabled_mask |= 1 << index;
 109         so->dirty_mask |= 1 << index;
 110         ctx->dirty |= FD_DIRTY_CONSTBUF;
 111 }
 112
 113 static void
 114 fd_set_framebuffer_state(struct pipe_context *pctx,
 115                 const struct pipe_framebuffer_state *framebuffer)
 116 {
 117         struct fd_context *ctx = fd_context(pctx);
 118         struct pipe_framebuffer_state *cso = &ctx->framebuffer;
 119         unsigned i;
 120
 121         DBG("%d: cbufs[0]=%p, zsbuf=%p", ctx->needs_flush,
 122                         cso->cbufs[0], cso->zsbuf);
 123
 124         fd_context_render(pctx);
 125
 126         for (i = 0; i < framebuffer->nr_cbufs; i++)
 127                 pipe_surface_reference(&cso->cbufs[i], framebuffer->cbufs[i]);
 128         for (; i < ctx->framebuffer.nr_cbufs; i++)
 129                 pipe_surface_reference(&cso->cbufs[i], NULL);
 130
 131         cso->nr_cbufs = framebuffer->nr_cbufs;
 132         cso->width = framebuffer->width;
 133         cso->height = framebuffer->height;
 134
 135         pipe_surface_reference(&cso->zsbuf, framebuffer->zsbuf);
 136
 137         ctx->dirty |= FD_DIRTY_FRAMEBUFFER;
 138 }
 139
 140 static void
 141 fd_set_polygon_stipple(struct pipe_context *pctx,
 142                 const struct pipe_poly_stipple *stipple)
 143 {
 144         struct fd_context *ctx = fd_context(pctx);
 145         ctx->stipple = *stipple;
 146         ctx->dirty |= FD_DIRTY_STIPPLE;
 147 }
 148
 149 static void
 150 fd_set_scissor_state(struct pipe_context *pctx,
 151                 const struct pipe_scissor_state *scissor)
 152 {
 153         struct fd_context *ctx = fd_context(pctx);
 154
 155         ctx->scissor = *scissor;
 156         ctx->dirty |= FD_DIRTY_SCISSOR;
 157 }
 158
 159 static void
 160 fd_set_viewport_state(struct pipe_context *pctx,
 161                 const struct pipe_viewport_state *viewport)
 162 {
 163         struct fd_context *ctx = fd_context(pctx);
 164         ctx->viewport = *viewport;
 165         ctx->dirty |= FD_DIRTY_VIEWPORT;
 166 }
 167
 168 static void
 169 fd_set_vertex_buffers(struct pipe_context *pctx,
 170                 unsigned start_slot, unsigned count,
 171                 const struct pipe_vertex_buffer *vb)
 172 {
 173         struct fd_context *ctx = fd_context(pctx);
 174         struct fd_vertexbuf_stateobj *so = &ctx->vertexbuf;
 175         int i;
 176
 177         /* on a2xx, pitch is encoded in the vtx fetch instruction, so
 178          * we need to mark VTXSTATE as dirty as well to trigger patching
 179          * and re-emitting the vtx shader:
 180          */
 181         for (i = 0; i < count; i++) {
 182                 bool new_enabled = vb && (vb[i].buffer || vb[i].user_buffer);
 183                 bool old_enabled = so->vb[i].buffer || so->vb[i].user_buffer;
 184                 uint32_t new_stride = vb ? vb[i].stride : 0;
 185                 uint32_t old_stride = so->vb[i].stride;
 186                 if ((new_enabled != old_enabled) || (new_stride != old_stride)) {
 187                         ctx->dirty |= FD_DIRTY_VTXSTATE;
 188                         break;
 189                 }
 190         }
 191
 192         util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb, start_slot, count);
 193         so->count = util_last_bit(so->enabled_mask);
 194
 195         ctx->dirty |= FD_DIRTY_VTXBUF;
 196 }
 197
 198 static void
 199 fd_set_index_buffer(struct pipe_context *pctx,
 200                 const struct pipe_index_buffer *ib)
 201 {
 202         struct fd_context *ctx = fd_context(pctx);
 203
 204         if (ib) {
 205                 pipe_resource_reference(&ctx->indexbuf.buffer, ib->buffer);
 206                 ctx->indexbuf.index_size = ib->index_size;
 207                 ctx->indexbuf.offset = ib->offset;
 208                 ctx->indexbuf.user_buffer = ib->user_buffer;
 209         } else {
 210                 pipe_resource_reference(&ctx->indexbuf.buffer, NULL);
 211         }
 212
 213         ctx->dirty |= FD_DIRTY_INDEXBUF;
 214 }
 215
 216 void
 217 fd_state_init(struct pipe_context *pctx)
 218 {
 219         pctx->set_blend_color = fd_set_blend_color;
 220         pctx->set_stencil_ref = fd_set_stencil_ref;
 221         pctx->set_clip_state = fd_set_clip_state;
 222         pctx->set_sample_mask = fd_set_sample_mask;
 223         pctx->set_constant_buffer = fd_set_constant_buffer;
 224         pctx->set_framebuffer_state = fd_set_framebuffer_state;
 225         pctx->set_polygon_stipple = fd_set_polygon_stipple;
 226         pctx->set_scissor_state = fd_set_scissor_state;
 227         pctx->set_viewport_state = fd_set_viewport_state;
 228
 229         pctx->set_vertex_buffers = fd_set_vertex_buffers;
 230         pctx->set_index_buffer = fd_set_index_buffer;
 231 }
 232
 233 /* NOTE: just define the position for const regs statically.. the blob
 234  * driver doesn't seem to change these dynamically, and I can't really
 235  * think of a good reason to so..
 236  */
 237 #define VS_CONST_BASE 0x20
 238 #define PS_CONST_BASE 0x120
 239
 240 static void
 241 emit_constants(struct fd_ringbuffer *ring, uint32_t base,
 242                 struct fd_constbuf_stateobj *constbuf,
 243                 struct fd_shader_stateobj *shader)
 244 {
 245         uint32_t enabled_mask = constbuf->enabled_mask;
 246         uint32_t start_base = base;
 247         unsigned i;
 248
 249         // XXX TODO only emit dirty consts.. but we need to keep track if
 250         // they are clobbered by a clear, gmem2mem, or mem2gmem..
 251         constbuf->dirty_mask = enabled_mask;
 252
 253         /* emit user constants: */
 254         while (enabled_mask) {
 255                 unsigned index = ffs(enabled_mask) - 1;
 256                 struct pipe_constant_buffer *cb = &constbuf->cb[index];
 257                 unsigned size = align(cb->buffer_size, 4) / 4; /* size in dwords */
 258
 259                 // I expect that size should be a multiple of vec4's:
 260                 assert(size == align(size, 4));
 261
 262                 /* hmm, sometimes we still seem to end up with consts bound,
 263                  * even if shader isn't using them, which ends up overwriting
 264                  * const reg's used for immediates.. this is a hack to work
 265                  * around that:
 266                  */
 267                 if (shader && ((base - start_base) >= (shader->first_immediate * 4)))
 268                         break;
 269
 270                 if (constbuf->dirty_mask & (1 << index)) {
 271                         const uint32_t *dwords;
 272
 273                         if (cb->user_buffer) {
 274                                 dwords = cb->user_buffer;
 275                         } else {
 276                                 struct fd_resource *rsc = fd_resource(cb->buffer);
 277                                 dwords = fd_bo_map(rsc->bo);
 278                         }
 279
 280                         dwords = (uint32_t *)(((uint8_t *)dwords) + cb->buffer_offset);
 281
 282                         OUT_PKT3(ring, CP_SET_CONSTANT, size + 1);
 283                         OUT_RING(ring, base);
 284                         for (i = 0; i < size; i++)
 285                                 OUT_RING(ring, *(dwords++));
 286
 287                         constbuf->dirty_mask &= ~(1 << index);
 288                 }
 289
 290                 base += size;
 291                 enabled_mask &= ~(1 << index);
 292         }
 293
 294         /* emit shader immediates: */
 295         if (shader) {
 296                 for (i = 0; i < shader->num_immediates; i++) {
 297                         OUT_PKT3(ring, CP_SET_CONSTANT, 5);
 298                         OUT_RING(ring, start_base + (4 * (shader->first_immediate + i)));
 299                         OUT_RING(ring, shader->immediates[i].val[0]);
 300                         OUT_RING(ring, shader->immediates[i].val[1]);
 301                         OUT_RING(ring, shader->immediates[i].val[2]);
 302                         OUT_RING(ring, shader->immediates[i].val[3]);
 303                         base += 4;
 304                 }
 305         }
 306 }
 307
 308 /* this works at least for a220 and earlier.. if later gpu's gain more than
 309  * 32 texture units, might need to bump this up to uint64_t
 310  */
 311 typedef uint32_t texmask;
 312
 313 static texmask
 314 emit_texture(struct fd_ringbuffer *ring, struct fd_context *ctx,
 315                 struct fd_texture_stateobj *tex, unsigned samp_id, texmask emitted)
 316 {
 317         unsigned const_idx = fd_get_const_idx(ctx, tex, samp_id);
 318         struct fd_sampler_stateobj *sampler;
 319         struct fd_pipe_sampler_view *view;
 320
 321         if (emitted & (1 << const_idx))
 322                 return 0;
 323
 324         sampler = tex->samplers[samp_id];
 325         view = fd_pipe_sampler_view(tex->textures[samp_id]);
 326
 327         OUT_PKT3(ring, CP_SET_CONSTANT, 7);
 328         OUT_RING(ring, 0x00010000 + (0x6 * const_idx));
 329
 330         OUT_RING(ring, sampler->tex0 | view->tex0);
 331         OUT_RELOC(ring, view->tex_resource->bo, 0, view->fmt);
 332         OUT_RING(ring, view->tex2);
 333         OUT_RING(ring, sampler->tex3 | view->tex3);
 334         OUT_RING(ring, sampler->tex4);
 335         OUT_RING(ring, sampler->tex5);
 336
 337         return (1 << const_idx);
 338 }
 339
 340 static void
 341 emit_textures(struct fd_ringbuffer *ring, struct fd_context *ctx)
 342 {
 343         texmask emitted = 0;
 344         unsigned i;
 345
 346         for (i = 0; i < ctx->verttex.num_samplers; i++)
 347                 if (ctx->verttex.samplers[i])
 348                         emitted |= emit_texture(ring, ctx, &ctx->verttex, i, emitted);
 349
 350         for (i = 0; i < ctx->fragtex.num_samplers; i++)
 351                 if (ctx->fragtex.samplers[i])
 352                         emitted |= emit_texture(ring, ctx, &ctx->fragtex, i, emitted);
 353 }
 354
 355 void
 356 fd_emit_vertex_bufs(struct fd_ringbuffer *ring, uint32_t val,
 357                 struct fd_vertex_buf *vbufs, uint32_t n)
 358 {
 359         unsigned i;
 360
 361         OUT_PKT3(ring, CP_SET_CONSTANT, 1 + (2 * n));
 362         OUT_RING(ring, (0x1 << 16) | (val & 0xffff));
 363         for (i = 0; i < n; i++) {
 364                 struct fd_resource *rsc = fd_resource(vbufs[i].prsc);
 365                 OUT_RELOC(ring, rsc->bo, vbufs[i].offset, 3);
 366                 OUT_RING (ring, vbufs[i].size);
 367         }
 368 }
 369
 370 void
 371 fd_state_emit(struct pipe_context *pctx, uint32_t dirty)
 372 {
 373         struct fd_context *ctx = fd_context(pctx);
 374         struct fd_ringbuffer *ring = ctx->ring;
 375
 376         /* NOTE: we probably want to eventually refactor this so each state
 377          * object handles emitting it's own state..  although the mapping of
 378          * state to registers is not always orthogonal, sometimes a single
 379          * register contains bitfields coming from multiple state objects,
 380          * so not sure the best way to deal with that yet.
 381          */
 382
 383         if (dirty & FD_DIRTY_SAMPLE_MASK) {
 384                 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 385                 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK));
 386                 OUT_RING(ring, ctx->sample_mask);
 387         }
 388
 389         if (dirty & FD_DIRTY_ZSA) {
 390                 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
 391
 392                 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 393                 OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL));
 394                 OUT_RING(ring, ctx->zsa->rb_depthcontrol);
 395
 396                 OUT_PKT3(ring, CP_SET_CONSTANT, 4);
 397                 OUT_RING(ring, CP_REG(REG_A2XX_RB_STENCILREFMASK_BF));
 398                 OUT_RING(ring, ctx->zsa->rb_stencilrefmask_bf |
 399                                 A2XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[1]));
 400                 OUT_RING(ring, ctx->zsa->rb_stencilrefmask |
 401                                 A2XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
 402                 OUT_RING(ring, ctx->zsa->rb_alpha_ref);
 403         }
 404
 405         if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_FRAMEBUFFER)) {
 406                 OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 407                 OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL));
 408                 OUT_RING(ring, ctx->rasterizer->pa_cl_clip_cntl);
 409                 OUT_RING(ring, ctx->rasterizer->pa_su_sc_mode_cntl |
 410                                 A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE);
 411
 412                 OUT_PKT3(ring, CP_SET_CONSTANT, 5);
 413                 OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_POINT_SIZE));
 414                 OUT_RING(ring, ctx->rasterizer->pa_su_point_size);
 415                 OUT_RING(ring, ctx->rasterizer->pa_su_point_minmax);
 416                 OUT_RING(ring, ctx->rasterizer->pa_su_line_cntl);
 417                 OUT_RING(ring, ctx->rasterizer->pa_sc_line_stipple);
 418
 419                 OUT_PKT3(ring, CP_SET_CONSTANT, 6);
 420                 OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_VTX_CNTL));
 421                 OUT_RING(ring, ctx->rasterizer->pa_su_vtx_cntl);
 422                 OUT_RING(ring, fui(1.0));                /* PA_CL_GB_VERT_CLIP_ADJ */
 423                 OUT_RING(ring, fui(1.0));                /* PA_CL_GB_VERT_DISC_ADJ */
 424                 OUT_RING(ring, fui(1.0));                /* PA_CL_GB_HORZ_CLIP_ADJ */
 425                 OUT_RING(ring, fui(1.0));                /* PA_CL_GB_HORZ_DISC_ADJ */
 426         }
 427
 428         if (dirty & FD_DIRTY_SCISSOR) {
 429                 OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 430                 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL));
 431                 OUT_RING(ring, xy2d(ctx->scissor.minx,   /* PA_SC_WINDOW_SCISSOR_TL */
 432                                 ctx->scissor.miny));
 433                 OUT_RING(ring, xy2d(ctx->scissor.maxx,   /* PA_SC_WINDOW_SCISSOR_BR */
 434                                 ctx->scissor.maxy));
 435
 436                 ctx->max_scissor.minx = MIN2(ctx->max_scissor.minx, ctx->scissor.minx);
 437                 ctx->max_scissor.miny = MIN2(ctx->max_scissor.miny, ctx->scissor.miny);
 438                 ctx->max_scissor.maxx = MAX2(ctx->max_scissor.maxx, ctx->scissor.maxx);
 439                 ctx->max_scissor.maxy = MAX2(ctx->max_scissor.maxy, ctx->scissor.maxy);
 440         }
 441
 442         if (dirty & FD_DIRTY_VIEWPORT) {
 443                 OUT_PKT3(ring, CP_SET_CONSTANT, 7);
 444                 OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VPORT_XSCALE));
 445                 OUT_RING(ring, fui(ctx->viewport.scale[0]));       /* PA_CL_VPORT_XSCALE */
 446                 OUT_RING(ring, fui(ctx->viewport.translate[0]));   /* PA_CL_VPORT_XOFFSET */
 447                 OUT_RING(ring, fui(ctx->viewport.scale[1]));       /* PA_CL_VPORT_YSCALE */
 448                 OUT_RING(ring, fui(ctx->viewport.translate[1]));   /* PA_CL_VPORT_YOFFSET */
 449                 OUT_RING(ring, fui(ctx->viewport.scale[2]));       /* PA_CL_VPORT_ZSCALE */
 450                 OUT_RING(ring, fui(ctx->viewport.translate[2]));   /* PA_CL_VPORT_ZOFFSET */
 451
 452                 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 453                 OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VTE_CNTL));
 454                 OUT_RING(ring, A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT |
 455                                 A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA |
 456                                 A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA |
 457                                 A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA |
 458                                 A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA |
 459                                 A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA |
 460                                 A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA);
 461         }
 462
 463         if (dirty & (FD_DIRTY_PROG | FD_DIRTY_VTXSTATE | FD_DIRTY_TEXSTATE)) {
 464                 fd_program_validate(ctx);
 465                 fd_program_emit(ring, &ctx->prog);
 466         }
 467
 468         if (dirty & (FD_DIRTY_PROG | FD_DIRTY_CONSTBUF)) {
 469                 emit_constants(ring,  VS_CONST_BASE * 4,
 470                                 &ctx->constbuf[PIPE_SHADER_VERTEX],
 471                                 (dirty & FD_DIRTY_PROG) ? ctx->prog.vp : NULL);
 472                 emit_constants(ring, PS_CONST_BASE * 4,
 473                                 &ctx->constbuf[PIPE_SHADER_FRAGMENT],
 474                                 (dirty & FD_DIRTY_PROG) ? ctx->prog.fp : NULL);
 475         }
 476
 477         if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_ZSA)) {
 478                 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 479                 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLORCONTROL));
 480                 OUT_RING(ring, ctx->zsa->rb_colorcontrol | ctx->blend->rb_colorcontrol);
 481         }
 482
 483         if (dirty & FD_DIRTY_BLEND) {
 484                 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 485                 OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_CONTROL));
 486                 OUT_RING(ring, ctx->blend->rb_blendcontrol);
 487
 488                 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 489                 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_MASK));
 490                 OUT_RING(ring, ctx->blend->rb_colormask);
 491         }
 492
 493         if (dirty & (FD_DIRTY_VERTTEX | FD_DIRTY_FRAGTEX | FD_DIRTY_PROG))
 494                 emit_textures(ring, ctx);
 495
 496         ctx->dirty &= ~dirty;
 497 }
 498
 499 /* emit per-context initialization:
 500  */
 501 void
 502 fd_state_emit_setup(struct pipe_context *pctx)
 503 {
 504         struct fd_context *ctx = fd_context(pctx);
 505         struct fd_ringbuffer *ring = ctx->ring;
 506
 507         OUT_PKT0(ring, REG_A2XX_TP0_CHICKEN, 1);
 508         OUT_RING(ring, 0x00000002);
 509
 510         OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
 511         OUT_RING(ring, 0x00007fff);
 512
 513         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 514         OUT_RING(ring, CP_REG(REG_A2XX_SQ_VS_CONST));
 515         OUT_RING(ring, A2XX_SQ_VS_CONST_BASE(VS_CONST_BASE) |
 516                         A2XX_SQ_VS_CONST_SIZE(0x100));
 517
 518         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 519         OUT_RING(ring, CP_REG(REG_A2XX_SQ_PS_CONST));
 520         OUT_RING(ring, A2XX_SQ_PS_CONST_BASE(PS_CONST_BASE) |
 521                         A2XX_SQ_PS_CONST_SIZE(0xe0));
 522
 523         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 524         OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
 525         OUT_RING(ring, 0xffffffff);        /* VGT_MAX_VTX_INDX */
 526         OUT_RING(ring, 0x00000000);        /* VGT_MIN_VTX_INDX */
 527
 528         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 529         OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
 530         OUT_RING(ring, 0x00000000);
 531
 532         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 533         OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
 534         OUT_RING(ring, 0x0000003b);
 535
 536         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 537         OUT_RING(ring, CP_REG(REG_A2XX_SQ_CONTEXT_MISC));
 538         OUT_RING(ring, A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(CENTERS_ONLY));
 539
 540         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 541         OUT_RING(ring, CP_REG(REG_A2XX_SQ_INTERPOLATOR_CNTL));
 542         OUT_RING(ring, 0xffffffff);
 543
 544         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 545         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_CONFIG));
 546         OUT_RING(ring, 0x00000000);
 547
 548         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 549         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_LINE_CNTL));
 550         OUT_RING(ring, 0x00000000);
 551
 552         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 553         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET));
 554         OUT_RING(ring, 0x00000000);
 555
 556         // XXX we change this dynamically for draw/clear.. vs gmem<->mem..
 557         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 558         OUT_RING(ring, CP_REG(REG_A2XX_RB_MODECONTROL));
 559         OUT_RING(ring, A2XX_RB_MODECONTROL_EDRAM_MODE(COLOR_DEPTH));
 560
 561         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 562         OUT_RING(ring, CP_REG(REG_A2XX_RB_SAMPLE_POS));
 563         OUT_RING(ring, 0x88888888);
 564
 565         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 566         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_DEST_MASK));
 567         OUT_RING(ring, 0xffffffff);
 568
 569         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 570         OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_DEST_INFO));
 571         OUT_RING(ring, A2XX_RB_COPY_DEST_INFO_FORMAT(COLORX_4_4_4_4) |
 572                         A2XX_RB_COPY_DEST_INFO_WRITE_RED |
 573                         A2XX_RB_COPY_DEST_INFO_WRITE_GREEN |
 574                         A2XX_RB_COPY_DEST_INFO_WRITE_BLUE |
 575                         A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA);
 576
 577         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 578         OUT_RING(ring, CP_REG(REG_A2XX_SQ_WRAPPING_0));
 579         OUT_RING(ring, 0x00000000);        /* SQ_WRAPPING_0 */
 580         OUT_RING(ring, 0x00000000);        /* SQ_WRAPPING_1 */
 581
 582         OUT_PKT3(ring, CP_SET_DRAW_INIT_FLAGS, 1);
 583         OUT_RING(ring, 0x00000000);
 584
 585         OUT_PKT3(ring, CP_WAIT_REG_EQ, 4);
 586         OUT_RING(ring, 0x000005d0);
 587         OUT_RING(ring, 0x00000000);
 588         OUT_RING(ring, 0x5f601000);
 589         OUT_RING(ring, 0x00000001);
 590
 591         OUT_PKT0(ring, REG_A2XX_SQ_INST_STORE_MANAGMENT, 1);
 592         OUT_RING(ring, 0x00000180);
 593
 594         OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
 595         OUT_RING(ring, 0x00000300);
 596
 597         OUT_PKT3(ring, CP_SET_SHADER_BASES, 1);
 598         OUT_RING(ring, 0x80000180);
 599
 600         /* not sure what this form of CP_SET_CONSTANT is.. */
 601         OUT_PKT3(ring, CP_SET_CONSTANT, 13);
 602         OUT_RING(ring, 0x00000000);
 603         OUT_RING(ring, 0x00000000);
 604         OUT_RING(ring, 0x00000000);
 605         OUT_RING(ring, 0x00000000);
 606         OUT_RING(ring, 0x00000000);
 607         OUT_RING(ring, 0x469c4000);
 608         OUT_RING(ring, 0x3f800000);
 609         OUT_RING(ring, 0x3f000000);
 610         OUT_RING(ring, 0x00000000);
 611         OUT_RING(ring, 0x40000000);
 612         OUT_RING(ring, 0x3f400000);
 613         OUT_RING(ring, 0x3ec00000);
 614         OUT_RING(ring, 0x3e800000);
 615
 616         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 617         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_MASK));
 618         OUT_RING(ring, A2XX_RB_COLOR_MASK_WRITE_RED |
 619                         A2XX_RB_COLOR_MASK_WRITE_GREEN |
 620                         A2XX_RB_COLOR_MASK_WRITE_BLUE |
 621                         A2XX_RB_COLOR_MASK_WRITE_ALPHA);
 622
 623         OUT_PKT3(ring, CP_SET_CONSTANT, 5);
 624         OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_RED));
 625         OUT_RING(ring, 0x00000000);        /* RB_BLEND_RED */
 626         OUT_RING(ring, 0x00000000);        /* RB_BLEND_GREEN */
 627         OUT_RING(ring, 0x00000000);        /* RB_BLEND_BLUE */
 628         OUT_RING(ring, 0x000000ff);        /* RB_BLEND_ALPHA */
 629
 630         fd_ringbuffer_flush(ring);
 631         fd_ringmarker_mark(ctx->draw_start);
 632 }