src/gallium/drivers/freedreno/freedreno_util.h

   1 /*
   2  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #ifndef FREEDRENO_UTIL_H_
  28 #define FREEDRENO_UTIL_H_
  29
  30 #include "drm/freedreno_drmif.h"
  31 #include "drm/freedreno_ringbuffer.h"
  32
  33 #include "pipe/p_format.h"
  34 #include "pipe/p_state.h"
  35 #include "util/u_debug.h"
  36 #include "util/u_math.h"
  37 #include "util/u_half.h"
  38 #include "util/u_dynarray.h"
  39 #include "util/u_pack_color.h"
  40
  41 #include "disasm.h"
  42 #include "adreno_common.xml.h"
  43 #include "adreno_pm4.xml.h"
  44
  45 enum adreno_rb_depth_format fd_pipe2depth(enum pipe_format format);
  46 enum pc_di_index_size fd_pipe2index(enum pipe_format format);
  47 enum pipe_format fd_gmem_restore_format(enum pipe_format format);
  48 enum adreno_rb_blend_factor fd_blend_factor(unsigned factor);
  49 enum adreno_pa_su_sc_draw fd_polygon_mode(unsigned mode);
  50 enum adreno_stencil_op fd_stencil_op(unsigned op);
  51
  52 #define A3XX_MAX_MIP_LEVELS 14
  53 /* TBD if it is same on a2xx, but for now: */
  54 #define MAX_MIP_LEVELS A3XX_MAX_MIP_LEVELS
  55
  56 #define A2XX_MAX_RENDER_TARGETS 1
  57 #define A3XX_MAX_RENDER_TARGETS 4
  58 #define A4XX_MAX_RENDER_TARGETS 8
  59 #define A5XX_MAX_RENDER_TARGETS 8
  60 #define A6XX_MAX_RENDER_TARGETS 8
  61
  62 #define MAX_RENDER_TARGETS A6XX_MAX_RENDER_TARGETS
  63
  64 #define FD_DBG_MSGS     0x0001
  65 #define FD_DBG_DISASM   0x0002
  66 #define FD_DBG_DCLEAR   0x0004
  67 #define FD_DBG_DDRAW    0x0008
  68 #define FD_DBG_NOSCIS   0x0010
  69 #define FD_DBG_DIRECT   0x0020
  70 #define FD_DBG_NOBYPASS 0x0040
  71 #define FD_DBG_FRAGHALF 0x0080
  72 #define FD_DBG_NOBIN    0x0100
  73 /* unused 0x0200 */
  74 #define FD_DBG_GLSL120  0x0400
  75 #define FD_DBG_SHADERDB 0x0800
  76 #define FD_DBG_FLUSH    0x1000
  77 #define FD_DBG_DEQP     0x2000
  78 #define FD_DBG_INORDER  0x4000
  79 #define FD_DBG_BSTAT    0x8000
  80 #define FD_DBG_NOGROW  0x10000
  81 #define FD_DBG_LRZ     0x20000
  82 #define FD_DBG_NOINDR  0x40000
  83 #define FD_DBG_NOBLIT  0x80000
  84 #define FD_DBG_HIPRIO 0x100000
  85 #define FD_DBG_TTILE  0x200000
  86 #define FD_DBG_PERFC  0x400000
  87 #define FD_DBG_SOFTPIN 0x800000
  88
  89 extern int fd_mesa_debug;
  90 extern bool fd_binning_enabled;
  91
  92 #define DBG(fmt, ...) \
  93                 do { if (fd_mesa_debug & FD_DBG_MSGS) \
  94                         debug_printf("%s:%d: "fmt "\n", \
  95                                 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
  96
  97 /* for conditionally setting boolean flag(s): */
  98 #define COND(bool, val) ((bool) ? (val) : 0)
  99
 100 #define CP_REG(reg) ((0x4 << 16) | ((unsigned int)((reg) - (0x2000))))
 101
 102 static inline uint32_t DRAW(enum pc_di_primtype prim_type,
 103                 enum pc_di_src_sel source_select, enum pc_di_index_size index_size,
 104                 enum pc_di_vis_cull_mode vis_cull_mode,
 105                 uint8_t instances)
 106 {
 107         return (prim_type         << 0) |
 108                         (source_select     << 6) |
 109                         ((index_size & 1)  << 11) |
 110                         ((index_size >> 1) << 13) |
 111                         (vis_cull_mode     << 9) |
 112                         (1                 << 14) |
 113                         (instances         << 24);
 114 }
 115
 116 static inline uint32_t DRAW_A20X(enum pc_di_primtype prim_type,
 117                 enum pc_di_src_sel source_select, enum pc_di_index_size index_size,
 118                 enum pc_di_vis_cull_mode vis_cull_mode,
 119                 uint16_t count)
 120 {
 121         return (prim_type         << 0) |
 122                         (source_select     << 6) |
 123                         ((index_size & 1)  << 11) |
 124                         ((index_size >> 1) << 13) |
 125                         (vis_cull_mode     << 9) |
 126                         (count         << 16);
 127 }
 128
 129 /* for tracking cmdstream positions that need to be patched: */
 130 struct fd_cs_patch {
 131         uint32_t *cs;
 132         uint32_t val;
 133 };
 134 #define fd_patch_num_elements(buf) ((buf)->size / sizeof(struct fd_cs_patch))
 135 #define fd_patch_element(buf, i)   util_dynarray_element(buf, struct fd_cs_patch, i)
 136
 137 static inline enum pipe_format
 138 pipe_surface_format(struct pipe_surface *psurf)
 139 {
 140         if (!psurf)
 141                 return PIPE_FORMAT_NONE;
 142         return psurf->format;
 143 }
 144
 145 static inline bool
 146 fd_surface_half_precision(const struct pipe_surface *psurf)
 147 {
 148         enum pipe_format format;
 149
 150         if (!psurf)
 151                 return true;
 152
 153         format = psurf->format;
 154
 155         /* colors are provided in consts, which go through cov.f32f16, which will
 156          * break these values
 157          */
 158         if (util_format_is_pure_integer(format))
 159                 return false;
 160
 161         /* avoid losing precision on 32-bit float formats */
 162         if (util_format_is_float(format) &&
 163                 util_format_get_component_bits(format, UTIL_FORMAT_COLORSPACE_RGB, 0) == 32)
 164                 return false;
 165
 166         return true;
 167 }
 168
 169 static inline unsigned
 170 fd_sampler_first_level(const struct pipe_sampler_view *view)
 171 {
 172         if (view->target == PIPE_BUFFER)
 173                 return 0;
 174         return view->u.tex.first_level;
 175 }
 176
 177 static inline unsigned
 178 fd_sampler_last_level(const struct pipe_sampler_view *view)
 179 {
 180         if (view->target == PIPE_BUFFER)
 181                 return 0;
 182         return view->u.tex.last_level;
 183 }
 184
 185 static inline bool
 186 fd_half_precision(struct pipe_framebuffer_state *pfb)
 187 {
 188         unsigned i;
 189
 190         for (i = 0; i < pfb->nr_cbufs; i++)
 191                 if (!fd_surface_half_precision(pfb->cbufs[i]))
 192                         return false;
 193
 194         return true;
 195 }
 196
 197 #define LOG_DWORDS 0
 198
 199 static inline void emit_marker(struct fd_ringbuffer *ring, int scratch_idx);
 200
 201 static inline void
 202 OUT_RING(struct fd_ringbuffer *ring, uint32_t data)
 203 {
 204         if (LOG_DWORDS) {
 205                 DBG("ring[%p]: OUT_RING   %04x:  %08x", ring,
 206                                 (uint32_t)(ring->cur - ring->start), data);
 207         }
 208         fd_ringbuffer_emit(ring, data);
 209 }
 210
 211 /* like OUT_RING() but appends a cmdstream patch point to 'buf' */
 212 static inline void
 213 OUT_RINGP(struct fd_ringbuffer *ring, uint32_t data,
 214                 struct util_dynarray *buf)
 215 {
 216         if (LOG_DWORDS) {
 217                 DBG("ring[%p]: OUT_RINGP  %04x:  %08x", ring,
 218                                 (uint32_t)(ring->cur - ring->start), data);
 219         }
 220         util_dynarray_append(buf, struct fd_cs_patch, ((struct fd_cs_patch){
 221                 .cs  = ring->cur++,
 222                 .val = data,
 223         }));
 224 }
 225
 226 /*
 227  * NOTE: OUT_RELOC*() is 2 dwords (64b) on a5xx+
 228  */
 229
 230 static inline void
 231 OUT_RELOC(struct fd_ringbuffer *ring, struct fd_bo *bo,
 232                 uint32_t offset, uint64_t or, int32_t shift)
 233 {
 234         if (LOG_DWORDS) {
 235                 DBG("ring[%p]: OUT_RELOC   %04x:  %p+%u << %d", ring,
 236                                 (uint32_t)(ring->cur - ring->start), bo, offset, shift);
 237         }
 238         debug_assert(offset < fd_bo_size(bo));
 239         fd_ringbuffer_reloc(ring, &(struct fd_reloc){
 240                 .bo = bo,
 241                 .flags = FD_RELOC_READ,
 242                 .offset = offset,
 243                 .or = or,
 244                 .shift = shift,
 245                 .orhi = or >> 32,
 246         });
 247 }
 248
 249 static inline void
 250 OUT_RELOCW(struct fd_ringbuffer *ring, struct fd_bo *bo,
 251                 uint32_t offset, uint64_t or, int32_t shift)
 252 {
 253         if (LOG_DWORDS) {
 254                 DBG("ring[%p]: OUT_RELOCW  %04x:  %p+%u << %d", ring,
 255                                 (uint32_t)(ring->cur - ring->start), bo, offset, shift);
 256         }
 257         debug_assert(offset < fd_bo_size(bo));
 258         fd_ringbuffer_reloc(ring, &(struct fd_reloc){
 259                 .bo = bo,
 260                 .flags = FD_RELOC_READ | FD_RELOC_WRITE,
 261                 .offset = offset,
 262                 .or = or,
 263                 .shift = shift,
 264                 .orhi = or >> 32,
 265         });
 266 }
 267
 268 static inline void
 269 OUT_RB(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
 270 {
 271         fd_ringbuffer_emit_reloc_ring_full(ring, target, 0);
 272 }
 273
 274 static inline void BEGIN_RING(struct fd_ringbuffer *ring, uint32_t ndwords)
 275 {
 276         if (ring->cur + ndwords > ring->end)
 277                 fd_ringbuffer_grow(ring, ndwords);
 278 }
 279
 280 static inline void
 281 OUT_PKT0(struct fd_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
 282 {
 283         BEGIN_RING(ring, cnt+1);
 284         OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
 285 }
 286
 287 static inline void
 288 OUT_PKT2(struct fd_ringbuffer *ring)
 289 {
 290         BEGIN_RING(ring, 1);
 291         OUT_RING(ring, CP_TYPE2_PKT);
 292 }
 293
 294 static inline void
 295 OUT_PKT3(struct fd_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
 296 {
 297         BEGIN_RING(ring, cnt+1);
 298         OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
 299 }
 300
 301 /*
 302  * Starting with a5xx, pkt4/pkt7 are used instead of pkt0/pkt3
 303  */
 304
 305 static inline unsigned
 306 _odd_parity_bit(unsigned val)
 307 {
 308         /* See: http://graphics.stanford.edu/~seander/bithacks.html#ParityParallel
 309          * note that we want odd parity so 0x6996 is inverted.
 310          */
 311         val ^= val >> 16;
 312         val ^= val >> 8;
 313         val ^= val >> 4;
 314         val &= 0xf;
 315         return (~0x6996 >> val) & 1;
 316 }
 317
 318 static inline void
 319 OUT_PKT4(struct fd_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
 320 {
 321         BEGIN_RING(ring, cnt+1);
 322         OUT_RING(ring, CP_TYPE4_PKT | cnt |
 323                         (_odd_parity_bit(cnt) << 7) |
 324                         ((regindx & 0x3ffff) << 8) |
 325                         ((_odd_parity_bit(regindx) << 27)));
 326 }
 327
 328 static inline void
 329 OUT_PKT7(struct fd_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
 330 {
 331         BEGIN_RING(ring, cnt+1);
 332         OUT_RING(ring, CP_TYPE7_PKT | cnt |
 333                         (_odd_parity_bit(cnt) << 15) |
 334                         ((opcode & 0x7f) << 16) |
 335                         ((_odd_parity_bit(opcode) << 23)));
 336 }
 337
 338 static inline void
 339 OUT_WFI(struct fd_ringbuffer *ring)
 340 {
 341         OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
 342         OUT_RING(ring, 0x00000000);
 343 }
 344
 345 static inline void
 346 OUT_WFI5(struct fd_ringbuffer *ring)
 347 {
 348         OUT_PKT7(ring, CP_WAIT_FOR_IDLE, 0);
 349 }
 350
 351 static inline void
 352 __OUT_IB(struct fd_ringbuffer *ring, bool prefetch, struct fd_ringbuffer *target)
 353 {
 354         if (target->cur == target->start)
 355                 return;
 356
 357         unsigned count = fd_ringbuffer_cmd_count(target);
 358
 359         /* for debug after a lock up, write a unique counter value
 360          * to scratch6 for each IB, to make it easier to match up
 361          * register dumps to cmdstream.  The combination of IB and
 362          * DRAW (scratch7) is enough to "triangulate" the particular
 363          * draw that caused lockup.
 364          */
 365         emit_marker(ring, 6);
 366
 367         for (unsigned i = 0; i < count; i++) {
 368                 uint32_t dwords;
 369                 OUT_PKT3(ring, prefetch ? CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2);
 370                 dwords = fd_ringbuffer_emit_reloc_ring_full(ring, target, i) / 4;
 371                 assert(dwords > 0);
 372                 OUT_RING(ring, dwords);
 373                 OUT_PKT2(ring);
 374         }
 375
 376         emit_marker(ring, 6);
 377 }
 378
 379 static inline void
 380 __OUT_IB5(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
 381 {
 382         if (target->cur == target->start)
 383                 return;
 384
 385         unsigned count = fd_ringbuffer_cmd_count(target);
 386
 387         for (unsigned i = 0; i < count; i++) {
 388                 uint32_t dwords;
 389                 OUT_PKT7(ring, CP_INDIRECT_BUFFER, 3);
 390                 dwords = fd_ringbuffer_emit_reloc_ring_full(ring, target, i) / 4;
 391                 assert(dwords > 0);
 392                 OUT_RING(ring, dwords);
 393         }
 394 }
 395
 396 /* CP_SCRATCH_REG4 is used to hold base address for query results: */
 397 // XXX annoyingly scratch regs move on a5xx.. and additionally different
 398 // packet types.. so freedreno_query_hw is going to need a bit of
 399 // rework..
 400 #define HW_QUERY_BASE_REG REG_AXXX_CP_SCRATCH_REG4
 401
 402 static inline void
 403 emit_marker(struct fd_ringbuffer *ring, int scratch_idx)
 404 {
 405         extern unsigned marker_cnt;
 406         unsigned reg = REG_AXXX_CP_SCRATCH_REG0 + scratch_idx;
 407         assert(reg != HW_QUERY_BASE_REG);
 408         if (reg == HW_QUERY_BASE_REG)
 409                 return;
 410         OUT_PKT0(ring, reg, 1);
 411         OUT_RING(ring, ++marker_cnt);
 412 }
 413
 414 /* helper to get numeric value from environment variable..  mostly
 415  * just leaving this here because it is helpful to brute-force figure
 416  * out unknown formats, etc, which blob driver does not support:
 417  */
 418 static inline uint32_t env2u(const char *envvar)
 419 {
 420         char *str = getenv(envvar);
 421         if (str)
 422                 return strtoul(str, NULL, 0);
 423         return 0;
 424 }
 425
 426 static inline uint32_t
 427 pack_rgba(enum pipe_format format, const float *rgba)
 428 {
 429         union util_color uc;
 430         util_pack_color(rgba, format, &uc);
 431         return uc.ui[0];
 432 }
 433
 434 /*
 435  * swap - swap value of @a and @b
 436  */
 437 #define swap(a, b) \
 438         do { __typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
 439
 440 #define foreach_bit(b, mask) \
 441         for (uint32_t _m = (mask); _m && ({(b) = u_bit_scan(&_m); 1;});)
 442
 443
 444 #define BIT(bit) (1u << bit)
 445
 446 /*
 447  * a3xx+ helpers:
 448  */
 449
 450 static inline enum a3xx_msaa_samples
 451 fd_msaa_samples(unsigned samples)
 452 {
 453         switch (samples) {
 454         default:
 455                 debug_assert(0);
 456         case 1: return MSAA_ONE;
 457         case 2: return MSAA_TWO;
 458         case 4: return MSAA_FOUR;
 459         }
 460 }
 461
 462 /*
 463  * a4xx+ helpers:
 464  */
 465
 466 static inline enum a4xx_state_block
 467 fd4_stage2shadersb(gl_shader_stage type)
 468 {
 469         switch (type) {
 470         case MESA_SHADER_VERTEX:
 471                 return SB4_VS_SHADER;
 472         case MESA_SHADER_FRAGMENT:
 473                 return SB4_FS_SHADER;
 474         case MESA_SHADER_COMPUTE:
 475                 return SB4_CS_SHADER;
 476         default:
 477                 unreachable("bad shader type");
 478                 return ~0;
 479         }
 480 }
 481
 482 #endif /* FREEDRENO_UTIL_H_ */