src/gallium/drivers/freedreno/freedreno_util.h

   1 /*
   2  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #ifndef FREEDRENO_UTIL_H_
  28 #define FREEDRENO_UTIL_H_
  29
  30 #include "drm/freedreno_drmif.h"
  31 #include "drm/freedreno_ringbuffer.h"
  32
  33 #include "pipe/p_format.h"
  34 #include "pipe/p_state.h"
  35 #include "util/u_debug.h"
  36 #include "util/u_math.h"
  37 #include "util/u_half.h"
  38 #include "util/u_dynarray.h"
  39 #include "util/u_pack_color.h"
  40
  41 #include "disasm.h"
  42 #include "adreno_common.xml.h"
  43 #include "adreno_pm4.xml.h"
  44
  45 enum adreno_rb_depth_format fd_pipe2depth(enum pipe_format format);
  46 enum pc_di_index_size fd_pipe2index(enum pipe_format format);
  47 enum pipe_format fd_gmem_restore_format(enum pipe_format format);
  48 enum adreno_rb_blend_factor fd_blend_factor(unsigned factor);
  49 enum adreno_pa_su_sc_draw fd_polygon_mode(unsigned mode);
  50 enum adreno_stencil_op fd_stencil_op(unsigned op);
  51
  52 #define A3XX_MAX_MIP_LEVELS 14
  53
  54 #define A2XX_MAX_RENDER_TARGETS 1
  55 #define A3XX_MAX_RENDER_TARGETS 4
  56 #define A4XX_MAX_RENDER_TARGETS 8
  57 #define A5XX_MAX_RENDER_TARGETS 8
  58 #define A6XX_MAX_RENDER_TARGETS 8
  59
  60 #define MAX_RENDER_TARGETS A6XX_MAX_RENDER_TARGETS
  61
  62 enum fd_debug_flag {
  63         FD_DBG_MSGS         = BITFIELD_BIT(0),
  64         FD_DBG_DISASM       = BITFIELD_BIT(1),
  65         FD_DBG_DCLEAR       = BITFIELD_BIT(2),
  66         FD_DBG_DDRAW        = BITFIELD_BIT(3),
  67         FD_DBG_NOSCIS       = BITFIELD_BIT(4),
  68         FD_DBG_DIRECT       = BITFIELD_BIT(5),
  69         FD_DBG_NOBYPASS     = BITFIELD_BIT(6),
  70         FD_DBG_LOG          = BITFIELD_BIT(7),
  71         FD_DBG_NOBIN        = BITFIELD_BIT(8),
  72         FD_DBG_NOGMEM       = BITFIELD_BIT(9),
  73         /* BIT(10) */
  74         FD_DBG_SHADERDB     = BITFIELD_BIT(11),
  75         FD_DBG_FLUSH        = BITFIELD_BIT(12),
  76         FD_DBG_DEQP         = BITFIELD_BIT(13),
  77         FD_DBG_INORDER      = BITFIELD_BIT(14),
  78         FD_DBG_BSTAT        = BITFIELD_BIT(15),
  79         FD_DBG_NOGROW       = BITFIELD_BIT(16),
  80         FD_DBG_LRZ          = BITFIELD_BIT(17),
  81         FD_DBG_NOINDR       = BITFIELD_BIT(18),
  82         FD_DBG_NOBLIT       = BITFIELD_BIT(19),
  83         FD_DBG_HIPRIO       = BITFIELD_BIT(20),
  84         FD_DBG_TTILE        = BITFIELD_BIT(21),
  85         FD_DBG_PERFC        = BITFIELD_BIT(22),
  86         FD_DBG_NOUBWC       = BITFIELD_BIT(23),
  87         FD_DBG_NOLRZ        = BITFIELD_BIT(24),
  88         FD_DBG_NOTILE       = BITFIELD_BIT(25),
  89         FD_DBG_LAYOUT       = BITFIELD_BIT(26),
  90         FD_DBG_NOFP16       = BITFIELD_BIT(27),
  91         FD_DBG_NOHW         = BITFIELD_BIT(28),
  92 };
  93
  94 extern int fd_mesa_debug;
  95 extern bool fd_binning_enabled;
  96
  97 #define DBG(fmt, ...) \
  98                 do { if (fd_mesa_debug & FD_DBG_MSGS) \
  99                         debug_printf("%s:%d: "fmt "\n", \
 100                                 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
 101
 102 /* for conditionally setting boolean flag(s): */
 103 #define COND(bool, val) ((bool) ? (val) : 0)
 104
 105 #define CP_REG(reg) ((0x4 << 16) | ((unsigned int)((reg) - (0x2000))))
 106
 107 static inline uint32_t DRAW(enum pc_di_primtype prim_type,
 108                 enum pc_di_src_sel source_select, enum pc_di_index_size index_size,
 109                 enum pc_di_vis_cull_mode vis_cull_mode,
 110                 uint8_t instances)
 111 {
 112         return (prim_type         << 0) |
 113                         (source_select     << 6) |
 114                         ((index_size & 1)  << 11) |
 115                         ((index_size >> 1) << 13) |
 116                         (vis_cull_mode     << 9) |
 117                         (1                 << 14) |
 118                         (instances         << 24);
 119 }
 120
 121 static inline uint32_t DRAW_A20X(enum pc_di_primtype prim_type,
 122                 enum pc_di_face_cull_sel faceness_cull_select,
 123                 enum pc_di_src_sel source_select, enum pc_di_index_size index_size,
 124                 bool pre_fetch_cull_enable,
 125                 bool grp_cull_enable,
 126                 uint16_t count)
 127 {
 128         return (prim_type         << 0) |
 129                         (source_select     << 6) |
 130                         (faceness_cull_select << 8) |
 131                         ((index_size & 1)  << 11) |
 132                         ((index_size >> 1) << 13) |
 133                         (pre_fetch_cull_enable << 14) |
 134                         (grp_cull_enable << 15) |
 135                         (count         << 16);
 136 }
 137
 138 /* for tracking cmdstream positions that need to be patched: */
 139 struct fd_cs_patch {
 140         uint32_t *cs;
 141         uint32_t val;
 142 };
 143 #define fd_patch_num_elements(buf) ((buf)->size / sizeof(struct fd_cs_patch))
 144 #define fd_patch_element(buf, i)   util_dynarray_element(buf, struct fd_cs_patch, i)
 145
 146 static inline enum pipe_format
 147 pipe_surface_format(struct pipe_surface *psurf)
 148 {
 149         if (!psurf)
 150                 return PIPE_FORMAT_NONE;
 151         return psurf->format;
 152 }
 153
 154 static inline bool
 155 fd_surface_half_precision(const struct pipe_surface *psurf)
 156 {
 157         enum pipe_format format;
 158
 159         if (!psurf)
 160                 return true;
 161
 162         format = psurf->format;
 163
 164         /* colors are provided in consts, which go through cov.f32f16, which will
 165          * break these values
 166          */
 167         if (util_format_is_pure_integer(format))
 168                 return false;
 169
 170         /* avoid losing precision on 32-bit float formats */
 171         if (util_format_is_float(format) &&
 172                 util_format_get_component_bits(format, UTIL_FORMAT_COLORSPACE_RGB, 0) == 32)
 173                 return false;
 174
 175         return true;
 176 }
 177
 178 static inline unsigned
 179 fd_sampler_first_level(const struct pipe_sampler_view *view)
 180 {
 181         if (view->target == PIPE_BUFFER)
 182                 return 0;
 183         return view->u.tex.first_level;
 184 }
 185
 186 static inline unsigned
 187 fd_sampler_last_level(const struct pipe_sampler_view *view)
 188 {
 189         if (view->target == PIPE_BUFFER)
 190                 return 0;
 191         return view->u.tex.last_level;
 192 }
 193
 194 static inline bool
 195 fd_half_precision(struct pipe_framebuffer_state *pfb)
 196 {
 197         unsigned i;
 198
 199         for (i = 0; i < pfb->nr_cbufs; i++)
 200                 if (!fd_surface_half_precision(pfb->cbufs[i]))
 201                         return false;
 202
 203         return true;
 204 }
 205
 206 /* Note sure if this is same on all gens, but seems to be same on the later
 207  * gen's
 208  */
 209 static inline unsigned
 210 fd_calc_guardband(unsigned x)
 211 {
 212         float l = log2(x);
 213         if (l <= 8)
 214                 return 511;
 215         return 511 - ((l - 8) * 65);
 216 }
 217
 218 static inline void emit_marker(struct fd_ringbuffer *ring, int scratch_idx);
 219
 220 /* like OUT_RING() but appends a cmdstream patch point to 'buf' */
 221 static inline void
 222 OUT_RINGP(struct fd_ringbuffer *ring, uint32_t data,
 223                 struct util_dynarray *buf)
 224 {
 225         if (LOG_DWORDS) {
 226                 DBG("ring[%p]: OUT_RINGP  %04x:  %08x", ring,
 227                                 (uint32_t)(ring->cur - ring->start), data);
 228         }
 229         util_dynarray_append(buf, struct fd_cs_patch, ((struct fd_cs_patch){
 230                 .cs  = ring->cur++,
 231                 .val = data,
 232         }));
 233 }
 234
 235 static inline void
 236 __OUT_IB(struct fd_ringbuffer *ring, bool prefetch, struct fd_ringbuffer *target)
 237 {
 238         if (target->cur == target->start)
 239                 return;
 240
 241         unsigned count = fd_ringbuffer_cmd_count(target);
 242
 243         /* for debug after a lock up, write a unique counter value
 244          * to scratch6 for each IB, to make it easier to match up
 245          * register dumps to cmdstream.  The combination of IB and
 246          * DRAW (scratch7) is enough to "triangulate" the particular
 247          * draw that caused lockup.
 248          */
 249         emit_marker(ring, 6);
 250
 251         for (unsigned i = 0; i < count; i++) {
 252                 uint32_t dwords;
 253                 OUT_PKT3(ring, prefetch ? CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2);
 254                 dwords = fd_ringbuffer_emit_reloc_ring_full(ring, target, i) / 4;
 255                 assert(dwords > 0);
 256                 OUT_RING(ring, dwords);
 257                 OUT_PKT2(ring);
 258         }
 259
 260         emit_marker(ring, 6);
 261 }
 262
 263 static inline void
 264 __OUT_IB5(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
 265 {
 266         if (target->cur == target->start)
 267                 return;
 268
 269         unsigned count = fd_ringbuffer_cmd_count(target);
 270
 271         for (unsigned i = 0; i < count; i++) {
 272                 uint32_t dwords;
 273                 OUT_PKT7(ring, CP_INDIRECT_BUFFER, 3);
 274                 dwords = fd_ringbuffer_emit_reloc_ring_full(ring, target, i) / 4;
 275                 assert(dwords > 0);
 276                 OUT_RING(ring, dwords);
 277         }
 278 }
 279
 280 /* CP_SCRATCH_REG4 is used to hold base address for query results: */
 281 // XXX annoyingly scratch regs move on a5xx.. and additionally different
 282 // packet types.. so freedreno_query_hw is going to need a bit of
 283 // rework..
 284 #define HW_QUERY_BASE_REG REG_AXXX_CP_SCRATCH_REG4
 285
 286 static inline void
 287 emit_marker(struct fd_ringbuffer *ring, int scratch_idx)
 288 {
 289         extern unsigned marker_cnt;
 290         unsigned reg = REG_AXXX_CP_SCRATCH_REG0 + scratch_idx;
 291         assert(reg != HW_QUERY_BASE_REG);
 292         if (reg == HW_QUERY_BASE_REG)
 293                 return;
 294         OUT_PKT0(ring, reg, 1);
 295         OUT_RING(ring, ++marker_cnt);
 296 }
 297
 298 static inline uint32_t
 299 pack_rgba(enum pipe_format format, const float *rgba)
 300 {
 301         union util_color uc;
 302         util_pack_color(rgba, format, &uc);
 303         return uc.ui[0];
 304 }
 305
 306 /*
 307  * swap - swap value of @a and @b
 308  */
 309 #define swap(a, b) \
 310         do { __typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
 311
 312 #define foreach_bit(b, mask) \
 313         for (uint32_t _m = (mask), b; _m && ({(b) = u_bit_scan(&_m); (void)(b); 1;});)
 314
 315
 316 #define BIT(bit) (1u << bit)
 317
 318 /*
 319  * a3xx+ helpers:
 320  */
 321
 322 static inline enum a3xx_msaa_samples
 323 fd_msaa_samples(unsigned samples)
 324 {
 325         switch (samples) {
 326         default:
 327                 debug_assert(0);
 328         case 0:
 329         case 1: return MSAA_ONE;
 330         case 2: return MSAA_TWO;
 331         case 4: return MSAA_FOUR;
 332         case 8: return MSAA_EIGHT;
 333         }
 334 }
 335
 336 /*
 337  * a4xx+ helpers:
 338  */
 339
 340 static inline enum a4xx_state_block
 341 fd4_stage2shadersb(gl_shader_stage type)
 342 {
 343         switch (type) {
 344         case MESA_SHADER_VERTEX:
 345                 return SB4_VS_SHADER;
 346         case MESA_SHADER_FRAGMENT:
 347                 return SB4_FS_SHADER;
 348         case MESA_SHADER_COMPUTE:
 349         case MESA_SHADER_KERNEL:
 350                 return SB4_CS_SHADER;
 351         default:
 352                 unreachable("bad shader type");
 353                 return ~0;
 354         }
 355 }
 356
 357 static inline enum a4xx_index_size
 358 fd4_size2indextype(unsigned index_size)
 359 {
 360         switch (index_size) {
 361         case 1: return INDEX4_SIZE_8_BIT;
 362         case 2: return INDEX4_SIZE_16_BIT;
 363         case 4: return INDEX4_SIZE_32_BIT;
 364         }
 365         DBG("unsupported index size: %d", index_size);
 366         assert(0);
 367         return INDEX4_SIZE_32_BIT;
 368 }
 369
 370 #endif /* FREEDRENO_UTIL_H_ */