2 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #ifndef FREEDRENO_UTIL_H_
28 #define FREEDRENO_UTIL_H_
30 #include "drm/freedreno_drmif.h"
31 #include "drm/freedreno_ringbuffer.h"
33 #include "pipe/p_format.h"
34 #include "pipe/p_state.h"
35 #include "util/u_debug.h"
36 #include "util/u_math.h"
37 #include "util/u_half.h"
38 #include "util/u_dynarray.h"
39 #include "util/u_pack_color.h"
42 #include "adreno_common.xml.h"
43 #include "adreno_pm4.xml.h"
45 enum adreno_rb_depth_format
fd_pipe2depth(enum pipe_format format
);
46 enum pc_di_index_size
fd_pipe2index(enum pipe_format format
);
47 enum pipe_format
fd_gmem_restore_format(enum pipe_format format
);
48 enum adreno_rb_blend_factor
fd_blend_factor(unsigned factor
);
49 enum adreno_pa_su_sc_draw
fd_polygon_mode(unsigned mode
);
50 enum adreno_stencil_op
fd_stencil_op(unsigned op
);
52 #define A3XX_MAX_MIP_LEVELS 14
53 /* TBD if it is same on a2xx, but for now: */
54 #define MAX_MIP_LEVELS A3XX_MAX_MIP_LEVELS
56 #define A2XX_MAX_RENDER_TARGETS 1
57 #define A3XX_MAX_RENDER_TARGETS 4
58 #define A4XX_MAX_RENDER_TARGETS 8
59 #define A5XX_MAX_RENDER_TARGETS 8
60 #define A6XX_MAX_RENDER_TARGETS 8
62 #define MAX_RENDER_TARGETS A6XX_MAX_RENDER_TARGETS
64 #define FD_DBG_MSGS 0x0001
65 #define FD_DBG_DISASM 0x0002
66 #define FD_DBG_DCLEAR 0x0004
67 #define FD_DBG_DDRAW 0x0008
68 #define FD_DBG_NOSCIS 0x0010
69 #define FD_DBG_DIRECT 0x0020
70 #define FD_DBG_NOBYPASS 0x0040
71 #define FD_DBG_FRAGHALF 0x0080
72 #define FD_DBG_NOBIN 0x0100
74 #define FD_DBG_GLSL120 0x0400
75 #define FD_DBG_SHADERDB 0x0800
76 #define FD_DBG_FLUSH 0x1000
77 #define FD_DBG_DEQP 0x2000
78 #define FD_DBG_INORDER 0x4000
79 #define FD_DBG_BSTAT 0x8000
80 #define FD_DBG_NOGROW 0x10000
81 #define FD_DBG_LRZ 0x20000
82 #define FD_DBG_NOINDR 0x40000
83 #define FD_DBG_NOBLIT 0x80000
84 #define FD_DBG_HIPRIO 0x100000
85 #define FD_DBG_TTILE 0x200000
86 #define FD_DBG_PERFC 0x400000
87 #define FD_DBG_NOUBWC 0x800000
88 extern int fd_mesa_debug
;
89 extern bool fd_binning_enabled
;
91 #define DBG(fmt, ...) \
92 do { if (fd_mesa_debug & FD_DBG_MSGS) \
93 debug_printf("%s:%d: "fmt "\n", \
94 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
96 /* for conditionally setting boolean flag(s): */
97 #define COND(bool, val) ((bool) ? (val) : 0)
99 #define CP_REG(reg) ((0x4 << 16) | ((unsigned int)((reg) - (0x2000))))
101 static inline uint32_t DRAW(enum pc_di_primtype prim_type
,
102 enum pc_di_src_sel source_select
, enum pc_di_index_size index_size
,
103 enum pc_di_vis_cull_mode vis_cull_mode
,
106 return (prim_type
<< 0) |
107 (source_select
<< 6) |
108 ((index_size
& 1) << 11) |
109 ((index_size
>> 1) << 13) |
110 (vis_cull_mode
<< 9) |
115 static inline uint32_t DRAW_A20X(enum pc_di_primtype prim_type
,
116 enum pc_di_face_cull_sel faceness_cull_select
,
117 enum pc_di_src_sel source_select
, enum pc_di_index_size index_size
,
118 bool pre_fetch_cull_enable
,
119 bool grp_cull_enable
,
122 return (prim_type
<< 0) |
123 (source_select
<< 6) |
124 (faceness_cull_select
<< 8) |
125 ((index_size
& 1) << 11) |
126 ((index_size
>> 1) << 13) |
127 (pre_fetch_cull_enable
<< 14) |
128 (grp_cull_enable
<< 15) |
132 /* for tracking cmdstream positions that need to be patched: */
137 #define fd_patch_num_elements(buf) ((buf)->size / sizeof(struct fd_cs_patch))
138 #define fd_patch_element(buf, i) util_dynarray_element(buf, struct fd_cs_patch, i)
140 static inline enum pipe_format
141 pipe_surface_format(struct pipe_surface
*psurf
)
144 return PIPE_FORMAT_NONE
;
145 return psurf
->format
;
149 fd_surface_half_precision(const struct pipe_surface
*psurf
)
151 enum pipe_format format
;
156 format
= psurf
->format
;
158 /* colors are provided in consts, which go through cov.f32f16, which will
161 if (util_format_is_pure_integer(format
))
164 /* avoid losing precision on 32-bit float formats */
165 if (util_format_is_float(format
) &&
166 util_format_get_component_bits(format
, UTIL_FORMAT_COLORSPACE_RGB
, 0) == 32)
172 static inline unsigned
173 fd_sampler_first_level(const struct pipe_sampler_view
*view
)
175 if (view
->target
== PIPE_BUFFER
)
177 return view
->u
.tex
.first_level
;
180 static inline unsigned
181 fd_sampler_last_level(const struct pipe_sampler_view
*view
)
183 if (view
->target
== PIPE_BUFFER
)
185 return view
->u
.tex
.last_level
;
189 fd_half_precision(struct pipe_framebuffer_state
*pfb
)
193 for (i
= 0; i
< pfb
->nr_cbufs
; i
++)
194 if (!fd_surface_half_precision(pfb
->cbufs
[i
]))
200 /* Note sure if this is same on all gens, but seems to be same on the later
203 static inline unsigned
204 fd_calc_guardband(unsigned x
)
209 return 511 - ((l
- 8) * 65);
214 static inline void emit_marker(struct fd_ringbuffer
*ring
, int scratch_idx
);
217 OUT_RING(struct fd_ringbuffer
*ring
, uint32_t data
)
220 DBG("ring[%p]: OUT_RING %04x: %08x", ring
,
221 (uint32_t)(ring
->cur
- ring
->start
), data
);
223 fd_ringbuffer_emit(ring
, data
);
226 /* like OUT_RING() but appends a cmdstream patch point to 'buf' */
228 OUT_RINGP(struct fd_ringbuffer
*ring
, uint32_t data
,
229 struct util_dynarray
*buf
)
232 DBG("ring[%p]: OUT_RINGP %04x: %08x", ring
,
233 (uint32_t)(ring
->cur
- ring
->start
), data
);
235 util_dynarray_append(buf
, struct fd_cs_patch
, ((struct fd_cs_patch
){
242 * NOTE: OUT_RELOC*() is 2 dwords (64b) on a5xx+
246 __out_reloc(struct fd_ringbuffer
*ring
, struct fd_bo
*bo
,
247 uint32_t offset
, uint64_t or, int32_t shift
, uint32_t flags
)
250 DBG("ring[%p]: OUT_RELOC %04x: %p+%u << %d", ring
,
251 (uint32_t)(ring
->cur
- ring
->start
), bo
, offset
, shift
);
253 debug_assert(offset
< fd_bo_size(bo
));
254 fd_ringbuffer_reloc(ring
, &(struct fd_reloc
){
265 OUT_RELOC(struct fd_ringbuffer
*ring
, struct fd_bo
*bo
,
266 uint32_t offset
, uint64_t or, int32_t shift
)
268 __out_reloc(ring
, bo
, offset
, or, shift
, FD_RELOC_READ
);
272 OUT_RELOCW(struct fd_ringbuffer
*ring
, struct fd_bo
*bo
,
273 uint32_t offset
, uint64_t or, int32_t shift
)
275 __out_reloc(ring
, bo
, offset
, or, shift
, FD_RELOC_READ
| FD_RELOC_WRITE
);
279 OUT_RELOCD(struct fd_ringbuffer
*ring
, struct fd_bo
*bo
,
280 uint32_t offset
, uint64_t or, int32_t shift
)
282 __out_reloc(ring
, bo
, offset
, or, shift
, FD_RELOC_READ
| FD_RELOC_DUMP
);
286 OUT_RB(struct fd_ringbuffer
*ring
, struct fd_ringbuffer
*target
)
288 fd_ringbuffer_emit_reloc_ring_full(ring
, target
, 0);
291 static inline void BEGIN_RING(struct fd_ringbuffer
*ring
, uint32_t ndwords
)
293 if (ring
->cur
+ ndwords
> ring
->end
)
294 fd_ringbuffer_grow(ring
, ndwords
);
298 OUT_PKT0(struct fd_ringbuffer
*ring
, uint16_t regindx
, uint16_t cnt
)
300 BEGIN_RING(ring
, cnt
+1);
301 OUT_RING(ring
, CP_TYPE0_PKT
| ((cnt
-1) << 16) | (regindx
& 0x7FFF));
305 OUT_PKT2(struct fd_ringbuffer
*ring
)
308 OUT_RING(ring
, CP_TYPE2_PKT
);
312 OUT_PKT3(struct fd_ringbuffer
*ring
, uint8_t opcode
, uint16_t cnt
)
314 BEGIN_RING(ring
, cnt
+1);
315 OUT_RING(ring
, CP_TYPE3_PKT
| ((cnt
-1) << 16) | ((opcode
& 0xFF) << 8));
319 * Starting with a5xx, pkt4/pkt7 are used instead of pkt0/pkt3
322 static inline unsigned
323 _odd_parity_bit(unsigned val
)
325 /* See: http://graphics.stanford.edu/~seander/bithacks.html#ParityParallel
326 * note that we want odd parity so 0x6996 is inverted.
332 return (~0x6996 >> val
) & 1;
336 OUT_PKT4(struct fd_ringbuffer
*ring
, uint16_t regindx
, uint16_t cnt
)
338 BEGIN_RING(ring
, cnt
+1);
339 OUT_RING(ring
, CP_TYPE4_PKT
| cnt
|
340 (_odd_parity_bit(cnt
) << 7) |
341 ((regindx
& 0x3ffff) << 8) |
342 ((_odd_parity_bit(regindx
) << 27)));
346 OUT_PKT7(struct fd_ringbuffer
*ring
, uint8_t opcode
, uint16_t cnt
)
348 BEGIN_RING(ring
, cnt
+1);
349 OUT_RING(ring
, CP_TYPE7_PKT
| cnt
|
350 (_odd_parity_bit(cnt
) << 15) |
351 ((opcode
& 0x7f) << 16) |
352 ((_odd_parity_bit(opcode
) << 23)));
356 OUT_WFI(struct fd_ringbuffer
*ring
)
358 OUT_PKT3(ring
, CP_WAIT_FOR_IDLE
, 1);
359 OUT_RING(ring
, 0x00000000);
363 OUT_WFI5(struct fd_ringbuffer
*ring
)
365 OUT_PKT7(ring
, CP_WAIT_FOR_IDLE
, 0);
369 __OUT_IB(struct fd_ringbuffer
*ring
, bool prefetch
, struct fd_ringbuffer
*target
)
371 if (target
->cur
== target
->start
)
374 unsigned count
= fd_ringbuffer_cmd_count(target
);
376 /* for debug after a lock up, write a unique counter value
377 * to scratch6 for each IB, to make it easier to match up
378 * register dumps to cmdstream. The combination of IB and
379 * DRAW (scratch7) is enough to "triangulate" the particular
380 * draw that caused lockup.
382 emit_marker(ring
, 6);
384 for (unsigned i
= 0; i
< count
; i
++) {
386 OUT_PKT3(ring
, prefetch
? CP_INDIRECT_BUFFER_PFE
: CP_INDIRECT_BUFFER_PFD
, 2);
387 dwords
= fd_ringbuffer_emit_reloc_ring_full(ring
, target
, i
) / 4;
389 OUT_RING(ring
, dwords
);
393 emit_marker(ring
, 6);
397 __OUT_IB5(struct fd_ringbuffer
*ring
, struct fd_ringbuffer
*target
)
399 if (target
->cur
== target
->start
)
402 unsigned count
= fd_ringbuffer_cmd_count(target
);
404 for (unsigned i
= 0; i
< count
; i
++) {
406 OUT_PKT7(ring
, CP_INDIRECT_BUFFER
, 3);
407 dwords
= fd_ringbuffer_emit_reloc_ring_full(ring
, target
, i
) / 4;
409 OUT_RING(ring
, dwords
);
413 /* CP_SCRATCH_REG4 is used to hold base address for query results: */
414 // XXX annoyingly scratch regs move on a5xx.. and additionally different
415 // packet types.. so freedreno_query_hw is going to need a bit of
417 #define HW_QUERY_BASE_REG REG_AXXX_CP_SCRATCH_REG4
420 emit_marker(struct fd_ringbuffer
*ring
, int scratch_idx
)
422 extern unsigned marker_cnt
;
423 unsigned reg
= REG_AXXX_CP_SCRATCH_REG0
+ scratch_idx
;
424 assert(reg
!= HW_QUERY_BASE_REG
);
425 if (reg
== HW_QUERY_BASE_REG
)
427 OUT_PKT0(ring
, reg
, 1);
428 OUT_RING(ring
, ++marker_cnt
);
431 static inline uint32_t
432 pack_rgba(enum pipe_format format
, const float *rgba
)
435 util_pack_color(rgba
, format
, &uc
);
440 * swap - swap value of @a and @b
443 do { __typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
445 #define foreach_bit(b, mask) \
446 for (uint32_t _m = (mask); _m && ({(b) = u_bit_scan(&_m); 1;});)
449 #define BIT(bit) (1u << bit)
455 static inline enum a3xx_msaa_samples
456 fd_msaa_samples(unsigned samples
)
462 case 1: return MSAA_ONE
;
463 case 2: return MSAA_TWO
;
464 case 4: return MSAA_FOUR
;
465 case 8: return MSAA_EIGHT
;
473 static inline enum a4xx_state_block
474 fd4_stage2shadersb(gl_shader_stage type
)
477 case MESA_SHADER_VERTEX
:
478 return SB4_VS_SHADER
;
479 case MESA_SHADER_FRAGMENT
:
480 return SB4_FS_SHADER
;
481 case MESA_SHADER_COMPUTE
:
482 case MESA_SHADER_KERNEL
:
483 return SB4_CS_SHADER
;
485 unreachable("bad shader type");
490 static inline enum a4xx_index_size
491 fd4_size2indextype(unsigned index_size
)
493 switch (index_size
) {
494 case 1: return INDEX4_SIZE_8_BIT
;
495 case 2: return INDEX4_SIZE_16_BIT
;
496 case 4: return INDEX4_SIZE_32_BIT
;
498 DBG("unsupported index size: %d", index_size
);
500 return INDEX4_SIZE_32_BIT
;
503 #endif /* FREEDRENO_UTIL_H_ */