src/gallium/drivers/freedreno/freedreno_util.h

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #ifndef FREEDRENO_UTIL_H_
  30 #define FREEDRENO_UTIL_H_
  31
  32 #include <freedreno_drmif.h>
  33 #include <freedreno_ringbuffer.h>
  34
  35 #include "pipe/p_format.h"
  36 #include "pipe/p_state.h"
  37 #include "util/u_debug.h"
  38 #include "util/u_math.h"
  39 #include "util/u_half.h"
  40 #include "util/u_dynarray.h"
  41 #include "util/u_pack_color.h"
  42
  43 #include "disasm.h"
  44 #include "adreno_common.xml.h"
  45 #include "adreno_pm4.xml.h"
  46
  47 enum adreno_rb_depth_format fd_pipe2depth(enum pipe_format format);
  48 enum pc_di_index_size fd_pipe2index(enum pipe_format format);
  49 enum adreno_rb_blend_factor fd_blend_factor(unsigned factor);
  50 enum adreno_pa_su_sc_draw fd_polygon_mode(unsigned mode);
  51 enum adreno_stencil_op fd_stencil_op(unsigned op);
  52
  53 #define A3XX_MAX_MIP_LEVELS 14
  54 /* TBD if it is same on a2xx, but for now: */
  55 #define MAX_MIP_LEVELS A3XX_MAX_MIP_LEVELS
  56
  57 #define A2XX_MAX_RENDER_TARGETS 1
  58 #define A3XX_MAX_RENDER_TARGETS 4
  59 #define A4XX_MAX_RENDER_TARGETS 8
  60 #define A5XX_MAX_RENDER_TARGETS 8
  61
  62 #define MAX_RENDER_TARGETS A5XX_MAX_RENDER_TARGETS
  63
  64 #define FD_DBG_MSGS     0x0001
  65 #define FD_DBG_DISASM   0x0002
  66 #define FD_DBG_DCLEAR   0x0004
  67 #define FD_DBG_DDRAW    0x0008
  68 #define FD_DBG_NOSCIS   0x0010
  69 #define FD_DBG_DIRECT   0x0020
  70 #define FD_DBG_NOBYPASS 0x0040
  71 #define FD_DBG_FRAGHALF 0x0080
  72 #define FD_DBG_NOBIN    0x0100
  73 #define FD_DBG_OPTMSGS  0x0200
  74 #define FD_DBG_GLSL120  0x0400
  75 #define FD_DBG_SHADERDB 0x0800
  76 #define FD_DBG_FLUSH    0x1000
  77 #define FD_DBG_DEQP     0x2000
  78 #define FD_DBG_NIR      0x4000
  79 #define FD_DBG_REORDER  0x8000
  80 #define FD_DBG_BSTAT   0x10000
  81
  82 extern int fd_mesa_debug;
  83 extern bool fd_binning_enabled;
  84
  85 #define DBG(fmt, ...) \
  86                 do { if (fd_mesa_debug & FD_DBG_MSGS) \
  87                         debug_printf("%s:%d: "fmt "\n", \
  88                                 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
  89
  90 /* for conditionally setting boolean flag(s): */
  91 #define COND(bool, val) ((bool) ? (val) : 0)
  92
  93 #define CP_REG(reg) ((0x4 << 16) | ((unsigned int)((reg) - (0x2000))))
  94
  95 static inline uint32_t DRAW(enum pc_di_primtype prim_type,
  96                 enum pc_di_src_sel source_select, enum pc_di_index_size index_size,
  97                 enum pc_di_vis_cull_mode vis_cull_mode,
  98                 uint8_t instances)
  99 {
 100         return (prim_type         << 0) |
 101                         (source_select     << 6) |
 102                         ((index_size & 1)  << 11) |
 103                         ((index_size >> 1) << 13) |
 104                         (vis_cull_mode     << 9) |
 105                         (1                 << 14) |
 106                         (instances         << 24);
 107 }
 108
 109 /* for tracking cmdstream positions that need to be patched: */
 110 struct fd_cs_patch {
 111         uint32_t *cs;
 112         uint32_t val;
 113 };
 114 #define fd_patch_num_elements(buf) ((buf)->size / sizeof(struct fd_cs_patch))
 115 #define fd_patch_element(buf, i)   util_dynarray_element(buf, struct fd_cs_patch, i)
 116
 117 static inline enum pipe_format
 118 pipe_surface_format(struct pipe_surface *psurf)
 119 {
 120         if (!psurf)
 121                 return PIPE_FORMAT_NONE;
 122         return psurf->format;
 123 }
 124
 125 static inline bool
 126 fd_surface_half_precision(const struct pipe_surface *psurf)
 127 {
 128         enum pipe_format format;
 129
 130         if (!psurf)
 131                 return true;
 132
 133         format = psurf->format;
 134
 135         /* colors are provided in consts, which go through cov.f32f16, which will
 136          * break these values
 137          */
 138         if (util_format_is_pure_integer(format))
 139                 return false;
 140
 141         /* avoid losing precision on 32-bit float formats */
 142         if (util_format_is_float(format) &&
 143                 util_format_get_component_bits(format, UTIL_FORMAT_COLORSPACE_RGB, 0) == 32)
 144                 return false;
 145
 146         return true;
 147 }
 148
 149 static inline unsigned
 150 fd_sampler_first_level(const struct pipe_sampler_view *view)
 151 {
 152         if (view->target == PIPE_BUFFER)
 153                 return 0;
 154         return view->u.tex.first_level;
 155 }
 156
 157 static inline unsigned
 158 fd_sampler_last_level(const struct pipe_sampler_view *view)
 159 {
 160         if (view->target == PIPE_BUFFER)
 161                 return 0;
 162         return view->u.tex.last_level;
 163 }
 164
 165 static inline bool
 166 fd_half_precision(struct pipe_framebuffer_state *pfb)
 167 {
 168         unsigned i;
 169
 170         for (i = 0; i < pfb->nr_cbufs; i++)
 171                 if (!fd_surface_half_precision(pfb->cbufs[i]))
 172                         return false;
 173
 174         return true;
 175 }
 176
 177 #define LOG_DWORDS 0
 178
 179 static inline void emit_marker(struct fd_ringbuffer *ring, int scratch_idx);
 180 static inline void emit_marker5(struct fd_ringbuffer *ring, int scratch_idx);
 181
 182 static inline void
 183 OUT_RING(struct fd_ringbuffer *ring, uint32_t data)
 184 {
 185         if (LOG_DWORDS) {
 186                 DBG("ring[%p]: OUT_RING   %04x:  %08x", ring,
 187                                 (uint32_t)(ring->cur - ring->last_start), data);
 188         }
 189         fd_ringbuffer_emit(ring, data);
 190 }
 191
 192 /* like OUT_RING() but appends a cmdstream patch point to 'buf' */
 193 static inline void
 194 OUT_RINGP(struct fd_ringbuffer *ring, uint32_t data,
 195                 struct util_dynarray *buf)
 196 {
 197         if (LOG_DWORDS) {
 198                 DBG("ring[%p]: OUT_RINGP  %04x:  %08x", ring,
 199                                 (uint32_t)(ring->cur - ring->last_start), data);
 200         }
 201         util_dynarray_append(buf, struct fd_cs_patch, ((struct fd_cs_patch){
 202                 .cs  = ring->cur++,
 203                 .val = data,
 204         }));
 205 }
 206
 207 /*
 208  * NOTE: OUT_RELOC*() is 2 dwords (64b) on a5xx+
 209  */
 210
 211 static inline void
 212 OUT_RELOC(struct fd_ringbuffer *ring, struct fd_bo *bo,
 213                 uint32_t offset, uint64_t or, int32_t shift)
 214 {
 215         if (LOG_DWORDS) {
 216                 DBG("ring[%p]: OUT_RELOC   %04x:  %p+%u << %d", ring,
 217                                 (uint32_t)(ring->cur - ring->last_start), bo, offset, shift);
 218         }
 219         debug_assert(offset < fd_bo_size(bo));
 220         fd_ringbuffer_reloc2(ring, &(struct fd_reloc){
 221                 .bo = bo,
 222                 .flags = FD_RELOC_READ,
 223                 .offset = offset,
 224                 .or = or,
 225                 .shift = shift,
 226                 .orhi = or >> 32,
 227         });
 228 }
 229
 230 static inline void
 231 OUT_RELOCW(struct fd_ringbuffer *ring, struct fd_bo *bo,
 232                 uint32_t offset, uint64_t or, int32_t shift)
 233 {
 234         if (LOG_DWORDS) {
 235                 DBG("ring[%p]: OUT_RELOCW  %04x:  %p+%u << %d", ring,
 236                                 (uint32_t)(ring->cur - ring->last_start), bo, offset, shift);
 237         }
 238         debug_assert(offset < fd_bo_size(bo));
 239         fd_ringbuffer_reloc2(ring, &(struct fd_reloc){
 240                 .bo = bo,
 241                 .flags = FD_RELOC_READ | FD_RELOC_WRITE,
 242                 .offset = offset,
 243                 .or = or,
 244                 .shift = shift,
 245                 .orhi = or >> 32,
 246         });
 247 }
 248
 249 static inline void BEGIN_RING(struct fd_ringbuffer *ring, uint32_t ndwords)
 250 {
 251         if (ring->cur + ndwords >= ring->end)
 252                 fd_ringbuffer_grow(ring, ndwords);
 253 }
 254
 255 static inline uint32_t
 256 __gpu_id(struct fd_ringbuffer *ring)
 257 {
 258         uint64_t val;
 259         fd_pipe_get_param(ring->pipe, FD_GPU_ID, &val);
 260         return val;
 261 }
 262
 263 static inline void
 264 OUT_PKT0(struct fd_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
 265 {
 266         debug_assert(__gpu_id(ring) < 500);
 267         BEGIN_RING(ring, cnt+1);
 268         OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
 269 }
 270
 271 static inline void
 272 OUT_PKT2(struct fd_ringbuffer *ring)
 273 {
 274         debug_assert(__gpu_id(ring) < 500);
 275         BEGIN_RING(ring, 1);
 276         OUT_RING(ring, CP_TYPE2_PKT);
 277 }
 278
 279 static inline void
 280 OUT_PKT3(struct fd_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
 281 {
 282         debug_assert(__gpu_id(ring) < 500);
 283         BEGIN_RING(ring, cnt+1);
 284         OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
 285 }
 286
 287 /*
 288  * Starting with a5xx, pkt4/pkt7 are used instead of pkt0/pkt3
 289  */
 290
 291 static inline unsigned
 292 _odd_parity_bit(unsigned val)
 293 {
 294         /* See: http://graphics.stanford.edu/~seander/bithacks.html#ParityParallel
 295          * note that we want odd parity so 0x6996 is inverted.
 296          */
 297         val ^= val >> 16;
 298         val ^= val >> 8;
 299         val ^= val >> 4;
 300         val &= 0xf;
 301         return (~0x6996 >> val) & 1;
 302 }
 303
 304 static inline void
 305 OUT_PKT4(struct fd_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
 306 {
 307         BEGIN_RING(ring, cnt+1);
 308         OUT_RING(ring, CP_TYPE4_PKT | cnt |
 309                         (_odd_parity_bit(cnt) << 7) |
 310                         ((regindx & 0x3ffff) << 8) |
 311                         ((_odd_parity_bit(regindx) << 27)));
 312 }
 313
 314 static inline void
 315 OUT_PKT7(struct fd_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
 316 {
 317         BEGIN_RING(ring, cnt+1);
 318         OUT_RING(ring, CP_TYPE7_PKT | cnt |
 319                         (_odd_parity_bit(cnt) << 15) |
 320                         ((opcode & 0x7f) << 16) |
 321                         ((_odd_parity_bit(opcode) << 23)));
 322 }
 323
 324 static inline void
 325 OUT_WFI(struct fd_ringbuffer *ring)
 326 {
 327         OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
 328         OUT_RING(ring, 0x00000000);
 329 }
 330
 331 static inline void
 332 OUT_WFI5(struct fd_ringbuffer *ring)
 333 {
 334         OUT_PKT7(ring, CP_WAIT_FOR_IDLE, 0);
 335 }
 336
 337 static inline void
 338 __OUT_IB(struct fd_ringbuffer *ring, bool prefetch, struct fd_ringbuffer *target)
 339 {
 340         unsigned count = fd_ringbuffer_cmd_count(target);
 341
 342         debug_assert(__gpu_id(ring) < 500);
 343
 344         /* for debug after a lock up, write a unique counter value
 345          * to scratch6 for each IB, to make it easier to match up
 346          * register dumps to cmdstream.  The combination of IB and
 347          * DRAW (scratch7) is enough to "triangulate" the particular
 348          * draw that caused lockup.
 349          */
 350         emit_marker(ring, 6);
 351
 352         for (unsigned i = 0; i < count; i++) {
 353                 uint32_t dwords;
 354                 OUT_PKT3(ring, prefetch ? CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2);
 355                 dwords = fd_ringbuffer_emit_reloc_ring_full(ring, target, i) / 4;
 356                 assert(dwords > 0);
 357                 OUT_RING(ring, dwords);
 358                 OUT_PKT2(ring);
 359         }
 360
 361         emit_marker(ring, 6);
 362 }
 363
 364 static inline void
 365 __OUT_IB5(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
 366 {
 367         unsigned count = fd_ringbuffer_cmd_count(target);
 368
 369         /* for debug after a lock up, write a unique counter value
 370          * to scratch6 for each IB, to make it easier to match up
 371          * register dumps to cmdstream.  The combination of IB and
 372          * DRAW (scratch7) is enough to "triangulate" the particular
 373          * draw that caused lockup.
 374          */
 375         emit_marker5(ring, 6);
 376
 377         for (unsigned i = 0; i < count; i++) {
 378                 uint32_t dwords;
 379                 OUT_PKT7(ring, CP_INDIRECT_BUFFER, 3);
 380                 dwords = fd_ringbuffer_emit_reloc_ring_full(ring, target, i) / 4;
 381                 assert(dwords > 0);
 382                 OUT_RING(ring, dwords);
 383         }
 384
 385         emit_marker5(ring, 6);
 386 }
 387
 388 /* CP_SCRATCH_REG4 is used to hold base address for query results: */
 389 // XXX annoyingly scratch regs move on a5xx.. and additionally different
 390 // packet types.. so freedreno_query_hw is going to need a bit of
 391 // rework..
 392 #define HW_QUERY_BASE_REG REG_AXXX_CP_SCRATCH_REG4
 393
 394 static inline void
 395 emit_marker(struct fd_ringbuffer *ring, int scratch_idx)
 396 {
 397         extern unsigned marker_cnt;
 398         unsigned reg = REG_AXXX_CP_SCRATCH_REG0 + scratch_idx;
 399         assert(reg != HW_QUERY_BASE_REG);
 400         if (reg == HW_QUERY_BASE_REG)
 401                 return;
 402         OUT_PKT0(ring, reg, 1);
 403         OUT_RING(ring, ++marker_cnt);
 404 }
 405
 406 static inline void
 407 emit_marker5(struct fd_ringbuffer *ring, int scratch_idx)
 408 {
 409         extern unsigned marker_cnt;
 410 //XXX   unsigned reg = REG_A5XX_CP_SCRATCH_REG(scratch_idx);
 411         unsigned reg = 0x00000b78 + scratch_idx;
 412         assert(reg != HW_QUERY_BASE_REG);
 413         if (reg == HW_QUERY_BASE_REG)
 414                 return;
 415         OUT_WFI5(ring);
 416         OUT_PKT4(ring, reg, 1);
 417         OUT_RING(ring, ++marker_cnt);
 418         OUT_WFI5(ring);
 419 }
 420
 421 /* helper to get numeric value from environment variable..  mostly
 422  * just leaving this here because it is helpful to brute-force figure
 423  * out unknown formats, etc, which blob driver does not support:
 424  */
 425 static inline uint32_t env2u(const char *envvar)
 426 {
 427         char *str = getenv(envvar);
 428         if (str)
 429                 return strtoul(str, NULL, 0);
 430         return 0;
 431 }
 432
 433 static inline uint32_t
 434 pack_rgba(enum pipe_format format, const float *rgba)
 435 {
 436         union util_color uc;
 437         util_pack_color(rgba, format, &uc);
 438         return uc.ui[0];
 439 }
 440
 441 /*
 442  * swap - swap value of @a and @b
 443  */
 444 #define swap(a, b) \
 445         do { __typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
 446
 447 #define foreach_bit(b, mask) \
 448         for (uint32_t _m = (mask); _m && ({(b) = u_bit_scan(&_m); 1;});)
 449
 450 #endif /* FREEDRENO_UTIL_H_ */