src/gallium/drivers/freedreno/freedreno_util.h

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #ifndef FREEDRENO_UTIL_H_
  30 #define FREEDRENO_UTIL_H_
  31
  32 #include <freedreno_drmif.h>
  33 #include <freedreno_ringbuffer.h>
  34
  35 #include "pipe/p_format.h"
  36 #include "pipe/p_state.h"
  37 #include "util/u_debug.h"
  38 #include "util/u_math.h"
  39 #include "util/u_half.h"
  40 #include "util/u_dynarray.h"
  41 #include "util/u_pack_color.h"
  42
  43 #include "disasm.h"
  44 #include "adreno_common.xml.h"
  45 #include "adreno_pm4.xml.h"
  46
  47 enum adreno_rb_depth_format fd_pipe2depth(enum pipe_format format);
  48 enum pc_di_index_size fd_pipe2index(enum pipe_format format);
  49 enum pipe_format fd_gmem_restore_format(enum pipe_format format);
  50 enum adreno_rb_blend_factor fd_blend_factor(unsigned factor);
  51 enum adreno_pa_su_sc_draw fd_polygon_mode(unsigned mode);
  52 enum adreno_stencil_op fd_stencil_op(unsigned op);
  53
  54 #define A3XX_MAX_MIP_LEVELS 14
  55 /* TBD if it is same on a2xx, but for now: */
  56 #define MAX_MIP_LEVELS A3XX_MAX_MIP_LEVELS
  57
  58 #define A2XX_MAX_RENDER_TARGETS 1
  59 #define A3XX_MAX_RENDER_TARGETS 4
  60 #define A4XX_MAX_RENDER_TARGETS 8
  61 #define A5XX_MAX_RENDER_TARGETS 8
  62
  63 #define MAX_RENDER_TARGETS A5XX_MAX_RENDER_TARGETS
  64
  65 #define FD_DBG_MSGS     0x0001
  66 #define FD_DBG_DISASM   0x0002
  67 #define FD_DBG_DCLEAR   0x0004
  68 #define FD_DBG_DDRAW    0x0008
  69 #define FD_DBG_NOSCIS   0x0010
  70 #define FD_DBG_DIRECT   0x0020
  71 #define FD_DBG_NOBYPASS 0x0040
  72 #define FD_DBG_FRAGHALF 0x0080
  73 #define FD_DBG_NOBIN    0x0100
  74 #define FD_DBG_OPTMSGS  0x0200
  75 #define FD_DBG_GLSL120  0x0400
  76 #define FD_DBG_SHADERDB 0x0800
  77 #define FD_DBG_FLUSH    0x1000
  78 #define FD_DBG_DEQP     0x2000
  79 #define FD_DBG_NIR      0x4000
  80 #define FD_DBG_REORDER  0x8000
  81 #define FD_DBG_BSTAT   0x10000
  82
  83 extern int fd_mesa_debug;
  84 extern bool fd_binning_enabled;
  85
  86 #define DBG(fmt, ...) \
  87                 do { if (fd_mesa_debug & FD_DBG_MSGS) \
  88                         debug_printf("%s:%d: "fmt "\n", \
  89                                 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
  90
  91 /* for conditionally setting boolean flag(s): */
  92 #define COND(bool, val) ((bool) ? (val) : 0)
  93
  94 #define CP_REG(reg) ((0x4 << 16) | ((unsigned int)((reg) - (0x2000))))
  95
  96 static inline uint32_t DRAW(enum pc_di_primtype prim_type,
  97                 enum pc_di_src_sel source_select, enum pc_di_index_size index_size,
  98                 enum pc_di_vis_cull_mode vis_cull_mode,
  99                 uint8_t instances)
 100 {
 101         return (prim_type         << 0) |
 102                         (source_select     << 6) |
 103                         ((index_size & 1)  << 11) |
 104                         ((index_size >> 1) << 13) |
 105                         (vis_cull_mode     << 9) |
 106                         (1                 << 14) |
 107                         (instances         << 24);
 108 }
 109
 110 /* for tracking cmdstream positions that need to be patched: */
 111 struct fd_cs_patch {
 112         uint32_t *cs;
 113         uint32_t val;
 114 };
 115 #define fd_patch_num_elements(buf) ((buf)->size / sizeof(struct fd_cs_patch))
 116 #define fd_patch_element(buf, i)   util_dynarray_element(buf, struct fd_cs_patch, i)
 117
 118 static inline enum pipe_format
 119 pipe_surface_format(struct pipe_surface *psurf)
 120 {
 121         if (!psurf)
 122                 return PIPE_FORMAT_NONE;
 123         return psurf->format;
 124 }
 125
 126 static inline bool
 127 fd_surface_half_precision(const struct pipe_surface *psurf)
 128 {
 129         enum pipe_format format;
 130
 131         if (!psurf)
 132                 return true;
 133
 134         format = psurf->format;
 135
 136         /* colors are provided in consts, which go through cov.f32f16, which will
 137          * break these values
 138          */
 139         if (util_format_is_pure_integer(format))
 140                 return false;
 141
 142         /* avoid losing precision on 32-bit float formats */
 143         if (util_format_is_float(format) &&
 144                 util_format_get_component_bits(format, UTIL_FORMAT_COLORSPACE_RGB, 0) == 32)
 145                 return false;
 146
 147         return true;
 148 }
 149
 150 static inline unsigned
 151 fd_sampler_first_level(const struct pipe_sampler_view *view)
 152 {
 153         if (view->target == PIPE_BUFFER)
 154                 return 0;
 155         return view->u.tex.first_level;
 156 }
 157
 158 static inline unsigned
 159 fd_sampler_last_level(const struct pipe_sampler_view *view)
 160 {
 161         if (view->target == PIPE_BUFFER)
 162                 return 0;
 163         return view->u.tex.last_level;
 164 }
 165
 166 static inline bool
 167 fd_half_precision(struct pipe_framebuffer_state *pfb)
 168 {
 169         unsigned i;
 170
 171         for (i = 0; i < pfb->nr_cbufs; i++)
 172                 if (!fd_surface_half_precision(pfb->cbufs[i]))
 173                         return false;
 174
 175         return true;
 176 }
 177
 178 #define LOG_DWORDS 0
 179
 180 static inline void emit_marker(struct fd_ringbuffer *ring, int scratch_idx);
 181 static inline void emit_marker5(struct fd_ringbuffer *ring, int scratch_idx);
 182
 183 static inline void
 184 OUT_RING(struct fd_ringbuffer *ring, uint32_t data)
 185 {
 186         if (LOG_DWORDS) {
 187                 DBG("ring[%p]: OUT_RING   %04x:  %08x", ring,
 188                                 (uint32_t)(ring->cur - ring->last_start), data);
 189         }
 190         fd_ringbuffer_emit(ring, data);
 191 }
 192
 193 /* like OUT_RING() but appends a cmdstream patch point to 'buf' */
 194 static inline void
 195 OUT_RINGP(struct fd_ringbuffer *ring, uint32_t data,
 196                 struct util_dynarray *buf)
 197 {
 198         if (LOG_DWORDS) {
 199                 DBG("ring[%p]: OUT_RINGP  %04x:  %08x", ring,
 200                                 (uint32_t)(ring->cur - ring->last_start), data);
 201         }
 202         util_dynarray_append(buf, struct fd_cs_patch, ((struct fd_cs_patch){
 203                 .cs  = ring->cur++,
 204                 .val = data,
 205         }));
 206 }
 207
 208 /*
 209  * NOTE: OUT_RELOC*() is 2 dwords (64b) on a5xx+
 210  */
 211
 212 static inline void
 213 OUT_RELOC(struct fd_ringbuffer *ring, struct fd_bo *bo,
 214                 uint32_t offset, uint64_t or, int32_t shift)
 215 {
 216         if (LOG_DWORDS) {
 217                 DBG("ring[%p]: OUT_RELOC   %04x:  %p+%u << %d", ring,
 218                                 (uint32_t)(ring->cur - ring->last_start), bo, offset, shift);
 219         }
 220         debug_assert(offset < fd_bo_size(bo));
 221         fd_ringbuffer_reloc2(ring, &(struct fd_reloc){
 222                 .bo = bo,
 223                 .flags = FD_RELOC_READ,
 224                 .offset = offset,
 225                 .or = or,
 226                 .shift = shift,
 227                 .orhi = or >> 32,
 228         });
 229 }
 230
 231 static inline void
 232 OUT_RELOCW(struct fd_ringbuffer *ring, struct fd_bo *bo,
 233                 uint32_t offset, uint64_t or, int32_t shift)
 234 {
 235         if (LOG_DWORDS) {
 236                 DBG("ring[%p]: OUT_RELOCW  %04x:  %p+%u << %d", ring,
 237                                 (uint32_t)(ring->cur - ring->last_start), bo, offset, shift);
 238         }
 239         debug_assert(offset < fd_bo_size(bo));
 240         fd_ringbuffer_reloc2(ring, &(struct fd_reloc){
 241                 .bo = bo,
 242                 .flags = FD_RELOC_READ | FD_RELOC_WRITE,
 243                 .offset = offset,
 244                 .or = or,
 245                 .shift = shift,
 246                 .orhi = or >> 32,
 247         });
 248 }
 249
 250 static inline void BEGIN_RING(struct fd_ringbuffer *ring, uint32_t ndwords)
 251 {
 252         if (ring->cur + ndwords >= ring->end)
 253                 fd_ringbuffer_grow(ring, ndwords);
 254 }
 255
 256 static inline uint32_t
 257 __gpu_id(struct fd_ringbuffer *ring)
 258 {
 259         uint64_t val;
 260         fd_pipe_get_param(ring->pipe, FD_GPU_ID, &val);
 261         return val;
 262 }
 263
 264 static inline void
 265 OUT_PKT0(struct fd_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
 266 {
 267         debug_assert(__gpu_id(ring) < 500);
 268         BEGIN_RING(ring, cnt+1);
 269         OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
 270 }
 271
 272 static inline void
 273 OUT_PKT2(struct fd_ringbuffer *ring)
 274 {
 275         debug_assert(__gpu_id(ring) < 500);
 276         BEGIN_RING(ring, 1);
 277         OUT_RING(ring, CP_TYPE2_PKT);
 278 }
 279
 280 static inline void
 281 OUT_PKT3(struct fd_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
 282 {
 283         debug_assert(__gpu_id(ring) < 500);
 284         BEGIN_RING(ring, cnt+1);
 285         OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
 286 }
 287
 288 /*
 289  * Starting with a5xx, pkt4/pkt7 are used instead of pkt0/pkt3
 290  */
 291
 292 static inline unsigned
 293 _odd_parity_bit(unsigned val)
 294 {
 295         /* See: http://graphics.stanford.edu/~seander/bithacks.html#ParityParallel
 296          * note that we want odd parity so 0x6996 is inverted.
 297          */
 298         val ^= val >> 16;
 299         val ^= val >> 8;
 300         val ^= val >> 4;
 301         val &= 0xf;
 302         return (~0x6996 >> val) & 1;
 303 }
 304
 305 static inline void
 306 OUT_PKT4(struct fd_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
 307 {
 308         BEGIN_RING(ring, cnt+1);
 309         OUT_RING(ring, CP_TYPE4_PKT | cnt |
 310                         (_odd_parity_bit(cnt) << 7) |
 311                         ((regindx & 0x3ffff) << 8) |
 312                         ((_odd_parity_bit(regindx) << 27)));
 313 }
 314
 315 static inline void
 316 OUT_PKT7(struct fd_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
 317 {
 318         BEGIN_RING(ring, cnt+1);
 319         OUT_RING(ring, CP_TYPE7_PKT | cnt |
 320                         (_odd_parity_bit(cnt) << 15) |
 321                         ((opcode & 0x7f) << 16) |
 322                         ((_odd_parity_bit(opcode) << 23)));
 323 }
 324
 325 static inline void
 326 OUT_WFI(struct fd_ringbuffer *ring)
 327 {
 328         OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
 329         OUT_RING(ring, 0x00000000);
 330 }
 331
 332 static inline void
 333 OUT_WFI5(struct fd_ringbuffer *ring)
 334 {
 335         OUT_PKT7(ring, CP_WAIT_FOR_IDLE, 0);
 336 }
 337
 338 static inline void
 339 __OUT_IB(struct fd_ringbuffer *ring, bool prefetch, struct fd_ringbuffer *target)
 340 {
 341         unsigned count = fd_ringbuffer_cmd_count(target);
 342
 343         debug_assert(__gpu_id(ring) < 500);
 344
 345         /* for debug after a lock up, write a unique counter value
 346          * to scratch6 for each IB, to make it easier to match up
 347          * register dumps to cmdstream.  The combination of IB and
 348          * DRAW (scratch7) is enough to "triangulate" the particular
 349          * draw that caused lockup.
 350          */
 351         emit_marker(ring, 6);
 352
 353         for (unsigned i = 0; i < count; i++) {
 354                 uint32_t dwords;
 355                 OUT_PKT3(ring, prefetch ? CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2);
 356                 dwords = fd_ringbuffer_emit_reloc_ring_full(ring, target, i) / 4;
 357                 assert(dwords > 0);
 358                 OUT_RING(ring, dwords);
 359                 OUT_PKT2(ring);
 360         }
 361
 362         emit_marker(ring, 6);
 363 }
 364
 365 static inline void
 366 __OUT_IB5(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
 367 {
 368         unsigned count = fd_ringbuffer_cmd_count(target);
 369
 370         /* for debug after a lock up, write a unique counter value
 371          * to scratch6 for each IB, to make it easier to match up
 372          * register dumps to cmdstream.  The combination of IB and
 373          * DRAW (scratch7) is enough to "triangulate" the particular
 374          * draw that caused lockup.
 375          */
 376         emit_marker5(ring, 6);
 377
 378         for (unsigned i = 0; i < count; i++) {
 379                 uint32_t dwords;
 380                 OUT_PKT7(ring, CP_INDIRECT_BUFFER, 3);
 381                 dwords = fd_ringbuffer_emit_reloc_ring_full(ring, target, i) / 4;
 382                 assert(dwords > 0);
 383                 OUT_RING(ring, dwords);
 384         }
 385
 386         emit_marker5(ring, 6);
 387 }
 388
 389 /* CP_SCRATCH_REG4 is used to hold base address for query results: */
 390 // XXX annoyingly scratch regs move on a5xx.. and additionally different
 391 // packet types.. so freedreno_query_hw is going to need a bit of
 392 // rework..
 393 #define HW_QUERY_BASE_REG REG_AXXX_CP_SCRATCH_REG4
 394
 395 static inline void
 396 emit_marker(struct fd_ringbuffer *ring, int scratch_idx)
 397 {
 398         extern unsigned marker_cnt;
 399         unsigned reg = REG_AXXX_CP_SCRATCH_REG0 + scratch_idx;
 400         assert(reg != HW_QUERY_BASE_REG);
 401         if (reg == HW_QUERY_BASE_REG)
 402                 return;
 403         OUT_PKT0(ring, reg, 1);
 404         OUT_RING(ring, ++marker_cnt);
 405 }
 406
 407 static inline void
 408 emit_marker5(struct fd_ringbuffer *ring, int scratch_idx)
 409 {
 410         extern unsigned marker_cnt;
 411 //XXX   unsigned reg = REG_A5XX_CP_SCRATCH_REG(scratch_idx);
 412         unsigned reg = 0x00000b78 + scratch_idx;
 413         assert(reg != HW_QUERY_BASE_REG);
 414         if (reg == HW_QUERY_BASE_REG)
 415                 return;
 416         OUT_WFI5(ring);
 417         OUT_PKT4(ring, reg, 1);
 418         OUT_RING(ring, ++marker_cnt);
 419         OUT_WFI5(ring);
 420 }
 421
 422 /* helper to get numeric value from environment variable..  mostly
 423  * just leaving this here because it is helpful to brute-force figure
 424  * out unknown formats, etc, which blob driver does not support:
 425  */
 426 static inline uint32_t env2u(const char *envvar)
 427 {
 428         char *str = getenv(envvar);
 429         if (str)
 430                 return strtoul(str, NULL, 0);
 431         return 0;
 432 }
 433
 434 static inline uint32_t
 435 pack_rgba(enum pipe_format format, const float *rgba)
 436 {
 437         union util_color uc;
 438         util_pack_color(rgba, format, &uc);
 439         return uc.ui[0];
 440 }
 441
 442 /*
 443  * swap - swap value of @a and @b
 444  */
 445 #define swap(a, b) \
 446         do { __typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
 447
 448 #define foreach_bit(b, mask) \
 449         for (uint32_t _m = (mask); _m && ({(b) = u_bit_scan(&_m); 1;});)
 450
 451 #endif /* FREEDRENO_UTIL_H_ */