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[mesa.git] / src / gallium / drivers / freedreno / freedreno_util.h
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #ifndef FREEDRENO_UTIL_H_
30 #define FREEDRENO_UTIL_H_
31
32 #include <freedreno_drmif.h>
33 #include <freedreno_ringbuffer.h>
34
35 #include "pipe/p_format.h"
36 #include "pipe/p_state.h"
37 #include "util/u_debug.h"
38 #include "util/u_math.h"
39 #include "util/u_half.h"
40 #include "util/u_dynarray.h"
41 #include "util/u_pack_color.h"
42
43 #include "disasm.h"
44 #include "adreno_common.xml.h"
45 #include "adreno_pm4.xml.h"
46
47 enum adreno_rb_depth_format fd_pipe2depth(enum pipe_format format);
48 enum pc_di_index_size fd_pipe2index(enum pipe_format format);
49 enum pipe_format fd_gmem_restore_format(enum pipe_format format);
50 enum adreno_rb_blend_factor fd_blend_factor(unsigned factor);
51 enum adreno_pa_su_sc_draw fd_polygon_mode(unsigned mode);
52 enum adreno_stencil_op fd_stencil_op(unsigned op);
53
54 #define A3XX_MAX_MIP_LEVELS 14
55 /* TBD if it is same on a2xx, but for now: */
56 #define MAX_MIP_LEVELS A3XX_MAX_MIP_LEVELS
57
58 #define A2XX_MAX_RENDER_TARGETS 1
59 #define A3XX_MAX_RENDER_TARGETS 4
60 #define A4XX_MAX_RENDER_TARGETS 8
61 #define A5XX_MAX_RENDER_TARGETS 8
62
63 #define MAX_RENDER_TARGETS A5XX_MAX_RENDER_TARGETS
64
65 #define FD_DBG_MSGS 0x0001
66 #define FD_DBG_DISASM 0x0002
67 #define FD_DBG_DCLEAR 0x0004
68 #define FD_DBG_DDRAW 0x0008
69 #define FD_DBG_NOSCIS 0x0010
70 #define FD_DBG_DIRECT 0x0020
71 #define FD_DBG_NOBYPASS 0x0040
72 #define FD_DBG_FRAGHALF 0x0080
73 #define FD_DBG_NOBIN 0x0100
74 #define FD_DBG_OPTMSGS 0x0200
75 #define FD_DBG_GLSL120 0x0400
76 #define FD_DBG_SHADERDB 0x0800
77 #define FD_DBG_FLUSH 0x1000
78 #define FD_DBG_DEQP 0x2000
79 #define FD_DBG_INORDER 0x4000
80 #define FD_DBG_BSTAT 0x8000
81 #define FD_DBG_NOGROW 0x10000
82 #define FD_DBG_LRZ 0x20000
83 #define FD_DBG_NOINDR 0x40000
84 #define FD_DBG_NOBLIT 0x80000
85 #define FD_DBG_HIPRIO 0x100000
86 #define FD_DBG_TTILE 0x200000
87
88 extern int fd_mesa_debug;
89 extern bool fd_binning_enabled;
90
91 #define DBG(fmt, ...) \
92 do { if (fd_mesa_debug & FD_DBG_MSGS) \
93 debug_printf("%s:%d: "fmt "\n", \
94 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
95
96 /* for conditionally setting boolean flag(s): */
97 #define COND(bool, val) ((bool) ? (val) : 0)
98
99 #define CP_REG(reg) ((0x4 << 16) | ((unsigned int)((reg) - (0x2000))))
100
101 static inline uint32_t DRAW(enum pc_di_primtype prim_type,
102 enum pc_di_src_sel source_select, enum pc_di_index_size index_size,
103 enum pc_di_vis_cull_mode vis_cull_mode,
104 uint8_t instances)
105 {
106 return (prim_type << 0) |
107 (source_select << 6) |
108 ((index_size & 1) << 11) |
109 ((index_size >> 1) << 13) |
110 (vis_cull_mode << 9) |
111 (1 << 14) |
112 (instances << 24);
113 }
114
115 static inline uint32_t DRAW_A20X(enum pc_di_primtype prim_type,
116 enum pc_di_src_sel source_select, enum pc_di_index_size index_size,
117 enum pc_di_vis_cull_mode vis_cull_mode,
118 uint16_t count)
119 {
120 return (prim_type << 0) |
121 (source_select << 6) |
122 ((index_size & 1) << 11) |
123 ((index_size >> 1) << 13) |
124 (vis_cull_mode << 9) |
125 (count << 16);
126 }
127
128 /* for tracking cmdstream positions that need to be patched: */
129 struct fd_cs_patch {
130 uint32_t *cs;
131 uint32_t val;
132 };
133 #define fd_patch_num_elements(buf) ((buf)->size / sizeof(struct fd_cs_patch))
134 #define fd_patch_element(buf, i) util_dynarray_element(buf, struct fd_cs_patch, i)
135
136 static inline enum pipe_format
137 pipe_surface_format(struct pipe_surface *psurf)
138 {
139 if (!psurf)
140 return PIPE_FORMAT_NONE;
141 return psurf->format;
142 }
143
144 static inline bool
145 fd_surface_half_precision(const struct pipe_surface *psurf)
146 {
147 enum pipe_format format;
148
149 if (!psurf)
150 return true;
151
152 format = psurf->format;
153
154 /* colors are provided in consts, which go through cov.f32f16, which will
155 * break these values
156 */
157 if (util_format_is_pure_integer(format))
158 return false;
159
160 /* avoid losing precision on 32-bit float formats */
161 if (util_format_is_float(format) &&
162 util_format_get_component_bits(format, UTIL_FORMAT_COLORSPACE_RGB, 0) == 32)
163 return false;
164
165 return true;
166 }
167
168 static inline unsigned
169 fd_sampler_first_level(const struct pipe_sampler_view *view)
170 {
171 if (view->target == PIPE_BUFFER)
172 return 0;
173 return view->u.tex.first_level;
174 }
175
176 static inline unsigned
177 fd_sampler_last_level(const struct pipe_sampler_view *view)
178 {
179 if (view->target == PIPE_BUFFER)
180 return 0;
181 return view->u.tex.last_level;
182 }
183
184 static inline bool
185 fd_half_precision(struct pipe_framebuffer_state *pfb)
186 {
187 unsigned i;
188
189 for (i = 0; i < pfb->nr_cbufs; i++)
190 if (!fd_surface_half_precision(pfb->cbufs[i]))
191 return false;
192
193 return true;
194 }
195
196 #define LOG_DWORDS 0
197
198 static inline void emit_marker(struct fd_ringbuffer *ring, int scratch_idx);
199
200 static inline void
201 OUT_RING(struct fd_ringbuffer *ring, uint32_t data)
202 {
203 if (LOG_DWORDS) {
204 DBG("ring[%p]: OUT_RING %04x: %08x", ring,
205 (uint32_t)(ring->cur - ring->last_start), data);
206 }
207 fd_ringbuffer_emit(ring, data);
208 }
209
210 /* like OUT_RING() but appends a cmdstream patch point to 'buf' */
211 static inline void
212 OUT_RINGP(struct fd_ringbuffer *ring, uint32_t data,
213 struct util_dynarray *buf)
214 {
215 if (LOG_DWORDS) {
216 DBG("ring[%p]: OUT_RINGP %04x: %08x", ring,
217 (uint32_t)(ring->cur - ring->last_start), data);
218 }
219 util_dynarray_append(buf, struct fd_cs_patch, ((struct fd_cs_patch){
220 .cs = ring->cur++,
221 .val = data,
222 }));
223 }
224
225 /*
226 * NOTE: OUT_RELOC*() is 2 dwords (64b) on a5xx+
227 */
228
229 static inline void
230 OUT_RELOC(struct fd_ringbuffer *ring, struct fd_bo *bo,
231 uint32_t offset, uint64_t or, int32_t shift)
232 {
233 if (LOG_DWORDS) {
234 DBG("ring[%p]: OUT_RELOC %04x: %p+%u << %d", ring,
235 (uint32_t)(ring->cur - ring->last_start), bo, offset, shift);
236 }
237 debug_assert(offset < fd_bo_size(bo));
238 fd_ringbuffer_reloc2(ring, &(struct fd_reloc){
239 .bo = bo,
240 .flags = FD_RELOC_READ,
241 .offset = offset,
242 .or = or,
243 .shift = shift,
244 .orhi = or >> 32,
245 });
246 }
247
248 static inline void
249 OUT_RELOCW(struct fd_ringbuffer *ring, struct fd_bo *bo,
250 uint32_t offset, uint64_t or, int32_t shift)
251 {
252 if (LOG_DWORDS) {
253 DBG("ring[%p]: OUT_RELOCW %04x: %p+%u << %d", ring,
254 (uint32_t)(ring->cur - ring->last_start), bo, offset, shift);
255 }
256 debug_assert(offset < fd_bo_size(bo));
257 fd_ringbuffer_reloc2(ring, &(struct fd_reloc){
258 .bo = bo,
259 .flags = FD_RELOC_READ | FD_RELOC_WRITE,
260 .offset = offset,
261 .or = or,
262 .shift = shift,
263 .orhi = or >> 32,
264 });
265 }
266
267 static inline void BEGIN_RING(struct fd_ringbuffer *ring, uint32_t ndwords)
268 {
269 if (ring->cur + ndwords >= ring->end)
270 fd_ringbuffer_grow(ring, ndwords);
271 }
272
273 static inline uint32_t
274 __gpu_id(struct fd_ringbuffer *ring)
275 {
276 uint64_t val;
277 fd_pipe_get_param(ring->pipe, FD_GPU_ID, &val);
278 return val;
279 }
280
281 static inline void
282 OUT_PKT0(struct fd_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
283 {
284 debug_assert(__gpu_id(ring) < 500);
285 BEGIN_RING(ring, cnt+1);
286 OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
287 }
288
289 static inline void
290 OUT_PKT2(struct fd_ringbuffer *ring)
291 {
292 debug_assert(__gpu_id(ring) < 500);
293 BEGIN_RING(ring, 1);
294 OUT_RING(ring, CP_TYPE2_PKT);
295 }
296
297 static inline void
298 OUT_PKT3(struct fd_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
299 {
300 debug_assert(__gpu_id(ring) < 500);
301 BEGIN_RING(ring, cnt+1);
302 OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
303 }
304
305 /*
306 * Starting with a5xx, pkt4/pkt7 are used instead of pkt0/pkt3
307 */
308
309 static inline unsigned
310 _odd_parity_bit(unsigned val)
311 {
312 /* See: http://graphics.stanford.edu/~seander/bithacks.html#ParityParallel
313 * note that we want odd parity so 0x6996 is inverted.
314 */
315 val ^= val >> 16;
316 val ^= val >> 8;
317 val ^= val >> 4;
318 val &= 0xf;
319 return (~0x6996 >> val) & 1;
320 }
321
322 static inline void
323 OUT_PKT4(struct fd_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
324 {
325 BEGIN_RING(ring, cnt+1);
326 OUT_RING(ring, CP_TYPE4_PKT | cnt |
327 (_odd_parity_bit(cnt) << 7) |
328 ((regindx & 0x3ffff) << 8) |
329 ((_odd_parity_bit(regindx) << 27)));
330 }
331
332 static inline void
333 OUT_PKT7(struct fd_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
334 {
335 BEGIN_RING(ring, cnt+1);
336 OUT_RING(ring, CP_TYPE7_PKT | cnt |
337 (_odd_parity_bit(cnt) << 15) |
338 ((opcode & 0x7f) << 16) |
339 ((_odd_parity_bit(opcode) << 23)));
340 }
341
342 static inline void
343 OUT_WFI(struct fd_ringbuffer *ring)
344 {
345 OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
346 OUT_RING(ring, 0x00000000);
347 }
348
349 static inline void
350 OUT_WFI5(struct fd_ringbuffer *ring)
351 {
352 OUT_PKT7(ring, CP_WAIT_FOR_IDLE, 0);
353 }
354
355 static inline void
356 __OUT_IB(struct fd_ringbuffer *ring, bool prefetch, struct fd_ringbuffer *target)
357 {
358 unsigned count = fd_ringbuffer_cmd_count(target);
359
360 debug_assert(__gpu_id(ring) < 500);
361
362 /* for debug after a lock up, write a unique counter value
363 * to scratch6 for each IB, to make it easier to match up
364 * register dumps to cmdstream. The combination of IB and
365 * DRAW (scratch7) is enough to "triangulate" the particular
366 * draw that caused lockup.
367 */
368 emit_marker(ring, 6);
369
370 for (unsigned i = 0; i < count; i++) {
371 uint32_t dwords;
372 OUT_PKT3(ring, prefetch ? CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2);
373 dwords = fd_ringbuffer_emit_reloc_ring_full(ring, target, i) / 4;
374 assert(dwords > 0);
375 OUT_RING(ring, dwords);
376 OUT_PKT2(ring);
377 }
378
379 emit_marker(ring, 6);
380 }
381
382 static inline void
383 __OUT_IB5(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
384 {
385 unsigned count = fd_ringbuffer_cmd_count(target);
386
387 for (unsigned i = 0; i < count; i++) {
388 uint32_t dwords;
389 OUT_PKT7(ring, CP_INDIRECT_BUFFER, 3);
390 dwords = fd_ringbuffer_emit_reloc_ring_full(ring, target, i) / 4;
391 assert(dwords > 0);
392 OUT_RING(ring, dwords);
393 }
394 }
395
396 /* CP_SCRATCH_REG4 is used to hold base address for query results: */
397 // XXX annoyingly scratch regs move on a5xx.. and additionally different
398 // packet types.. so freedreno_query_hw is going to need a bit of
399 // rework..
400 #define HW_QUERY_BASE_REG REG_AXXX_CP_SCRATCH_REG4
401
402 static inline void
403 emit_marker(struct fd_ringbuffer *ring, int scratch_idx)
404 {
405 extern unsigned marker_cnt;
406 unsigned reg = REG_AXXX_CP_SCRATCH_REG0 + scratch_idx;
407 assert(reg != HW_QUERY_BASE_REG);
408 if (reg == HW_QUERY_BASE_REG)
409 return;
410 OUT_PKT0(ring, reg, 1);
411 OUT_RING(ring, ++marker_cnt);
412 }
413
414 /* helper to get numeric value from environment variable.. mostly
415 * just leaving this here because it is helpful to brute-force figure
416 * out unknown formats, etc, which blob driver does not support:
417 */
418 static inline uint32_t env2u(const char *envvar)
419 {
420 char *str = getenv(envvar);
421 if (str)
422 return strtoul(str, NULL, 0);
423 return 0;
424 }
425
426 static inline uint32_t
427 pack_rgba(enum pipe_format format, const float *rgba)
428 {
429 union util_color uc;
430 util_pack_color(rgba, format, &uc);
431 return uc.ui[0];
432 }
433
434 /*
435 * swap - swap value of @a and @b
436 */
437 #define swap(a, b) \
438 do { __typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
439
440 #define foreach_bit(b, mask) \
441 for (uint32_t _m = (mask); _m && ({(b) = u_bit_scan(&_m); 1;});)
442
443
444 #define BIT(bit) (1u << bit)
445
446 /*
447 * a3xx+ helpers:
448 */
449
450 static inline enum a3xx_msaa_samples
451 fd_msaa_samples(unsigned samples)
452 {
453 switch (samples) {
454 default:
455 debug_assert(0);
456 case 1: return MSAA_ONE;
457 case 2: return MSAA_TWO;
458 case 4: return MSAA_FOUR;
459 }
460 }
461
462 /*
463 * a4xx+ helpers:
464 */
465
466 static inline enum a4xx_state_block
467 fd4_stage2shadersb(enum shader_t type)
468 {
469 switch (type) {
470 case SHADER_VERTEX:
471 return SB4_VS_SHADER;
472 case SHADER_FRAGMENT:
473 return SB4_FS_SHADER;
474 case SHADER_COMPUTE:
475 return SB4_CS_SHADER;
476 default:
477 unreachable("bad shader type");
478 return ~0;
479 }
480 }
481
482 #endif /* FREEDRENO_UTIL_H_ */