src/gallium/drivers/freedreno/freedreno_util.h

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #ifndef FREEDRENO_UTIL_H_
  30 #define FREEDRENO_UTIL_H_
  31
  32 #include <freedreno_drmif.h>
  33 #include <freedreno_ringbuffer.h>
  34
  35 #include "pipe/p_format.h"
  36 #include "pipe/p_state.h"
  37 #include "util/u_debug.h"
  38 #include "util/u_math.h"
  39 #include "util/u_half.h"
  40 #include "util/u_dynarray.h"
  41 #include "util/u_pack_color.h"
  42
  43 #include "disasm.h"
  44 #include "adreno_common.xml.h"
  45 #include "adreno_pm4.xml.h"
  46
  47 enum adreno_rb_depth_format fd_pipe2depth(enum pipe_format format);
  48 enum pc_di_index_size fd_pipe2index(enum pipe_format format);
  49 enum pipe_format fd_gmem_restore_format(enum pipe_format format);
  50 enum adreno_rb_blend_factor fd_blend_factor(unsigned factor);
  51 enum adreno_pa_su_sc_draw fd_polygon_mode(unsigned mode);
  52 enum adreno_stencil_op fd_stencil_op(unsigned op);
  53
  54 #define A3XX_MAX_MIP_LEVELS 14
  55 /* TBD if it is same on a2xx, but for now: */
  56 #define MAX_MIP_LEVELS A3XX_MAX_MIP_LEVELS
  57
  58 #define A2XX_MAX_RENDER_TARGETS 1
  59 #define A3XX_MAX_RENDER_TARGETS 4
  60 #define A4XX_MAX_RENDER_TARGETS 8
  61 #define A5XX_MAX_RENDER_TARGETS 8
  62
  63 #define MAX_RENDER_TARGETS A5XX_MAX_RENDER_TARGETS
  64
  65 #define FD_DBG_MSGS     0x0001
  66 #define FD_DBG_DISASM   0x0002
  67 #define FD_DBG_DCLEAR   0x0004
  68 #define FD_DBG_DDRAW    0x0008
  69 #define FD_DBG_NOSCIS   0x0010
  70 #define FD_DBG_DIRECT   0x0020
  71 #define FD_DBG_NOBYPASS 0x0040
  72 #define FD_DBG_FRAGHALF 0x0080
  73 #define FD_DBG_NOBIN    0x0100
  74 #define FD_DBG_OPTMSGS  0x0200
  75 #define FD_DBG_GLSL120  0x0400
  76 #define FD_DBG_SHADERDB 0x0800
  77 #define FD_DBG_FLUSH    0x1000
  78 #define FD_DBG_DEQP     0x2000
  79 #define FD_DBG_INORDER  0x4000
  80 #define FD_DBG_BSTAT    0x8000
  81 #define FD_DBG_NOGROW  0x10000
  82 #define FD_DBG_LRZ     0x20000
  83 #define FD_DBG_NOINDR  0x40000
  84 #define FD_DBG_NOBLIT  0x80000
  85 #define FD_DBG_HIPRIO 0x100000
  86 #define FD_DBG_TTILE  0x200000
  87
  88 extern int fd_mesa_debug;
  89 extern bool fd_binning_enabled;
  90
  91 #define DBG(fmt, ...) \
  92                 do { if (fd_mesa_debug & FD_DBG_MSGS) \
  93                         debug_printf("%s:%d: "fmt "\n", \
  94                                 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
  95
  96 /* for conditionally setting boolean flag(s): */
  97 #define COND(bool, val) ((bool) ? (val) : 0)
  98
  99 #define CP_REG(reg) ((0x4 << 16) | ((unsigned int)((reg) - (0x2000))))
 100
 101 static inline uint32_t DRAW(enum pc_di_primtype prim_type,
 102                 enum pc_di_src_sel source_select, enum pc_di_index_size index_size,
 103                 enum pc_di_vis_cull_mode vis_cull_mode,
 104                 uint8_t instances)
 105 {
 106         return (prim_type         << 0) |
 107                         (source_select     << 6) |
 108                         ((index_size & 1)  << 11) |
 109                         ((index_size >> 1) << 13) |
 110                         (vis_cull_mode     << 9) |
 111                         (1                 << 14) |
 112                         (instances         << 24);
 113 }
 114
 115 /* for tracking cmdstream positions that need to be patched: */
 116 struct fd_cs_patch {
 117         uint32_t *cs;
 118         uint32_t val;
 119 };
 120 #define fd_patch_num_elements(buf) ((buf)->size / sizeof(struct fd_cs_patch))
 121 #define fd_patch_element(buf, i)   util_dynarray_element(buf, struct fd_cs_patch, i)
 122
 123 static inline enum pipe_format
 124 pipe_surface_format(struct pipe_surface *psurf)
 125 {
 126         if (!psurf)
 127                 return PIPE_FORMAT_NONE;
 128         return psurf->format;
 129 }
 130
 131 static inline bool
 132 fd_surface_half_precision(const struct pipe_surface *psurf)
 133 {
 134         enum pipe_format format;
 135
 136         if (!psurf)
 137                 return true;
 138
 139         format = psurf->format;
 140
 141         /* colors are provided in consts, which go through cov.f32f16, which will
 142          * break these values
 143          */
 144         if (util_format_is_pure_integer(format))
 145                 return false;
 146
 147         /* avoid losing precision on 32-bit float formats */
 148         if (util_format_is_float(format) &&
 149                 util_format_get_component_bits(format, UTIL_FORMAT_COLORSPACE_RGB, 0) == 32)
 150                 return false;
 151
 152         return true;
 153 }
 154
 155 static inline unsigned
 156 fd_sampler_first_level(const struct pipe_sampler_view *view)
 157 {
 158         if (view->target == PIPE_BUFFER)
 159                 return 0;
 160         return view->u.tex.first_level;
 161 }
 162
 163 static inline unsigned
 164 fd_sampler_last_level(const struct pipe_sampler_view *view)
 165 {
 166         if (view->target == PIPE_BUFFER)
 167                 return 0;
 168         return view->u.tex.last_level;
 169 }
 170
 171 static inline bool
 172 fd_half_precision(struct pipe_framebuffer_state *pfb)
 173 {
 174         unsigned i;
 175
 176         for (i = 0; i < pfb->nr_cbufs; i++)
 177                 if (!fd_surface_half_precision(pfb->cbufs[i]))
 178                         return false;
 179
 180         return true;
 181 }
 182
 183 #define LOG_DWORDS 0
 184
 185 static inline void emit_marker(struct fd_ringbuffer *ring, int scratch_idx);
 186
 187 static inline void
 188 OUT_RING(struct fd_ringbuffer *ring, uint32_t data)
 189 {
 190         if (LOG_DWORDS) {
 191                 DBG("ring[%p]: OUT_RING   %04x:  %08x", ring,
 192                                 (uint32_t)(ring->cur - ring->last_start), data);
 193         }
 194         fd_ringbuffer_emit(ring, data);
 195 }
 196
 197 /* like OUT_RING() but appends a cmdstream patch point to 'buf' */
 198 static inline void
 199 OUT_RINGP(struct fd_ringbuffer *ring, uint32_t data,
 200                 struct util_dynarray *buf)
 201 {
 202         if (LOG_DWORDS) {
 203                 DBG("ring[%p]: OUT_RINGP  %04x:  %08x", ring,
 204                                 (uint32_t)(ring->cur - ring->last_start), data);
 205         }
 206         util_dynarray_append(buf, struct fd_cs_patch, ((struct fd_cs_patch){
 207                 .cs  = ring->cur++,
 208                 .val = data,
 209         }));
 210 }
 211
 212 /*
 213  * NOTE: OUT_RELOC*() is 2 dwords (64b) on a5xx+
 214  */
 215
 216 static inline void
 217 OUT_RELOC(struct fd_ringbuffer *ring, struct fd_bo *bo,
 218                 uint32_t offset, uint64_t or, int32_t shift)
 219 {
 220         if (LOG_DWORDS) {
 221                 DBG("ring[%p]: OUT_RELOC   %04x:  %p+%u << %d", ring,
 222                                 (uint32_t)(ring->cur - ring->last_start), bo, offset, shift);
 223         }
 224         debug_assert(offset < fd_bo_size(bo));
 225         fd_ringbuffer_reloc2(ring, &(struct fd_reloc){
 226                 .bo = bo,
 227                 .flags = FD_RELOC_READ,
 228                 .offset = offset,
 229                 .or = or,
 230                 .shift = shift,
 231                 .orhi = or >> 32,
 232         });
 233 }
 234
 235 static inline void
 236 OUT_RELOCW(struct fd_ringbuffer *ring, struct fd_bo *bo,
 237                 uint32_t offset, uint64_t or, int32_t shift)
 238 {
 239         if (LOG_DWORDS) {
 240                 DBG("ring[%p]: OUT_RELOCW  %04x:  %p+%u << %d", ring,
 241                                 (uint32_t)(ring->cur - ring->last_start), bo, offset, shift);
 242         }
 243         debug_assert(offset < fd_bo_size(bo));
 244         fd_ringbuffer_reloc2(ring, &(struct fd_reloc){
 245                 .bo = bo,
 246                 .flags = FD_RELOC_READ | FD_RELOC_WRITE,
 247                 .offset = offset,
 248                 .or = or,
 249                 .shift = shift,
 250                 .orhi = or >> 32,
 251         });
 252 }
 253
 254 static inline void BEGIN_RING(struct fd_ringbuffer *ring, uint32_t ndwords)
 255 {
 256         if (ring->cur + ndwords >= ring->end)
 257                 fd_ringbuffer_grow(ring, ndwords);
 258 }
 259
 260 static inline uint32_t
 261 __gpu_id(struct fd_ringbuffer *ring)
 262 {
 263         uint64_t val;
 264         fd_pipe_get_param(ring->pipe, FD_GPU_ID, &val);
 265         return val;
 266 }
 267
 268 static inline void
 269 OUT_PKT0(struct fd_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
 270 {
 271         debug_assert(__gpu_id(ring) < 500);
 272         BEGIN_RING(ring, cnt+1);
 273         OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
 274 }
 275
 276 static inline void
 277 OUT_PKT2(struct fd_ringbuffer *ring)
 278 {
 279         debug_assert(__gpu_id(ring) < 500);
 280         BEGIN_RING(ring, 1);
 281         OUT_RING(ring, CP_TYPE2_PKT);
 282 }
 283
 284 static inline void
 285 OUT_PKT3(struct fd_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
 286 {
 287         debug_assert(__gpu_id(ring) < 500);
 288         BEGIN_RING(ring, cnt+1);
 289         OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
 290 }
 291
 292 /*
 293  * Starting with a5xx, pkt4/pkt7 are used instead of pkt0/pkt3
 294  */
 295
 296 static inline unsigned
 297 _odd_parity_bit(unsigned val)
 298 {
 299         /* See: http://graphics.stanford.edu/~seander/bithacks.html#ParityParallel
 300          * note that we want odd parity so 0x6996 is inverted.
 301          */
 302         val ^= val >> 16;
 303         val ^= val >> 8;
 304         val ^= val >> 4;
 305         val &= 0xf;
 306         return (~0x6996 >> val) & 1;
 307 }
 308
 309 static inline void
 310 OUT_PKT4(struct fd_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
 311 {
 312         BEGIN_RING(ring, cnt+1);
 313         OUT_RING(ring, CP_TYPE4_PKT | cnt |
 314                         (_odd_parity_bit(cnt) << 7) |
 315                         ((regindx & 0x3ffff) << 8) |
 316                         ((_odd_parity_bit(regindx) << 27)));
 317 }
 318
 319 static inline void
 320 OUT_PKT7(struct fd_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
 321 {
 322         BEGIN_RING(ring, cnt+1);
 323         OUT_RING(ring, CP_TYPE7_PKT | cnt |
 324                         (_odd_parity_bit(cnt) << 15) |
 325                         ((opcode & 0x7f) << 16) |
 326                         ((_odd_parity_bit(opcode) << 23)));
 327 }
 328
 329 static inline void
 330 OUT_WFI(struct fd_ringbuffer *ring)
 331 {
 332         OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
 333         OUT_RING(ring, 0x00000000);
 334 }
 335
 336 static inline void
 337 OUT_WFI5(struct fd_ringbuffer *ring)
 338 {
 339         OUT_PKT7(ring, CP_WAIT_FOR_IDLE, 0);
 340 }
 341
 342 static inline void
 343 __OUT_IB(struct fd_ringbuffer *ring, bool prefetch, struct fd_ringbuffer *target)
 344 {
 345         unsigned count = fd_ringbuffer_cmd_count(target);
 346
 347         debug_assert(__gpu_id(ring) < 500);
 348
 349         /* for debug after a lock up, write a unique counter value
 350          * to scratch6 for each IB, to make it easier to match up
 351          * register dumps to cmdstream.  The combination of IB and
 352          * DRAW (scratch7) is enough to "triangulate" the particular
 353          * draw that caused lockup.
 354          */
 355         emit_marker(ring, 6);
 356
 357         for (unsigned i = 0; i < count; i++) {
 358                 uint32_t dwords;
 359                 OUT_PKT3(ring, prefetch ? CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2);
 360                 dwords = fd_ringbuffer_emit_reloc_ring_full(ring, target, i) / 4;
 361                 assert(dwords > 0);
 362                 OUT_RING(ring, dwords);
 363                 OUT_PKT2(ring);
 364         }
 365
 366         emit_marker(ring, 6);
 367 }
 368
 369 static inline void
 370 __OUT_IB5(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
 371 {
 372         unsigned count = fd_ringbuffer_cmd_count(target);
 373
 374         for (unsigned i = 0; i < count; i++) {
 375                 uint32_t dwords;
 376                 OUT_PKT7(ring, CP_INDIRECT_BUFFER, 3);
 377                 dwords = fd_ringbuffer_emit_reloc_ring_full(ring, target, i) / 4;
 378                 assert(dwords > 0);
 379                 OUT_RING(ring, dwords);
 380         }
 381 }
 382
 383 /* CP_SCRATCH_REG4 is used to hold base address for query results: */
 384 // XXX annoyingly scratch regs move on a5xx.. and additionally different
 385 // packet types.. so freedreno_query_hw is going to need a bit of
 386 // rework..
 387 #define HW_QUERY_BASE_REG REG_AXXX_CP_SCRATCH_REG4
 388
 389 static inline void
 390 emit_marker(struct fd_ringbuffer *ring, int scratch_idx)
 391 {
 392         extern unsigned marker_cnt;
 393         unsigned reg = REG_AXXX_CP_SCRATCH_REG0 + scratch_idx;
 394         assert(reg != HW_QUERY_BASE_REG);
 395         if (reg == HW_QUERY_BASE_REG)
 396                 return;
 397         OUT_PKT0(ring, reg, 1);
 398         OUT_RING(ring, ++marker_cnt);
 399 }
 400
 401 /* helper to get numeric value from environment variable..  mostly
 402  * just leaving this here because it is helpful to brute-force figure
 403  * out unknown formats, etc, which blob driver does not support:
 404  */
 405 static inline uint32_t env2u(const char *envvar)
 406 {
 407         char *str = getenv(envvar);
 408         if (str)
 409                 return strtoul(str, NULL, 0);
 410         return 0;
 411 }
 412
 413 static inline uint32_t
 414 pack_rgba(enum pipe_format format, const float *rgba)
 415 {
 416         union util_color uc;
 417         util_pack_color(rgba, format, &uc);
 418         return uc.ui[0];
 419 }
 420
 421 /*
 422  * swap - swap value of @a and @b
 423  */
 424 #define swap(a, b) \
 425         do { __typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
 426
 427 #define foreach_bit(b, mask) \
 428         for (uint32_t _m = (mask); _m && ({(b) = u_bit_scan(&_m); 1;});)
 429
 430
 431 #define BIT(bit) (1u << bit)
 432
 433 /*
 434  * a4xx+ helpers:
 435  */
 436
 437 static inline enum a4xx_state_block
 438 fd4_stage2shadersb(enum shader_t type)
 439 {
 440         switch (type) {
 441         case SHADER_VERTEX:
 442                 return SB4_VS_SHADER;
 443         case SHADER_FRAGMENT:
 444                 return SB4_FS_SHADER;
 445         case SHADER_COMPUTE:
 446                 return SB4_CS_SHADER;
 447         default:
 448                 unreachable("bad shader type");
 449                 return ~0;
 450         }
 451 }
 452
 453 #endif /* FREEDRENO_UTIL_H_ */