src/gallium/drivers/freedreno/freedreno_util.h

   1 /*
   2  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #ifndef FREEDRENO_UTIL_H_
  28 #define FREEDRENO_UTIL_H_
  29
  30 #include "drm/freedreno_drmif.h"
  31 #include "drm/freedreno_ringbuffer.h"
  32
  33 #include "pipe/p_format.h"
  34 #include "pipe/p_state.h"
  35 #include "util/u_debug.h"
  36 #include "util/u_math.h"
  37 #include "util/u_half.h"
  38 #include "util/u_dynarray.h"
  39 #include "util/u_pack_color.h"
  40
  41 #include "disasm.h"
  42 #include "adreno_common.xml.h"
  43 #include "adreno_pm4.xml.h"
  44
  45 enum adreno_rb_depth_format fd_pipe2depth(enum pipe_format format);
  46 enum pc_di_index_size fd_pipe2index(enum pipe_format format);
  47 enum pipe_format fd_gmem_restore_format(enum pipe_format format);
  48 enum adreno_rb_blend_factor fd_blend_factor(unsigned factor);
  49 enum adreno_pa_su_sc_draw fd_polygon_mode(unsigned mode);
  50 enum adreno_stencil_op fd_stencil_op(unsigned op);
  51
  52 #define A3XX_MAX_MIP_LEVELS 14
  53 /* TBD if it is same on a2xx, but for now: */
  54 #define MAX_MIP_LEVELS A3XX_MAX_MIP_LEVELS
  55
  56 #define A2XX_MAX_RENDER_TARGETS 1
  57 #define A3XX_MAX_RENDER_TARGETS 4
  58 #define A4XX_MAX_RENDER_TARGETS 8
  59 #define A5XX_MAX_RENDER_TARGETS 8
  60 #define A6XX_MAX_RENDER_TARGETS 8
  61
  62 #define MAX_RENDER_TARGETS A6XX_MAX_RENDER_TARGETS
  63
  64 #define FD_DBG_MSGS     0x0001
  65 #define FD_DBG_DISASM   0x0002
  66 #define FD_DBG_DCLEAR   0x0004
  67 #define FD_DBG_DDRAW    0x0008
  68 #define FD_DBG_NOSCIS   0x0010
  69 #define FD_DBG_DIRECT   0x0020
  70 #define FD_DBG_NOBYPASS 0x0040
  71 #define FD_DBG_FRAGHALF 0x0080
  72 #define FD_DBG_NOBIN    0x0100
  73 /* unused 0x0200 */
  74 #define FD_DBG_GLSL120  0x0400
  75 #define FD_DBG_SHADERDB 0x0800
  76 #define FD_DBG_FLUSH    0x1000
  77 #define FD_DBG_DEQP     0x2000
  78 #define FD_DBG_INORDER  0x4000
  79 #define FD_DBG_BSTAT    0x8000
  80 #define FD_DBG_NOGROW  0x10000
  81 #define FD_DBG_LRZ     0x20000
  82 #define FD_DBG_NOINDR  0x40000
  83 #define FD_DBG_NOBLIT  0x80000
  84 #define FD_DBG_HIPRIO 0x100000
  85 #define FD_DBG_TTILE  0x200000
  86 #define FD_DBG_PERFC  0x400000
  87 #define FD_DBG_SOFTPIN 0x800000
  88
  89 extern int fd_mesa_debug;
  90 extern bool fd_binning_enabled;
  91
  92 #define DBG(fmt, ...) \
  93                 do { if (fd_mesa_debug & FD_DBG_MSGS) \
  94                         debug_printf("%s:%d: "fmt "\n", \
  95                                 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
  96
  97 /* for conditionally setting boolean flag(s): */
  98 #define COND(bool, val) ((bool) ? (val) : 0)
  99
 100 #define CP_REG(reg) ((0x4 << 16) | ((unsigned int)((reg) - (0x2000))))
 101
 102 static inline uint32_t DRAW(enum pc_di_primtype prim_type,
 103                 enum pc_di_src_sel source_select, enum pc_di_index_size index_size,
 104                 enum pc_di_vis_cull_mode vis_cull_mode,
 105                 uint8_t instances)
 106 {
 107         return (prim_type         << 0) |
 108                         (source_select     << 6) |
 109                         ((index_size & 1)  << 11) |
 110                         ((index_size >> 1) << 13) |
 111                         (vis_cull_mode     << 9) |
 112                         (1                 << 14) |
 113                         (instances         << 24);
 114 }
 115
 116 static inline uint32_t DRAW_A20X(enum pc_di_primtype prim_type,
 117                 enum pc_di_face_cull_sel faceness_cull_select,
 118                 enum pc_di_src_sel source_select, enum pc_di_index_size index_size,
 119                 bool pre_fetch_cull_enable,
 120                 bool grp_cull_enable,
 121                 uint16_t count)
 122 {
 123         return (prim_type         << 0) |
 124                         (source_select     << 6) |
 125                         (faceness_cull_select << 8) |
 126                         ((index_size & 1)  << 11) |
 127                         ((index_size >> 1) << 13) |
 128                         (pre_fetch_cull_enable << 14) |
 129                         (grp_cull_enable << 15) |
 130                         (count         << 16);
 131 }
 132
 133 /* for tracking cmdstream positions that need to be patched: */
 134 struct fd_cs_patch {
 135         uint32_t *cs;
 136         uint32_t val;
 137 };
 138 #define fd_patch_num_elements(buf) ((buf)->size / sizeof(struct fd_cs_patch))
 139 #define fd_patch_element(buf, i)   util_dynarray_element(buf, struct fd_cs_patch, i)
 140
 141 static inline enum pipe_format
 142 pipe_surface_format(struct pipe_surface *psurf)
 143 {
 144         if (!psurf)
 145                 return PIPE_FORMAT_NONE;
 146         return psurf->format;
 147 }
 148
 149 static inline bool
 150 fd_surface_half_precision(const struct pipe_surface *psurf)
 151 {
 152         enum pipe_format format;
 153
 154         if (!psurf)
 155                 return true;
 156
 157         format = psurf->format;
 158
 159         /* colors are provided in consts, which go through cov.f32f16, which will
 160          * break these values
 161          */
 162         if (util_format_is_pure_integer(format))
 163                 return false;
 164
 165         /* avoid losing precision on 32-bit float formats */
 166         if (util_format_is_float(format) &&
 167                 util_format_get_component_bits(format, UTIL_FORMAT_COLORSPACE_RGB, 0) == 32)
 168                 return false;
 169
 170         return true;
 171 }
 172
 173 static inline unsigned
 174 fd_sampler_first_level(const struct pipe_sampler_view *view)
 175 {
 176         if (view->target == PIPE_BUFFER)
 177                 return 0;
 178         return view->u.tex.first_level;
 179 }
 180
 181 static inline unsigned
 182 fd_sampler_last_level(const struct pipe_sampler_view *view)
 183 {
 184         if (view->target == PIPE_BUFFER)
 185                 return 0;
 186         return view->u.tex.last_level;
 187 }
 188
 189 static inline bool
 190 fd_half_precision(struct pipe_framebuffer_state *pfb)
 191 {
 192         unsigned i;
 193
 194         for (i = 0; i < pfb->nr_cbufs; i++)
 195                 if (!fd_surface_half_precision(pfb->cbufs[i]))
 196                         return false;
 197
 198         return true;
 199 }
 200
 201 /* Note sure if this is same on all gens, but seems to be same on the later
 202  * gen's
 203  */
 204 static inline unsigned
 205 fd_calc_guardband(unsigned x)
 206 {
 207         float l = log2(x);
 208         if (l <= 8)
 209                 return 511;
 210         return 511 - ((l - 8) * 65);
 211 }
 212
 213 #define LOG_DWORDS 0
 214
 215 static inline void emit_marker(struct fd_ringbuffer *ring, int scratch_idx);
 216
 217 static inline void
 218 OUT_RING(struct fd_ringbuffer *ring, uint32_t data)
 219 {
 220         if (LOG_DWORDS) {
 221                 DBG("ring[%p]: OUT_RING   %04x:  %08x", ring,
 222                                 (uint32_t)(ring->cur - ring->start), data);
 223         }
 224         fd_ringbuffer_emit(ring, data);
 225 }
 226
 227 /* like OUT_RING() but appends a cmdstream patch point to 'buf' */
 228 static inline void
 229 OUT_RINGP(struct fd_ringbuffer *ring, uint32_t data,
 230                 struct util_dynarray *buf)
 231 {
 232         if (LOG_DWORDS) {
 233                 DBG("ring[%p]: OUT_RINGP  %04x:  %08x", ring,
 234                                 (uint32_t)(ring->cur - ring->start), data);
 235         }
 236         util_dynarray_append(buf, struct fd_cs_patch, ((struct fd_cs_patch){
 237                 .cs  = ring->cur++,
 238                 .val = data,
 239         }));
 240 }
 241
 242 /*
 243  * NOTE: OUT_RELOC*() is 2 dwords (64b) on a5xx+
 244  */
 245
 246 static inline void
 247 OUT_RELOC(struct fd_ringbuffer *ring, struct fd_bo *bo,
 248                 uint32_t offset, uint64_t or, int32_t shift)
 249 {
 250         if (LOG_DWORDS) {
 251                 DBG("ring[%p]: OUT_RELOC   %04x:  %p+%u << %d", ring,
 252                                 (uint32_t)(ring->cur - ring->start), bo, offset, shift);
 253         }
 254         debug_assert(offset < fd_bo_size(bo));
 255         fd_ringbuffer_reloc(ring, &(struct fd_reloc){
 256                 .bo = bo,
 257                 .flags = FD_RELOC_READ,
 258                 .offset = offset,
 259                 .or = or,
 260                 .shift = shift,
 261                 .orhi = or >> 32,
 262         });
 263 }
 264
 265 static inline void
 266 OUT_RELOCW(struct fd_ringbuffer *ring, struct fd_bo *bo,
 267                 uint32_t offset, uint64_t or, int32_t shift)
 268 {
 269         if (LOG_DWORDS) {
 270                 DBG("ring[%p]: OUT_RELOCW  %04x:  %p+%u << %d", ring,
 271                                 (uint32_t)(ring->cur - ring->start), bo, offset, shift);
 272         }
 273         debug_assert(offset < fd_bo_size(bo));
 274         fd_ringbuffer_reloc(ring, &(struct fd_reloc){
 275                 .bo = bo,
 276                 .flags = FD_RELOC_READ | FD_RELOC_WRITE,
 277                 .offset = offset,
 278                 .or = or,
 279                 .shift = shift,
 280                 .orhi = or >> 32,
 281         });
 282 }
 283
 284 static inline void
 285 OUT_RB(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
 286 {
 287         fd_ringbuffer_emit_reloc_ring_full(ring, target, 0);
 288 }
 289
 290 static inline void BEGIN_RING(struct fd_ringbuffer *ring, uint32_t ndwords)
 291 {
 292         if (ring->cur + ndwords > ring->end)
 293                 fd_ringbuffer_grow(ring, ndwords);
 294 }
 295
 296 static inline void
 297 OUT_PKT0(struct fd_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
 298 {
 299         BEGIN_RING(ring, cnt+1);
 300         OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
 301 }
 302
 303 static inline void
 304 OUT_PKT2(struct fd_ringbuffer *ring)
 305 {
 306         BEGIN_RING(ring, 1);
 307         OUT_RING(ring, CP_TYPE2_PKT);
 308 }
 309
 310 static inline void
 311 OUT_PKT3(struct fd_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
 312 {
 313         BEGIN_RING(ring, cnt+1);
 314         OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
 315 }
 316
 317 /*
 318  * Starting with a5xx, pkt4/pkt7 are used instead of pkt0/pkt3
 319  */
 320
 321 static inline unsigned
 322 _odd_parity_bit(unsigned val)
 323 {
 324         /* See: http://graphics.stanford.edu/~seander/bithacks.html#ParityParallel
 325          * note that we want odd parity so 0x6996 is inverted.
 326          */
 327         val ^= val >> 16;
 328         val ^= val >> 8;
 329         val ^= val >> 4;
 330         val &= 0xf;
 331         return (~0x6996 >> val) & 1;
 332 }
 333
 334 static inline void
 335 OUT_PKT4(struct fd_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
 336 {
 337         BEGIN_RING(ring, cnt+1);
 338         OUT_RING(ring, CP_TYPE4_PKT | cnt |
 339                         (_odd_parity_bit(cnt) << 7) |
 340                         ((regindx & 0x3ffff) << 8) |
 341                         ((_odd_parity_bit(regindx) << 27)));
 342 }
 343
 344 static inline void
 345 OUT_PKT7(struct fd_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
 346 {
 347         BEGIN_RING(ring, cnt+1);
 348         OUT_RING(ring, CP_TYPE7_PKT | cnt |
 349                         (_odd_parity_bit(cnt) << 15) |
 350                         ((opcode & 0x7f) << 16) |
 351                         ((_odd_parity_bit(opcode) << 23)));
 352 }
 353
 354 static inline void
 355 OUT_WFI(struct fd_ringbuffer *ring)
 356 {
 357         OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
 358         OUT_RING(ring, 0x00000000);
 359 }
 360
 361 static inline void
 362 OUT_WFI5(struct fd_ringbuffer *ring)
 363 {
 364         OUT_PKT7(ring, CP_WAIT_FOR_IDLE, 0);
 365 }
 366
 367 static inline void
 368 __OUT_IB(struct fd_ringbuffer *ring, bool prefetch, struct fd_ringbuffer *target)
 369 {
 370         if (target->cur == target->start)
 371                 return;
 372
 373         unsigned count = fd_ringbuffer_cmd_count(target);
 374
 375         /* for debug after a lock up, write a unique counter value
 376          * to scratch6 for each IB, to make it easier to match up
 377          * register dumps to cmdstream.  The combination of IB and
 378          * DRAW (scratch7) is enough to "triangulate" the particular
 379          * draw that caused lockup.
 380          */
 381         emit_marker(ring, 6);
 382
 383         for (unsigned i = 0; i < count; i++) {
 384                 uint32_t dwords;
 385                 OUT_PKT3(ring, prefetch ? CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2);
 386                 dwords = fd_ringbuffer_emit_reloc_ring_full(ring, target, i) / 4;
 387                 assert(dwords > 0);
 388                 OUT_RING(ring, dwords);
 389                 OUT_PKT2(ring);
 390         }
 391
 392         emit_marker(ring, 6);
 393 }
 394
 395 static inline void
 396 __OUT_IB5(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
 397 {
 398         if (target->cur == target->start)
 399                 return;
 400
 401         unsigned count = fd_ringbuffer_cmd_count(target);
 402
 403         for (unsigned i = 0; i < count; i++) {
 404                 uint32_t dwords;
 405                 OUT_PKT7(ring, CP_INDIRECT_BUFFER, 3);
 406                 dwords = fd_ringbuffer_emit_reloc_ring_full(ring, target, i) / 4;
 407                 assert(dwords > 0);
 408                 OUT_RING(ring, dwords);
 409         }
 410 }
 411
 412 /* CP_SCRATCH_REG4 is used to hold base address for query results: */
 413 // XXX annoyingly scratch regs move on a5xx.. and additionally different
 414 // packet types.. so freedreno_query_hw is going to need a bit of
 415 // rework..
 416 #define HW_QUERY_BASE_REG REG_AXXX_CP_SCRATCH_REG4
 417
 418 static inline void
 419 emit_marker(struct fd_ringbuffer *ring, int scratch_idx)
 420 {
 421         extern unsigned marker_cnt;
 422         unsigned reg = REG_AXXX_CP_SCRATCH_REG0 + scratch_idx;
 423         assert(reg != HW_QUERY_BASE_REG);
 424         if (reg == HW_QUERY_BASE_REG)
 425                 return;
 426         OUT_PKT0(ring, reg, 1);
 427         OUT_RING(ring, ++marker_cnt);
 428 }
 429
 430 static inline uint32_t
 431 pack_rgba(enum pipe_format format, const float *rgba)
 432 {
 433         union util_color uc;
 434         util_pack_color(rgba, format, &uc);
 435         return uc.ui[0];
 436 }
 437
 438 /*
 439  * swap - swap value of @a and @b
 440  */
 441 #define swap(a, b) \
 442         do { __typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
 443
 444 #define foreach_bit(b, mask) \
 445         for (uint32_t _m = (mask); _m && ({(b) = u_bit_scan(&_m); 1;});)
 446
 447
 448 #define BIT(bit) (1u << bit)
 449
 450 /*
 451  * a3xx+ helpers:
 452  */
 453
 454 static inline enum a3xx_msaa_samples
 455 fd_msaa_samples(unsigned samples)
 456 {
 457         switch (samples) {
 458         default:
 459                 debug_assert(0);
 460         case 0:
 461         case 1: return MSAA_ONE;
 462         case 2: return MSAA_TWO;
 463         case 4: return MSAA_FOUR;
 464         case 8: return MSAA_EIGHT;
 465         }
 466 }
 467
 468 /*
 469  * a4xx+ helpers:
 470  */
 471
 472 static inline enum a4xx_state_block
 473 fd4_stage2shadersb(gl_shader_stage type)
 474 {
 475         switch (type) {
 476         case MESA_SHADER_VERTEX:
 477                 return SB4_VS_SHADER;
 478         case MESA_SHADER_FRAGMENT:
 479                 return SB4_FS_SHADER;
 480         case MESA_SHADER_COMPUTE:
 481                 return SB4_CS_SHADER;
 482         default:
 483                 unreachable("bad shader type");
 484                 return ~0;
 485         }
 486 }
 487
 488 #endif /* FREEDRENO_UTIL_H_ */