src/gallium/drivers/freedreno/freedreno_util.h

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #ifndef FREEDRENO_UTIL_H_
  30 #define FREEDRENO_UTIL_H_
  31
  32 #include <freedreno_drmif.h>
  33 #include <freedreno_ringbuffer.h>
  34
  35 #include "pipe/p_format.h"
  36 #include "pipe/p_state.h"
  37 #include "util/u_debug.h"
  38 #include "util/u_math.h"
  39 #include "util/u_half.h"
  40 #include "util/u_dynarray.h"
  41 #include "util/u_pack_color.h"
  42
  43 #include "disasm.h"
  44 #include "adreno_common.xml.h"
  45 #include "adreno_pm4.xml.h"
  46
  47 enum adreno_rb_depth_format fd_pipe2depth(enum pipe_format format);
  48 enum pc_di_index_size fd_pipe2index(enum pipe_format format);
  49 enum pipe_format fd_gmem_restore_format(enum pipe_format format);
  50 enum adreno_rb_blend_factor fd_blend_factor(unsigned factor);
  51 enum adreno_pa_su_sc_draw fd_polygon_mode(unsigned mode);
  52 enum adreno_stencil_op fd_stencil_op(unsigned op);
  53
  54 #define A3XX_MAX_MIP_LEVELS 14
  55 /* TBD if it is same on a2xx, but for now: */
  56 #define MAX_MIP_LEVELS A3XX_MAX_MIP_LEVELS
  57
  58 #define A2XX_MAX_RENDER_TARGETS 1
  59 #define A3XX_MAX_RENDER_TARGETS 4
  60 #define A4XX_MAX_RENDER_TARGETS 8
  61 #define A5XX_MAX_RENDER_TARGETS 8
  62
  63 #define MAX_RENDER_TARGETS A5XX_MAX_RENDER_TARGETS
  64
  65 #define FD_DBG_MSGS     0x0001
  66 #define FD_DBG_DISASM   0x0002
  67 #define FD_DBG_DCLEAR   0x0004
  68 #define FD_DBG_DDRAW    0x0008
  69 #define FD_DBG_NOSCIS   0x0010
  70 #define FD_DBG_DIRECT   0x0020
  71 #define FD_DBG_NOBYPASS 0x0040
  72 #define FD_DBG_FRAGHALF 0x0080
  73 #define FD_DBG_NOBIN    0x0100
  74 #define FD_DBG_OPTMSGS  0x0200
  75 #define FD_DBG_GLSL120  0x0400
  76 #define FD_DBG_SHADERDB 0x0800
  77 #define FD_DBG_FLUSH    0x1000
  78 #define FD_DBG_DEQP     0x2000
  79 #define FD_DBG_INORDER  0x4000
  80 #define FD_DBG_BSTAT    0x8000
  81 #define FD_DBG_NOGROW  0x10000
  82 #define FD_DBG_LRZ     0x20000
  83 #define FD_DBG_NOINDR  0x40000
  84
  85 extern int fd_mesa_debug;
  86 extern bool fd_binning_enabled;
  87
  88 #define DBG(fmt, ...) \
  89                 do { if (fd_mesa_debug & FD_DBG_MSGS) \
  90                         debug_printf("%s:%d: "fmt "\n", \
  91                                 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
  92
  93 /* for conditionally setting boolean flag(s): */
  94 #define COND(bool, val) ((bool) ? (val) : 0)
  95
  96 #define CP_REG(reg) ((0x4 << 16) | ((unsigned int)((reg) - (0x2000))))
  97
  98 static inline uint32_t DRAW(enum pc_di_primtype prim_type,
  99                 enum pc_di_src_sel source_select, enum pc_di_index_size index_size,
 100                 enum pc_di_vis_cull_mode vis_cull_mode,
 101                 uint8_t instances)
 102 {
 103         return (prim_type         << 0) |
 104                         (source_select     << 6) |
 105                         ((index_size & 1)  << 11) |
 106                         ((index_size >> 1) << 13) |
 107                         (vis_cull_mode     << 9) |
 108                         (1                 << 14) |
 109                         (instances         << 24);
 110 }
 111
 112 /* for tracking cmdstream positions that need to be patched: */
 113 struct fd_cs_patch {
 114         uint32_t *cs;
 115         uint32_t val;
 116 };
 117 #define fd_patch_num_elements(buf) ((buf)->size / sizeof(struct fd_cs_patch))
 118 #define fd_patch_element(buf, i)   util_dynarray_element(buf, struct fd_cs_patch, i)
 119
 120 static inline enum pipe_format
 121 pipe_surface_format(struct pipe_surface *psurf)
 122 {
 123         if (!psurf)
 124                 return PIPE_FORMAT_NONE;
 125         return psurf->format;
 126 }
 127
 128 static inline bool
 129 fd_surface_half_precision(const struct pipe_surface *psurf)
 130 {
 131         enum pipe_format format;
 132
 133         if (!psurf)
 134                 return true;
 135
 136         format = psurf->format;
 137
 138         /* colors are provided in consts, which go through cov.f32f16, which will
 139          * break these values
 140          */
 141         if (util_format_is_pure_integer(format))
 142                 return false;
 143
 144         /* avoid losing precision on 32-bit float formats */
 145         if (util_format_is_float(format) &&
 146                 util_format_get_component_bits(format, UTIL_FORMAT_COLORSPACE_RGB, 0) == 32)
 147                 return false;
 148
 149         return true;
 150 }
 151
 152 static inline unsigned
 153 fd_sampler_first_level(const struct pipe_sampler_view *view)
 154 {
 155         if (view->target == PIPE_BUFFER)
 156                 return 0;
 157         return view->u.tex.first_level;
 158 }
 159
 160 static inline unsigned
 161 fd_sampler_last_level(const struct pipe_sampler_view *view)
 162 {
 163         if (view->target == PIPE_BUFFER)
 164                 return 0;
 165         return view->u.tex.last_level;
 166 }
 167
 168 static inline bool
 169 fd_half_precision(struct pipe_framebuffer_state *pfb)
 170 {
 171         unsigned i;
 172
 173         for (i = 0; i < pfb->nr_cbufs; i++)
 174                 if (!fd_surface_half_precision(pfb->cbufs[i]))
 175                         return false;
 176
 177         return true;
 178 }
 179
 180 #define LOG_DWORDS 0
 181
 182 static inline void emit_marker(struct fd_ringbuffer *ring, int scratch_idx);
 183 static inline void emit_marker5(struct fd_ringbuffer *ring, int scratch_idx);
 184
 185 static inline void
 186 OUT_RING(struct fd_ringbuffer *ring, uint32_t data)
 187 {
 188         if (LOG_DWORDS) {
 189                 DBG("ring[%p]: OUT_RING   %04x:  %08x", ring,
 190                                 (uint32_t)(ring->cur - ring->last_start), data);
 191         }
 192         fd_ringbuffer_emit(ring, data);
 193 }
 194
 195 /* like OUT_RING() but appends a cmdstream patch point to 'buf' */
 196 static inline void
 197 OUT_RINGP(struct fd_ringbuffer *ring, uint32_t data,
 198                 struct util_dynarray *buf)
 199 {
 200         if (LOG_DWORDS) {
 201                 DBG("ring[%p]: OUT_RINGP  %04x:  %08x", ring,
 202                                 (uint32_t)(ring->cur - ring->last_start), data);
 203         }
 204         util_dynarray_append(buf, struct fd_cs_patch, ((struct fd_cs_patch){
 205                 .cs  = ring->cur++,
 206                 .val = data,
 207         }));
 208 }
 209
 210 /*
 211  * NOTE: OUT_RELOC*() is 2 dwords (64b) on a5xx+
 212  */
 213
 214 static inline void
 215 OUT_RELOC(struct fd_ringbuffer *ring, struct fd_bo *bo,
 216                 uint32_t offset, uint64_t or, int32_t shift)
 217 {
 218         if (LOG_DWORDS) {
 219                 DBG("ring[%p]: OUT_RELOC   %04x:  %p+%u << %d", ring,
 220                                 (uint32_t)(ring->cur - ring->last_start), bo, offset, shift);
 221         }
 222         debug_assert(offset < fd_bo_size(bo));
 223         fd_ringbuffer_reloc2(ring, &(struct fd_reloc){
 224                 .bo = bo,
 225                 .flags = FD_RELOC_READ,
 226                 .offset = offset,
 227                 .or = or,
 228                 .shift = shift,
 229                 .orhi = or >> 32,
 230         });
 231 }
 232
 233 static inline void
 234 OUT_RELOCW(struct fd_ringbuffer *ring, struct fd_bo *bo,
 235                 uint32_t offset, uint64_t or, int32_t shift)
 236 {
 237         if (LOG_DWORDS) {
 238                 DBG("ring[%p]: OUT_RELOCW  %04x:  %p+%u << %d", ring,
 239                                 (uint32_t)(ring->cur - ring->last_start), bo, offset, shift);
 240         }
 241         debug_assert(offset < fd_bo_size(bo));
 242         fd_ringbuffer_reloc2(ring, &(struct fd_reloc){
 243                 .bo = bo,
 244                 .flags = FD_RELOC_READ | FD_RELOC_WRITE,
 245                 .offset = offset,
 246                 .or = or,
 247                 .shift = shift,
 248                 .orhi = or >> 32,
 249         });
 250 }
 251
 252 static inline void BEGIN_RING(struct fd_ringbuffer *ring, uint32_t ndwords)
 253 {
 254         if (ring->cur + ndwords >= ring->end)
 255                 fd_ringbuffer_grow(ring, ndwords);
 256 }
 257
 258 static inline uint32_t
 259 __gpu_id(struct fd_ringbuffer *ring)
 260 {
 261         uint64_t val;
 262         fd_pipe_get_param(ring->pipe, FD_GPU_ID, &val);
 263         return val;
 264 }
 265
 266 static inline void
 267 OUT_PKT0(struct fd_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
 268 {
 269         debug_assert(__gpu_id(ring) < 500);
 270         BEGIN_RING(ring, cnt+1);
 271         OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
 272 }
 273
 274 static inline void
 275 OUT_PKT2(struct fd_ringbuffer *ring)
 276 {
 277         debug_assert(__gpu_id(ring) < 500);
 278         BEGIN_RING(ring, 1);
 279         OUT_RING(ring, CP_TYPE2_PKT);
 280 }
 281
 282 static inline void
 283 OUT_PKT3(struct fd_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
 284 {
 285         debug_assert(__gpu_id(ring) < 500);
 286         BEGIN_RING(ring, cnt+1);
 287         OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
 288 }
 289
 290 /*
 291  * Starting with a5xx, pkt4/pkt7 are used instead of pkt0/pkt3
 292  */
 293
 294 static inline unsigned
 295 _odd_parity_bit(unsigned val)
 296 {
 297         /* See: http://graphics.stanford.edu/~seander/bithacks.html#ParityParallel
 298          * note that we want odd parity so 0x6996 is inverted.
 299          */
 300         val ^= val >> 16;
 301         val ^= val >> 8;
 302         val ^= val >> 4;
 303         val &= 0xf;
 304         return (~0x6996 >> val) & 1;
 305 }
 306
 307 static inline void
 308 OUT_PKT4(struct fd_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
 309 {
 310         BEGIN_RING(ring, cnt+1);
 311         OUT_RING(ring, CP_TYPE4_PKT | cnt |
 312                         (_odd_parity_bit(cnt) << 7) |
 313                         ((regindx & 0x3ffff) << 8) |
 314                         ((_odd_parity_bit(regindx) << 27)));
 315 }
 316
 317 static inline void
 318 OUT_PKT7(struct fd_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
 319 {
 320         BEGIN_RING(ring, cnt+1);
 321         OUT_RING(ring, CP_TYPE7_PKT | cnt |
 322                         (_odd_parity_bit(cnt) << 15) |
 323                         ((opcode & 0x7f) << 16) |
 324                         ((_odd_parity_bit(opcode) << 23)));
 325 }
 326
 327 static inline void
 328 OUT_WFI(struct fd_ringbuffer *ring)
 329 {
 330         OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
 331         OUT_RING(ring, 0x00000000);
 332 }
 333
 334 static inline void
 335 OUT_WFI5(struct fd_ringbuffer *ring)
 336 {
 337         OUT_PKT7(ring, CP_WAIT_FOR_IDLE, 0);
 338 }
 339
 340 static inline void
 341 __OUT_IB(struct fd_ringbuffer *ring, bool prefetch, struct fd_ringbuffer *target)
 342 {
 343         unsigned count = fd_ringbuffer_cmd_count(target);
 344
 345         debug_assert(__gpu_id(ring) < 500);
 346
 347         /* for debug after a lock up, write a unique counter value
 348          * to scratch6 for each IB, to make it easier to match up
 349          * register dumps to cmdstream.  The combination of IB and
 350          * DRAW (scratch7) is enough to "triangulate" the particular
 351          * draw that caused lockup.
 352          */
 353         emit_marker(ring, 6);
 354
 355         for (unsigned i = 0; i < count; i++) {
 356                 uint32_t dwords;
 357                 OUT_PKT3(ring, prefetch ? CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2);
 358                 dwords = fd_ringbuffer_emit_reloc_ring_full(ring, target, i) / 4;
 359                 assert(dwords > 0);
 360                 OUT_RING(ring, dwords);
 361                 OUT_PKT2(ring);
 362         }
 363
 364         emit_marker(ring, 6);
 365 }
 366
 367 static inline void
 368 __OUT_IB5(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
 369 {
 370         unsigned count = fd_ringbuffer_cmd_count(target);
 371
 372         /* for debug after a lock up, write a unique counter value
 373          * to scratch6 for each IB, to make it easier to match up
 374          * register dumps to cmdstream.  The combination of IB and
 375          * DRAW (scratch7) is enough to "triangulate" the particular
 376          * draw that caused lockup.
 377          */
 378         emit_marker5(ring, 6);
 379
 380         for (unsigned i = 0; i < count; i++) {
 381                 uint32_t dwords;
 382                 OUT_PKT7(ring, CP_INDIRECT_BUFFER, 3);
 383                 dwords = fd_ringbuffer_emit_reloc_ring_full(ring, target, i) / 4;
 384                 assert(dwords > 0);
 385                 OUT_RING(ring, dwords);
 386         }
 387
 388         emit_marker5(ring, 6);
 389 }
 390
 391 /* CP_SCRATCH_REG4 is used to hold base address for query results: */
 392 // XXX annoyingly scratch regs move on a5xx.. and additionally different
 393 // packet types.. so freedreno_query_hw is going to need a bit of
 394 // rework..
 395 #define HW_QUERY_BASE_REG REG_AXXX_CP_SCRATCH_REG4
 396
 397 static inline void
 398 emit_marker(struct fd_ringbuffer *ring, int scratch_idx)
 399 {
 400         extern unsigned marker_cnt;
 401         unsigned reg = REG_AXXX_CP_SCRATCH_REG0 + scratch_idx;
 402         assert(reg != HW_QUERY_BASE_REG);
 403         if (reg == HW_QUERY_BASE_REG)
 404                 return;
 405         OUT_PKT0(ring, reg, 1);
 406         OUT_RING(ring, ++marker_cnt);
 407 }
 408
 409 static inline void
 410 emit_marker5(struct fd_ringbuffer *ring, int scratch_idx)
 411 {
 412         extern unsigned marker_cnt;
 413 //XXX   unsigned reg = REG_A5XX_CP_SCRATCH_REG(scratch_idx);
 414         unsigned reg = 0x00000b78 + scratch_idx;
 415         OUT_PKT4(ring, reg, 1);
 416         OUT_RING(ring, ++marker_cnt);
 417 }
 418
 419 /* helper to get numeric value from environment variable..  mostly
 420  * just leaving this here because it is helpful to brute-force figure
 421  * out unknown formats, etc, which blob driver does not support:
 422  */
 423 static inline uint32_t env2u(const char *envvar)
 424 {
 425         char *str = getenv(envvar);
 426         if (str)
 427                 return strtoul(str, NULL, 0);
 428         return 0;
 429 }
 430
 431 static inline uint32_t
 432 pack_rgba(enum pipe_format format, const float *rgba)
 433 {
 434         union util_color uc;
 435         util_pack_color(rgba, format, &uc);
 436         return uc.ui[0];
 437 }
 438
 439 /*
 440  * swap - swap value of @a and @b
 441  */
 442 #define swap(a, b) \
 443         do { __typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
 444
 445 #define foreach_bit(b, mask) \
 446         for (uint32_t _m = (mask); _m && ({(b) = u_bit_scan(&_m); 1;});)
 447
 448
 449 #define BIT(bit) (1u << bit)
 450
 451 /*
 452  * a4xx+ helpers:
 453  */
 454
 455 static inline enum a4xx_state_block
 456 fd4_stage2shadersb(enum shader_t type)
 457 {
 458         switch (type) {
 459         case SHADER_VERTEX:
 460                 return SB4_VS_SHADER;
 461         case SHADER_FRAGMENT:
 462                 return SB4_FS_SHADER;
 463         case SHADER_COMPUTE:
 464                 return SB4_CS_SHADER;
 465         default:
 466                 unreachable("bad shader type");
 467                 return ~0;
 468         }
 469 }
 470
 471 #endif /* FREEDRENO_UTIL_H_ */