freedreno: use autogenerated register defs
[mesa.git] / src / gallium / drivers / freedreno / freedreno_zsa.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29
30 #include "pipe/p_state.h"
31 #include "util/u_string.h"
32 #include "util/u_memory.h"
33
34 #include "freedreno_zsa.h"
35 #include "freedreno_context.h"
36 #include "freedreno_util.h"
37
38 static enum adreno_stencil_op
39 stencil_op(unsigned op)
40 {
41 switch (op) {
42 case PIPE_STENCIL_OP_KEEP:
43 return STENCIL_KEEP;
44 case PIPE_STENCIL_OP_ZERO:
45 return STENCIL_ZERO;
46 case PIPE_STENCIL_OP_REPLACE:
47 return STENCIL_REPLACE;
48 case PIPE_STENCIL_OP_INCR:
49 return STENCIL_INCR_CLAMP;
50 case PIPE_STENCIL_OP_DECR:
51 return STENCIL_DECR_CLAMP;
52 case PIPE_STENCIL_OP_INCR_WRAP:
53 return STENCIL_INCR_WRAP;
54 case PIPE_STENCIL_OP_DECR_WRAP:
55 return STENCIL_DECR_WRAP;
56 case PIPE_STENCIL_OP_INVERT:
57 return STENCIL_INVERT;
58 default:
59 DBG("invalid stencil op: %u", op);
60 return 0;
61 }
62 }
63
64 static void *
65 fd_zsa_state_create(struct pipe_context *pctx,
66 const struct pipe_depth_stencil_alpha_state *cso)
67 {
68 struct fd_zsa_stateobj *so;
69
70 so = CALLOC_STRUCT(fd_zsa_stateobj);
71 if (!so)
72 return NULL;
73
74 so->base = *cso;
75
76 so->rb_depthcontrol |=
77 A2XX_RB_DEPTHCONTROL_ZFUNC(cso->depth.func); /* maps 1:1 */
78
79 if (cso->depth.enabled)
80 so->rb_depthcontrol |= A2XX_RB_DEPTHCONTROL_Z_ENABLE;
81 if (cso->depth.writemask)
82 so->rb_depthcontrol |= A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE;
83
84 if (cso->stencil[0].enabled) {
85 const struct pipe_stencil_state *s = &cso->stencil[0];
86
87 so->rb_depthcontrol |=
88 A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE |
89 A2XX_RB_DEPTHCONTROL_STENCILFUNC(s->func) | /* maps 1:1 */
90 A2XX_RB_DEPTHCONTROL_STENCILFAIL(stencil_op(s->fail_op)) |
91 A2XX_RB_DEPTHCONTROL_STENCILZPASS(stencil_op(s->zpass_op)) |
92 A2XX_RB_DEPTHCONTROL_STENCILZFAIL(stencil_op(s->zfail_op));
93 so->rb_stencilrefmask |=
94 0xff000000 | /* ??? */
95 A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(s->writemask) |
96 A2XX_RB_STENCILREFMASK_STENCILMASK(s->valuemask);
97
98 if (cso->stencil[1].enabled) {
99 const struct pipe_stencil_state *bs = &cso->stencil[1];
100
101 so->rb_depthcontrol |=
102 A2XX_RB_DEPTHCONTROL_BACKFACE_ENABLE |
103 A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(bs->func) | /* maps 1:1 */
104 A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(stencil_op(bs->fail_op)) |
105 A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(stencil_op(bs->zpass_op)) |
106 A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(stencil_op(bs->zfail_op));
107 so->rb_stencilrefmask_bf |=
108 0xff000000 | /* ??? */
109 A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(bs->writemask) |
110 A2XX_RB_STENCILREFMASK_STENCILMASK(bs->valuemask);
111 }
112 }
113
114 if (cso->alpha.enabled) {
115 so->rb_colorcontrol =
116 A2XX_RB_COLORCONTROL_ALPHA_FUNC(cso->alpha.func) |
117 A2XX_RB_COLORCONTROL_ALPHA_TEST_ENABLE;
118 so->rb_alpha_ref = fui(cso->alpha.ref_value);
119 }
120
121 return so;
122 }
123
124 static void
125 fd_zsa_state_bind(struct pipe_context *pctx, void *hwcso)
126 {
127 struct fd_context *ctx = fd_context(pctx);
128 ctx->zsa = hwcso;
129 ctx->dirty |= FD_DIRTY_ZSA;
130 }
131
132 static void
133 fd_zsa_state_delete(struct pipe_context *pctx, void *hwcso)
134 {
135 FREE(hwcso);
136 }
137
138 void
139 fd_zsa_init(struct pipe_context *pctx)
140 {
141 pctx->create_depth_stencil_alpha_state = fd_zsa_state_create;
142 pctx->bind_depth_stencil_alpha_state = fd_zsa_state_bind;
143 pctx->delete_depth_stencil_alpha_state = fd_zsa_state_delete;
144 }