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[mesa.git] / src / gallium / drivers / freedreno / ir3 / ir3.c
1 /*
2 * Copyright (c) 2012 Rob Clark <robdclark@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include "ir3.h"
25
26 #include <stdlib.h>
27 #include <stdio.h>
28 #include <string.h>
29 #include <assert.h>
30 #include <stdbool.h>
31 #include <errno.h>
32
33 #include "util/ralloc.h"
34
35 #include "freedreno_util.h"
36 #include "instr-a3xx.h"
37
38 /* simple allocator to carve allocations out of an up-front allocated heap,
39 * so that we can free everything easily in one shot.
40 */
41 void * ir3_alloc(struct ir3 *shader, int sz)
42 {
43 return rzalloc_size(shader, sz); /* TODO: don't use rzalloc */
44 }
45
46 struct ir3 * ir3_create(struct ir3_compiler *compiler,
47 unsigned nin, unsigned nout)
48 {
49 struct ir3 *shader = rzalloc(compiler, struct ir3);
50
51 shader->compiler = compiler;
52 shader->ninputs = nin;
53 shader->inputs = ir3_alloc(shader, sizeof(shader->inputs[0]) * nin);
54
55 shader->noutputs = nout;
56 shader->outputs = ir3_alloc(shader, sizeof(shader->outputs[0]) * nout);
57
58 list_inithead(&shader->block_list);
59 list_inithead(&shader->array_list);
60
61 return shader;
62 }
63
64 void ir3_destroy(struct ir3 *shader)
65 {
66 ralloc_free(shader);
67 }
68
69 #define iassert(cond) do { \
70 if (!(cond)) { \
71 debug_assert(cond); \
72 return -1; \
73 } } while (0)
74
75 #define iassert_type(reg, full) do { \
76 if ((full)) { \
77 iassert(!((reg)->flags & IR3_REG_HALF)); \
78 } else { \
79 iassert((reg)->flags & IR3_REG_HALF); \
80 } } while (0);
81
82 static uint32_t reg(struct ir3_register *reg, struct ir3_info *info,
83 uint32_t repeat, uint32_t valid_flags)
84 {
85 reg_t val = { .dummy32 = 0 };
86
87 if (reg->flags & ~valid_flags) {
88 debug_printf("INVALID FLAGS: %x vs %x\n",
89 reg->flags, valid_flags);
90 }
91
92 if (!(reg->flags & IR3_REG_R))
93 repeat = 0;
94
95 if (reg->flags & IR3_REG_IMMED) {
96 val.iim_val = reg->iim_val;
97 } else {
98 unsigned components;
99 int16_t max;
100
101 if (reg->flags & IR3_REG_RELATIV) {
102 components = reg->size;
103 val.idummy10 = reg->array.offset;
104 max = (reg->array.offset + repeat + components - 1) >> 2;
105 } else {
106 components = util_last_bit(reg->wrmask);
107 val.comp = reg->num & 0x3;
108 val.num = reg->num >> 2;
109 max = (reg->num + repeat + components - 1) >> 2;
110 }
111
112 if (reg->flags & IR3_REG_CONST) {
113 info->max_const = MAX2(info->max_const, max);
114 } else if (val.num == 63) {
115 /* ignore writes to dummy register r63.x */
116 } else if (max < 48) {
117 if (reg->flags & IR3_REG_HALF) {
118 if (info->gpu_id >= 600) {
119 /* starting w/ a6xx, half regs conflict with full regs: */
120 info->max_reg = MAX2(info->max_reg, (max+1)/2);
121 } else {
122 info->max_half_reg = MAX2(info->max_half_reg, max);
123 }
124 } else {
125 info->max_reg = MAX2(info->max_reg, max);
126 }
127 }
128 }
129
130 return val.dummy32;
131 }
132
133 static int emit_cat0(struct ir3_instruction *instr, void *ptr,
134 struct ir3_info *info)
135 {
136 instr_cat0_t *cat0 = ptr;
137
138 if (info->gpu_id >= 500) {
139 cat0->a5xx.immed = instr->cat0.immed;
140 } else if (info->gpu_id >= 400) {
141 cat0->a4xx.immed = instr->cat0.immed;
142 } else {
143 cat0->a3xx.immed = instr->cat0.immed;
144 }
145 cat0->repeat = instr->repeat;
146 cat0->ss = !!(instr->flags & IR3_INSTR_SS);
147 cat0->inv = instr->cat0.inv;
148 cat0->comp = instr->cat0.comp;
149 cat0->opc = instr->opc;
150 cat0->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
151 cat0->sync = !!(instr->flags & IR3_INSTR_SY);
152 cat0->opc_cat = 0;
153
154 return 0;
155 }
156
157 static int emit_cat1(struct ir3_instruction *instr, void *ptr,
158 struct ir3_info *info)
159 {
160 struct ir3_register *dst = instr->regs[0];
161 struct ir3_register *src = instr->regs[1];
162 instr_cat1_t *cat1 = ptr;
163
164 iassert(instr->regs_count == 2);
165 iassert_type(dst, type_size(instr->cat1.dst_type) == 32);
166 if (!(src->flags & IR3_REG_IMMED))
167 iassert_type(src, type_size(instr->cat1.src_type) == 32);
168
169 if (src->flags & IR3_REG_IMMED) {
170 cat1->iim_val = src->iim_val;
171 cat1->src_im = 1;
172 } else if (src->flags & IR3_REG_RELATIV) {
173 cat1->off = reg(src, info, instr->repeat,
174 IR3_REG_R | IR3_REG_CONST | IR3_REG_HALF | IR3_REG_RELATIV);
175 cat1->src_rel = 1;
176 cat1->src_rel_c = !!(src->flags & IR3_REG_CONST);
177 } else {
178 cat1->src = reg(src, info, instr->repeat,
179 IR3_REG_R | IR3_REG_CONST | IR3_REG_HALF);
180 cat1->src_c = !!(src->flags & IR3_REG_CONST);
181 }
182
183 cat1->dst = reg(dst, info, instr->repeat,
184 IR3_REG_RELATIV | IR3_REG_EVEN |
185 IR3_REG_R | IR3_REG_POS_INF | IR3_REG_HALF);
186 cat1->repeat = instr->repeat;
187 cat1->src_r = !!(src->flags & IR3_REG_R);
188 cat1->ss = !!(instr->flags & IR3_INSTR_SS);
189 cat1->ul = !!(instr->flags & IR3_INSTR_UL);
190 cat1->dst_type = instr->cat1.dst_type;
191 cat1->dst_rel = !!(dst->flags & IR3_REG_RELATIV);
192 cat1->src_type = instr->cat1.src_type;
193 cat1->even = !!(dst->flags & IR3_REG_EVEN);
194 cat1->pos_inf = !!(dst->flags & IR3_REG_POS_INF);
195 cat1->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
196 cat1->sync = !!(instr->flags & IR3_INSTR_SY);
197 cat1->opc_cat = 1;
198
199 return 0;
200 }
201
202 static int emit_cat2(struct ir3_instruction *instr, void *ptr,
203 struct ir3_info *info)
204 {
205 struct ir3_register *dst = instr->regs[0];
206 struct ir3_register *src1 = instr->regs[1];
207 struct ir3_register *src2 = instr->regs[2];
208 instr_cat2_t *cat2 = ptr;
209 unsigned absneg = ir3_cat2_absneg(instr->opc);
210
211 iassert((instr->regs_count == 2) || (instr->regs_count == 3));
212
213 if (src1->flags & IR3_REG_RELATIV) {
214 iassert(src1->array.offset < (1 << 10));
215 cat2->rel1.src1 = reg(src1, info, instr->repeat,
216 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_R |
217 IR3_REG_HALF | absneg);
218 cat2->rel1.src1_c = !!(src1->flags & IR3_REG_CONST);
219 cat2->rel1.src1_rel = 1;
220 } else if (src1->flags & IR3_REG_CONST) {
221 iassert(src1->num < (1 << 12));
222 cat2->c1.src1 = reg(src1, info, instr->repeat,
223 IR3_REG_CONST | IR3_REG_R | IR3_REG_HALF);
224 cat2->c1.src1_c = 1;
225 } else {
226 iassert(src1->num < (1 << 11));
227 cat2->src1 = reg(src1, info, instr->repeat,
228 IR3_REG_IMMED | IR3_REG_R | IR3_REG_HALF |
229 absneg);
230 }
231 cat2->src1_im = !!(src1->flags & IR3_REG_IMMED);
232 cat2->src1_neg = !!(src1->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT));
233 cat2->src1_abs = !!(src1->flags & (IR3_REG_FABS | IR3_REG_SABS));
234 cat2->src1_r = !!(src1->flags & IR3_REG_R);
235
236 if (src2) {
237 iassert((src2->flags & IR3_REG_IMMED) ||
238 !((src1->flags ^ src2->flags) & IR3_REG_HALF));
239
240 if (src2->flags & IR3_REG_RELATIV) {
241 iassert(src2->array.offset < (1 << 10));
242 cat2->rel2.src2 = reg(src2, info, instr->repeat,
243 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_R |
244 IR3_REG_HALF | absneg);
245 cat2->rel2.src2_c = !!(src2->flags & IR3_REG_CONST);
246 cat2->rel2.src2_rel = 1;
247 } else if (src2->flags & IR3_REG_CONST) {
248 iassert(src2->num < (1 << 12));
249 cat2->c2.src2 = reg(src2, info, instr->repeat,
250 IR3_REG_CONST | IR3_REG_R | IR3_REG_HALF);
251 cat2->c2.src2_c = 1;
252 } else {
253 iassert(src2->num < (1 << 11));
254 cat2->src2 = reg(src2, info, instr->repeat,
255 IR3_REG_IMMED | IR3_REG_R | IR3_REG_HALF |
256 absneg);
257 }
258
259 cat2->src2_im = !!(src2->flags & IR3_REG_IMMED);
260 cat2->src2_neg = !!(src2->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT));
261 cat2->src2_abs = !!(src2->flags & (IR3_REG_FABS | IR3_REG_SABS));
262 cat2->src2_r = !!(src2->flags & IR3_REG_R);
263 }
264
265 cat2->dst = reg(dst, info, instr->repeat,
266 IR3_REG_R | IR3_REG_EI | IR3_REG_HALF);
267 cat2->repeat = instr->repeat;
268 cat2->sat = !!(instr->flags & IR3_INSTR_SAT);
269 cat2->ss = !!(instr->flags & IR3_INSTR_SS);
270 cat2->ul = !!(instr->flags & IR3_INSTR_UL);
271 cat2->dst_half = !!((src1->flags ^ dst->flags) & IR3_REG_HALF);
272 cat2->ei = !!(dst->flags & IR3_REG_EI);
273 cat2->cond = instr->cat2.condition;
274 cat2->full = ! (src1->flags & IR3_REG_HALF);
275 cat2->opc = instr->opc;
276 cat2->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
277 cat2->sync = !!(instr->flags & IR3_INSTR_SY);
278 cat2->opc_cat = 2;
279
280 return 0;
281 }
282
283 static int emit_cat3(struct ir3_instruction *instr, void *ptr,
284 struct ir3_info *info)
285 {
286 struct ir3_register *dst = instr->regs[0];
287 struct ir3_register *src1 = instr->regs[1];
288 struct ir3_register *src2 = instr->regs[2];
289 struct ir3_register *src3 = instr->regs[3];
290 unsigned absneg = ir3_cat3_absneg(instr->opc);
291 instr_cat3_t *cat3 = ptr;
292 uint32_t src_flags = 0;
293
294 switch (instr->opc) {
295 case OPC_MAD_F16:
296 case OPC_MAD_U16:
297 case OPC_MAD_S16:
298 case OPC_SEL_B16:
299 case OPC_SEL_S16:
300 case OPC_SEL_F16:
301 case OPC_SAD_S16:
302 case OPC_SAD_S32: // really??
303 src_flags |= IR3_REG_HALF;
304 break;
305 default:
306 break;
307 }
308
309 iassert(instr->regs_count == 4);
310 iassert(!((src1->flags ^ src_flags) & IR3_REG_HALF));
311 iassert(!((src2->flags ^ src_flags) & IR3_REG_HALF));
312 iassert(!((src3->flags ^ src_flags) & IR3_REG_HALF));
313
314 if (src1->flags & IR3_REG_RELATIV) {
315 iassert(src1->array.offset < (1 << 10));
316 cat3->rel1.src1 = reg(src1, info, instr->repeat,
317 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_R |
318 IR3_REG_HALF | absneg);
319 cat3->rel1.src1_c = !!(src1->flags & IR3_REG_CONST);
320 cat3->rel1.src1_rel = 1;
321 } else if (src1->flags & IR3_REG_CONST) {
322 iassert(src1->num < (1 << 12));
323 cat3->c1.src1 = reg(src1, info, instr->repeat,
324 IR3_REG_CONST | IR3_REG_R | IR3_REG_HALF);
325 cat3->c1.src1_c = 1;
326 } else {
327 iassert(src1->num < (1 << 11));
328 cat3->src1 = reg(src1, info, instr->repeat,
329 IR3_REG_R | IR3_REG_HALF | absneg);
330 }
331
332 cat3->src1_neg = !!(src1->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT));
333 cat3->src1_r = !!(src1->flags & IR3_REG_R);
334
335 cat3->src2 = reg(src2, info, instr->repeat,
336 IR3_REG_CONST | IR3_REG_R | IR3_REG_HALF | absneg);
337 cat3->src2_c = !!(src2->flags & IR3_REG_CONST);
338 cat3->src2_neg = !!(src2->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT));
339 cat3->src2_r = !!(src2->flags & IR3_REG_R);
340
341
342 if (src3->flags & IR3_REG_RELATIV) {
343 iassert(src3->array.offset < (1 << 10));
344 cat3->rel2.src3 = reg(src3, info, instr->repeat,
345 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_R |
346 IR3_REG_HALF | absneg);
347 cat3->rel2.src3_c = !!(src3->flags & IR3_REG_CONST);
348 cat3->rel2.src3_rel = 1;
349 } else if (src3->flags & IR3_REG_CONST) {
350 iassert(src3->num < (1 << 12));
351 cat3->c2.src3 = reg(src3, info, instr->repeat,
352 IR3_REG_CONST | IR3_REG_R | IR3_REG_HALF);
353 cat3->c2.src3_c = 1;
354 } else {
355 iassert(src3->num < (1 << 11));
356 cat3->src3 = reg(src3, info, instr->repeat,
357 IR3_REG_R | IR3_REG_HALF | absneg);
358 }
359
360 cat3->src3_neg = !!(src3->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT));
361 cat3->src3_r = !!(src3->flags & IR3_REG_R);
362
363 cat3->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
364 cat3->repeat = instr->repeat;
365 cat3->sat = !!(instr->flags & IR3_INSTR_SAT);
366 cat3->ss = !!(instr->flags & IR3_INSTR_SS);
367 cat3->ul = !!(instr->flags & IR3_INSTR_UL);
368 cat3->dst_half = !!((src_flags ^ dst->flags) & IR3_REG_HALF);
369 cat3->opc = instr->opc;
370 cat3->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
371 cat3->sync = !!(instr->flags & IR3_INSTR_SY);
372 cat3->opc_cat = 3;
373
374 return 0;
375 }
376
377 static int emit_cat4(struct ir3_instruction *instr, void *ptr,
378 struct ir3_info *info)
379 {
380 struct ir3_register *dst = instr->regs[0];
381 struct ir3_register *src = instr->regs[1];
382 instr_cat4_t *cat4 = ptr;
383
384 iassert(instr->regs_count == 2);
385
386 if (src->flags & IR3_REG_RELATIV) {
387 iassert(src->array.offset < (1 << 10));
388 cat4->rel.src = reg(src, info, instr->repeat,
389 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_FNEG |
390 IR3_REG_FABS | IR3_REG_R | IR3_REG_HALF);
391 cat4->rel.src_c = !!(src->flags & IR3_REG_CONST);
392 cat4->rel.src_rel = 1;
393 } else if (src->flags & IR3_REG_CONST) {
394 iassert(src->num < (1 << 12));
395 cat4->c.src = reg(src, info, instr->repeat,
396 IR3_REG_CONST | IR3_REG_FNEG | IR3_REG_FABS |
397 IR3_REG_R | IR3_REG_HALF);
398 cat4->c.src_c = 1;
399 } else {
400 iassert(src->num < (1 << 11));
401 cat4->src = reg(src, info, instr->repeat,
402 IR3_REG_IMMED | IR3_REG_FNEG | IR3_REG_FABS |
403 IR3_REG_R | IR3_REG_HALF);
404 }
405
406 cat4->src_im = !!(src->flags & IR3_REG_IMMED);
407 cat4->src_neg = !!(src->flags & IR3_REG_FNEG);
408 cat4->src_abs = !!(src->flags & IR3_REG_FABS);
409 cat4->src_r = !!(src->flags & IR3_REG_R);
410
411 cat4->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
412 cat4->repeat = instr->repeat;
413 cat4->sat = !!(instr->flags & IR3_INSTR_SAT);
414 cat4->ss = !!(instr->flags & IR3_INSTR_SS);
415 cat4->ul = !!(instr->flags & IR3_INSTR_UL);
416 cat4->dst_half = !!((src->flags ^ dst->flags) & IR3_REG_HALF);
417 cat4->full = ! (src->flags & IR3_REG_HALF);
418 cat4->opc = instr->opc;
419 cat4->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
420 cat4->sync = !!(instr->flags & IR3_INSTR_SY);
421 cat4->opc_cat = 4;
422
423 return 0;
424 }
425
426 static int emit_cat5(struct ir3_instruction *instr, void *ptr,
427 struct ir3_info *info)
428 {
429 struct ir3_register *dst = instr->regs[0];
430 struct ir3_register *src1 = instr->regs[1];
431 struct ir3_register *src2 = instr->regs[2];
432 struct ir3_register *src3 = instr->regs[3];
433 instr_cat5_t *cat5 = ptr;
434
435 iassert_type(dst, type_size(instr->cat5.type) == 32)
436
437 assume(src1 || !src2);
438 assume(src2 || !src3);
439
440 if (src1) {
441 cat5->full = ! (src1->flags & IR3_REG_HALF);
442 cat5->src1 = reg(src1, info, instr->repeat, IR3_REG_HALF);
443 }
444
445 if (instr->flags & IR3_INSTR_S2EN) {
446 if (src2) {
447 iassert(!((src1->flags ^ src2->flags) & IR3_REG_HALF));
448 cat5->s2en.src2 = reg(src2, info, instr->repeat, IR3_REG_HALF);
449 }
450 if (src3) {
451 iassert(src3->flags & IR3_REG_HALF);
452 cat5->s2en.src3 = reg(src3, info, instr->repeat, IR3_REG_HALF);
453 }
454 iassert(!(instr->cat5.samp | instr->cat5.tex));
455 } else {
456 iassert(!src3);
457 if (src2) {
458 iassert(!((src1->flags ^ src2->flags) & IR3_REG_HALF));
459 cat5->norm.src2 = reg(src2, info, instr->repeat, IR3_REG_HALF);
460 }
461 cat5->norm.samp = instr->cat5.samp;
462 cat5->norm.tex = instr->cat5.tex;
463 }
464
465 cat5->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
466 cat5->wrmask = dst->wrmask;
467 cat5->type = instr->cat5.type;
468 cat5->is_3d = !!(instr->flags & IR3_INSTR_3D);
469 cat5->is_a = !!(instr->flags & IR3_INSTR_A);
470 cat5->is_s = !!(instr->flags & IR3_INSTR_S);
471 cat5->is_s2en = !!(instr->flags & IR3_INSTR_S2EN);
472 cat5->is_o = !!(instr->flags & IR3_INSTR_O);
473 cat5->is_p = !!(instr->flags & IR3_INSTR_P);
474 cat5->opc = instr->opc;
475 cat5->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
476 cat5->sync = !!(instr->flags & IR3_INSTR_SY);
477 cat5->opc_cat = 5;
478
479 return 0;
480 }
481
482 static int emit_cat6(struct ir3_instruction *instr, void *ptr,
483 struct ir3_info *info)
484 {
485 struct ir3_register *dst, *src1, *src2;
486 instr_cat6_t *cat6 = ptr;
487 bool type_full = type_size(instr->cat6.type) == 32;
488
489 cat6->type = instr->cat6.type;
490 cat6->opc = instr->opc;
491 cat6->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
492 cat6->sync = !!(instr->flags & IR3_INSTR_SY);
493 cat6->g = !!(instr->flags & IR3_INSTR_G);
494 cat6->opc_cat = 6;
495
496 switch (instr->opc) {
497 case OPC_RESINFO:
498 case OPC_RESFMT:
499 iassert_type(instr->regs[0], type_full); /* dst */
500 iassert_type(instr->regs[1], type_full); /* src1 */
501 break;
502 case OPC_L2G:
503 case OPC_G2L:
504 iassert_type(instr->regs[0], true); /* dst */
505 iassert_type(instr->regs[1], true); /* src1 */
506 break;
507 case OPC_STG:
508 case OPC_STL:
509 case OPC_STP:
510 case OPC_STI:
511 case OPC_STLW:
512 case OPC_STIB:
513 /* no dst, so regs[0] is dummy */
514 iassert_type(instr->regs[1], true); /* dst */
515 iassert_type(instr->regs[2], type_full); /* src1 */
516 iassert_type(instr->regs[3], true); /* src2 */
517 break;
518 default:
519 iassert_type(instr->regs[0], type_full); /* dst */
520 iassert_type(instr->regs[1], true); /* src1 */
521 if (instr->regs_count > 2)
522 iassert_type(instr->regs[2], true); /* src1 */
523 break;
524 }
525
526 /* the "dst" for a store instruction is (from the perspective
527 * of data flow in the shader, ie. register use/def, etc) in
528 * fact a register that is read by the instruction, rather
529 * than written:
530 */
531 if (is_store(instr)) {
532 iassert(instr->regs_count >= 3);
533
534 dst = instr->regs[1];
535 src1 = instr->regs[2];
536 src2 = (instr->regs_count >= 4) ? instr->regs[3] : NULL;
537 } else {
538 iassert(instr->regs_count >= 2);
539
540 dst = instr->regs[0];
541 src1 = instr->regs[1];
542 src2 = (instr->regs_count >= 3) ? instr->regs[2] : NULL;
543 }
544
545 /* TODO we need a more comprehensive list about which instructions
546 * can be encoded which way. Or possibly use IR3_INSTR_0 flag to
547 * indicate to use the src_off encoding even if offset is zero
548 * (but then what to do about dst_off?)
549 */
550 if (is_atomic(instr->opc)) {
551 instr_cat6ldgb_t *ldgb = ptr;
552
553 /* maybe these two bits both determine the instruction encoding? */
554 cat6->src_off = false;
555
556 ldgb->d = instr->cat6.d - 1;
557 ldgb->typed = instr->cat6.typed;
558 ldgb->type_size = instr->cat6.iim_val - 1;
559
560 ldgb->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
561
562 if (ldgb->g) {
563 struct ir3_register *src3 = instr->regs[3];
564 struct ir3_register *src4 = instr->regs[4];
565
566 /* first src is src_ssbo: */
567 iassert(src1->flags & IR3_REG_IMMED);
568 ldgb->src_ssbo = src1->uim_val;
569
570 ldgb->src1 = reg(src2, info, instr->repeat, IR3_REG_IMMED);
571 ldgb->src1_im = !!(src2->flags & IR3_REG_IMMED);
572 ldgb->src2 = reg(src3, info, instr->repeat, IR3_REG_IMMED);
573 ldgb->src2_im = !!(src3->flags & IR3_REG_IMMED);
574
575 ldgb->src3 = reg(src4, info, instr->repeat, 0);
576 ldgb->pad0 = 0x1;
577 ldgb->pad3 = 0x1;
578 } else {
579 ldgb->src1 = reg(src1, info, instr->repeat, IR3_REG_IMMED);
580 ldgb->src1_im = !!(src1->flags & IR3_REG_IMMED);
581 ldgb->src2 = reg(src2, info, instr->repeat, IR3_REG_IMMED);
582 ldgb->src2_im = !!(src2->flags & IR3_REG_IMMED);
583 ldgb->pad0 = 0x1;
584 ldgb->pad3 = 0x0;
585 }
586
587 return 0;
588 } else if (instr->opc == OPC_LDGB) {
589 struct ir3_register *src3 = instr->regs[3];
590 instr_cat6ldgb_t *ldgb = ptr;
591
592 /* maybe these two bits both determine the instruction encoding? */
593 cat6->src_off = false;
594
595 ldgb->d = instr->cat6.d - 1;
596 ldgb->typed = instr->cat6.typed;
597 ldgb->type_size = instr->cat6.iim_val - 1;
598
599 ldgb->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
600
601 /* first src is src_ssbo: */
602 iassert(src1->flags & IR3_REG_IMMED);
603 ldgb->src_ssbo = src1->uim_val;
604
605 /* then next two are src1/src2: */
606 ldgb->src1 = reg(src2, info, instr->repeat, IR3_REG_IMMED);
607 ldgb->src1_im = !!(src2->flags & IR3_REG_IMMED);
608 ldgb->src2 = reg(src3, info, instr->repeat, IR3_REG_IMMED);
609 ldgb->src2_im = !!(src3->flags & IR3_REG_IMMED);
610
611 ldgb->pad0 = 0x0;
612 ldgb->pad3 = 0x1;
613
614 return 0;
615 } else if (instr->opc == OPC_RESINFO) {
616 instr_cat6ldgb_t *ldgb = ptr;
617
618 ldgb->d = instr->cat6.d - 1;
619
620 ldgb->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
621
622 /* first src is src_ssbo: */
623 iassert(src1->flags & IR3_REG_IMMED);
624 ldgb->src_ssbo = src1->uim_val;
625
626 return 0;
627 } else if ((instr->opc == OPC_STGB) || (instr->opc == OPC_STIB)) {
628 struct ir3_register *src3 = instr->regs[4];
629 instr_cat6stgb_t *stgb = ptr;
630
631 /* maybe these two bits both determine the instruction encoding? */
632 cat6->src_off = true;
633 stgb->pad3 = 0x2;
634
635 stgb->d = instr->cat6.d - 1;
636 stgb->typed = instr->cat6.typed;
637 stgb->type_size = instr->cat6.iim_val - 1;
638
639 /* first src is dst_ssbo: */
640 iassert(dst->flags & IR3_REG_IMMED);
641 stgb->dst_ssbo = dst->uim_val;
642
643 /* then src1/src2/src3: */
644 stgb->src1 = reg(src1, info, instr->repeat, 0);
645 stgb->src2 = reg(src2, info, instr->repeat, IR3_REG_IMMED);
646 stgb->src2_im = !!(src2->flags & IR3_REG_IMMED);
647 stgb->src3 = reg(src3, info, instr->repeat, IR3_REG_IMMED);
648 stgb->src3_im = !!(src3->flags & IR3_REG_IMMED);
649
650 return 0;
651 } else if (instr->cat6.src_offset || (instr->opc == OPC_LDG) ||
652 (instr->opc == OPC_LDL)) {
653 instr_cat6a_t *cat6a = ptr;
654
655 cat6->src_off = true;
656
657 cat6a->src1 = reg(src1, info, instr->repeat, IR3_REG_IMMED);
658 cat6a->src1_im = !!(src1->flags & IR3_REG_IMMED);
659 if (src2) {
660 cat6a->src2 = reg(src2, info, instr->repeat, IR3_REG_IMMED);
661 cat6a->src2_im = !!(src2->flags & IR3_REG_IMMED);
662 }
663 cat6a->off = instr->cat6.src_offset;
664 } else {
665 instr_cat6b_t *cat6b = ptr;
666
667 cat6->src_off = false;
668
669 cat6b->src1 = reg(src1, info, instr->repeat, IR3_REG_IMMED | IR3_REG_HALF);
670 cat6b->src1_im = !!(src1->flags & IR3_REG_IMMED);
671 if (src2) {
672 cat6b->src2 = reg(src2, info, instr->repeat, IR3_REG_IMMED);
673 cat6b->src2_im = !!(src2->flags & IR3_REG_IMMED);
674 }
675 }
676
677 if (instr->cat6.dst_offset || (instr->opc == OPC_STG) ||
678 (instr->opc == OPC_STL)) {
679 instr_cat6c_t *cat6c = ptr;
680 cat6->dst_off = true;
681 cat6c->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
682 cat6c->off = instr->cat6.dst_offset;
683 } else {
684 instr_cat6d_t *cat6d = ptr;
685 cat6->dst_off = false;
686 cat6d->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
687 }
688
689 return 0;
690 }
691
692 static int emit_cat7(struct ir3_instruction *instr, void *ptr,
693 struct ir3_info *info)
694 {
695 instr_cat7_t *cat7 = ptr;
696
697 cat7->ss = !!(instr->flags & IR3_INSTR_SS);
698 cat7->w = instr->cat7.w;
699 cat7->r = instr->cat7.r;
700 cat7->l = instr->cat7.l;
701 cat7->g = instr->cat7.g;
702 cat7->opc = instr->opc;
703 cat7->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
704 cat7->sync = !!(instr->flags & IR3_INSTR_SY);
705 cat7->opc_cat = 7;
706
707 return 0;
708 }
709
710 static int (*emit[])(struct ir3_instruction *instr, void *ptr,
711 struct ir3_info *info) = {
712 emit_cat0, emit_cat1, emit_cat2, emit_cat3, emit_cat4, emit_cat5, emit_cat6,
713 emit_cat7,
714 };
715
716 void * ir3_assemble(struct ir3 *shader, struct ir3_info *info,
717 uint32_t gpu_id)
718 {
719 uint32_t *ptr, *dwords;
720
721 info->gpu_id = gpu_id;
722 info->max_reg = -1;
723 info->max_half_reg = -1;
724 info->max_const = -1;
725 info->instrs_count = 0;
726 info->sizedwords = 0;
727 info->ss = info->sy = 0;
728
729 list_for_each_entry (struct ir3_block, block, &shader->block_list, node) {
730 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
731 info->sizedwords += 2;
732 }
733 }
734
735 /* need an integer number of instruction "groups" (sets of 16
736 * instructions on a4xx or sets of 4 instructions on a3xx),
737 * so pad out w/ NOPs if needed: (NOTE each instruction is 64bits)
738 */
739 if (gpu_id >= 400) {
740 info->sizedwords = align(info->sizedwords, 16 * 2);
741 } else {
742 info->sizedwords = align(info->sizedwords, 4 * 2);
743 }
744
745 ptr = dwords = calloc(4, info->sizedwords);
746
747 list_for_each_entry (struct ir3_block, block, &shader->block_list, node) {
748 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
749 int ret = emit[opc_cat(instr->opc)](instr, dwords, info);
750 if (ret)
751 goto fail;
752 info->instrs_count += 1 + instr->repeat;
753 dwords += 2;
754
755 if (instr->flags & IR3_INSTR_SS)
756 info->ss++;
757
758 if (instr->flags & IR3_INSTR_SY)
759 info->sy++;
760 }
761 }
762
763 return ptr;
764
765 fail:
766 free(ptr);
767 return NULL;
768 }
769
770 static struct ir3_register * reg_create(struct ir3 *shader,
771 int num, int flags)
772 {
773 struct ir3_register *reg =
774 ir3_alloc(shader, sizeof(struct ir3_register));
775 reg->wrmask = 1;
776 reg->flags = flags;
777 reg->num = num;
778 return reg;
779 }
780
781 static void insert_instr(struct ir3_block *block,
782 struct ir3_instruction *instr)
783 {
784 struct ir3 *shader = block->shader;
785 #ifdef DEBUG
786 instr->serialno = ++shader->instr_count;
787 #endif
788 list_addtail(&instr->node, &block->instr_list);
789
790 if (is_input(instr))
791 array_insert(shader, shader->baryfs, instr);
792 }
793
794 struct ir3_block * ir3_block_create(struct ir3 *shader)
795 {
796 struct ir3_block *block = ir3_alloc(shader, sizeof(*block));
797 #ifdef DEBUG
798 block->serialno = ++shader->block_count;
799 #endif
800 block->shader = shader;
801 list_inithead(&block->node);
802 list_inithead(&block->instr_list);
803 return block;
804 }
805
806 static struct ir3_instruction *instr_create(struct ir3_block *block, int nreg)
807 {
808 struct ir3_instruction *instr;
809 unsigned sz = sizeof(*instr) + (nreg * sizeof(instr->regs[0]));
810 char *ptr = ir3_alloc(block->shader, sz);
811
812 instr = (struct ir3_instruction *)ptr;
813 ptr += sizeof(*instr);
814 instr->regs = (struct ir3_register **)ptr;
815
816 #ifdef DEBUG
817 instr->regs_max = nreg;
818 #endif
819
820 return instr;
821 }
822
823 struct ir3_instruction * ir3_instr_create2(struct ir3_block *block,
824 opc_t opc, int nreg)
825 {
826 struct ir3_instruction *instr = instr_create(block, nreg);
827 instr->block = block;
828 instr->opc = opc;
829 insert_instr(block, instr);
830 return instr;
831 }
832
833 struct ir3_instruction * ir3_instr_create(struct ir3_block *block, opc_t opc)
834 {
835 /* NOTE: we could be slightly more clever, at least for non-meta,
836 * and choose # of regs based on category.
837 */
838 return ir3_instr_create2(block, opc, 4);
839 }
840
841 struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr)
842 {
843 struct ir3_instruction *new_instr = instr_create(instr->block,
844 instr->regs_count);
845 struct ir3_register **regs;
846 unsigned i;
847
848 regs = new_instr->regs;
849 *new_instr = *instr;
850 new_instr->regs = regs;
851
852 insert_instr(instr->block, new_instr);
853
854 /* clone registers: */
855 new_instr->regs_count = 0;
856 for (i = 0; i < instr->regs_count; i++) {
857 struct ir3_register *reg = instr->regs[i];
858 struct ir3_register *new_reg =
859 ir3_reg_create(new_instr, reg->num, reg->flags);
860 *new_reg = *reg;
861 }
862
863 return new_instr;
864 }
865
866 /* Add a false dependency to instruction, to ensure it is scheduled first: */
867 void ir3_instr_add_dep(struct ir3_instruction *instr, struct ir3_instruction *dep)
868 {
869 array_insert(instr, instr->deps, dep);
870 }
871
872 struct ir3_register * ir3_reg_create(struct ir3_instruction *instr,
873 int num, int flags)
874 {
875 struct ir3 *shader = instr->block->shader;
876 struct ir3_register *reg = reg_create(shader, num, flags);
877 #ifdef DEBUG
878 debug_assert(instr->regs_count < instr->regs_max);
879 #endif
880 instr->regs[instr->regs_count++] = reg;
881 return reg;
882 }
883
884 struct ir3_register * ir3_reg_clone(struct ir3 *shader,
885 struct ir3_register *reg)
886 {
887 struct ir3_register *new_reg = reg_create(shader, 0, 0);
888 *new_reg = *reg;
889 return new_reg;
890 }
891
892 void
893 ir3_instr_set_address(struct ir3_instruction *instr,
894 struct ir3_instruction *addr)
895 {
896 if (instr->address != addr) {
897 struct ir3 *ir = instr->block->shader;
898 instr->address = addr;
899 array_insert(ir, ir->indirects, instr);
900 }
901 }
902
903 void
904 ir3_block_clear_mark(struct ir3_block *block)
905 {
906 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node)
907 instr->flags &= ~IR3_INSTR_MARK;
908 }
909
910 void
911 ir3_clear_mark(struct ir3 *ir)
912 {
913 list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
914 ir3_block_clear_mark(block);
915 }
916 }
917
918 /* note: this will destroy instr->depth, don't do it until after sched! */
919 unsigned
920 ir3_count_instructions(struct ir3 *ir)
921 {
922 unsigned cnt = 0;
923 list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
924 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
925 instr->ip = cnt++;
926 }
927 block->start_ip = list_first_entry(&block->instr_list, struct ir3_instruction, node)->ip;
928 block->end_ip = list_last_entry(&block->instr_list, struct ir3_instruction, node)->ip;
929 }
930 return cnt;
931 }
932
933 struct ir3_array *
934 ir3_lookup_array(struct ir3 *ir, unsigned id)
935 {
936 list_for_each_entry (struct ir3_array, arr, &ir->array_list, node)
937 if (arr->id == id)
938 return arr;
939 return NULL;
940 }