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[mesa.git] / src / gallium / drivers / freedreno / ir3 / ir3.c
1 /*
2 * Copyright (c) 2012 Rob Clark <robdclark@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include "ir3.h"
25
26 #include <stdlib.h>
27 #include <stdio.h>
28 #include <string.h>
29 #include <assert.h>
30 #include <stdbool.h>
31 #include <errno.h>
32
33 #include "freedreno_util.h"
34 #include "instr-a3xx.h"
35
36 #define CHUNK_SZ 1020
37
38 struct ir3_heap_chunk {
39 struct ir3_heap_chunk *next;
40 uint32_t heap[CHUNK_SZ];
41 };
42
43 static void grow_heap(struct ir3 *shader)
44 {
45 struct ir3_heap_chunk *chunk = calloc(1, sizeof(*chunk));
46 chunk->next = shader->chunk;
47 shader->chunk = chunk;
48 shader->heap_idx = 0;
49 }
50
51 /* simple allocator to carve allocations out of an up-front allocated heap,
52 * so that we can free everything easily in one shot.
53 */
54 void * ir3_alloc(struct ir3 *shader, int sz)
55 {
56 void *ptr;
57
58 sz = align(sz, 4) / 4;
59
60 if ((shader->heap_idx + sz) > CHUNK_SZ)
61 grow_heap(shader);
62
63 ptr = &shader->chunk->heap[shader->heap_idx];
64 shader->heap_idx += sz;
65
66 return ptr;
67 }
68
69 struct ir3 * ir3_create(void)
70 {
71 struct ir3 *shader =
72 calloc(1, sizeof(struct ir3));
73 grow_heap(shader);
74 return shader;
75 }
76
77 void ir3_destroy(struct ir3 *shader)
78 {
79 while (shader->chunk) {
80 struct ir3_heap_chunk *chunk = shader->chunk;
81 shader->chunk = chunk->next;
82 free(chunk);
83 }
84 free(shader->instrs);
85 free(shader->baryfs);
86 free(shader);
87 }
88
89 #define iassert(cond) do { \
90 if (!(cond)) { \
91 assert(cond); \
92 return -1; \
93 } } while (0)
94
95 static uint32_t reg(struct ir3_register *reg, struct ir3_info *info,
96 uint32_t repeat, uint32_t valid_flags)
97 {
98 reg_t val = { .dummy32 = 0 };
99
100 assert(!(reg->flags & ~valid_flags));
101
102 if (!(reg->flags & IR3_REG_R))
103 repeat = 0;
104
105 if (reg->flags & IR3_REG_IMMED) {
106 val.iim_val = reg->iim_val;
107 } else {
108 int8_t components = util_last_bit(reg->wrmask);
109 int16_t max = (reg->num + repeat + components - 1) >> 2;
110
111 val.comp = reg->num & 0x3;
112 val.num = reg->num >> 2;
113
114 if (reg->flags & IR3_REG_CONST) {
115 info->max_const = MAX2(info->max_const, max);
116 } else if ((max != REG_A0) && (max != REG_P0)) {
117 if (reg->flags & IR3_REG_HALF) {
118 info->max_half_reg = MAX2(info->max_half_reg, max);
119 } else {
120 info->max_reg = MAX2(info->max_reg, max);
121 }
122 }
123 }
124
125 return val.dummy32;
126 }
127
128 static int emit_cat0(struct ir3_instruction *instr, void *ptr,
129 struct ir3_info *info)
130 {
131 instr_cat0_t *cat0 = ptr;
132
133 cat0->immed = instr->cat0.immed;
134 cat0->repeat = instr->repeat;
135 cat0->ss = !!(instr->flags & IR3_INSTR_SS);
136 cat0->inv = instr->cat0.inv;
137 cat0->comp = instr->cat0.comp;
138 cat0->opc = instr->opc;
139 cat0->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
140 cat0->sync = !!(instr->flags & IR3_INSTR_SY);
141 cat0->opc_cat = 0;
142
143 return 0;
144 }
145
146 static uint32_t type_flags(type_t type)
147 {
148 return (type_size(type) == 32) ? 0 : IR3_REG_HALF;
149 }
150
151 static int emit_cat1(struct ir3_instruction *instr, void *ptr,
152 struct ir3_info *info)
153 {
154 struct ir3_register *dst = instr->regs[0];
155 struct ir3_register *src = instr->regs[1];
156 instr_cat1_t *cat1 = ptr;
157
158 iassert(instr->regs_count == 2);
159 iassert(!((dst->flags ^ type_flags(instr->cat1.dst_type)) & IR3_REG_HALF));
160 iassert((src->flags & IR3_REG_IMMED) ||
161 !((src->flags ^ type_flags(instr->cat1.src_type)) & IR3_REG_HALF));
162
163 if (src->flags & IR3_REG_IMMED) {
164 cat1->iim_val = src->iim_val;
165 cat1->src_im = 1;
166 } else if (src->flags & IR3_REG_RELATIV) {
167 cat1->off = src->offset;
168 cat1->src_rel = 1;
169 cat1->src_rel_c = !!(src->flags & IR3_REG_CONST);
170 } else {
171 cat1->src = reg(src, info, instr->repeat,
172 IR3_REG_IMMED | IR3_REG_R |
173 IR3_REG_CONST | IR3_REG_HALF);
174 cat1->src_c = !!(src->flags & IR3_REG_CONST);
175 }
176
177 cat1->dst = reg(dst, info, instr->repeat,
178 IR3_REG_RELATIV | IR3_REG_EVEN |
179 IR3_REG_R | IR3_REG_POS_INF | IR3_REG_HALF);
180 cat1->repeat = instr->repeat;
181 cat1->src_r = !!(src->flags & IR3_REG_R);
182 cat1->ss = !!(instr->flags & IR3_INSTR_SS);
183 cat1->ul = !!(instr->flags & IR3_INSTR_UL);
184 cat1->dst_type = instr->cat1.dst_type;
185 cat1->dst_rel = !!(dst->flags & IR3_REG_RELATIV);
186 cat1->src_type = instr->cat1.src_type;
187 cat1->even = !!(dst->flags & IR3_REG_EVEN);
188 cat1->pos_inf = !!(dst->flags & IR3_REG_POS_INF);
189 cat1->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
190 cat1->sync = !!(instr->flags & IR3_INSTR_SY);
191 cat1->opc_cat = 1;
192
193 return 0;
194 }
195
196 static int emit_cat2(struct ir3_instruction *instr, void *ptr,
197 struct ir3_info *info)
198 {
199 struct ir3_register *dst = instr->regs[0];
200 struct ir3_register *src1 = instr->regs[1];
201 struct ir3_register *src2 = instr->regs[2];
202 instr_cat2_t *cat2 = ptr;
203
204 iassert((instr->regs_count == 2) || (instr->regs_count == 3));
205
206 if (src1->flags & IR3_REG_RELATIV) {
207 iassert(src1->num < (1 << 10));
208 cat2->rel1.src1 = reg(src1, info, instr->repeat,
209 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_NEGATE |
210 IR3_REG_ABS | IR3_REG_R | IR3_REG_HALF);
211 cat2->rel1.src1_c = !!(src1->flags & IR3_REG_CONST);
212 cat2->rel1.src1_rel = 1;
213 } else if (src1->flags & IR3_REG_CONST) {
214 iassert(src1->num < (1 << 12));
215 cat2->c1.src1 = reg(src1, info, instr->repeat,
216 IR3_REG_CONST | IR3_REG_NEGATE | IR3_REG_ABS |
217 IR3_REG_R | IR3_REG_HALF);
218 cat2->c1.src1_c = 1;
219 } else {
220 iassert(src1->num < (1 << 11));
221 cat2->src1 = reg(src1, info, instr->repeat,
222 IR3_REG_IMMED | IR3_REG_NEGATE | IR3_REG_ABS |
223 IR3_REG_R | IR3_REG_HALF);
224 }
225 cat2->src1_im = !!(src1->flags & IR3_REG_IMMED);
226 cat2->src1_neg = !!(src1->flags & IR3_REG_NEGATE);
227 cat2->src1_abs = !!(src1->flags & IR3_REG_ABS);
228 cat2->src1_r = !!(src1->flags & IR3_REG_R);
229
230 if (src2) {
231 iassert((src2->flags & IR3_REG_IMMED) ||
232 !((src1->flags ^ src2->flags) & IR3_REG_HALF));
233
234 if (src2->flags & IR3_REG_RELATIV) {
235 iassert(src2->num < (1 << 10));
236 cat2->rel2.src2 = reg(src2, info, instr->repeat,
237 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_NEGATE |
238 IR3_REG_ABS | IR3_REG_R | IR3_REG_HALF);
239 cat2->rel2.src2_c = !!(src2->flags & IR3_REG_CONST);
240 cat2->rel2.src2_rel = 1;
241 } else if (src2->flags & IR3_REG_CONST) {
242 iassert(src2->num < (1 << 12));
243 cat2->c2.src2 = reg(src2, info, instr->repeat,
244 IR3_REG_CONST | IR3_REG_NEGATE | IR3_REG_ABS |
245 IR3_REG_R | IR3_REG_HALF);
246 cat2->c2.src2_c = 1;
247 } else {
248 iassert(src2->num < (1 << 11));
249 cat2->src2 = reg(src2, info, instr->repeat,
250 IR3_REG_IMMED | IR3_REG_NEGATE | IR3_REG_ABS |
251 IR3_REG_R | IR3_REG_HALF);
252 }
253
254 cat2->src2_im = !!(src2->flags & IR3_REG_IMMED);
255 cat2->src2_neg = !!(src2->flags & IR3_REG_NEGATE);
256 cat2->src2_abs = !!(src2->flags & IR3_REG_ABS);
257 cat2->src2_r = !!(src2->flags & IR3_REG_R);
258 }
259
260 cat2->dst = reg(dst, info, instr->repeat,
261 IR3_REG_R | IR3_REG_EI | IR3_REG_HALF);
262 cat2->repeat = instr->repeat;
263 cat2->ss = !!(instr->flags & IR3_INSTR_SS);
264 cat2->ul = !!(instr->flags & IR3_INSTR_UL);
265 cat2->dst_half = !!((src1->flags ^ dst->flags) & IR3_REG_HALF);
266 cat2->ei = !!(dst->flags & IR3_REG_EI);
267 cat2->cond = instr->cat2.condition;
268 cat2->full = ! (src1->flags & IR3_REG_HALF);
269 cat2->opc = instr->opc;
270 cat2->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
271 cat2->sync = !!(instr->flags & IR3_INSTR_SY);
272 cat2->opc_cat = 2;
273
274 return 0;
275 }
276
277 static int emit_cat3(struct ir3_instruction *instr, void *ptr,
278 struct ir3_info *info)
279 {
280 struct ir3_register *dst = instr->regs[0];
281 struct ir3_register *src1 = instr->regs[1];
282 struct ir3_register *src2 = instr->regs[2];
283 struct ir3_register *src3 = instr->regs[3];
284 instr_cat3_t *cat3 = ptr;
285 uint32_t src_flags = 0;
286
287 switch (instr->opc) {
288 case OPC_MAD_F16:
289 case OPC_MAD_U16:
290 case OPC_MAD_S16:
291 case OPC_SEL_B16:
292 case OPC_SEL_S16:
293 case OPC_SEL_F16:
294 case OPC_SAD_S16:
295 case OPC_SAD_S32: // really??
296 src_flags |= IR3_REG_HALF;
297 break;
298 default:
299 break;
300 }
301
302 iassert(instr->regs_count == 4);
303 iassert(!((src1->flags ^ src_flags) & IR3_REG_HALF));
304 iassert(!((src2->flags ^ src_flags) & IR3_REG_HALF));
305 iassert(!((src3->flags ^ src_flags) & IR3_REG_HALF));
306
307 if (src1->flags & IR3_REG_RELATIV) {
308 iassert(src1->num < (1 << 10));
309 cat3->rel1.src1 = reg(src1, info, instr->repeat,
310 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_NEGATE |
311 IR3_REG_R | IR3_REG_HALF);
312 cat3->rel1.src1_c = !!(src1->flags & IR3_REG_CONST);
313 cat3->rel1.src1_rel = 1;
314 } else if (src1->flags & IR3_REG_CONST) {
315 iassert(src1->num < (1 << 12));
316 cat3->c1.src1 = reg(src1, info, instr->repeat,
317 IR3_REG_CONST | IR3_REG_NEGATE | IR3_REG_R |
318 IR3_REG_HALF);
319 cat3->c1.src1_c = 1;
320 } else {
321 iassert(src1->num < (1 << 11));
322 cat3->src1 = reg(src1, info, instr->repeat,
323 IR3_REG_NEGATE | IR3_REG_R | IR3_REG_HALF);
324 }
325
326 cat3->src1_neg = !!(src1->flags & IR3_REG_NEGATE);
327 cat3->src1_r = !!(src1->flags & IR3_REG_R);
328
329 cat3->src2 = reg(src2, info, instr->repeat,
330 IR3_REG_CONST | IR3_REG_NEGATE |
331 IR3_REG_R | IR3_REG_HALF);
332 cat3->src2_c = !!(src2->flags & IR3_REG_CONST);
333 cat3->src2_neg = !!(src2->flags & IR3_REG_NEGATE);
334 cat3->src2_r = !!(src2->flags & IR3_REG_R);
335
336
337 if (src3->flags & IR3_REG_RELATIV) {
338 iassert(src3->num < (1 << 10));
339 cat3->rel2.src3 = reg(src3, info, instr->repeat,
340 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_NEGATE |
341 IR3_REG_R | IR3_REG_HALF);
342 cat3->rel2.src3_c = !!(src3->flags & IR3_REG_CONST);
343 cat3->rel2.src3_rel = 1;
344 } else if (src3->flags & IR3_REG_CONST) {
345 iassert(src3->num < (1 << 12));
346 cat3->c2.src3 = reg(src3, info, instr->repeat,
347 IR3_REG_CONST | IR3_REG_NEGATE | IR3_REG_R |
348 IR3_REG_HALF);
349 cat3->c2.src3_c = 1;
350 } else {
351 iassert(src3->num < (1 << 11));
352 cat3->src3 = reg(src3, info, instr->repeat,
353 IR3_REG_NEGATE | IR3_REG_R | IR3_REG_HALF);
354 }
355
356 cat3->src3_neg = !!(src3->flags & IR3_REG_NEGATE);
357 cat3->src3_r = !!(src3->flags & IR3_REG_R);
358
359 cat3->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
360 cat3->repeat = instr->repeat;
361 cat3->ss = !!(instr->flags & IR3_INSTR_SS);
362 cat3->ul = !!(instr->flags & IR3_INSTR_UL);
363 cat3->dst_half = !!((src_flags ^ dst->flags) & IR3_REG_HALF);
364 cat3->opc = instr->opc;
365 cat3->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
366 cat3->sync = !!(instr->flags & IR3_INSTR_SY);
367 cat3->opc_cat = 3;
368
369 return 0;
370 }
371
372 static int emit_cat4(struct ir3_instruction *instr, void *ptr,
373 struct ir3_info *info)
374 {
375 struct ir3_register *dst = instr->regs[0];
376 struct ir3_register *src = instr->regs[1];
377 instr_cat4_t *cat4 = ptr;
378
379 iassert(instr->regs_count == 2);
380
381 if (src->flags & IR3_REG_RELATIV) {
382 iassert(src->num < (1 << 10));
383 cat4->rel.src = reg(src, info, instr->repeat,
384 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_NEGATE |
385 IR3_REG_ABS | IR3_REG_R | IR3_REG_HALF);
386 cat4->rel.src_c = !!(src->flags & IR3_REG_CONST);
387 cat4->rel.src_rel = 1;
388 } else if (src->flags & IR3_REG_CONST) {
389 iassert(src->num < (1 << 12));
390 cat4->c.src = reg(src, info, instr->repeat,
391 IR3_REG_CONST | IR3_REG_NEGATE | IR3_REG_ABS |
392 IR3_REG_R | IR3_REG_HALF);
393 cat4->c.src_c = 1;
394 } else {
395 iassert(src->num < (1 << 11));
396 cat4->src = reg(src, info, instr->repeat,
397 IR3_REG_IMMED | IR3_REG_NEGATE | IR3_REG_ABS |
398 IR3_REG_R | IR3_REG_HALF);
399 }
400
401 cat4->src_im = !!(src->flags & IR3_REG_IMMED);
402 cat4->src_neg = !!(src->flags & IR3_REG_NEGATE);
403 cat4->src_abs = !!(src->flags & IR3_REG_ABS);
404 cat4->src_r = !!(src->flags & IR3_REG_R);
405
406 cat4->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
407 cat4->repeat = instr->repeat;
408 cat4->ss = !!(instr->flags & IR3_INSTR_SS);
409 cat4->ul = !!(instr->flags & IR3_INSTR_UL);
410 cat4->dst_half = !!((src->flags ^ dst->flags) & IR3_REG_HALF);
411 cat4->full = ! (src->flags & IR3_REG_HALF);
412 cat4->opc = instr->opc;
413 cat4->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
414 cat4->sync = !!(instr->flags & IR3_INSTR_SY);
415 cat4->opc_cat = 4;
416
417 return 0;
418 }
419
420 static int emit_cat5(struct ir3_instruction *instr, void *ptr,
421 struct ir3_info *info)
422 {
423 struct ir3_register *dst = instr->regs[0];
424 struct ir3_register *src1 = instr->regs[1];
425 struct ir3_register *src2 = instr->regs[2];
426 struct ir3_register *src3 = instr->regs[3];
427 instr_cat5_t *cat5 = ptr;
428
429 iassert(!((dst->flags ^ type_flags(instr->cat5.type)) & IR3_REG_HALF));
430
431 if (src1) {
432 cat5->full = ! (src1->flags & IR3_REG_HALF);
433 cat5->src1 = reg(src1, info, instr->repeat, IR3_REG_HALF);
434 }
435
436
437 if (instr->flags & IR3_INSTR_S2EN) {
438 if (src2) {
439 iassert(!((src1->flags ^ src2->flags) & IR3_REG_HALF));
440 cat5->s2en.src2 = reg(src2, info, instr->repeat, IR3_REG_HALF);
441 }
442 if (src3) {
443 iassert(src3->flags & IR3_REG_HALF);
444 cat5->s2en.src3 = reg(src3, info, instr->repeat, IR3_REG_HALF);
445 }
446 iassert(!(instr->cat5.samp | instr->cat5.tex));
447 } else {
448 iassert(!src3);
449 if (src2) {
450 iassert(!((src1->flags ^ src2->flags) & IR3_REG_HALF));
451 cat5->norm.src2 = reg(src2, info, instr->repeat, IR3_REG_HALF);
452 }
453 cat5->norm.samp = instr->cat5.samp;
454 cat5->norm.tex = instr->cat5.tex;
455 }
456
457 cat5->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
458 cat5->wrmask = dst->wrmask;
459 cat5->type = instr->cat5.type;
460 cat5->is_3d = !!(instr->flags & IR3_INSTR_3D);
461 cat5->is_a = !!(instr->flags & IR3_INSTR_A);
462 cat5->is_s = !!(instr->flags & IR3_INSTR_S);
463 cat5->is_s2en = !!(instr->flags & IR3_INSTR_S2EN);
464 cat5->is_o = !!(instr->flags & IR3_INSTR_O);
465 cat5->is_p = !!(instr->flags & IR3_INSTR_P);
466 cat5->opc = instr->opc;
467 cat5->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
468 cat5->sync = !!(instr->flags & IR3_INSTR_SY);
469 cat5->opc_cat = 5;
470
471 return 0;
472 }
473
474 static int emit_cat6(struct ir3_instruction *instr, void *ptr,
475 struct ir3_info *info)
476 {
477 struct ir3_register *dst = instr->regs[0];
478 struct ir3_register *src = instr->regs[1];
479 instr_cat6_t *cat6 = ptr;
480
481 iassert(instr->regs_count == 2);
482
483 switch (instr->opc) {
484 /* load instructions: */
485 case OPC_LDG:
486 case OPC_LDP:
487 case OPC_LDL:
488 case OPC_LDLW:
489 case OPC_LDLV:
490 case OPC_PREFETCH: {
491 instr_cat6a_t *cat6a = ptr;
492
493 iassert(!((dst->flags ^ type_flags(instr->cat6.type)) & IR3_REG_HALF));
494
495 cat6a->must_be_one1 = 1;
496 cat6a->must_be_one2 = 1;
497 cat6a->off = instr->cat6.offset;
498 cat6a->src = reg(src, info, instr->repeat, 0);
499 cat6a->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
500 break;
501 }
502 /* store instructions: */
503 case OPC_STG:
504 case OPC_STP:
505 case OPC_STL:
506 case OPC_STLW:
507 case OPC_STI: {
508 instr_cat6b_t *cat6b = ptr;
509 uint32_t src_flags = type_flags(instr->cat6.type);
510 uint32_t dst_flags = (instr->opc == OPC_STI) ? IR3_REG_HALF : 0;
511
512 iassert(!((src->flags ^ src_flags) & IR3_REG_HALF));
513
514 cat6b->must_be_one1 = 1;
515 cat6b->must_be_one2 = 1;
516 cat6b->src = reg(src, info, instr->repeat, src_flags);
517 cat6b->off_hi = instr->cat6.offset >> 8;
518 cat6b->off = instr->cat6.offset;
519 cat6b->dst = reg(dst, info, instr->repeat, IR3_REG_R | dst_flags);
520
521 break;
522 }
523 default:
524 // TODO
525 break;
526 }
527
528 cat6->iim_val = instr->cat6.iim_val;
529 cat6->type = instr->cat6.type;
530 cat6->opc = instr->opc;
531 cat6->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
532 cat6->sync = !!(instr->flags & IR3_INSTR_SY);
533 cat6->opc_cat = 6;
534
535 return 0;
536 }
537
538 static int (*emit[])(struct ir3_instruction *instr, void *ptr,
539 struct ir3_info *info) = {
540 emit_cat0, emit_cat1, emit_cat2, emit_cat3, emit_cat4, emit_cat5, emit_cat6,
541 };
542
543 void * ir3_assemble(struct ir3 *shader, struct ir3_info *info)
544 {
545 uint32_t *ptr, *dwords;
546 uint32_t i;
547
548 info->max_reg = -1;
549 info->max_half_reg = -1;
550 info->max_const = -1;
551 info->instrs_count = 0;
552
553 /* need a integer number of instruction "groups" (sets of four
554 * instructions), so pad out w/ NOPs if needed:
555 * (each instruction is 64bits)
556 */
557 info->sizedwords = 2 * align(shader->instrs_count, 4);
558
559 ptr = dwords = calloc(4, info->sizedwords);
560
561 for (i = 0; i < shader->instrs_count; i++) {
562 struct ir3_instruction *instr = shader->instrs[i];
563 int ret = emit[instr->category](instr, dwords, info);
564 if (ret)
565 goto fail;
566 info->instrs_count += 1 + instr->repeat;
567 dwords += 2;
568 }
569
570 return ptr;
571
572 fail:
573 free(ptr);
574 return NULL;
575 }
576
577 static struct ir3_register * reg_create(struct ir3 *shader,
578 int num, int flags)
579 {
580 struct ir3_register *reg =
581 ir3_alloc(shader, sizeof(struct ir3_register));
582 reg->wrmask = 1;
583 reg->flags = flags;
584 reg->num = num;
585 return reg;
586 }
587
588 static void insert_instr(struct ir3 *shader,
589 struct ir3_instruction *instr)
590 {
591 #ifdef DEBUG
592 static uint32_t serialno = 0;
593 instr->serialno = ++serialno;
594 #endif
595 if (shader->instrs_count == shader->instrs_sz) {
596 shader->instrs_sz = MAX2(2 * shader->instrs_sz, 16);
597 shader->instrs = realloc(shader->instrs,
598 shader->instrs_sz * sizeof(shader->instrs[0]));
599 }
600 shader->instrs[shader->instrs_count++] = instr;
601
602 if (is_input(instr)) {
603 if (shader->baryfs_count == shader->baryfs_sz) {
604 shader->baryfs_sz = MAX2(2 * shader->baryfs_sz, 16);
605 shader->baryfs = realloc(shader->baryfs,
606 shader->baryfs_sz * sizeof(shader->baryfs[0]));
607 }
608 shader->baryfs[shader->baryfs_count++] = instr;
609 }
610 }
611
612 struct ir3_block * ir3_block_create(struct ir3 *shader,
613 unsigned ntmp, unsigned nin, unsigned nout)
614 {
615 struct ir3_block *block;
616 unsigned size;
617 char *ptr;
618
619 size = sizeof(*block);
620 size += sizeof(block->temporaries[0]) * ntmp;
621 size += sizeof(block->inputs[0]) * nin;
622 size += sizeof(block->outputs[0]) * nout;
623
624 ptr = ir3_alloc(shader, size);
625
626 block = (void *)ptr;
627 ptr += sizeof(*block);
628
629 block->temporaries = (void *)ptr;
630 block->ntemporaries = ntmp;
631 ptr += sizeof(block->temporaries[0]) * ntmp;
632
633 block->inputs = (void *)ptr;
634 block->ninputs = nin;
635 ptr += sizeof(block->inputs[0]) * nin;
636
637 block->outputs = (void *)ptr;
638 block->noutputs = nout;
639 ptr += sizeof(block->outputs[0]) * nout;
640
641 block->shader = shader;
642
643 return block;
644 }
645
646 struct ir3_instruction * ir3_instr_create(struct ir3_block *block,
647 int category, opc_t opc)
648 {
649 struct ir3_instruction *instr =
650 ir3_alloc(block->shader, sizeof(struct ir3_instruction));
651 instr->block = block;
652 instr->category = category;
653 instr->opc = opc;
654 insert_instr(block->shader, instr);
655 return instr;
656 }
657
658 struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr)
659 {
660 struct ir3_instruction *new_instr =
661 ir3_alloc(instr->block->shader, sizeof(struct ir3_instruction));
662 unsigned i;
663
664 *new_instr = *instr;
665 insert_instr(instr->block->shader, new_instr);
666
667 /* clone registers: */
668 new_instr->regs_count = 0;
669 for (i = 0; i < instr->regs_count; i++) {
670 struct ir3_register *reg = instr->regs[i];
671 struct ir3_register *new_reg =
672 ir3_reg_create(new_instr, reg->num, reg->flags);
673 *new_reg = *reg;
674 }
675
676 return new_instr;
677 }
678
679 struct ir3_register * ir3_reg_create(struct ir3_instruction *instr,
680 int num, int flags)
681 {
682 struct ir3_register *reg = reg_create(instr->block->shader, num, flags);
683 assert(instr->regs_count < ARRAY_SIZE(instr->regs));
684 instr->regs[instr->regs_count++] = reg;
685 return reg;
686 }