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freedreno/ir3: large const support
[mesa.git] / src / gallium / drivers / freedreno / ir3 / ir3.c
1 /*
2 * Copyright (c) 2012 Rob Clark <robdclark@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include "ir3.h"
25
26 #include <stdlib.h>
27 #include <stdio.h>
28 #include <string.h>
29 #include <assert.h>
30 #include <stdbool.h>
31 #include <errno.h>
32
33 #include "freedreno_util.h"
34 #include "instr-a3xx.h"
35
36 #define CHUNK_SZ 1020
37
38 struct ir3_heap_chunk {
39 struct ir3_heap_chunk *next;
40 uint32_t heap[CHUNK_SZ];
41 };
42
43 static void grow_heap(struct ir3 *shader)
44 {
45 struct ir3_heap_chunk *chunk = calloc(1, sizeof(*chunk));
46 chunk->next = shader->chunk;
47 shader->chunk = chunk;
48 shader->heap_idx = 0;
49 }
50
51 /* simple allocator to carve allocations out of an up-front allocated heap,
52 * so that we can free everything easily in one shot.
53 */
54 void * ir3_alloc(struct ir3 *shader, int sz)
55 {
56 void *ptr;
57
58 sz = align(sz, 4) / 4;
59
60 if ((shader->heap_idx + sz) > CHUNK_SZ)
61 grow_heap(shader);
62
63 ptr = &shader->chunk->heap[shader->heap_idx];
64 shader->heap_idx += sz;
65
66 return ptr;
67 }
68
69 struct ir3 * ir3_create(void)
70 {
71 struct ir3 *shader =
72 calloc(1, sizeof(struct ir3));
73 grow_heap(shader);
74 return shader;
75 }
76
77 void ir3_destroy(struct ir3 *shader)
78 {
79 while (shader->chunk) {
80 struct ir3_heap_chunk *chunk = shader->chunk;
81 shader->chunk = chunk->next;
82 free(chunk);
83 }
84 free(shader);
85 }
86
87 #define iassert(cond) do { \
88 if (!(cond)) { \
89 assert(cond); \
90 return -1; \
91 } } while (0)
92
93 static uint32_t reg(struct ir3_register *reg, struct ir3_info *info,
94 uint32_t repeat, uint32_t valid_flags)
95 {
96 reg_t val = { .dummy32 = 0 };
97
98 assert(!(reg->flags & ~valid_flags));
99
100 if (!(reg->flags & IR3_REG_R))
101 repeat = 0;
102
103 if (reg->flags & IR3_REG_IMMED) {
104 val.iim_val = reg->iim_val;
105 } else {
106 int8_t components = util_last_bit(reg->wrmask);
107 int16_t max = (reg->num + repeat + components - 1) >> 2;
108
109 val.comp = reg->num & 0x3;
110 val.num = reg->num >> 2;
111
112 if (reg->flags & IR3_REG_CONST) {
113 info->max_const = MAX2(info->max_const, max);
114 } else if ((max != REG_A0) && (max != REG_P0)) {
115 if (reg->flags & IR3_REG_HALF) {
116 info->max_half_reg = MAX2(info->max_half_reg, max);
117 } else {
118 info->max_reg = MAX2(info->max_reg, max);
119 }
120 }
121 }
122
123 return val.dummy32;
124 }
125
126 static int emit_cat0(struct ir3_instruction *instr, void *ptr,
127 struct ir3_info *info)
128 {
129 instr_cat0_t *cat0 = ptr;
130
131 cat0->immed = instr->cat0.immed;
132 cat0->repeat = instr->repeat;
133 cat0->ss = !!(instr->flags & IR3_INSTR_SS);
134 cat0->inv = instr->cat0.inv;
135 cat0->comp = instr->cat0.comp;
136 cat0->opc = instr->opc;
137 cat0->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
138 cat0->sync = !!(instr->flags & IR3_INSTR_SY);
139 cat0->opc_cat = 0;
140
141 return 0;
142 }
143
144 static uint32_t type_flags(type_t type)
145 {
146 return (type_size(type) == 32) ? 0 : IR3_REG_HALF;
147 }
148
149 static int emit_cat1(struct ir3_instruction *instr, void *ptr,
150 struct ir3_info *info)
151 {
152 struct ir3_register *dst = instr->regs[0];
153 struct ir3_register *src = instr->regs[1];
154 instr_cat1_t *cat1 = ptr;
155
156 iassert(instr->regs_count == 2);
157 iassert(!((dst->flags ^ type_flags(instr->cat1.dst_type)) & IR3_REG_HALF));
158 iassert((src->flags & IR3_REG_IMMED) ||
159 !((src->flags ^ type_flags(instr->cat1.src_type)) & IR3_REG_HALF));
160
161 if (src->flags & IR3_REG_IMMED) {
162 cat1->iim_val = src->iim_val;
163 cat1->src_im = 1;
164 } else if (src->flags & IR3_REG_RELATIV) {
165 cat1->off = src->offset;
166 cat1->src_rel = 1;
167 cat1->src_rel_c = !!(src->flags & IR3_REG_CONST);
168 } else {
169 cat1->src = reg(src, info, instr->repeat,
170 IR3_REG_IMMED | IR3_REG_R |
171 IR3_REG_CONST | IR3_REG_HALF);
172 cat1->src_c = !!(src->flags & IR3_REG_CONST);
173 }
174
175 cat1->dst = reg(dst, info, instr->repeat,
176 IR3_REG_RELATIV | IR3_REG_EVEN |
177 IR3_REG_R | IR3_REG_POS_INF | IR3_REG_HALF);
178 cat1->repeat = instr->repeat;
179 cat1->src_r = !!(src->flags & IR3_REG_R);
180 cat1->ss = !!(instr->flags & IR3_INSTR_SS);
181 cat1->ul = !!(instr->flags & IR3_INSTR_UL);
182 cat1->dst_type = instr->cat1.dst_type;
183 cat1->dst_rel = !!(dst->flags & IR3_REG_RELATIV);
184 cat1->src_type = instr->cat1.src_type;
185 cat1->even = !!(dst->flags & IR3_REG_EVEN);
186 cat1->pos_inf = !!(dst->flags & IR3_REG_POS_INF);
187 cat1->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
188 cat1->sync = !!(instr->flags & IR3_INSTR_SY);
189 cat1->opc_cat = 1;
190
191 return 0;
192 }
193
194 static int emit_cat2(struct ir3_instruction *instr, void *ptr,
195 struct ir3_info *info)
196 {
197 struct ir3_register *dst = instr->regs[0];
198 struct ir3_register *src1 = instr->regs[1];
199 struct ir3_register *src2 = instr->regs[2];
200 instr_cat2_t *cat2 = ptr;
201
202 iassert((instr->regs_count == 2) || (instr->regs_count == 3));
203
204 if (src1->flags & IR3_REG_RELATIV) {
205 iassert(src1->num < (1 << 10));
206 cat2->rel1.src1 = reg(src1, info, instr->repeat,
207 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_NEGATE |
208 IR3_REG_ABS | IR3_REG_R | IR3_REG_HALF);
209 cat2->rel1.src1_c = !!(src1->flags & IR3_REG_CONST);
210 cat2->rel1.src1_rel = 1;
211 } else if (src1->flags & IR3_REG_CONST) {
212 iassert(src1->num < (1 << 12));
213 cat2->c1.src1 = reg(src1, info, instr->repeat,
214 IR3_REG_CONST | IR3_REG_NEGATE | IR3_REG_ABS |
215 IR3_REG_R | IR3_REG_HALF);
216 cat2->c1.src1_c = 1;
217 } else {
218 iassert(src1->num < (1 << 11));
219 cat2->src1 = reg(src1, info, instr->repeat,
220 IR3_REG_IMMED | IR3_REG_NEGATE | IR3_REG_ABS |
221 IR3_REG_R | IR3_REG_HALF);
222 }
223 cat2->src1_im = !!(src1->flags & IR3_REG_IMMED);
224 cat2->src1_neg = !!(src1->flags & IR3_REG_NEGATE);
225 cat2->src1_abs = !!(src1->flags & IR3_REG_ABS);
226 cat2->src1_r = !!(src1->flags & IR3_REG_R);
227
228 if (src2) {
229 iassert((src2->flags & IR3_REG_IMMED) ||
230 !((src1->flags ^ src2->flags) & IR3_REG_HALF));
231
232 if (src2->flags & IR3_REG_RELATIV) {
233 iassert(src2->num < (1 << 10));
234 cat2->rel2.src2 = reg(src2, info, instr->repeat,
235 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_NEGATE |
236 IR3_REG_ABS | IR3_REG_R | IR3_REG_HALF);
237 cat2->rel2.src2_c = !!(src2->flags & IR3_REG_CONST);
238 cat2->rel2.src2_rel = 1;
239 } else if (src2->flags & IR3_REG_CONST) {
240 iassert(src2->num < (1 << 12));
241 cat2->c2.src2 = reg(src2, info, instr->repeat,
242 IR3_REG_CONST | IR3_REG_NEGATE | IR3_REG_ABS |
243 IR3_REG_R | IR3_REG_HALF);
244 cat2->c2.src2_c = 1;
245 } else {
246 iassert(src2->num < (1 << 11));
247 cat2->src2 = reg(src2, info, instr->repeat,
248 IR3_REG_IMMED | IR3_REG_NEGATE | IR3_REG_ABS |
249 IR3_REG_R | IR3_REG_HALF);
250 }
251
252 cat2->src2_im = !!(src2->flags & IR3_REG_IMMED);
253 cat2->src2_neg = !!(src2->flags & IR3_REG_NEGATE);
254 cat2->src2_abs = !!(src2->flags & IR3_REG_ABS);
255 cat2->src2_r = !!(src2->flags & IR3_REG_R);
256 }
257
258 cat2->dst = reg(dst, info, instr->repeat,
259 IR3_REG_R | IR3_REG_EI | IR3_REG_HALF);
260 cat2->repeat = instr->repeat;
261 cat2->ss = !!(instr->flags & IR3_INSTR_SS);
262 cat2->ul = !!(instr->flags & IR3_INSTR_UL);
263 cat2->dst_half = !!((src1->flags ^ dst->flags) & IR3_REG_HALF);
264 cat2->ei = !!(dst->flags & IR3_REG_EI);
265 cat2->cond = instr->cat2.condition;
266 cat2->full = ! (src1->flags & IR3_REG_HALF);
267 cat2->opc = instr->opc;
268 cat2->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
269 cat2->sync = !!(instr->flags & IR3_INSTR_SY);
270 cat2->opc_cat = 2;
271
272 return 0;
273 }
274
275 static int emit_cat3(struct ir3_instruction *instr, void *ptr,
276 struct ir3_info *info)
277 {
278 struct ir3_register *dst = instr->regs[0];
279 struct ir3_register *src1 = instr->regs[1];
280 struct ir3_register *src2 = instr->regs[2];
281 struct ir3_register *src3 = instr->regs[3];
282 instr_cat3_t *cat3 = ptr;
283 uint32_t src_flags = 0;
284
285 switch (instr->opc) {
286 case OPC_MAD_F16:
287 case OPC_MAD_U16:
288 case OPC_MAD_S16:
289 case OPC_SEL_B16:
290 case OPC_SEL_S16:
291 case OPC_SEL_F16:
292 case OPC_SAD_S16:
293 case OPC_SAD_S32: // really??
294 src_flags |= IR3_REG_HALF;
295 break;
296 default:
297 break;
298 }
299
300 iassert(instr->regs_count == 4);
301 iassert(!((src1->flags ^ src_flags) & IR3_REG_HALF));
302 iassert(!((src2->flags ^ src_flags) & IR3_REG_HALF));
303 iassert(!((src3->flags ^ src_flags) & IR3_REG_HALF));
304
305 if (src1->flags & IR3_REG_RELATIV) {
306 iassert(src1->num < (1 << 10));
307 cat3->rel1.src1 = reg(src1, info, instr->repeat,
308 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_NEGATE |
309 IR3_REG_R | IR3_REG_HALF);
310 cat3->rel1.src1_c = !!(src1->flags & IR3_REG_CONST);
311 cat3->rel1.src1_rel = 1;
312 } else if (src1->flags & IR3_REG_CONST) {
313 iassert(src1->num < (1 << 12));
314 cat3->c1.src1 = reg(src1, info, instr->repeat,
315 IR3_REG_CONST | IR3_REG_NEGATE | IR3_REG_R |
316 IR3_REG_HALF);
317 cat3->c1.src1_c = 1;
318 } else {
319 iassert(src1->num < (1 << 11));
320 cat3->src1 = reg(src1, info, instr->repeat,
321 IR3_REG_NEGATE | IR3_REG_R | IR3_REG_HALF);
322 }
323
324 cat3->src1_neg = !!(src1->flags & IR3_REG_NEGATE);
325 cat3->src1_r = !!(src1->flags & IR3_REG_R);
326
327 cat3->src2 = reg(src2, info, instr->repeat,
328 IR3_REG_CONST | IR3_REG_NEGATE |
329 IR3_REG_R | IR3_REG_HALF);
330 cat3->src2_c = !!(src2->flags & IR3_REG_CONST);
331 cat3->src2_neg = !!(src2->flags & IR3_REG_NEGATE);
332 cat3->src2_r = !!(src2->flags & IR3_REG_R);
333
334
335 if (src3->flags & IR3_REG_RELATIV) {
336 iassert(src3->num < (1 << 10));
337 cat3->rel2.src3 = reg(src3, info, instr->repeat,
338 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_NEGATE |
339 IR3_REG_R | IR3_REG_HALF);
340 cat3->rel2.src3_c = !!(src3->flags & IR3_REG_CONST);
341 cat3->rel2.src3_rel = 1;
342 } else if (src3->flags & IR3_REG_CONST) {
343 iassert(src3->num < (1 << 12));
344 cat3->c2.src3 = reg(src3, info, instr->repeat,
345 IR3_REG_CONST | IR3_REG_NEGATE | IR3_REG_R |
346 IR3_REG_HALF);
347 cat3->c2.src3_c = 1;
348 } else {
349 iassert(src3->num < (1 << 11));
350 cat3->src3 = reg(src3, info, instr->repeat,
351 IR3_REG_NEGATE | IR3_REG_R | IR3_REG_HALF);
352 }
353
354 cat3->src3_neg = !!(src3->flags & IR3_REG_NEGATE);
355 cat3->src3_r = !!(src3->flags & IR3_REG_R);
356
357 cat3->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
358 cat3->repeat = instr->repeat;
359 cat3->ss = !!(instr->flags & IR3_INSTR_SS);
360 cat3->ul = !!(instr->flags & IR3_INSTR_UL);
361 cat3->dst_half = !!((src_flags ^ dst->flags) & IR3_REG_HALF);
362 cat3->opc = instr->opc;
363 cat3->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
364 cat3->sync = !!(instr->flags & IR3_INSTR_SY);
365 cat3->opc_cat = 3;
366
367 return 0;
368 }
369
370 static int emit_cat4(struct ir3_instruction *instr, void *ptr,
371 struct ir3_info *info)
372 {
373 struct ir3_register *dst = instr->regs[0];
374 struct ir3_register *src = instr->regs[1];
375 instr_cat4_t *cat4 = ptr;
376
377 iassert(instr->regs_count == 2);
378
379 if (src->flags & IR3_REG_RELATIV) {
380 iassert(src->num < (1 << 10));
381 cat4->rel.src = reg(src, info, instr->repeat,
382 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_NEGATE |
383 IR3_REG_ABS | IR3_REG_R | IR3_REG_HALF);
384 cat4->rel.src_c = !!(src->flags & IR3_REG_CONST);
385 cat4->rel.src_rel = 1;
386 } else if (src->flags & IR3_REG_CONST) {
387 iassert(src->num < (1 << 12));
388 cat4->c.src = reg(src, info, instr->repeat,
389 IR3_REG_CONST | IR3_REG_NEGATE | IR3_REG_ABS |
390 IR3_REG_R | IR3_REG_HALF);
391 cat4->c.src_c = 1;
392 } else {
393 iassert(src->num < (1 << 11));
394 cat4->src = reg(src, info, instr->repeat,
395 IR3_REG_IMMED | IR3_REG_NEGATE | IR3_REG_ABS |
396 IR3_REG_R | IR3_REG_HALF);
397 }
398
399 cat4->src_im = !!(src->flags & IR3_REG_IMMED);
400 cat4->src_neg = !!(src->flags & IR3_REG_NEGATE);
401 cat4->src_abs = !!(src->flags & IR3_REG_ABS);
402 cat4->src_r = !!(src->flags & IR3_REG_R);
403
404 cat4->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
405 cat4->repeat = instr->repeat;
406 cat4->ss = !!(instr->flags & IR3_INSTR_SS);
407 cat4->ul = !!(instr->flags & IR3_INSTR_UL);
408 cat4->dst_half = !!((src->flags ^ dst->flags) & IR3_REG_HALF);
409 cat4->full = ! (src->flags & IR3_REG_HALF);
410 cat4->opc = instr->opc;
411 cat4->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
412 cat4->sync = !!(instr->flags & IR3_INSTR_SY);
413 cat4->opc_cat = 4;
414
415 return 0;
416 }
417
418 static int emit_cat5(struct ir3_instruction *instr, void *ptr,
419 struct ir3_info *info)
420 {
421 struct ir3_register *dst = instr->regs[0];
422 struct ir3_register *src1 = instr->regs[1];
423 struct ir3_register *src2 = instr->regs[2];
424 struct ir3_register *src3 = instr->regs[3];
425 instr_cat5_t *cat5 = ptr;
426
427 iassert(!((dst->flags ^ type_flags(instr->cat5.type)) & IR3_REG_HALF));
428
429 if (src1) {
430 cat5->full = ! (src1->flags & IR3_REG_HALF);
431 cat5->src1 = reg(src1, info, instr->repeat, IR3_REG_HALF);
432 }
433
434
435 if (instr->flags & IR3_INSTR_S2EN) {
436 if (src2) {
437 iassert(!((src1->flags ^ src2->flags) & IR3_REG_HALF));
438 cat5->s2en.src2 = reg(src2, info, instr->repeat, IR3_REG_HALF);
439 }
440 if (src3) {
441 iassert(src3->flags & IR3_REG_HALF);
442 cat5->s2en.src3 = reg(src3, info, instr->repeat, IR3_REG_HALF);
443 }
444 iassert(!(instr->cat5.samp | instr->cat5.tex));
445 } else {
446 iassert(!src3);
447 if (src2) {
448 iassert(!((src1->flags ^ src2->flags) & IR3_REG_HALF));
449 cat5->norm.src2 = reg(src2, info, instr->repeat, IR3_REG_HALF);
450 }
451 cat5->norm.samp = instr->cat5.samp;
452 cat5->norm.tex = instr->cat5.tex;
453 }
454
455 cat5->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
456 cat5->wrmask = dst->wrmask;
457 cat5->type = instr->cat5.type;
458 cat5->is_3d = !!(instr->flags & IR3_INSTR_3D);
459 cat5->is_a = !!(instr->flags & IR3_INSTR_A);
460 cat5->is_s = !!(instr->flags & IR3_INSTR_S);
461 cat5->is_s2en = !!(instr->flags & IR3_INSTR_S2EN);
462 cat5->is_o = !!(instr->flags & IR3_INSTR_O);
463 cat5->is_p = !!(instr->flags & IR3_INSTR_P);
464 cat5->opc = instr->opc;
465 cat5->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
466 cat5->sync = !!(instr->flags & IR3_INSTR_SY);
467 cat5->opc_cat = 5;
468
469 return 0;
470 }
471
472 static int emit_cat6(struct ir3_instruction *instr, void *ptr,
473 struct ir3_info *info)
474 {
475 struct ir3_register *dst = instr->regs[0];
476 struct ir3_register *src = instr->regs[1];
477 instr_cat6_t *cat6 = ptr;
478
479 iassert(instr->regs_count == 2);
480
481 switch (instr->opc) {
482 /* load instructions: */
483 case OPC_LDG:
484 case OPC_LDP:
485 case OPC_LDL:
486 case OPC_LDLW:
487 case OPC_LDLV:
488 case OPC_PREFETCH: {
489 instr_cat6a_t *cat6a = ptr;
490
491 iassert(!((dst->flags ^ type_flags(instr->cat6.type)) & IR3_REG_HALF));
492
493 cat6a->must_be_one1 = 1;
494 cat6a->must_be_one2 = 1;
495 cat6a->off = instr->cat6.offset;
496 cat6a->src = reg(src, info, instr->repeat, 0);
497 cat6a->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
498 break;
499 }
500 /* store instructions: */
501 case OPC_STG:
502 case OPC_STP:
503 case OPC_STL:
504 case OPC_STLW:
505 case OPC_STI: {
506 instr_cat6b_t *cat6b = ptr;
507 uint32_t src_flags = type_flags(instr->cat6.type);
508 uint32_t dst_flags = (instr->opc == OPC_STI) ? IR3_REG_HALF : 0;
509
510 iassert(!((src->flags ^ src_flags) & IR3_REG_HALF));
511
512 cat6b->must_be_one1 = 1;
513 cat6b->must_be_one2 = 1;
514 cat6b->src = reg(src, info, instr->repeat, src_flags);
515 cat6b->off_hi = instr->cat6.offset >> 8;
516 cat6b->off = instr->cat6.offset;
517 cat6b->dst = reg(dst, info, instr->repeat, IR3_REG_R | dst_flags);
518
519 break;
520 }
521 default:
522 // TODO
523 break;
524 }
525
526 cat6->iim_val = instr->cat6.iim_val;
527 cat6->type = instr->cat6.type;
528 cat6->opc = instr->opc;
529 cat6->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
530 cat6->sync = !!(instr->flags & IR3_INSTR_SY);
531 cat6->opc_cat = 6;
532
533 return 0;
534 }
535
536 static int (*emit[])(struct ir3_instruction *instr, void *ptr,
537 struct ir3_info *info) = {
538 emit_cat0, emit_cat1, emit_cat2, emit_cat3, emit_cat4, emit_cat5, emit_cat6,
539 };
540
541 void * ir3_assemble(struct ir3 *shader, struct ir3_info *info)
542 {
543 uint32_t *ptr, *dwords;
544 uint32_t i;
545
546 info->max_reg = -1;
547 info->max_half_reg = -1;
548 info->max_const = -1;
549 info->instrs_count = 0;
550
551 /* need a integer number of instruction "groups" (sets of four
552 * instructions), so pad out w/ NOPs if needed:
553 * (each instruction is 64bits)
554 */
555 info->sizedwords = 2 * align(shader->instrs_count, 4);
556
557 ptr = dwords = calloc(4, info->sizedwords);
558
559 for (i = 0; i < shader->instrs_count; i++) {
560 struct ir3_instruction *instr = shader->instrs[i];
561 int ret = emit[instr->category](instr, dwords, info);
562 if (ret)
563 goto fail;
564 info->instrs_count += 1 + instr->repeat;
565 dwords += 2;
566 }
567
568 return ptr;
569
570 fail:
571 free(ptr);
572 return NULL;
573 }
574
575 static struct ir3_register * reg_create(struct ir3 *shader,
576 int num, int flags)
577 {
578 struct ir3_register *reg =
579 ir3_alloc(shader, sizeof(struct ir3_register));
580 reg->wrmask = 1;
581 reg->flags = flags;
582 reg->num = num;
583 return reg;
584 }
585
586 static void insert_instr(struct ir3 *shader,
587 struct ir3_instruction *instr)
588 {
589 #ifdef DEBUG
590 static uint32_t serialno = 0;
591 instr->serialno = ++serialno;
592 #endif
593 if (shader->instrs_count == shader->instrs_sz) {
594 shader->instrs_sz = MAX2(2 * shader->instrs_sz, 16);
595 shader->instrs = realloc(shader->instrs,
596 shader->instrs_sz * sizeof(shader->instrs[0]));
597 }
598 shader->instrs[shader->instrs_count++] = instr;
599 }
600
601 struct ir3_block * ir3_block_create(struct ir3 *shader,
602 unsigned ntmp, unsigned nin, unsigned nout)
603 {
604 struct ir3_block *block;
605 unsigned size;
606 char *ptr;
607
608 size = sizeof(*block);
609 size += sizeof(block->temporaries[0]) * ntmp;
610 size += sizeof(block->inputs[0]) * nin;
611 size += sizeof(block->outputs[0]) * nout;
612
613 ptr = ir3_alloc(shader, size);
614
615 block = (void *)ptr;
616 ptr += sizeof(*block);
617
618 block->temporaries = (void *)ptr;
619 block->ntemporaries = ntmp;
620 ptr += sizeof(block->temporaries[0]) * ntmp;
621
622 block->inputs = (void *)ptr;
623 block->ninputs = nin;
624 ptr += sizeof(block->inputs[0]) * nin;
625
626 block->outputs = (void *)ptr;
627 block->noutputs = nout;
628 ptr += sizeof(block->outputs[0]) * nout;
629
630 block->shader = shader;
631
632 return block;
633 }
634
635 struct ir3_instruction * ir3_instr_create(struct ir3_block *block,
636 int category, opc_t opc)
637 {
638 struct ir3_instruction *instr =
639 ir3_alloc(block->shader, sizeof(struct ir3_instruction));
640 instr->block = block;
641 instr->category = category;
642 instr->opc = opc;
643 insert_instr(block->shader, instr);
644 return instr;
645 }
646
647 struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr)
648 {
649 struct ir3_instruction *new_instr =
650 ir3_alloc(instr->block->shader, sizeof(struct ir3_instruction));
651 unsigned i;
652
653 *new_instr = *instr;
654 insert_instr(instr->block->shader, new_instr);
655
656 /* clone registers: */
657 new_instr->regs_count = 0;
658 for (i = 0; i < instr->regs_count; i++) {
659 struct ir3_register *reg = instr->regs[i];
660 struct ir3_register *new_reg =
661 ir3_reg_create(new_instr, reg->num, reg->flags);
662 *new_reg = *reg;
663 }
664
665 return new_instr;
666 }
667
668 struct ir3_register * ir3_reg_create(struct ir3_instruction *instr,
669 int num, int flags)
670 {
671 struct ir3_register *reg = reg_create(instr->block->shader, num, flags);
672 assert(instr->regs_count < ARRAY_SIZE(instr->regs));
673 instr->regs[instr->regs_count++] = reg;
674 return reg;
675 }