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ralloc: use rzalloc where it's necessary
[mesa.git] / src / gallium / drivers / freedreno / ir3 / ir3.c
1 /*
2 * Copyright (c) 2012 Rob Clark <robdclark@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include "ir3.h"
25
26 #include <stdlib.h>
27 #include <stdio.h>
28 #include <string.h>
29 #include <assert.h>
30 #include <stdbool.h>
31 #include <errno.h>
32
33 #include "util/ralloc.h"
34
35 #include "freedreno_util.h"
36 #include "instr-a3xx.h"
37
38 /* simple allocator to carve allocations out of an up-front allocated heap,
39 * so that we can free everything easily in one shot.
40 */
41 void * ir3_alloc(struct ir3 *shader, int sz)
42 {
43 return rzalloc_size(shader, sz); /* TODO: don't use rzalloc */
44 }
45
46 struct ir3 * ir3_create(struct ir3_compiler *compiler,
47 unsigned nin, unsigned nout)
48 {
49 struct ir3 *shader = ralloc(compiler, struct ir3);
50
51 shader->compiler = compiler;
52 shader->ninputs = nin;
53 shader->inputs = ir3_alloc(shader, sizeof(shader->inputs[0]) * nin);
54
55 shader->noutputs = nout;
56 shader->outputs = ir3_alloc(shader, sizeof(shader->outputs[0]) * nout);
57
58 list_inithead(&shader->block_list);
59 list_inithead(&shader->array_list);
60
61 return shader;
62 }
63
64 void ir3_destroy(struct ir3 *shader)
65 {
66 /* TODO convert the dynamic array to ralloc too: */
67 free(shader->indirects);
68 free(shader->predicates);
69 free(shader->baryfs);
70 free(shader->keeps);
71 free(shader->astc_srgb);
72 ralloc_free(shader);
73 }
74
75 #define iassert(cond) do { \
76 if (!(cond)) { \
77 assert(cond); \
78 return -1; \
79 } } while (0)
80
81 static uint32_t reg(struct ir3_register *reg, struct ir3_info *info,
82 uint32_t repeat, uint32_t valid_flags)
83 {
84 reg_t val = { .dummy32 = 0 };
85
86 if (reg->flags & ~valid_flags) {
87 debug_printf("INVALID FLAGS: %x vs %x\n",
88 reg->flags, valid_flags);
89 }
90
91 if (!(reg->flags & IR3_REG_R))
92 repeat = 0;
93
94 if (reg->flags & IR3_REG_IMMED) {
95 val.iim_val = reg->iim_val;
96 } else {
97 unsigned components;
98 int16_t max;
99
100 if (reg->flags & IR3_REG_RELATIV) {
101 components = reg->size;
102 val.idummy10 = reg->array.offset;
103 max = (reg->array.offset + repeat + components - 1) >> 2;
104 } else {
105 components = util_last_bit(reg->wrmask);
106 val.comp = reg->num & 0x3;
107 val.num = reg->num >> 2;
108 max = (reg->num + repeat + components - 1) >> 2;
109 }
110
111 if (reg->flags & IR3_REG_CONST) {
112 info->max_const = MAX2(info->max_const, max);
113 } else if (val.num == 63) {
114 /* ignore writes to dummy register r63.x */
115 } else if ((max != REG_A0) && (max != REG_P0)) {
116 if (reg->flags & IR3_REG_HALF) {
117 info->max_half_reg = MAX2(info->max_half_reg, max);
118 } else {
119 info->max_reg = MAX2(info->max_reg, max);
120 }
121 }
122 }
123
124 return val.dummy32;
125 }
126
127 static int emit_cat0(struct ir3_instruction *instr, void *ptr,
128 struct ir3_info *info)
129 {
130 instr_cat0_t *cat0 = ptr;
131
132 if (info->gpu_id >= 400) {
133 cat0->a4xx.immed = instr->cat0.immed;
134 } else {
135 cat0->a3xx.immed = instr->cat0.immed;
136 }
137 cat0->repeat = instr->repeat;
138 cat0->ss = !!(instr->flags & IR3_INSTR_SS);
139 cat0->inv = instr->cat0.inv;
140 cat0->comp = instr->cat0.comp;
141 cat0->opc = instr->opc;
142 cat0->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
143 cat0->sync = !!(instr->flags & IR3_INSTR_SY);
144 cat0->opc_cat = 0;
145
146 return 0;
147 }
148
149 static uint32_t type_flags(type_t type)
150 {
151 return (type_size(type) == 32) ? 0 : IR3_REG_HALF;
152 }
153
154 static int emit_cat1(struct ir3_instruction *instr, void *ptr,
155 struct ir3_info *info)
156 {
157 struct ir3_register *dst = instr->regs[0];
158 struct ir3_register *src = instr->regs[1];
159 instr_cat1_t *cat1 = ptr;
160
161 iassert(instr->regs_count == 2);
162 iassert(!((dst->flags ^ type_flags(instr->cat1.dst_type)) & IR3_REG_HALF));
163 iassert((src->flags & IR3_REG_IMMED) ||
164 !((src->flags ^ type_flags(instr->cat1.src_type)) & IR3_REG_HALF));
165
166 if (src->flags & IR3_REG_IMMED) {
167 cat1->iim_val = src->iim_val;
168 cat1->src_im = 1;
169 } else if (src->flags & IR3_REG_RELATIV) {
170 cat1->off = reg(src, info, instr->repeat,
171 IR3_REG_R | IR3_REG_CONST | IR3_REG_HALF | IR3_REG_RELATIV);
172 cat1->src_rel = 1;
173 cat1->src_rel_c = !!(src->flags & IR3_REG_CONST);
174 } else {
175 cat1->src = reg(src, info, instr->repeat,
176 IR3_REG_R | IR3_REG_CONST | IR3_REG_HALF);
177 cat1->src_c = !!(src->flags & IR3_REG_CONST);
178 }
179
180 cat1->dst = reg(dst, info, instr->repeat,
181 IR3_REG_RELATIV | IR3_REG_EVEN |
182 IR3_REG_R | IR3_REG_POS_INF | IR3_REG_HALF);
183 cat1->repeat = instr->repeat;
184 cat1->src_r = !!(src->flags & IR3_REG_R);
185 cat1->ss = !!(instr->flags & IR3_INSTR_SS);
186 cat1->ul = !!(instr->flags & IR3_INSTR_UL);
187 cat1->dst_type = instr->cat1.dst_type;
188 cat1->dst_rel = !!(dst->flags & IR3_REG_RELATIV);
189 cat1->src_type = instr->cat1.src_type;
190 cat1->even = !!(dst->flags & IR3_REG_EVEN);
191 cat1->pos_inf = !!(dst->flags & IR3_REG_POS_INF);
192 cat1->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
193 cat1->sync = !!(instr->flags & IR3_INSTR_SY);
194 cat1->opc_cat = 1;
195
196 return 0;
197 }
198
199 static int emit_cat2(struct ir3_instruction *instr, void *ptr,
200 struct ir3_info *info)
201 {
202 struct ir3_register *dst = instr->regs[0];
203 struct ir3_register *src1 = instr->regs[1];
204 struct ir3_register *src2 = instr->regs[2];
205 instr_cat2_t *cat2 = ptr;
206 unsigned absneg = ir3_cat2_absneg(instr->opc);
207
208 iassert((instr->regs_count == 2) || (instr->regs_count == 3));
209
210 if (src1->flags & IR3_REG_RELATIV) {
211 iassert(src1->array.offset < (1 << 10));
212 cat2->rel1.src1 = reg(src1, info, instr->repeat,
213 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_R |
214 IR3_REG_HALF | absneg);
215 cat2->rel1.src1_c = !!(src1->flags & IR3_REG_CONST);
216 cat2->rel1.src1_rel = 1;
217 } else if (src1->flags & IR3_REG_CONST) {
218 iassert(src1->num < (1 << 12));
219 cat2->c1.src1 = reg(src1, info, instr->repeat,
220 IR3_REG_CONST | IR3_REG_R | IR3_REG_HALF);
221 cat2->c1.src1_c = 1;
222 } else {
223 iassert(src1->num < (1 << 11));
224 cat2->src1 = reg(src1, info, instr->repeat,
225 IR3_REG_IMMED | IR3_REG_R | IR3_REG_HALF |
226 absneg);
227 }
228 cat2->src1_im = !!(src1->flags & IR3_REG_IMMED);
229 cat2->src1_neg = !!(src1->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT));
230 cat2->src1_abs = !!(src1->flags & (IR3_REG_FABS | IR3_REG_SABS));
231 cat2->src1_r = !!(src1->flags & IR3_REG_R);
232
233 if (src2) {
234 iassert((src2->flags & IR3_REG_IMMED) ||
235 !((src1->flags ^ src2->flags) & IR3_REG_HALF));
236
237 if (src2->flags & IR3_REG_RELATIV) {
238 iassert(src2->array.offset < (1 << 10));
239 cat2->rel2.src2 = reg(src2, info, instr->repeat,
240 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_R |
241 IR3_REG_HALF | absneg);
242 cat2->rel2.src2_c = !!(src2->flags & IR3_REG_CONST);
243 cat2->rel2.src2_rel = 1;
244 } else if (src2->flags & IR3_REG_CONST) {
245 iassert(src2->num < (1 << 12));
246 cat2->c2.src2 = reg(src2, info, instr->repeat,
247 IR3_REG_CONST | IR3_REG_R | IR3_REG_HALF);
248 cat2->c2.src2_c = 1;
249 } else {
250 iassert(src2->num < (1 << 11));
251 cat2->src2 = reg(src2, info, instr->repeat,
252 IR3_REG_IMMED | IR3_REG_R | IR3_REG_HALF |
253 absneg);
254 }
255
256 cat2->src2_im = !!(src2->flags & IR3_REG_IMMED);
257 cat2->src2_neg = !!(src2->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT));
258 cat2->src2_abs = !!(src2->flags & (IR3_REG_FABS | IR3_REG_SABS));
259 cat2->src2_r = !!(src2->flags & IR3_REG_R);
260 }
261
262 cat2->dst = reg(dst, info, instr->repeat,
263 IR3_REG_R | IR3_REG_EI | IR3_REG_HALF);
264 cat2->repeat = instr->repeat;
265 cat2->ss = !!(instr->flags & IR3_INSTR_SS);
266 cat2->ul = !!(instr->flags & IR3_INSTR_UL);
267 cat2->dst_half = !!((src1->flags ^ dst->flags) & IR3_REG_HALF);
268 cat2->ei = !!(dst->flags & IR3_REG_EI);
269 cat2->cond = instr->cat2.condition;
270 cat2->full = ! (src1->flags & IR3_REG_HALF);
271 cat2->opc = instr->opc;
272 cat2->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
273 cat2->sync = !!(instr->flags & IR3_INSTR_SY);
274 cat2->opc_cat = 2;
275
276 return 0;
277 }
278
279 static int emit_cat3(struct ir3_instruction *instr, void *ptr,
280 struct ir3_info *info)
281 {
282 struct ir3_register *dst = instr->regs[0];
283 struct ir3_register *src1 = instr->regs[1];
284 struct ir3_register *src2 = instr->regs[2];
285 struct ir3_register *src3 = instr->regs[3];
286 unsigned absneg = ir3_cat3_absneg(instr->opc);
287 instr_cat3_t *cat3 = ptr;
288 uint32_t src_flags = 0;
289
290 switch (instr->opc) {
291 case OPC_MAD_F16:
292 case OPC_MAD_U16:
293 case OPC_MAD_S16:
294 case OPC_SEL_B16:
295 case OPC_SEL_S16:
296 case OPC_SEL_F16:
297 case OPC_SAD_S16:
298 case OPC_SAD_S32: // really??
299 src_flags |= IR3_REG_HALF;
300 break;
301 default:
302 break;
303 }
304
305 iassert(instr->regs_count == 4);
306 iassert(!((src1->flags ^ src_flags) & IR3_REG_HALF));
307 iassert(!((src2->flags ^ src_flags) & IR3_REG_HALF));
308 iassert(!((src3->flags ^ src_flags) & IR3_REG_HALF));
309
310 if (src1->flags & IR3_REG_RELATIV) {
311 iassert(src1->array.offset < (1 << 10));
312 cat3->rel1.src1 = reg(src1, info, instr->repeat,
313 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_R |
314 IR3_REG_HALF | absneg);
315 cat3->rel1.src1_c = !!(src1->flags & IR3_REG_CONST);
316 cat3->rel1.src1_rel = 1;
317 } else if (src1->flags & IR3_REG_CONST) {
318 iassert(src1->num < (1 << 12));
319 cat3->c1.src1 = reg(src1, info, instr->repeat,
320 IR3_REG_CONST | IR3_REG_R | IR3_REG_HALF);
321 cat3->c1.src1_c = 1;
322 } else {
323 iassert(src1->num < (1 << 11));
324 cat3->src1 = reg(src1, info, instr->repeat,
325 IR3_REG_R | IR3_REG_HALF | absneg);
326 }
327
328 cat3->src1_neg = !!(src1->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT));
329 cat3->src1_r = !!(src1->flags & IR3_REG_R);
330
331 cat3->src2 = reg(src2, info, instr->repeat,
332 IR3_REG_CONST | IR3_REG_R | IR3_REG_HALF | absneg);
333 cat3->src2_c = !!(src2->flags & IR3_REG_CONST);
334 cat3->src2_neg = !!(src2->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT));
335 cat3->src2_r = !!(src2->flags & IR3_REG_R);
336
337
338 if (src3->flags & IR3_REG_RELATIV) {
339 iassert(src3->array.offset < (1 << 10));
340 cat3->rel2.src3 = reg(src3, info, instr->repeat,
341 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_R |
342 IR3_REG_HALF | absneg);
343 cat3->rel2.src3_c = !!(src3->flags & IR3_REG_CONST);
344 cat3->rel2.src3_rel = 1;
345 } else if (src3->flags & IR3_REG_CONST) {
346 iassert(src3->num < (1 << 12));
347 cat3->c2.src3 = reg(src3, info, instr->repeat,
348 IR3_REG_CONST | IR3_REG_R | IR3_REG_HALF);
349 cat3->c2.src3_c = 1;
350 } else {
351 iassert(src3->num < (1 << 11));
352 cat3->src3 = reg(src3, info, instr->repeat,
353 IR3_REG_R | IR3_REG_HALF | absneg);
354 }
355
356 cat3->src3_neg = !!(src3->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT));
357 cat3->src3_r = !!(src3->flags & IR3_REG_R);
358
359 cat3->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
360 cat3->repeat = instr->repeat;
361 cat3->ss = !!(instr->flags & IR3_INSTR_SS);
362 cat3->ul = !!(instr->flags & IR3_INSTR_UL);
363 cat3->dst_half = !!((src_flags ^ dst->flags) & IR3_REG_HALF);
364 cat3->opc = instr->opc;
365 cat3->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
366 cat3->sync = !!(instr->flags & IR3_INSTR_SY);
367 cat3->opc_cat = 3;
368
369 return 0;
370 }
371
372 static int emit_cat4(struct ir3_instruction *instr, void *ptr,
373 struct ir3_info *info)
374 {
375 struct ir3_register *dst = instr->regs[0];
376 struct ir3_register *src = instr->regs[1];
377 instr_cat4_t *cat4 = ptr;
378
379 iassert(instr->regs_count == 2);
380
381 if (src->flags & IR3_REG_RELATIV) {
382 iassert(src->array.offset < (1 << 10));
383 cat4->rel.src = reg(src, info, instr->repeat,
384 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_FNEG |
385 IR3_REG_FABS | IR3_REG_R | IR3_REG_HALF);
386 cat4->rel.src_c = !!(src->flags & IR3_REG_CONST);
387 cat4->rel.src_rel = 1;
388 } else if (src->flags & IR3_REG_CONST) {
389 iassert(src->num < (1 << 12));
390 cat4->c.src = reg(src, info, instr->repeat,
391 IR3_REG_CONST | IR3_REG_FNEG | IR3_REG_FABS |
392 IR3_REG_R | IR3_REG_HALF);
393 cat4->c.src_c = 1;
394 } else {
395 iassert(src->num < (1 << 11));
396 cat4->src = reg(src, info, instr->repeat,
397 IR3_REG_IMMED | IR3_REG_FNEG | IR3_REG_FABS |
398 IR3_REG_R | IR3_REG_HALF);
399 }
400
401 cat4->src_im = !!(src->flags & IR3_REG_IMMED);
402 cat4->src_neg = !!(src->flags & IR3_REG_FNEG);
403 cat4->src_abs = !!(src->flags & IR3_REG_FABS);
404 cat4->src_r = !!(src->flags & IR3_REG_R);
405
406 cat4->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
407 cat4->repeat = instr->repeat;
408 cat4->ss = !!(instr->flags & IR3_INSTR_SS);
409 cat4->ul = !!(instr->flags & IR3_INSTR_UL);
410 cat4->dst_half = !!((src->flags ^ dst->flags) & IR3_REG_HALF);
411 cat4->full = ! (src->flags & IR3_REG_HALF);
412 cat4->opc = instr->opc;
413 cat4->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
414 cat4->sync = !!(instr->flags & IR3_INSTR_SY);
415 cat4->opc_cat = 4;
416
417 return 0;
418 }
419
420 static int emit_cat5(struct ir3_instruction *instr, void *ptr,
421 struct ir3_info *info)
422 {
423 struct ir3_register *dst = instr->regs[0];
424 struct ir3_register *src1 = instr->regs[1];
425 struct ir3_register *src2 = instr->regs[2];
426 struct ir3_register *src3 = instr->regs[3];
427 instr_cat5_t *cat5 = ptr;
428
429 iassert(!((dst->flags ^ type_flags(instr->cat5.type)) & IR3_REG_HALF));
430
431 assume(src1 || !src2);
432 assume(src2 || !src3);
433
434 if (src1) {
435 cat5->full = ! (src1->flags & IR3_REG_HALF);
436 cat5->src1 = reg(src1, info, instr->repeat, IR3_REG_HALF);
437 }
438
439 if (instr->flags & IR3_INSTR_S2EN) {
440 if (src2) {
441 iassert(!((src1->flags ^ src2->flags) & IR3_REG_HALF));
442 cat5->s2en.src2 = reg(src2, info, instr->repeat, IR3_REG_HALF);
443 }
444 if (src3) {
445 iassert(src3->flags & IR3_REG_HALF);
446 cat5->s2en.src3 = reg(src3, info, instr->repeat, IR3_REG_HALF);
447 }
448 iassert(!(instr->cat5.samp | instr->cat5.tex));
449 } else {
450 iassert(!src3);
451 if (src2) {
452 iassert(!((src1->flags ^ src2->flags) & IR3_REG_HALF));
453 cat5->norm.src2 = reg(src2, info, instr->repeat, IR3_REG_HALF);
454 }
455 cat5->norm.samp = instr->cat5.samp;
456 cat5->norm.tex = instr->cat5.tex;
457 }
458
459 cat5->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
460 cat5->wrmask = dst->wrmask;
461 cat5->type = instr->cat5.type;
462 cat5->is_3d = !!(instr->flags & IR3_INSTR_3D);
463 cat5->is_a = !!(instr->flags & IR3_INSTR_A);
464 cat5->is_s = !!(instr->flags & IR3_INSTR_S);
465 cat5->is_s2en = !!(instr->flags & IR3_INSTR_S2EN);
466 cat5->is_o = !!(instr->flags & IR3_INSTR_O);
467 cat5->is_p = !!(instr->flags & IR3_INSTR_P);
468 cat5->opc = instr->opc;
469 cat5->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
470 cat5->sync = !!(instr->flags & IR3_INSTR_SY);
471 cat5->opc_cat = 5;
472
473 return 0;
474 }
475
476 static int emit_cat6(struct ir3_instruction *instr, void *ptr,
477 struct ir3_info *info)
478 {
479 struct ir3_register *dst, *src1, *src2;
480 instr_cat6_t *cat6 = ptr;
481
482 /* the "dst" for a store instruction is (from the perspective
483 * of data flow in the shader, ie. register use/def, etc) in
484 * fact a register that is read by the instruction, rather
485 * than written:
486 */
487 if (is_store(instr)) {
488 iassert(instr->regs_count >= 3);
489
490 dst = instr->regs[1];
491 src1 = instr->regs[2];
492 src2 = (instr->regs_count >= 4) ? instr->regs[3] : NULL;
493 } else {
494 iassert(instr->regs_count >= 2);
495
496 dst = instr->regs[0];
497 src1 = instr->regs[1];
498 src2 = (instr->regs_count >= 3) ? instr->regs[2] : NULL;
499 }
500
501
502 /* TODO we need a more comprehensive list about which instructions
503 * can be encoded which way. Or possibly use IR3_INSTR_0 flag to
504 * indicate to use the src_off encoding even if offset is zero
505 * (but then what to do about dst_off?)
506 */
507 if (instr->cat6.src_offset || (instr->opc == OPC_LDG)) {
508 instr_cat6a_t *cat6a = ptr;
509
510 cat6->src_off = true;
511
512 cat6a->src1 = reg(src1, info, instr->repeat, IR3_REG_IMMED);
513 cat6a->src1_im = !!(src1->flags & IR3_REG_IMMED);
514 if (src2) {
515 cat6a->src2 = reg(src2, info, instr->repeat, IR3_REG_IMMED);
516 cat6a->src2_im = !!(src2->flags & IR3_REG_IMMED);
517 }
518 cat6a->off = instr->cat6.src_offset;
519 } else {
520 instr_cat6b_t *cat6b = ptr;
521
522 cat6->src_off = false;
523
524 cat6b->src1 = reg(src1, info, instr->repeat, IR3_REG_IMMED);
525 cat6b->src1_im = !!(src1->flags & IR3_REG_IMMED);
526 if (src2) {
527 cat6b->src2 = reg(src2, info, instr->repeat, IR3_REG_IMMED);
528 cat6b->src2_im = !!(src2->flags & IR3_REG_IMMED);
529 }
530 }
531
532 if (instr->cat6.dst_offset || (instr->opc == OPC_STG)) {
533 instr_cat6c_t *cat6c = ptr;
534 cat6->dst_off = true;
535 cat6c->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
536 cat6c->off = instr->cat6.dst_offset;
537 } else {
538 instr_cat6d_t *cat6d = ptr;
539 cat6->dst_off = false;
540 cat6d->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
541 }
542
543 cat6->type = instr->cat6.type;
544 cat6->opc = instr->opc;
545 cat6->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
546 cat6->sync = !!(instr->flags & IR3_INSTR_SY);
547 cat6->g = !!(instr->flags & IR3_INSTR_G);
548 cat6->opc_cat = 6;
549
550 return 0;
551 }
552
553 static int (*emit[])(struct ir3_instruction *instr, void *ptr,
554 struct ir3_info *info) = {
555 emit_cat0, emit_cat1, emit_cat2, emit_cat3, emit_cat4, emit_cat5, emit_cat6,
556 };
557
558 void * ir3_assemble(struct ir3 *shader, struct ir3_info *info,
559 uint32_t gpu_id)
560 {
561 uint32_t *ptr, *dwords;
562
563 info->gpu_id = gpu_id;
564 info->max_reg = -1;
565 info->max_half_reg = -1;
566 info->max_const = -1;
567 info->instrs_count = 0;
568 info->sizedwords = 0;
569
570 list_for_each_entry (struct ir3_block, block, &shader->block_list, node) {
571 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
572 info->sizedwords += 2;
573 }
574 }
575
576 /* need an integer number of instruction "groups" (sets of 16
577 * instructions on a4xx or sets of 4 instructions on a3xx),
578 * so pad out w/ NOPs if needed: (NOTE each instruction is 64bits)
579 */
580 if (gpu_id >= 400) {
581 info->sizedwords = align(info->sizedwords, 16 * 2);
582 } else {
583 info->sizedwords = align(info->sizedwords, 4 * 2);
584 }
585
586 ptr = dwords = calloc(4, info->sizedwords);
587
588 list_for_each_entry (struct ir3_block, block, &shader->block_list, node) {
589 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
590 int ret = emit[opc_cat(instr->opc)](instr, dwords, info);
591 if (ret)
592 goto fail;
593 info->instrs_count += 1 + instr->repeat;
594 dwords += 2;
595 }
596 }
597
598 return ptr;
599
600 fail:
601 free(ptr);
602 return NULL;
603 }
604
605 static struct ir3_register * reg_create(struct ir3 *shader,
606 int num, int flags)
607 {
608 struct ir3_register *reg =
609 ir3_alloc(shader, sizeof(struct ir3_register));
610 reg->wrmask = 1;
611 reg->flags = flags;
612 reg->num = num;
613 return reg;
614 }
615
616 static void insert_instr(struct ir3_block *block,
617 struct ir3_instruction *instr)
618 {
619 struct ir3 *shader = block->shader;
620 #ifdef DEBUG
621 static uint32_t serialno = 0;
622 instr->serialno = ++serialno;
623 #endif
624 list_addtail(&instr->node, &block->instr_list);
625
626 if (is_input(instr))
627 array_insert(shader->baryfs, instr);
628 }
629
630 struct ir3_block * ir3_block_create(struct ir3 *shader)
631 {
632 struct ir3_block *block = ir3_alloc(shader, sizeof(*block));
633 #ifdef DEBUG
634 static uint32_t serialno = 0;
635 block->serialno = ++serialno;
636 #endif
637 block->shader = shader;
638 list_inithead(&block->node);
639 list_inithead(&block->instr_list);
640 return block;
641 }
642
643 static struct ir3_instruction *instr_create(struct ir3_block *block, int nreg)
644 {
645 struct ir3_instruction *instr;
646 unsigned sz = sizeof(*instr) + (nreg * sizeof(instr->regs[0]));
647 char *ptr = ir3_alloc(block->shader, sz);
648
649 instr = (struct ir3_instruction *)ptr;
650 ptr += sizeof(*instr);
651 instr->regs = (struct ir3_register **)ptr;
652
653 #ifdef DEBUG
654 instr->regs_max = nreg;
655 #endif
656
657 return instr;
658 }
659
660 struct ir3_instruction * ir3_instr_create2(struct ir3_block *block,
661 opc_t opc, int nreg)
662 {
663 struct ir3_instruction *instr = instr_create(block, nreg);
664 instr->block = block;
665 instr->opc = opc;
666 insert_instr(block, instr);
667 return instr;
668 }
669
670 struct ir3_instruction * ir3_instr_create(struct ir3_block *block, opc_t opc)
671 {
672 /* NOTE: we could be slightly more clever, at least for non-meta,
673 * and choose # of regs based on category.
674 */
675 return ir3_instr_create2(block, opc, 4);
676 }
677
678 struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr)
679 {
680 struct ir3_instruction *new_instr = instr_create(instr->block,
681 instr->regs_count);
682 struct ir3_register **regs;
683 unsigned i;
684
685 regs = new_instr->regs;
686 *new_instr = *instr;
687 new_instr->regs = regs;
688
689 insert_instr(instr->block, new_instr);
690
691 /* clone registers: */
692 new_instr->regs_count = 0;
693 for (i = 0; i < instr->regs_count; i++) {
694 struct ir3_register *reg = instr->regs[i];
695 struct ir3_register *new_reg =
696 ir3_reg_create(new_instr, reg->num, reg->flags);
697 *new_reg = *reg;
698 }
699
700 return new_instr;
701 }
702
703 struct ir3_register * ir3_reg_create(struct ir3_instruction *instr,
704 int num, int flags)
705 {
706 struct ir3 *shader = instr->block->shader;
707 struct ir3_register *reg = reg_create(shader, num, flags);
708 #ifdef DEBUG
709 debug_assert(instr->regs_count < instr->regs_max);
710 #endif
711 instr->regs[instr->regs_count++] = reg;
712 return reg;
713 }
714
715 struct ir3_register * ir3_reg_clone(struct ir3 *shader,
716 struct ir3_register *reg)
717 {
718 struct ir3_register *new_reg = reg_create(shader, 0, 0);
719 *new_reg = *reg;
720 return new_reg;
721 }
722
723 void
724 ir3_instr_set_address(struct ir3_instruction *instr,
725 struct ir3_instruction *addr)
726 {
727 if (instr->address != addr) {
728 struct ir3 *ir = instr->block->shader;
729 instr->address = addr;
730 array_insert(ir->indirects, instr);
731 }
732 }
733
734 void
735 ir3_block_clear_mark(struct ir3_block *block)
736 {
737 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node)
738 instr->flags &= ~IR3_INSTR_MARK;
739 }
740
741 void
742 ir3_clear_mark(struct ir3 *ir)
743 {
744 list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
745 ir3_block_clear_mark(block);
746 }
747 }
748
749 /* note: this will destroy instr->depth, don't do it until after sched! */
750 unsigned
751 ir3_count_instructions(struct ir3 *ir)
752 {
753 unsigned cnt = 0;
754 list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
755 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
756 instr->ip = cnt++;
757 }
758 block->start_ip = list_first_entry(&block->instr_list, struct ir3_instruction, node)->ip;
759 block->end_ip = list_last_entry(&block->instr_list, struct ir3_instruction, node)->ip;
760 }
761 return cnt;
762 }
763
764 struct ir3_array *
765 ir3_lookup_array(struct ir3 *ir, unsigned id)
766 {
767 list_for_each_entry (struct ir3_array, arr, &ir->array_list, node)
768 if (arr->id == id)
769 return arr;
770 return NULL;
771 }