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freedreno/ir3: handle flat bypass for a4xx
[mesa.git] / src / gallium / drivers / freedreno / ir3 / ir3.c
1 /*
2 * Copyright (c) 2012 Rob Clark <robdclark@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include "ir3.h"
25
26 #include <stdlib.h>
27 #include <stdio.h>
28 #include <string.h>
29 #include <assert.h>
30 #include <stdbool.h>
31 #include <errno.h>
32
33 #include "freedreno_util.h"
34 #include "instr-a3xx.h"
35
36 #define CHUNK_SZ 1020
37
38 struct ir3_heap_chunk {
39 struct ir3_heap_chunk *next;
40 uint32_t heap[CHUNK_SZ];
41 };
42
43 static void grow_heap(struct ir3 *shader)
44 {
45 struct ir3_heap_chunk *chunk = calloc(1, sizeof(*chunk));
46 chunk->next = shader->chunk;
47 shader->chunk = chunk;
48 shader->heap_idx = 0;
49 }
50
51 /* simple allocator to carve allocations out of an up-front allocated heap,
52 * so that we can free everything easily in one shot.
53 */
54 void * ir3_alloc(struct ir3 *shader, int sz)
55 {
56 void *ptr;
57
58 sz = align(sz, 4) / 4;
59
60 if ((shader->heap_idx + sz) > CHUNK_SZ)
61 grow_heap(shader);
62
63 ptr = &shader->chunk->heap[shader->heap_idx];
64 shader->heap_idx += sz;
65
66 return ptr;
67 }
68
69 struct ir3 * ir3_create(void)
70 {
71 struct ir3 *shader =
72 calloc(1, sizeof(struct ir3));
73 grow_heap(shader);
74 return shader;
75 }
76
77 void ir3_destroy(struct ir3 *shader)
78 {
79 while (shader->chunk) {
80 struct ir3_heap_chunk *chunk = shader->chunk;
81 shader->chunk = chunk->next;
82 free(chunk);
83 }
84 free(shader->instrs);
85 free(shader->baryfs);
86 free(shader);
87 }
88
89 #define iassert(cond) do { \
90 if (!(cond)) { \
91 assert(cond); \
92 return -1; \
93 } } while (0)
94
95 static uint32_t reg(struct ir3_register *reg, struct ir3_info *info,
96 uint32_t repeat, uint32_t valid_flags)
97 {
98 reg_t val = { .dummy32 = 0 };
99
100 assert(!(reg->flags & ~valid_flags));
101
102 if (!(reg->flags & IR3_REG_R))
103 repeat = 0;
104
105 if (reg->flags & IR3_REG_IMMED) {
106 val.iim_val = reg->iim_val;
107 } else {
108 int8_t components = util_last_bit(reg->wrmask);
109 int16_t max = (reg->num + repeat + components - 1) >> 2;
110
111 val.comp = reg->num & 0x3;
112 val.num = reg->num >> 2;
113
114 if (reg->flags & IR3_REG_CONST) {
115 info->max_const = MAX2(info->max_const, max);
116 } else if (val.num == 63) {
117 /* ignore writes to dummy register r63.x */
118 } else if ((max != REG_A0) && (max != REG_P0)) {
119 if (reg->flags & IR3_REG_HALF) {
120 info->max_half_reg = MAX2(info->max_half_reg, max);
121 } else {
122 info->max_reg = MAX2(info->max_reg, max);
123 }
124 }
125 }
126
127 return val.dummy32;
128 }
129
130 static int emit_cat0(struct ir3_instruction *instr, void *ptr,
131 struct ir3_info *info)
132 {
133 instr_cat0_t *cat0 = ptr;
134
135 cat0->immed = instr->cat0.immed;
136 cat0->repeat = instr->repeat;
137 cat0->ss = !!(instr->flags & IR3_INSTR_SS);
138 cat0->inv = instr->cat0.inv;
139 cat0->comp = instr->cat0.comp;
140 cat0->opc = instr->opc;
141 cat0->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
142 cat0->sync = !!(instr->flags & IR3_INSTR_SY);
143 cat0->opc_cat = 0;
144
145 return 0;
146 }
147
148 static uint32_t type_flags(type_t type)
149 {
150 return (type_size(type) == 32) ? 0 : IR3_REG_HALF;
151 }
152
153 static int emit_cat1(struct ir3_instruction *instr, void *ptr,
154 struct ir3_info *info)
155 {
156 struct ir3_register *dst = instr->regs[0];
157 struct ir3_register *src = instr->regs[1];
158 instr_cat1_t *cat1 = ptr;
159
160 iassert(instr->regs_count == 2);
161 iassert(!((dst->flags ^ type_flags(instr->cat1.dst_type)) & IR3_REG_HALF));
162 iassert((src->flags & IR3_REG_IMMED) ||
163 !((src->flags ^ type_flags(instr->cat1.src_type)) & IR3_REG_HALF));
164
165 if (src->flags & IR3_REG_IMMED) {
166 cat1->iim_val = src->iim_val;
167 cat1->src_im = 1;
168 } else if (src->flags & IR3_REG_RELATIV) {
169 cat1->off = src->offset;
170 cat1->src_rel = 1;
171 cat1->src_rel_c = !!(src->flags & IR3_REG_CONST);
172 } else {
173 cat1->src = reg(src, info, instr->repeat,
174 IR3_REG_IMMED | IR3_REG_R |
175 IR3_REG_CONST | IR3_REG_HALF);
176 cat1->src_c = !!(src->flags & IR3_REG_CONST);
177 }
178
179 cat1->dst = reg(dst, info, instr->repeat,
180 IR3_REG_RELATIV | IR3_REG_EVEN |
181 IR3_REG_R | IR3_REG_POS_INF | IR3_REG_HALF);
182 cat1->repeat = instr->repeat;
183 cat1->src_r = !!(src->flags & IR3_REG_R);
184 cat1->ss = !!(instr->flags & IR3_INSTR_SS);
185 cat1->ul = !!(instr->flags & IR3_INSTR_UL);
186 cat1->dst_type = instr->cat1.dst_type;
187 cat1->dst_rel = !!(dst->flags & IR3_REG_RELATIV);
188 cat1->src_type = instr->cat1.src_type;
189 cat1->even = !!(dst->flags & IR3_REG_EVEN);
190 cat1->pos_inf = !!(dst->flags & IR3_REG_POS_INF);
191 cat1->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
192 cat1->sync = !!(instr->flags & IR3_INSTR_SY);
193 cat1->opc_cat = 1;
194
195 return 0;
196 }
197
198 static int emit_cat2(struct ir3_instruction *instr, void *ptr,
199 struct ir3_info *info)
200 {
201 struct ir3_register *dst = instr->regs[0];
202 struct ir3_register *src1 = instr->regs[1];
203 struct ir3_register *src2 = instr->regs[2];
204 instr_cat2_t *cat2 = ptr;
205
206 iassert((instr->regs_count == 2) || (instr->regs_count == 3));
207
208 if (src1->flags & IR3_REG_RELATIV) {
209 iassert(src1->num < (1 << 10));
210 cat2->rel1.src1 = reg(src1, info, instr->repeat,
211 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_NEGATE |
212 IR3_REG_ABS | IR3_REG_R | IR3_REG_HALF);
213 cat2->rel1.src1_c = !!(src1->flags & IR3_REG_CONST);
214 cat2->rel1.src1_rel = 1;
215 } else if (src1->flags & IR3_REG_CONST) {
216 iassert(src1->num < (1 << 12));
217 cat2->c1.src1 = reg(src1, info, instr->repeat,
218 IR3_REG_CONST | IR3_REG_NEGATE | IR3_REG_ABS |
219 IR3_REG_R | IR3_REG_HALF);
220 cat2->c1.src1_c = 1;
221 } else {
222 iassert(src1->num < (1 << 11));
223 cat2->src1 = reg(src1, info, instr->repeat,
224 IR3_REG_IMMED | IR3_REG_NEGATE | IR3_REG_ABS |
225 IR3_REG_R | IR3_REG_HALF);
226 }
227 cat2->src1_im = !!(src1->flags & IR3_REG_IMMED);
228 cat2->src1_neg = !!(src1->flags & IR3_REG_NEGATE);
229 cat2->src1_abs = !!(src1->flags & IR3_REG_ABS);
230 cat2->src1_r = !!(src1->flags & IR3_REG_R);
231
232 if (src2) {
233 iassert((src2->flags & IR3_REG_IMMED) ||
234 !((src1->flags ^ src2->flags) & IR3_REG_HALF));
235
236 if (src2->flags & IR3_REG_RELATIV) {
237 iassert(src2->num < (1 << 10));
238 cat2->rel2.src2 = reg(src2, info, instr->repeat,
239 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_NEGATE |
240 IR3_REG_ABS | IR3_REG_R | IR3_REG_HALF);
241 cat2->rel2.src2_c = !!(src2->flags & IR3_REG_CONST);
242 cat2->rel2.src2_rel = 1;
243 } else if (src2->flags & IR3_REG_CONST) {
244 iassert(src2->num < (1 << 12));
245 cat2->c2.src2 = reg(src2, info, instr->repeat,
246 IR3_REG_CONST | IR3_REG_NEGATE | IR3_REG_ABS |
247 IR3_REG_R | IR3_REG_HALF);
248 cat2->c2.src2_c = 1;
249 } else {
250 iassert(src2->num < (1 << 11));
251 cat2->src2 = reg(src2, info, instr->repeat,
252 IR3_REG_IMMED | IR3_REG_NEGATE | IR3_REG_ABS |
253 IR3_REG_R | IR3_REG_HALF);
254 }
255
256 cat2->src2_im = !!(src2->flags & IR3_REG_IMMED);
257 cat2->src2_neg = !!(src2->flags & IR3_REG_NEGATE);
258 cat2->src2_abs = !!(src2->flags & IR3_REG_ABS);
259 cat2->src2_r = !!(src2->flags & IR3_REG_R);
260 }
261
262 cat2->dst = reg(dst, info, instr->repeat,
263 IR3_REG_R | IR3_REG_EI | IR3_REG_HALF);
264 cat2->repeat = instr->repeat;
265 cat2->ss = !!(instr->flags & IR3_INSTR_SS);
266 cat2->ul = !!(instr->flags & IR3_INSTR_UL);
267 cat2->dst_half = !!((src1->flags ^ dst->flags) & IR3_REG_HALF);
268 cat2->ei = !!(dst->flags & IR3_REG_EI);
269 cat2->cond = instr->cat2.condition;
270 cat2->full = ! (src1->flags & IR3_REG_HALF);
271 cat2->opc = instr->opc;
272 cat2->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
273 cat2->sync = !!(instr->flags & IR3_INSTR_SY);
274 cat2->opc_cat = 2;
275
276 return 0;
277 }
278
279 static int emit_cat3(struct ir3_instruction *instr, void *ptr,
280 struct ir3_info *info)
281 {
282 struct ir3_register *dst = instr->regs[0];
283 struct ir3_register *src1 = instr->regs[1];
284 struct ir3_register *src2 = instr->regs[2];
285 struct ir3_register *src3 = instr->regs[3];
286 instr_cat3_t *cat3 = ptr;
287 uint32_t src_flags = 0;
288
289 switch (instr->opc) {
290 case OPC_MAD_F16:
291 case OPC_MAD_U16:
292 case OPC_MAD_S16:
293 case OPC_SEL_B16:
294 case OPC_SEL_S16:
295 case OPC_SEL_F16:
296 case OPC_SAD_S16:
297 case OPC_SAD_S32: // really??
298 src_flags |= IR3_REG_HALF;
299 break;
300 default:
301 break;
302 }
303
304 iassert(instr->regs_count == 4);
305 iassert(!((src1->flags ^ src_flags) & IR3_REG_HALF));
306 iassert(!((src2->flags ^ src_flags) & IR3_REG_HALF));
307 iassert(!((src3->flags ^ src_flags) & IR3_REG_HALF));
308
309 if (src1->flags & IR3_REG_RELATIV) {
310 iassert(src1->num < (1 << 10));
311 cat3->rel1.src1 = reg(src1, info, instr->repeat,
312 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_NEGATE |
313 IR3_REG_R | IR3_REG_HALF);
314 cat3->rel1.src1_c = !!(src1->flags & IR3_REG_CONST);
315 cat3->rel1.src1_rel = 1;
316 } else if (src1->flags & IR3_REG_CONST) {
317 iassert(src1->num < (1 << 12));
318 cat3->c1.src1 = reg(src1, info, instr->repeat,
319 IR3_REG_CONST | IR3_REG_NEGATE | IR3_REG_R |
320 IR3_REG_HALF);
321 cat3->c1.src1_c = 1;
322 } else {
323 iassert(src1->num < (1 << 11));
324 cat3->src1 = reg(src1, info, instr->repeat,
325 IR3_REG_NEGATE | IR3_REG_R | IR3_REG_HALF);
326 }
327
328 cat3->src1_neg = !!(src1->flags & IR3_REG_NEGATE);
329 cat3->src1_r = !!(src1->flags & IR3_REG_R);
330
331 cat3->src2 = reg(src2, info, instr->repeat,
332 IR3_REG_CONST | IR3_REG_NEGATE |
333 IR3_REG_R | IR3_REG_HALF);
334 cat3->src2_c = !!(src2->flags & IR3_REG_CONST);
335 cat3->src2_neg = !!(src2->flags & IR3_REG_NEGATE);
336 cat3->src2_r = !!(src2->flags & IR3_REG_R);
337
338
339 if (src3->flags & IR3_REG_RELATIV) {
340 iassert(src3->num < (1 << 10));
341 cat3->rel2.src3 = reg(src3, info, instr->repeat,
342 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_NEGATE |
343 IR3_REG_R | IR3_REG_HALF);
344 cat3->rel2.src3_c = !!(src3->flags & IR3_REG_CONST);
345 cat3->rel2.src3_rel = 1;
346 } else if (src3->flags & IR3_REG_CONST) {
347 iassert(src3->num < (1 << 12));
348 cat3->c2.src3 = reg(src3, info, instr->repeat,
349 IR3_REG_CONST | IR3_REG_NEGATE | IR3_REG_R |
350 IR3_REG_HALF);
351 cat3->c2.src3_c = 1;
352 } else {
353 iassert(src3->num < (1 << 11));
354 cat3->src3 = reg(src3, info, instr->repeat,
355 IR3_REG_NEGATE | IR3_REG_R | IR3_REG_HALF);
356 }
357
358 cat3->src3_neg = !!(src3->flags & IR3_REG_NEGATE);
359 cat3->src3_r = !!(src3->flags & IR3_REG_R);
360
361 cat3->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
362 cat3->repeat = instr->repeat;
363 cat3->ss = !!(instr->flags & IR3_INSTR_SS);
364 cat3->ul = !!(instr->flags & IR3_INSTR_UL);
365 cat3->dst_half = !!((src_flags ^ dst->flags) & IR3_REG_HALF);
366 cat3->opc = instr->opc;
367 cat3->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
368 cat3->sync = !!(instr->flags & IR3_INSTR_SY);
369 cat3->opc_cat = 3;
370
371 return 0;
372 }
373
374 static int emit_cat4(struct ir3_instruction *instr, void *ptr,
375 struct ir3_info *info)
376 {
377 struct ir3_register *dst = instr->regs[0];
378 struct ir3_register *src = instr->regs[1];
379 instr_cat4_t *cat4 = ptr;
380
381 iassert(instr->regs_count == 2);
382
383 if (src->flags & IR3_REG_RELATIV) {
384 iassert(src->num < (1 << 10));
385 cat4->rel.src = reg(src, info, instr->repeat,
386 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_NEGATE |
387 IR3_REG_ABS | IR3_REG_R | IR3_REG_HALF);
388 cat4->rel.src_c = !!(src->flags & IR3_REG_CONST);
389 cat4->rel.src_rel = 1;
390 } else if (src->flags & IR3_REG_CONST) {
391 iassert(src->num < (1 << 12));
392 cat4->c.src = reg(src, info, instr->repeat,
393 IR3_REG_CONST | IR3_REG_NEGATE | IR3_REG_ABS |
394 IR3_REG_R | IR3_REG_HALF);
395 cat4->c.src_c = 1;
396 } else {
397 iassert(src->num < (1 << 11));
398 cat4->src = reg(src, info, instr->repeat,
399 IR3_REG_IMMED | IR3_REG_NEGATE | IR3_REG_ABS |
400 IR3_REG_R | IR3_REG_HALF);
401 }
402
403 cat4->src_im = !!(src->flags & IR3_REG_IMMED);
404 cat4->src_neg = !!(src->flags & IR3_REG_NEGATE);
405 cat4->src_abs = !!(src->flags & IR3_REG_ABS);
406 cat4->src_r = !!(src->flags & IR3_REG_R);
407
408 cat4->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
409 cat4->repeat = instr->repeat;
410 cat4->ss = !!(instr->flags & IR3_INSTR_SS);
411 cat4->ul = !!(instr->flags & IR3_INSTR_UL);
412 cat4->dst_half = !!((src->flags ^ dst->flags) & IR3_REG_HALF);
413 cat4->full = ! (src->flags & IR3_REG_HALF);
414 cat4->opc = instr->opc;
415 cat4->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
416 cat4->sync = !!(instr->flags & IR3_INSTR_SY);
417 cat4->opc_cat = 4;
418
419 return 0;
420 }
421
422 static int emit_cat5(struct ir3_instruction *instr, void *ptr,
423 struct ir3_info *info)
424 {
425 struct ir3_register *dst = instr->regs[0];
426 struct ir3_register *src1 = instr->regs[1];
427 struct ir3_register *src2 = instr->regs[2];
428 struct ir3_register *src3 = instr->regs[3];
429 instr_cat5_t *cat5 = ptr;
430
431 iassert(!((dst->flags ^ type_flags(instr->cat5.type)) & IR3_REG_HALF));
432
433 if (src1) {
434 cat5->full = ! (src1->flags & IR3_REG_HALF);
435 cat5->src1 = reg(src1, info, instr->repeat, IR3_REG_HALF);
436 }
437
438
439 if (instr->flags & IR3_INSTR_S2EN) {
440 if (src2) {
441 iassert(!((src1->flags ^ src2->flags) & IR3_REG_HALF));
442 cat5->s2en.src2 = reg(src2, info, instr->repeat, IR3_REG_HALF);
443 }
444 if (src3) {
445 iassert(src3->flags & IR3_REG_HALF);
446 cat5->s2en.src3 = reg(src3, info, instr->repeat, IR3_REG_HALF);
447 }
448 iassert(!(instr->cat5.samp | instr->cat5.tex));
449 } else {
450 iassert(!src3);
451 if (src2) {
452 iassert(!((src1->flags ^ src2->flags) & IR3_REG_HALF));
453 cat5->norm.src2 = reg(src2, info, instr->repeat, IR3_REG_HALF);
454 }
455 cat5->norm.samp = instr->cat5.samp;
456 cat5->norm.tex = instr->cat5.tex;
457 }
458
459 cat5->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
460 cat5->wrmask = dst->wrmask;
461 cat5->type = instr->cat5.type;
462 cat5->is_3d = !!(instr->flags & IR3_INSTR_3D);
463 cat5->is_a = !!(instr->flags & IR3_INSTR_A);
464 cat5->is_s = !!(instr->flags & IR3_INSTR_S);
465 cat5->is_s2en = !!(instr->flags & IR3_INSTR_S2EN);
466 cat5->is_o = !!(instr->flags & IR3_INSTR_O);
467 cat5->is_p = !!(instr->flags & IR3_INSTR_P);
468 cat5->opc = instr->opc;
469 cat5->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
470 cat5->sync = !!(instr->flags & IR3_INSTR_SY);
471 cat5->opc_cat = 5;
472
473 return 0;
474 }
475
476 static int emit_cat6(struct ir3_instruction *instr, void *ptr,
477 struct ir3_info *info)
478 {
479 struct ir3_register *dst = instr->regs[0];
480 struct ir3_register *src1 = instr->regs[1];
481 struct ir3_register *src2 = (instr->regs_count >= 3) ? instr->regs[2] : NULL;
482 instr_cat6_t *cat6 = ptr;
483
484 iassert(instr->regs_count >= 2);
485
486 if (instr->cat6.offset) {
487 instr_cat6a_t *cat6a = ptr;
488
489 cat6->has_off = true;
490
491 cat6a->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
492 cat6a->src1 = reg(src1, info, instr->repeat, IR3_REG_IMMED);
493 cat6a->src1_im = !!(src1->flags & IR3_REG_IMMED);
494 if (src2) {
495 cat6a->src2 = reg(src2, info, instr->repeat, IR3_REG_IMMED);
496 cat6a->src2_im = !!(src2->flags & IR3_REG_IMMED);
497 }
498 cat6a->off = instr->cat6.offset;
499 } else {
500 instr_cat6b_t *cat6b = ptr;
501
502 cat6->has_off = false;
503
504 cat6b->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
505 cat6b->src1 = reg(src1, info, instr->repeat, IR3_REG_IMMED);
506 cat6b->src1_im = !!(src1->flags & IR3_REG_IMMED);
507 if (src2) {
508 cat6b->src2 = reg(src2, info, instr->repeat, IR3_REG_IMMED);
509 cat6b->src2_im = !!(src2->flags & IR3_REG_IMMED);
510 }
511 }
512
513 cat6->type = instr->cat6.type;
514 cat6->opc = instr->opc;
515 cat6->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
516 cat6->sync = !!(instr->flags & IR3_INSTR_SY);
517 cat6->opc_cat = 6;
518
519 return 0;
520 }
521
522 static int (*emit[])(struct ir3_instruction *instr, void *ptr,
523 struct ir3_info *info) = {
524 emit_cat0, emit_cat1, emit_cat2, emit_cat3, emit_cat4, emit_cat5, emit_cat6,
525 };
526
527 void * ir3_assemble(struct ir3 *shader, struct ir3_info *info,
528 uint32_t gpu_id)
529 {
530 uint32_t *ptr, *dwords;
531 uint32_t i;
532
533 info->max_reg = -1;
534 info->max_half_reg = -1;
535 info->max_const = -1;
536 info->instrs_count = 0;
537
538 /* need a integer number of instruction "groups" (sets of 16
539 * instructions on a4xx or sets of 4 instructions on a3xx),
540 * so pad out w/ NOPs if needed: (NOTE each instruction is 64bits)
541 */
542 if (gpu_id >= 400) {
543 info->sizedwords = 2 * align(shader->instrs_count, 16);
544 } else {
545 info->sizedwords = 2 * align(shader->instrs_count, 4);
546 }
547
548 ptr = dwords = calloc(4, info->sizedwords);
549
550 for (i = 0; i < shader->instrs_count; i++) {
551 struct ir3_instruction *instr = shader->instrs[i];
552 int ret = emit[instr->category](instr, dwords, info);
553 if (ret)
554 goto fail;
555 info->instrs_count += 1 + instr->repeat;
556 dwords += 2;
557 }
558
559 return ptr;
560
561 fail:
562 free(ptr);
563 return NULL;
564 }
565
566 static struct ir3_register * reg_create(struct ir3 *shader,
567 int num, int flags)
568 {
569 struct ir3_register *reg =
570 ir3_alloc(shader, sizeof(struct ir3_register));
571 reg->wrmask = 1;
572 reg->flags = flags;
573 reg->num = num;
574 return reg;
575 }
576
577 static void insert_instr(struct ir3 *shader,
578 struct ir3_instruction *instr)
579 {
580 #ifdef DEBUG
581 static uint32_t serialno = 0;
582 instr->serialno = ++serialno;
583 #endif
584 if (shader->instrs_count == shader->instrs_sz) {
585 shader->instrs_sz = MAX2(2 * shader->instrs_sz, 16);
586 shader->instrs = realloc(shader->instrs,
587 shader->instrs_sz * sizeof(shader->instrs[0]));
588 }
589 shader->instrs[shader->instrs_count++] = instr;
590
591 if (is_input(instr)) {
592 if (shader->baryfs_count == shader->baryfs_sz) {
593 shader->baryfs_sz = MAX2(2 * shader->baryfs_sz, 16);
594 shader->baryfs = realloc(shader->baryfs,
595 shader->baryfs_sz * sizeof(shader->baryfs[0]));
596 }
597 shader->baryfs[shader->baryfs_count++] = instr;
598 }
599 }
600
601 struct ir3_block * ir3_block_create(struct ir3 *shader,
602 unsigned ntmp, unsigned nin, unsigned nout)
603 {
604 struct ir3_block *block;
605 unsigned size;
606 char *ptr;
607
608 size = sizeof(*block);
609 size += sizeof(block->temporaries[0]) * ntmp;
610 size += sizeof(block->inputs[0]) * nin;
611 size += sizeof(block->outputs[0]) * nout;
612
613 ptr = ir3_alloc(shader, size);
614
615 block = (void *)ptr;
616 ptr += sizeof(*block);
617
618 block->temporaries = (void *)ptr;
619 block->ntemporaries = ntmp;
620 ptr += sizeof(block->temporaries[0]) * ntmp;
621
622 block->inputs = (void *)ptr;
623 block->ninputs = nin;
624 ptr += sizeof(block->inputs[0]) * nin;
625
626 block->outputs = (void *)ptr;
627 block->noutputs = nout;
628 ptr += sizeof(block->outputs[0]) * nout;
629
630 block->shader = shader;
631
632 return block;
633 }
634
635 static struct ir3_instruction *instr_create(struct ir3_block *block, int nreg)
636 {
637 struct ir3_instruction *instr;
638 unsigned sz = sizeof(*instr) + (nreg * sizeof(instr->regs[0]));
639 char *ptr = ir3_alloc(block->shader, sz);
640
641 instr = (struct ir3_instruction *)ptr;
642 ptr += sizeof(*instr);
643 instr->regs = (struct ir3_register **)ptr;
644
645 #ifdef DEBUG
646 instr->regs_max = nreg;
647 #endif
648
649 return instr;
650 }
651
652 struct ir3_instruction * ir3_instr_create2(struct ir3_block *block,
653 int category, opc_t opc, int nreg)
654 {
655 struct ir3_instruction *instr = instr_create(block, nreg);
656 instr->block = block;
657 instr->category = category;
658 instr->opc = opc;
659 insert_instr(block->shader, instr);
660 return instr;
661 }
662
663 struct ir3_instruction * ir3_instr_create(struct ir3_block *block,
664 int category, opc_t opc)
665 {
666 /* NOTE: we could be slightly more clever, at least for non-meta,
667 * and choose # of regs based on category.
668 */
669 return ir3_instr_create2(block, category, opc, 4);
670 }
671
672 /* only used by old compiler: */
673 struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr)
674 {
675 struct ir3_instruction *new_instr = instr_create(instr->block,
676 instr->regs_count);
677 struct ir3_register **regs;
678 unsigned i;
679
680 regs = new_instr->regs;
681 *new_instr = *instr;
682 new_instr->regs = regs;
683
684 insert_instr(instr->block->shader, new_instr);
685
686 /* clone registers: */
687 new_instr->regs_count = 0;
688 for (i = 0; i < instr->regs_count; i++) {
689 struct ir3_register *reg = instr->regs[i];
690 struct ir3_register *new_reg =
691 ir3_reg_create(new_instr, reg->num, reg->flags);
692 *new_reg = *reg;
693 }
694
695 return new_instr;
696 }
697
698 struct ir3_register * ir3_reg_create(struct ir3_instruction *instr,
699 int num, int flags)
700 {
701 struct ir3_register *reg = reg_create(instr->block->shader, num, flags);
702 #ifdef DEBUG
703 debug_assert(instr->regs_count < instr->regs_max);
704 #endif
705 instr->regs[instr->regs_count++] = reg;
706 return reg;
707 }