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freedreno/ir3: block reshuffling and loops!
[mesa.git] / src / gallium / drivers / freedreno / ir3 / ir3.c
1 /*
2 * Copyright (c) 2012 Rob Clark <robdclark@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include "ir3.h"
25
26 #include <stdlib.h>
27 #include <stdio.h>
28 #include <string.h>
29 #include <assert.h>
30 #include <stdbool.h>
31 #include <errno.h>
32
33 #include "freedreno_util.h"
34 #include "instr-a3xx.h"
35
36 #define CHUNK_SZ 1020
37
38 struct ir3_heap_chunk {
39 struct ir3_heap_chunk *next;
40 uint32_t heap[CHUNK_SZ];
41 };
42
43 static void grow_heap(struct ir3 *shader)
44 {
45 struct ir3_heap_chunk *chunk = calloc(1, sizeof(*chunk));
46 chunk->next = shader->chunk;
47 shader->chunk = chunk;
48 shader->heap_idx = 0;
49 }
50
51 /* simple allocator to carve allocations out of an up-front allocated heap,
52 * so that we can free everything easily in one shot.
53 */
54 void * ir3_alloc(struct ir3 *shader, int sz)
55 {
56 void *ptr;
57
58 sz = align(sz, 4) / 4;
59
60 if ((shader->heap_idx + sz) > CHUNK_SZ)
61 grow_heap(shader);
62
63 ptr = &shader->chunk->heap[shader->heap_idx];
64 shader->heap_idx += sz;
65
66 return ptr;
67 }
68
69 struct ir3 * ir3_create(struct ir3_compiler *compiler,
70 unsigned nin, unsigned nout)
71 {
72 struct ir3 *shader = calloc(1, sizeof(struct ir3));
73
74 grow_heap(shader);
75
76 shader->compiler = compiler;
77 shader->ninputs = nin;
78 shader->inputs = ir3_alloc(shader, sizeof(shader->inputs[0]) * nin);
79
80 shader->noutputs = nout;
81 shader->outputs = ir3_alloc(shader, sizeof(shader->outputs[0]) * nout);
82
83 list_inithead(&shader->block_list);
84
85 return shader;
86 }
87
88 void ir3_destroy(struct ir3 *shader)
89 {
90 while (shader->chunk) {
91 struct ir3_heap_chunk *chunk = shader->chunk;
92 shader->chunk = chunk->next;
93 free(chunk);
94 }
95 free(shader->indirects);
96 free(shader->predicates);
97 free(shader->baryfs);
98 free(shader);
99 }
100
101 #define iassert(cond) do { \
102 if (!(cond)) { \
103 assert(cond); \
104 return -1; \
105 } } while (0)
106
107 static uint32_t reg(struct ir3_register *reg, struct ir3_info *info,
108 uint32_t repeat, uint32_t valid_flags)
109 {
110 reg_t val = { .dummy32 = 0 };
111
112 if (reg->flags & ~valid_flags) {
113 debug_printf("INVALID FLAGS: %x vs %x\n",
114 reg->flags, valid_flags);
115 }
116
117 if (!(reg->flags & IR3_REG_R))
118 repeat = 0;
119
120 if (reg->flags & IR3_REG_IMMED) {
121 val.iim_val = reg->iim_val;
122 } else {
123 unsigned components;
124
125 if (reg->flags & IR3_REG_RELATIV) {
126 components = reg->size;
127 val.dummy10 = reg->offset;
128 } else {
129 components = util_last_bit(reg->wrmask);
130 val.comp = reg->num & 0x3;
131 val.num = reg->num >> 2;
132 }
133
134 int16_t max = (reg->num + repeat + components - 1) >> 2;
135
136 if (reg->flags & IR3_REG_CONST) {
137 info->max_const = MAX2(info->max_const, max);
138 } else if (val.num == 63) {
139 /* ignore writes to dummy register r63.x */
140 } else if ((max != REG_A0) && (max != REG_P0)) {
141 if (reg->flags & IR3_REG_HALF) {
142 info->max_half_reg = MAX2(info->max_half_reg, max);
143 } else {
144 info->max_reg = MAX2(info->max_reg, max);
145 }
146 }
147 }
148
149 return val.dummy32;
150 }
151
152 static int emit_cat0(struct ir3_instruction *instr, void *ptr,
153 struct ir3_info *info)
154 {
155 instr_cat0_t *cat0 = ptr;
156
157 if (info->gpu_id >= 400) {
158 cat0->a4xx.immed = instr->cat0.immed;
159 } else {
160 cat0->a3xx.immed = instr->cat0.immed;
161 }
162 cat0->repeat = instr->repeat;
163 cat0->ss = !!(instr->flags & IR3_INSTR_SS);
164 cat0->inv = instr->cat0.inv;
165 cat0->comp = instr->cat0.comp;
166 cat0->opc = instr->opc;
167 cat0->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
168 cat0->sync = !!(instr->flags & IR3_INSTR_SY);
169 cat0->opc_cat = 0;
170
171 return 0;
172 }
173
174 static uint32_t type_flags(type_t type)
175 {
176 return (type_size(type) == 32) ? 0 : IR3_REG_HALF;
177 }
178
179 static int emit_cat1(struct ir3_instruction *instr, void *ptr,
180 struct ir3_info *info)
181 {
182 struct ir3_register *dst = instr->regs[0];
183 struct ir3_register *src = instr->regs[1];
184 instr_cat1_t *cat1 = ptr;
185
186 iassert(instr->regs_count == 2);
187 iassert(!((dst->flags ^ type_flags(instr->cat1.dst_type)) & IR3_REG_HALF));
188 iassert((src->flags & IR3_REG_IMMED) ||
189 !((src->flags ^ type_flags(instr->cat1.src_type)) & IR3_REG_HALF));
190
191 if (src->flags & IR3_REG_IMMED) {
192 cat1->iim_val = src->iim_val;
193 cat1->src_im = 1;
194 } else if (src->flags & IR3_REG_RELATIV) {
195 cat1->off = reg(src, info, instr->repeat,
196 IR3_REG_R | IR3_REG_CONST | IR3_REG_HALF | IR3_REG_RELATIV);
197 cat1->src_rel = 1;
198 cat1->src_rel_c = !!(src->flags & IR3_REG_CONST);
199 } else {
200 cat1->src = reg(src, info, instr->repeat,
201 IR3_REG_R | IR3_REG_CONST | IR3_REG_HALF);
202 cat1->src_c = !!(src->flags & IR3_REG_CONST);
203 }
204
205 cat1->dst = reg(dst, info, instr->repeat,
206 IR3_REG_RELATIV | IR3_REG_EVEN |
207 IR3_REG_R | IR3_REG_POS_INF | IR3_REG_HALF);
208 cat1->repeat = instr->repeat;
209 cat1->src_r = !!(src->flags & IR3_REG_R);
210 cat1->ss = !!(instr->flags & IR3_INSTR_SS);
211 cat1->ul = !!(instr->flags & IR3_INSTR_UL);
212 cat1->dst_type = instr->cat1.dst_type;
213 cat1->dst_rel = !!(dst->flags & IR3_REG_RELATIV);
214 cat1->src_type = instr->cat1.src_type;
215 cat1->even = !!(dst->flags & IR3_REG_EVEN);
216 cat1->pos_inf = !!(dst->flags & IR3_REG_POS_INF);
217 cat1->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
218 cat1->sync = !!(instr->flags & IR3_INSTR_SY);
219 cat1->opc_cat = 1;
220
221 return 0;
222 }
223
224 static int emit_cat2(struct ir3_instruction *instr, void *ptr,
225 struct ir3_info *info)
226 {
227 struct ir3_register *dst = instr->regs[0];
228 struct ir3_register *src1 = instr->regs[1];
229 struct ir3_register *src2 = instr->regs[2];
230 instr_cat2_t *cat2 = ptr;
231 unsigned absneg = ir3_cat2_absneg(instr->opc);
232
233 iassert((instr->regs_count == 2) || (instr->regs_count == 3));
234
235 if (src1->flags & IR3_REG_RELATIV) {
236 iassert(src1->num < (1 << 10));
237 cat2->rel1.src1 = reg(src1, info, instr->repeat,
238 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_R |
239 IR3_REG_HALF | absneg);
240 cat2->rel1.src1_c = !!(src1->flags & IR3_REG_CONST);
241 cat2->rel1.src1_rel = 1;
242 } else if (src1->flags & IR3_REG_CONST) {
243 iassert(src1->num < (1 << 12));
244 cat2->c1.src1 = reg(src1, info, instr->repeat,
245 IR3_REG_CONST | IR3_REG_R | IR3_REG_HALF);
246 cat2->c1.src1_c = 1;
247 } else {
248 iassert(src1->num < (1 << 11));
249 cat2->src1 = reg(src1, info, instr->repeat,
250 IR3_REG_IMMED | IR3_REG_R | IR3_REG_HALF |
251 absneg);
252 }
253 cat2->src1_im = !!(src1->flags & IR3_REG_IMMED);
254 cat2->src1_neg = !!(src1->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT));
255 cat2->src1_abs = !!(src1->flags & (IR3_REG_FABS | IR3_REG_SABS));
256 cat2->src1_r = !!(src1->flags & IR3_REG_R);
257
258 if (src2) {
259 iassert((src2->flags & IR3_REG_IMMED) ||
260 !((src1->flags ^ src2->flags) & IR3_REG_HALF));
261
262 if (src2->flags & IR3_REG_RELATIV) {
263 iassert(src2->num < (1 << 10));
264 cat2->rel2.src2 = reg(src2, info, instr->repeat,
265 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_R |
266 IR3_REG_HALF | absneg);
267 cat2->rel2.src2_c = !!(src2->flags & IR3_REG_CONST);
268 cat2->rel2.src2_rel = 1;
269 } else if (src2->flags & IR3_REG_CONST) {
270 iassert(src2->num < (1 << 12));
271 cat2->c2.src2 = reg(src2, info, instr->repeat,
272 IR3_REG_CONST | IR3_REG_R | IR3_REG_HALF);
273 cat2->c2.src2_c = 1;
274 } else {
275 iassert(src2->num < (1 << 11));
276 cat2->src2 = reg(src2, info, instr->repeat,
277 IR3_REG_IMMED | IR3_REG_R | IR3_REG_HALF |
278 absneg);
279 }
280
281 cat2->src2_im = !!(src2->flags & IR3_REG_IMMED);
282 cat2->src2_neg = !!(src2->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT));
283 cat2->src2_abs = !!(src2->flags & (IR3_REG_FABS | IR3_REG_SABS));
284 cat2->src2_r = !!(src2->flags & IR3_REG_R);
285 }
286
287 cat2->dst = reg(dst, info, instr->repeat,
288 IR3_REG_R | IR3_REG_EI | IR3_REG_HALF);
289 cat2->repeat = instr->repeat;
290 cat2->ss = !!(instr->flags & IR3_INSTR_SS);
291 cat2->ul = !!(instr->flags & IR3_INSTR_UL);
292 cat2->dst_half = !!((src1->flags ^ dst->flags) & IR3_REG_HALF);
293 cat2->ei = !!(dst->flags & IR3_REG_EI);
294 cat2->cond = instr->cat2.condition;
295 cat2->full = ! (src1->flags & IR3_REG_HALF);
296 cat2->opc = instr->opc;
297 cat2->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
298 cat2->sync = !!(instr->flags & IR3_INSTR_SY);
299 cat2->opc_cat = 2;
300
301 return 0;
302 }
303
304 static int emit_cat3(struct ir3_instruction *instr, void *ptr,
305 struct ir3_info *info)
306 {
307 struct ir3_register *dst = instr->regs[0];
308 struct ir3_register *src1 = instr->regs[1];
309 struct ir3_register *src2 = instr->regs[2];
310 struct ir3_register *src3 = instr->regs[3];
311 unsigned absneg = ir3_cat3_absneg(instr->opc);
312 instr_cat3_t *cat3 = ptr;
313 uint32_t src_flags = 0;
314
315 switch (instr->opc) {
316 case OPC_MAD_F16:
317 case OPC_MAD_U16:
318 case OPC_MAD_S16:
319 case OPC_SEL_B16:
320 case OPC_SEL_S16:
321 case OPC_SEL_F16:
322 case OPC_SAD_S16:
323 case OPC_SAD_S32: // really??
324 src_flags |= IR3_REG_HALF;
325 break;
326 default:
327 break;
328 }
329
330 iassert(instr->regs_count == 4);
331 iassert(!((src1->flags ^ src_flags) & IR3_REG_HALF));
332 iassert(!((src2->flags ^ src_flags) & IR3_REG_HALF));
333 iassert(!((src3->flags ^ src_flags) & IR3_REG_HALF));
334
335 if (src1->flags & IR3_REG_RELATIV) {
336 iassert(src1->num < (1 << 10));
337 cat3->rel1.src1 = reg(src1, info, instr->repeat,
338 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_R |
339 IR3_REG_HALF | absneg);
340 cat3->rel1.src1_c = !!(src1->flags & IR3_REG_CONST);
341 cat3->rel1.src1_rel = 1;
342 } else if (src1->flags & IR3_REG_CONST) {
343 iassert(src1->num < (1 << 12));
344 cat3->c1.src1 = reg(src1, info, instr->repeat,
345 IR3_REG_CONST | IR3_REG_R | IR3_REG_HALF);
346 cat3->c1.src1_c = 1;
347 } else {
348 iassert(src1->num < (1 << 11));
349 cat3->src1 = reg(src1, info, instr->repeat,
350 IR3_REG_R | IR3_REG_HALF | absneg);
351 }
352
353 cat3->src1_neg = !!(src1->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT));
354 cat3->src1_r = !!(src1->flags & IR3_REG_R);
355
356 cat3->src2 = reg(src2, info, instr->repeat,
357 IR3_REG_CONST | IR3_REG_R | IR3_REG_HALF | absneg);
358 cat3->src2_c = !!(src2->flags & IR3_REG_CONST);
359 cat3->src2_neg = !!(src2->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT));
360 cat3->src2_r = !!(src2->flags & IR3_REG_R);
361
362
363 if (src3->flags & IR3_REG_RELATIV) {
364 iassert(src3->num < (1 << 10));
365 cat3->rel2.src3 = reg(src3, info, instr->repeat,
366 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_R |
367 IR3_REG_HALF | absneg);
368 cat3->rel2.src3_c = !!(src3->flags & IR3_REG_CONST);
369 cat3->rel2.src3_rel = 1;
370 } else if (src3->flags & IR3_REG_CONST) {
371 iassert(src3->num < (1 << 12));
372 cat3->c2.src3 = reg(src3, info, instr->repeat,
373 IR3_REG_CONST | IR3_REG_R | IR3_REG_HALF);
374 cat3->c2.src3_c = 1;
375 } else {
376 iassert(src3->num < (1 << 11));
377 cat3->src3 = reg(src3, info, instr->repeat,
378 IR3_REG_R | IR3_REG_HALF | absneg);
379 }
380
381 cat3->src3_neg = !!(src3->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT));
382 cat3->src3_r = !!(src3->flags & IR3_REG_R);
383
384 cat3->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
385 cat3->repeat = instr->repeat;
386 cat3->ss = !!(instr->flags & IR3_INSTR_SS);
387 cat3->ul = !!(instr->flags & IR3_INSTR_UL);
388 cat3->dst_half = !!((src_flags ^ dst->flags) & IR3_REG_HALF);
389 cat3->opc = instr->opc;
390 cat3->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
391 cat3->sync = !!(instr->flags & IR3_INSTR_SY);
392 cat3->opc_cat = 3;
393
394 return 0;
395 }
396
397 static int emit_cat4(struct ir3_instruction *instr, void *ptr,
398 struct ir3_info *info)
399 {
400 struct ir3_register *dst = instr->regs[0];
401 struct ir3_register *src = instr->regs[1];
402 instr_cat4_t *cat4 = ptr;
403
404 iassert(instr->regs_count == 2);
405
406 if (src->flags & IR3_REG_RELATIV) {
407 iassert(src->num < (1 << 10));
408 cat4->rel.src = reg(src, info, instr->repeat,
409 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_FNEG |
410 IR3_REG_FABS | IR3_REG_R | IR3_REG_HALF);
411 cat4->rel.src_c = !!(src->flags & IR3_REG_CONST);
412 cat4->rel.src_rel = 1;
413 } else if (src->flags & IR3_REG_CONST) {
414 iassert(src->num < (1 << 12));
415 cat4->c.src = reg(src, info, instr->repeat,
416 IR3_REG_CONST | IR3_REG_FNEG | IR3_REG_FABS |
417 IR3_REG_R | IR3_REG_HALF);
418 cat4->c.src_c = 1;
419 } else {
420 iassert(src->num < (1 << 11));
421 cat4->src = reg(src, info, instr->repeat,
422 IR3_REG_IMMED | IR3_REG_FNEG | IR3_REG_FABS |
423 IR3_REG_R | IR3_REG_HALF);
424 }
425
426 cat4->src_im = !!(src->flags & IR3_REG_IMMED);
427 cat4->src_neg = !!(src->flags & IR3_REG_FNEG);
428 cat4->src_abs = !!(src->flags & IR3_REG_FABS);
429 cat4->src_r = !!(src->flags & IR3_REG_R);
430
431 cat4->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
432 cat4->repeat = instr->repeat;
433 cat4->ss = !!(instr->flags & IR3_INSTR_SS);
434 cat4->ul = !!(instr->flags & IR3_INSTR_UL);
435 cat4->dst_half = !!((src->flags ^ dst->flags) & IR3_REG_HALF);
436 cat4->full = ! (src->flags & IR3_REG_HALF);
437 cat4->opc = instr->opc;
438 cat4->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
439 cat4->sync = !!(instr->flags & IR3_INSTR_SY);
440 cat4->opc_cat = 4;
441
442 return 0;
443 }
444
445 static int emit_cat5(struct ir3_instruction *instr, void *ptr,
446 struct ir3_info *info)
447 {
448 struct ir3_register *dst = instr->regs[0];
449 struct ir3_register *src1 = instr->regs[1];
450 struct ir3_register *src2 = instr->regs[2];
451 struct ir3_register *src3 = instr->regs[3];
452 instr_cat5_t *cat5 = ptr;
453
454 iassert(!((dst->flags ^ type_flags(instr->cat5.type)) & IR3_REG_HALF));
455
456 if (src1) {
457 cat5->full = ! (src1->flags & IR3_REG_HALF);
458 cat5->src1 = reg(src1, info, instr->repeat, IR3_REG_HALF);
459 }
460
461
462 if (instr->flags & IR3_INSTR_S2EN) {
463 if (src2) {
464 iassert(!((src1->flags ^ src2->flags) & IR3_REG_HALF));
465 cat5->s2en.src2 = reg(src2, info, instr->repeat, IR3_REG_HALF);
466 }
467 if (src3) {
468 iassert(src3->flags & IR3_REG_HALF);
469 cat5->s2en.src3 = reg(src3, info, instr->repeat, IR3_REG_HALF);
470 }
471 iassert(!(instr->cat5.samp | instr->cat5.tex));
472 } else {
473 iassert(!src3);
474 if (src2) {
475 iassert(!((src1->flags ^ src2->flags) & IR3_REG_HALF));
476 cat5->norm.src2 = reg(src2, info, instr->repeat, IR3_REG_HALF);
477 }
478 cat5->norm.samp = instr->cat5.samp;
479 cat5->norm.tex = instr->cat5.tex;
480 }
481
482 cat5->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
483 cat5->wrmask = dst->wrmask;
484 cat5->type = instr->cat5.type;
485 cat5->is_3d = !!(instr->flags & IR3_INSTR_3D);
486 cat5->is_a = !!(instr->flags & IR3_INSTR_A);
487 cat5->is_s = !!(instr->flags & IR3_INSTR_S);
488 cat5->is_s2en = !!(instr->flags & IR3_INSTR_S2EN);
489 cat5->is_o = !!(instr->flags & IR3_INSTR_O);
490 cat5->is_p = !!(instr->flags & IR3_INSTR_P);
491 cat5->opc = instr->opc;
492 cat5->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
493 cat5->sync = !!(instr->flags & IR3_INSTR_SY);
494 cat5->opc_cat = 5;
495
496 return 0;
497 }
498
499 static int emit_cat6(struct ir3_instruction *instr, void *ptr,
500 struct ir3_info *info)
501 {
502 struct ir3_register *dst = instr->regs[0];
503 struct ir3_register *src1 = instr->regs[1];
504 struct ir3_register *src2 = (instr->regs_count >= 3) ? instr->regs[2] : NULL;
505 instr_cat6_t *cat6 = ptr;
506
507 iassert(instr->regs_count >= 2);
508
509 if (instr->cat6.offset || instr->opc == OPC_LDG) {
510 instr_cat6a_t *cat6a = ptr;
511
512 cat6->has_off = true;
513
514 cat6a->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
515 cat6a->src1 = reg(src1, info, instr->repeat, IR3_REG_IMMED);
516 cat6a->src1_im = !!(src1->flags & IR3_REG_IMMED);
517 if (src2) {
518 cat6a->src2 = reg(src2, info, instr->repeat, IR3_REG_IMMED);
519 cat6a->src2_im = !!(src2->flags & IR3_REG_IMMED);
520 }
521 cat6a->off = instr->cat6.offset;
522 } else {
523 instr_cat6b_t *cat6b = ptr;
524
525 cat6->has_off = false;
526
527 cat6b->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
528 cat6b->src1 = reg(src1, info, instr->repeat, IR3_REG_IMMED);
529 cat6b->src1_im = !!(src1->flags & IR3_REG_IMMED);
530 if (src2) {
531 cat6b->src2 = reg(src2, info, instr->repeat, IR3_REG_IMMED);
532 cat6b->src2_im = !!(src2->flags & IR3_REG_IMMED);
533 }
534 }
535
536 cat6->type = instr->cat6.type;
537 cat6->opc = instr->opc;
538 cat6->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
539 cat6->sync = !!(instr->flags & IR3_INSTR_SY);
540 cat6->opc_cat = 6;
541
542 return 0;
543 }
544
545 static int (*emit[])(struct ir3_instruction *instr, void *ptr,
546 struct ir3_info *info) = {
547 emit_cat0, emit_cat1, emit_cat2, emit_cat3, emit_cat4, emit_cat5, emit_cat6,
548 };
549
550 void * ir3_assemble(struct ir3 *shader, struct ir3_info *info,
551 uint32_t gpu_id)
552 {
553 uint32_t *ptr, *dwords;
554
555 info->gpu_id = gpu_id;
556 info->max_reg = -1;
557 info->max_half_reg = -1;
558 info->max_const = -1;
559 info->instrs_count = 0;
560 info->sizedwords = 0;
561
562 list_for_each_entry (struct ir3_block, block, &shader->block_list, node) {
563 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
564 info->sizedwords += 2;
565 }
566 }
567
568 /* need a integer number of instruction "groups" (sets of 16
569 * instructions on a4xx or sets of 4 instructions on a3xx),
570 * so pad out w/ NOPs if needed: (NOTE each instruction is 64bits)
571 */
572 if (gpu_id >= 400) {
573 info->sizedwords = align(info->sizedwords, 16 * 2);
574 } else {
575 info->sizedwords = align(info->sizedwords, 4 * 2);
576 }
577
578 ptr = dwords = calloc(4, info->sizedwords);
579
580 list_for_each_entry (struct ir3_block, block, &shader->block_list, node) {
581 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
582 int ret = emit[instr->category](instr, dwords, info);
583 if (ret)
584 goto fail;
585 info->instrs_count += 1 + instr->repeat;
586 dwords += 2;
587 }
588 }
589
590 return ptr;
591
592 fail:
593 free(ptr);
594 return NULL;
595 }
596
597 static struct ir3_register * reg_create(struct ir3 *shader,
598 int num, int flags)
599 {
600 struct ir3_register *reg =
601 ir3_alloc(shader, sizeof(struct ir3_register));
602 reg->wrmask = 1;
603 reg->flags = flags;
604 reg->num = num;
605 return reg;
606 }
607
608 static void insert_instr(struct ir3_block *block,
609 struct ir3_instruction *instr)
610 {
611 struct ir3 *shader = block->shader;
612 #ifdef DEBUG
613 static uint32_t serialno = 0;
614 instr->serialno = ++serialno;
615 #endif
616 list_addtail(&instr->node, &block->instr_list);
617
618 if (is_input(instr))
619 array_insert(shader->baryfs, instr);
620 }
621
622 struct ir3_block * ir3_block_create(struct ir3 *shader)
623 {
624 struct ir3_block *block = ir3_alloc(shader, sizeof(*block));
625 #ifdef DEBUG
626 static uint32_t serialno = 0;
627 block->serialno = ++serialno;
628 #endif
629 block->shader = shader;
630 list_inithead(&block->node);
631 list_inithead(&block->instr_list);
632 return block;
633 }
634
635 static struct ir3_instruction *instr_create(struct ir3_block *block, int nreg)
636 {
637 struct ir3_instruction *instr;
638 unsigned sz = sizeof(*instr) + (nreg * sizeof(instr->regs[0]));
639 char *ptr = ir3_alloc(block->shader, sz);
640
641 instr = (struct ir3_instruction *)ptr;
642 ptr += sizeof(*instr);
643 instr->regs = (struct ir3_register **)ptr;
644
645 #ifdef DEBUG
646 instr->regs_max = nreg;
647 #endif
648
649 return instr;
650 }
651
652 struct ir3_instruction * ir3_instr_create2(struct ir3_block *block,
653 int category, opc_t opc, int nreg)
654 {
655 struct ir3_instruction *instr = instr_create(block, nreg);
656 instr->block = block;
657 instr->category = category;
658 instr->opc = opc;
659 insert_instr(block, instr);
660 return instr;
661 }
662
663 struct ir3_instruction * ir3_instr_create(struct ir3_block *block,
664 int category, opc_t opc)
665 {
666 /* NOTE: we could be slightly more clever, at least for non-meta,
667 * and choose # of regs based on category.
668 */
669 return ir3_instr_create2(block, category, opc, 4);
670 }
671
672 /* only used by old compiler: */
673 struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr)
674 {
675 struct ir3_instruction *new_instr = instr_create(instr->block,
676 instr->regs_count);
677 struct ir3_register **regs;
678 unsigned i;
679
680 regs = new_instr->regs;
681 *new_instr = *instr;
682 new_instr->regs = regs;
683
684 insert_instr(instr->block, new_instr);
685
686 /* clone registers: */
687 new_instr->regs_count = 0;
688 for (i = 0; i < instr->regs_count; i++) {
689 struct ir3_register *reg = instr->regs[i];
690 struct ir3_register *new_reg =
691 ir3_reg_create(new_instr, reg->num, reg->flags);
692 *new_reg = *reg;
693 }
694
695 return new_instr;
696 }
697
698 struct ir3_register * ir3_reg_create(struct ir3_instruction *instr,
699 int num, int flags)
700 {
701 struct ir3 *shader = instr->block->shader;
702 struct ir3_register *reg = reg_create(shader, num, flags);
703 #ifdef DEBUG
704 debug_assert(instr->regs_count < instr->regs_max);
705 #endif
706 instr->regs[instr->regs_count++] = reg;
707 return reg;
708 }
709
710 void
711 ir3_block_clear_mark(struct ir3_block *block)
712 {
713 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node)
714 instr->flags &= ~IR3_INSTR_MARK;
715 }
716
717 void
718 ir3_clear_mark(struct ir3 *ir)
719 {
720 list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
721 ir3_block_clear_mark(block);
722 }
723 }
724
725 /* note: this will destroy instr->depth, don't do it until after sched! */
726 void
727 ir3_count_instructions(struct ir3 *ir)
728 {
729 unsigned ip = 0;
730 list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
731 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
732 instr->ip = ip++;
733 }
734 block->start_ip = list_first_entry(&block->instr_list, struct ir3_instruction, node)->ip;
735 block->end_ip = list_last_entry(&block->instr_list, struct ir3_instruction, node)->ip;
736 }
737 }