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freedreno/ir3: encode instruction category in opc_t
[mesa.git] / src / gallium / drivers / freedreno / ir3 / ir3.c
1 /*
2 * Copyright (c) 2012 Rob Clark <robdclark@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include "ir3.h"
25
26 #include <stdlib.h>
27 #include <stdio.h>
28 #include <string.h>
29 #include <assert.h>
30 #include <stdbool.h>
31 #include <errno.h>
32
33 #include "freedreno_util.h"
34 #include "instr-a3xx.h"
35
36 #define CHUNK_SZ 1020
37
38 struct ir3_heap_chunk {
39 struct ir3_heap_chunk *next;
40 uint32_t heap[CHUNK_SZ];
41 };
42
43 static void grow_heap(struct ir3 *shader)
44 {
45 struct ir3_heap_chunk *chunk = calloc(1, sizeof(*chunk));
46 chunk->next = shader->chunk;
47 shader->chunk = chunk;
48 shader->heap_idx = 0;
49 }
50
51 /* simple allocator to carve allocations out of an up-front allocated heap,
52 * so that we can free everything easily in one shot.
53 */
54 void * ir3_alloc(struct ir3 *shader, int sz)
55 {
56 void *ptr;
57
58 sz = align(sz, 4) / 4;
59
60 if ((shader->heap_idx + sz) > CHUNK_SZ)
61 grow_heap(shader);
62
63 ptr = &shader->chunk->heap[shader->heap_idx];
64 shader->heap_idx += sz;
65
66 return ptr;
67 }
68
69 struct ir3 * ir3_create(struct ir3_compiler *compiler,
70 unsigned nin, unsigned nout)
71 {
72 struct ir3 *shader = calloc(1, sizeof(struct ir3));
73
74 grow_heap(shader);
75
76 shader->compiler = compiler;
77 shader->ninputs = nin;
78 shader->inputs = ir3_alloc(shader, sizeof(shader->inputs[0]) * nin);
79
80 shader->noutputs = nout;
81 shader->outputs = ir3_alloc(shader, sizeof(shader->outputs[0]) * nout);
82
83 list_inithead(&shader->block_list);
84 list_inithead(&shader->array_list);
85
86 return shader;
87 }
88
89 void ir3_destroy(struct ir3 *shader)
90 {
91 while (shader->chunk) {
92 struct ir3_heap_chunk *chunk = shader->chunk;
93 shader->chunk = chunk->next;
94 free(chunk);
95 }
96 free(shader->indirects);
97 free(shader->predicates);
98 free(shader->baryfs);
99 free(shader);
100 }
101
102 #define iassert(cond) do { \
103 if (!(cond)) { \
104 assert(cond); \
105 return -1; \
106 } } while (0)
107
108 static uint32_t reg(struct ir3_register *reg, struct ir3_info *info,
109 uint32_t repeat, uint32_t valid_flags)
110 {
111 reg_t val = { .dummy32 = 0 };
112
113 if (reg->flags & ~valid_flags) {
114 debug_printf("INVALID FLAGS: %x vs %x\n",
115 reg->flags, valid_flags);
116 }
117
118 if (!(reg->flags & IR3_REG_R))
119 repeat = 0;
120
121 if (reg->flags & IR3_REG_IMMED) {
122 val.iim_val = reg->iim_val;
123 } else {
124 unsigned components;
125 int16_t max;
126
127 if (reg->flags & IR3_REG_RELATIV) {
128 components = reg->size;
129 val.idummy10 = reg->array.offset;
130 max = (reg->array.offset + repeat + components - 1) >> 2;
131 } else {
132 components = util_last_bit(reg->wrmask);
133 val.comp = reg->num & 0x3;
134 val.num = reg->num >> 2;
135 max = (reg->num + repeat + components - 1) >> 2;
136 }
137
138 if (reg->flags & IR3_REG_CONST) {
139 info->max_const = MAX2(info->max_const, max);
140 } else if (val.num == 63) {
141 /* ignore writes to dummy register r63.x */
142 } else if ((max != REG_A0) && (max != REG_P0)) {
143 if (reg->flags & IR3_REG_HALF) {
144 info->max_half_reg = MAX2(info->max_half_reg, max);
145 } else {
146 info->max_reg = MAX2(info->max_reg, max);
147 }
148 }
149 }
150
151 return val.dummy32;
152 }
153
154 static int emit_cat0(struct ir3_instruction *instr, void *ptr,
155 struct ir3_info *info)
156 {
157 instr_cat0_t *cat0 = ptr;
158
159 if (info->gpu_id >= 400) {
160 cat0->a4xx.immed = instr->cat0.immed;
161 } else {
162 cat0->a3xx.immed = instr->cat0.immed;
163 }
164 cat0->repeat = instr->repeat;
165 cat0->ss = !!(instr->flags & IR3_INSTR_SS);
166 cat0->inv = instr->cat0.inv;
167 cat0->comp = instr->cat0.comp;
168 cat0->opc = instr->opc;
169 cat0->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
170 cat0->sync = !!(instr->flags & IR3_INSTR_SY);
171 cat0->opc_cat = 0;
172
173 return 0;
174 }
175
176 static uint32_t type_flags(type_t type)
177 {
178 return (type_size(type) == 32) ? 0 : IR3_REG_HALF;
179 }
180
181 static int emit_cat1(struct ir3_instruction *instr, void *ptr,
182 struct ir3_info *info)
183 {
184 struct ir3_register *dst = instr->regs[0];
185 struct ir3_register *src = instr->regs[1];
186 instr_cat1_t *cat1 = ptr;
187
188 iassert(instr->regs_count == 2);
189 iassert(!((dst->flags ^ type_flags(instr->cat1.dst_type)) & IR3_REG_HALF));
190 iassert((src->flags & IR3_REG_IMMED) ||
191 !((src->flags ^ type_flags(instr->cat1.src_type)) & IR3_REG_HALF));
192
193 if (src->flags & IR3_REG_IMMED) {
194 cat1->iim_val = src->iim_val;
195 cat1->src_im = 1;
196 } else if (src->flags & IR3_REG_RELATIV) {
197 cat1->off = reg(src, info, instr->repeat,
198 IR3_REG_R | IR3_REG_CONST | IR3_REG_HALF | IR3_REG_RELATIV);
199 cat1->src_rel = 1;
200 cat1->src_rel_c = !!(src->flags & IR3_REG_CONST);
201 } else {
202 cat1->src = reg(src, info, instr->repeat,
203 IR3_REG_R | IR3_REG_CONST | IR3_REG_HALF);
204 cat1->src_c = !!(src->flags & IR3_REG_CONST);
205 }
206
207 cat1->dst = reg(dst, info, instr->repeat,
208 IR3_REG_RELATIV | IR3_REG_EVEN |
209 IR3_REG_R | IR3_REG_POS_INF | IR3_REG_HALF);
210 cat1->repeat = instr->repeat;
211 cat1->src_r = !!(src->flags & IR3_REG_R);
212 cat1->ss = !!(instr->flags & IR3_INSTR_SS);
213 cat1->ul = !!(instr->flags & IR3_INSTR_UL);
214 cat1->dst_type = instr->cat1.dst_type;
215 cat1->dst_rel = !!(dst->flags & IR3_REG_RELATIV);
216 cat1->src_type = instr->cat1.src_type;
217 cat1->even = !!(dst->flags & IR3_REG_EVEN);
218 cat1->pos_inf = !!(dst->flags & IR3_REG_POS_INF);
219 cat1->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
220 cat1->sync = !!(instr->flags & IR3_INSTR_SY);
221 cat1->opc_cat = 1;
222
223 return 0;
224 }
225
226 static int emit_cat2(struct ir3_instruction *instr, void *ptr,
227 struct ir3_info *info)
228 {
229 struct ir3_register *dst = instr->regs[0];
230 struct ir3_register *src1 = instr->regs[1];
231 struct ir3_register *src2 = instr->regs[2];
232 instr_cat2_t *cat2 = ptr;
233 unsigned absneg = ir3_cat2_absneg(instr->opc);
234
235 iassert((instr->regs_count == 2) || (instr->regs_count == 3));
236
237 if (src1->flags & IR3_REG_RELATIV) {
238 iassert(src1->array.offset < (1 << 10));
239 cat2->rel1.src1 = reg(src1, info, instr->repeat,
240 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_R |
241 IR3_REG_HALF | absneg);
242 cat2->rel1.src1_c = !!(src1->flags & IR3_REG_CONST);
243 cat2->rel1.src1_rel = 1;
244 } else if (src1->flags & IR3_REG_CONST) {
245 iassert(src1->num < (1 << 12));
246 cat2->c1.src1 = reg(src1, info, instr->repeat,
247 IR3_REG_CONST | IR3_REG_R | IR3_REG_HALF);
248 cat2->c1.src1_c = 1;
249 } else {
250 iassert(src1->num < (1 << 11));
251 cat2->src1 = reg(src1, info, instr->repeat,
252 IR3_REG_IMMED | IR3_REG_R | IR3_REG_HALF |
253 absneg);
254 }
255 cat2->src1_im = !!(src1->flags & IR3_REG_IMMED);
256 cat2->src1_neg = !!(src1->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT));
257 cat2->src1_abs = !!(src1->flags & (IR3_REG_FABS | IR3_REG_SABS));
258 cat2->src1_r = !!(src1->flags & IR3_REG_R);
259
260 if (src2) {
261 iassert((src2->flags & IR3_REG_IMMED) ||
262 !((src1->flags ^ src2->flags) & IR3_REG_HALF));
263
264 if (src2->flags & IR3_REG_RELATIV) {
265 iassert(src2->array.offset < (1 << 10));
266 cat2->rel2.src2 = reg(src2, info, instr->repeat,
267 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_R |
268 IR3_REG_HALF | absneg);
269 cat2->rel2.src2_c = !!(src2->flags & IR3_REG_CONST);
270 cat2->rel2.src2_rel = 1;
271 } else if (src2->flags & IR3_REG_CONST) {
272 iassert(src2->num < (1 << 12));
273 cat2->c2.src2 = reg(src2, info, instr->repeat,
274 IR3_REG_CONST | IR3_REG_R | IR3_REG_HALF);
275 cat2->c2.src2_c = 1;
276 } else {
277 iassert(src2->num < (1 << 11));
278 cat2->src2 = reg(src2, info, instr->repeat,
279 IR3_REG_IMMED | IR3_REG_R | IR3_REG_HALF |
280 absneg);
281 }
282
283 cat2->src2_im = !!(src2->flags & IR3_REG_IMMED);
284 cat2->src2_neg = !!(src2->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT));
285 cat2->src2_abs = !!(src2->flags & (IR3_REG_FABS | IR3_REG_SABS));
286 cat2->src2_r = !!(src2->flags & IR3_REG_R);
287 }
288
289 cat2->dst = reg(dst, info, instr->repeat,
290 IR3_REG_R | IR3_REG_EI | IR3_REG_HALF);
291 cat2->repeat = instr->repeat;
292 cat2->ss = !!(instr->flags & IR3_INSTR_SS);
293 cat2->ul = !!(instr->flags & IR3_INSTR_UL);
294 cat2->dst_half = !!((src1->flags ^ dst->flags) & IR3_REG_HALF);
295 cat2->ei = !!(dst->flags & IR3_REG_EI);
296 cat2->cond = instr->cat2.condition;
297 cat2->full = ! (src1->flags & IR3_REG_HALF);
298 cat2->opc = instr->opc;
299 cat2->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
300 cat2->sync = !!(instr->flags & IR3_INSTR_SY);
301 cat2->opc_cat = 2;
302
303 return 0;
304 }
305
306 static int emit_cat3(struct ir3_instruction *instr, void *ptr,
307 struct ir3_info *info)
308 {
309 struct ir3_register *dst = instr->regs[0];
310 struct ir3_register *src1 = instr->regs[1];
311 struct ir3_register *src2 = instr->regs[2];
312 struct ir3_register *src3 = instr->regs[3];
313 unsigned absneg = ir3_cat3_absneg(instr->opc);
314 instr_cat3_t *cat3 = ptr;
315 uint32_t src_flags = 0;
316
317 switch (instr->opc) {
318 case OPC_MAD_F16:
319 case OPC_MAD_U16:
320 case OPC_MAD_S16:
321 case OPC_SEL_B16:
322 case OPC_SEL_S16:
323 case OPC_SEL_F16:
324 case OPC_SAD_S16:
325 case OPC_SAD_S32: // really??
326 src_flags |= IR3_REG_HALF;
327 break;
328 default:
329 break;
330 }
331
332 iassert(instr->regs_count == 4);
333 iassert(!((src1->flags ^ src_flags) & IR3_REG_HALF));
334 iassert(!((src2->flags ^ src_flags) & IR3_REG_HALF));
335 iassert(!((src3->flags ^ src_flags) & IR3_REG_HALF));
336
337 if (src1->flags & IR3_REG_RELATIV) {
338 iassert(src1->array.offset < (1 << 10));
339 cat3->rel1.src1 = reg(src1, info, instr->repeat,
340 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_R |
341 IR3_REG_HALF | absneg);
342 cat3->rel1.src1_c = !!(src1->flags & IR3_REG_CONST);
343 cat3->rel1.src1_rel = 1;
344 } else if (src1->flags & IR3_REG_CONST) {
345 iassert(src1->num < (1 << 12));
346 cat3->c1.src1 = reg(src1, info, instr->repeat,
347 IR3_REG_CONST | IR3_REG_R | IR3_REG_HALF);
348 cat3->c1.src1_c = 1;
349 } else {
350 iassert(src1->num < (1 << 11));
351 cat3->src1 = reg(src1, info, instr->repeat,
352 IR3_REG_R | IR3_REG_HALF | absneg);
353 }
354
355 cat3->src1_neg = !!(src1->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT));
356 cat3->src1_r = !!(src1->flags & IR3_REG_R);
357
358 cat3->src2 = reg(src2, info, instr->repeat,
359 IR3_REG_CONST | IR3_REG_R | IR3_REG_HALF | absneg);
360 cat3->src2_c = !!(src2->flags & IR3_REG_CONST);
361 cat3->src2_neg = !!(src2->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT));
362 cat3->src2_r = !!(src2->flags & IR3_REG_R);
363
364
365 if (src3->flags & IR3_REG_RELATIV) {
366 iassert(src3->array.offset < (1 << 10));
367 cat3->rel2.src3 = reg(src3, info, instr->repeat,
368 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_R |
369 IR3_REG_HALF | absneg);
370 cat3->rel2.src3_c = !!(src3->flags & IR3_REG_CONST);
371 cat3->rel2.src3_rel = 1;
372 } else if (src3->flags & IR3_REG_CONST) {
373 iassert(src3->num < (1 << 12));
374 cat3->c2.src3 = reg(src3, info, instr->repeat,
375 IR3_REG_CONST | IR3_REG_R | IR3_REG_HALF);
376 cat3->c2.src3_c = 1;
377 } else {
378 iassert(src3->num < (1 << 11));
379 cat3->src3 = reg(src3, info, instr->repeat,
380 IR3_REG_R | IR3_REG_HALF | absneg);
381 }
382
383 cat3->src3_neg = !!(src3->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT));
384 cat3->src3_r = !!(src3->flags & IR3_REG_R);
385
386 cat3->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
387 cat3->repeat = instr->repeat;
388 cat3->ss = !!(instr->flags & IR3_INSTR_SS);
389 cat3->ul = !!(instr->flags & IR3_INSTR_UL);
390 cat3->dst_half = !!((src_flags ^ dst->flags) & IR3_REG_HALF);
391 cat3->opc = instr->opc;
392 cat3->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
393 cat3->sync = !!(instr->flags & IR3_INSTR_SY);
394 cat3->opc_cat = 3;
395
396 return 0;
397 }
398
399 static int emit_cat4(struct ir3_instruction *instr, void *ptr,
400 struct ir3_info *info)
401 {
402 struct ir3_register *dst = instr->regs[0];
403 struct ir3_register *src = instr->regs[1];
404 instr_cat4_t *cat4 = ptr;
405
406 iassert(instr->regs_count == 2);
407
408 if (src->flags & IR3_REG_RELATIV) {
409 iassert(src->array.offset < (1 << 10));
410 cat4->rel.src = reg(src, info, instr->repeat,
411 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_FNEG |
412 IR3_REG_FABS | IR3_REG_R | IR3_REG_HALF);
413 cat4->rel.src_c = !!(src->flags & IR3_REG_CONST);
414 cat4->rel.src_rel = 1;
415 } else if (src->flags & IR3_REG_CONST) {
416 iassert(src->num < (1 << 12));
417 cat4->c.src = reg(src, info, instr->repeat,
418 IR3_REG_CONST | IR3_REG_FNEG | IR3_REG_FABS |
419 IR3_REG_R | IR3_REG_HALF);
420 cat4->c.src_c = 1;
421 } else {
422 iassert(src->num < (1 << 11));
423 cat4->src = reg(src, info, instr->repeat,
424 IR3_REG_IMMED | IR3_REG_FNEG | IR3_REG_FABS |
425 IR3_REG_R | IR3_REG_HALF);
426 }
427
428 cat4->src_im = !!(src->flags & IR3_REG_IMMED);
429 cat4->src_neg = !!(src->flags & IR3_REG_FNEG);
430 cat4->src_abs = !!(src->flags & IR3_REG_FABS);
431 cat4->src_r = !!(src->flags & IR3_REG_R);
432
433 cat4->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
434 cat4->repeat = instr->repeat;
435 cat4->ss = !!(instr->flags & IR3_INSTR_SS);
436 cat4->ul = !!(instr->flags & IR3_INSTR_UL);
437 cat4->dst_half = !!((src->flags ^ dst->flags) & IR3_REG_HALF);
438 cat4->full = ! (src->flags & IR3_REG_HALF);
439 cat4->opc = instr->opc;
440 cat4->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
441 cat4->sync = !!(instr->flags & IR3_INSTR_SY);
442 cat4->opc_cat = 4;
443
444 return 0;
445 }
446
447 static int emit_cat5(struct ir3_instruction *instr, void *ptr,
448 struct ir3_info *info)
449 {
450 struct ir3_register *dst = instr->regs[0];
451 struct ir3_register *src1 = instr->regs[1];
452 struct ir3_register *src2 = instr->regs[2];
453 struct ir3_register *src3 = instr->regs[3];
454 instr_cat5_t *cat5 = ptr;
455
456 iassert(!((dst->flags ^ type_flags(instr->cat5.type)) & IR3_REG_HALF));
457
458 if (src1) {
459 cat5->full = ! (src1->flags & IR3_REG_HALF);
460 cat5->src1 = reg(src1, info, instr->repeat, IR3_REG_HALF);
461 }
462
463
464 if (instr->flags & IR3_INSTR_S2EN) {
465 if (src2) {
466 iassert(!((src1->flags ^ src2->flags) & IR3_REG_HALF));
467 cat5->s2en.src2 = reg(src2, info, instr->repeat, IR3_REG_HALF);
468 }
469 if (src3) {
470 iassert(src3->flags & IR3_REG_HALF);
471 cat5->s2en.src3 = reg(src3, info, instr->repeat, IR3_REG_HALF);
472 }
473 iassert(!(instr->cat5.samp | instr->cat5.tex));
474 } else {
475 iassert(!src3);
476 if (src2) {
477 iassert(!((src1->flags ^ src2->flags) & IR3_REG_HALF));
478 cat5->norm.src2 = reg(src2, info, instr->repeat, IR3_REG_HALF);
479 }
480 cat5->norm.samp = instr->cat5.samp;
481 cat5->norm.tex = instr->cat5.tex;
482 }
483
484 cat5->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
485 cat5->wrmask = dst->wrmask;
486 cat5->type = instr->cat5.type;
487 cat5->is_3d = !!(instr->flags & IR3_INSTR_3D);
488 cat5->is_a = !!(instr->flags & IR3_INSTR_A);
489 cat5->is_s = !!(instr->flags & IR3_INSTR_S);
490 cat5->is_s2en = !!(instr->flags & IR3_INSTR_S2EN);
491 cat5->is_o = !!(instr->flags & IR3_INSTR_O);
492 cat5->is_p = !!(instr->flags & IR3_INSTR_P);
493 cat5->opc = instr->opc;
494 cat5->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
495 cat5->sync = !!(instr->flags & IR3_INSTR_SY);
496 cat5->opc_cat = 5;
497
498 return 0;
499 }
500
501 static int emit_cat6(struct ir3_instruction *instr, void *ptr,
502 struct ir3_info *info)
503 {
504 struct ir3_register *dst, *src1, *src2;
505 instr_cat6_t *cat6 = ptr;
506
507 /* the "dst" for a store instruction is (from the perspective
508 * of data flow in the shader, ie. register use/def, etc) in
509 * fact a register that is read by the instruction, rather
510 * than written:
511 */
512 if (is_store(instr)) {
513 iassert(instr->regs_count >= 3);
514
515 dst = instr->regs[1];
516 src1 = instr->regs[2];
517 src2 = (instr->regs_count >= 4) ? instr->regs[3] : NULL;
518 } else {
519 iassert(instr->regs_count >= 2);
520
521 dst = instr->regs[0];
522 src1 = instr->regs[1];
523 src2 = (instr->regs_count >= 3) ? instr->regs[2] : NULL;
524 }
525
526
527 /* TODO we need a more comprehensive list about which instructions
528 * can be encoded which way. Or possibly use IR3_INSTR_0 flag to
529 * indicate to use the src_off encoding even if offset is zero
530 * (but then what to do about dst_off?)
531 */
532 if (instr->cat6.src_offset || (instr->opc == OPC_LDG)) {
533 instr_cat6a_t *cat6a = ptr;
534
535 cat6->src_off = true;
536
537 cat6a->src1 = reg(src1, info, instr->repeat, IR3_REG_IMMED);
538 cat6a->src1_im = !!(src1->flags & IR3_REG_IMMED);
539 if (src2) {
540 cat6a->src2 = reg(src2, info, instr->repeat, IR3_REG_IMMED);
541 cat6a->src2_im = !!(src2->flags & IR3_REG_IMMED);
542 }
543 cat6a->off = instr->cat6.src_offset;
544 } else {
545 instr_cat6b_t *cat6b = ptr;
546
547 cat6->src_off = false;
548
549 cat6b->src1 = reg(src1, info, instr->repeat, IR3_REG_IMMED);
550 cat6b->src1_im = !!(src1->flags & IR3_REG_IMMED);
551 if (src2) {
552 cat6b->src2 = reg(src2, info, instr->repeat, IR3_REG_IMMED);
553 cat6b->src2_im = !!(src2->flags & IR3_REG_IMMED);
554 }
555 }
556
557 if (instr->cat6.dst_offset || (instr->opc == OPC_STG)) {
558 instr_cat6c_t *cat6c = ptr;
559 cat6->dst_off = true;
560 cat6c->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
561 cat6c->off = instr->cat6.dst_offset;
562 } else {
563 instr_cat6d_t *cat6d = ptr;
564 cat6->dst_off = false;
565 cat6d->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
566 }
567
568 cat6->type = instr->cat6.type;
569 cat6->opc = instr->opc;
570 cat6->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
571 cat6->sync = !!(instr->flags & IR3_INSTR_SY);
572 cat6->g = !!(instr->flags & IR3_INSTR_G);
573 cat6->opc_cat = 6;
574
575 return 0;
576 }
577
578 static int (*emit[])(struct ir3_instruction *instr, void *ptr,
579 struct ir3_info *info) = {
580 emit_cat0, emit_cat1, emit_cat2, emit_cat3, emit_cat4, emit_cat5, emit_cat6,
581 };
582
583 void * ir3_assemble(struct ir3 *shader, struct ir3_info *info,
584 uint32_t gpu_id)
585 {
586 uint32_t *ptr, *dwords;
587
588 info->gpu_id = gpu_id;
589 info->max_reg = -1;
590 info->max_half_reg = -1;
591 info->max_const = -1;
592 info->instrs_count = 0;
593 info->sizedwords = 0;
594
595 list_for_each_entry (struct ir3_block, block, &shader->block_list, node) {
596 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
597 info->sizedwords += 2;
598 }
599 }
600
601 /* need a integer number of instruction "groups" (sets of 16
602 * instructions on a4xx or sets of 4 instructions on a3xx),
603 * so pad out w/ NOPs if needed: (NOTE each instruction is 64bits)
604 */
605 if (gpu_id >= 400) {
606 info->sizedwords = align(info->sizedwords, 16 * 2);
607 } else {
608 info->sizedwords = align(info->sizedwords, 4 * 2);
609 }
610
611 ptr = dwords = calloc(4, info->sizedwords);
612
613 list_for_each_entry (struct ir3_block, block, &shader->block_list, node) {
614 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
615 int ret = emit[instr->category](instr, dwords, info);
616 if (ret)
617 goto fail;
618 info->instrs_count += 1 + instr->repeat;
619 dwords += 2;
620 }
621 }
622
623 return ptr;
624
625 fail:
626 free(ptr);
627 return NULL;
628 }
629
630 static struct ir3_register * reg_create(struct ir3 *shader,
631 int num, int flags)
632 {
633 struct ir3_register *reg =
634 ir3_alloc(shader, sizeof(struct ir3_register));
635 reg->wrmask = 1;
636 reg->flags = flags;
637 reg->num = num;
638 return reg;
639 }
640
641 static void insert_instr(struct ir3_block *block,
642 struct ir3_instruction *instr)
643 {
644 struct ir3 *shader = block->shader;
645 #ifdef DEBUG
646 static uint32_t serialno = 0;
647 instr->serialno = ++serialno;
648 #endif
649 list_addtail(&instr->node, &block->instr_list);
650
651 if (is_input(instr))
652 array_insert(shader->baryfs, instr);
653 }
654
655 struct ir3_block * ir3_block_create(struct ir3 *shader)
656 {
657 struct ir3_block *block = ir3_alloc(shader, sizeof(*block));
658 #ifdef DEBUG
659 static uint32_t serialno = 0;
660 block->serialno = ++serialno;
661 #endif
662 block->shader = shader;
663 list_inithead(&block->node);
664 list_inithead(&block->instr_list);
665 return block;
666 }
667
668 static struct ir3_instruction *instr_create(struct ir3_block *block, int nreg)
669 {
670 struct ir3_instruction *instr;
671 unsigned sz = sizeof(*instr) + (nreg * sizeof(instr->regs[0]));
672 char *ptr = ir3_alloc(block->shader, sz);
673
674 instr = (struct ir3_instruction *)ptr;
675 ptr += sizeof(*instr);
676 instr->regs = (struct ir3_register **)ptr;
677
678 #ifdef DEBUG
679 instr->regs_max = nreg;
680 #endif
681
682 return instr;
683 }
684
685 struct ir3_instruction * ir3_instr_create2(struct ir3_block *block,
686 int category, opc_t opc, int nreg)
687 {
688 struct ir3_instruction *instr = instr_create(block, nreg);
689 instr->block = block;
690 instr->category = category;
691 debug_assert(opc_cat(opc) == category);
692 instr->opc = opc;
693 insert_instr(block, instr);
694 return instr;
695 }
696
697 struct ir3_instruction * ir3_instr_create(struct ir3_block *block,
698 int category, opc_t opc)
699 {
700 /* NOTE: we could be slightly more clever, at least for non-meta,
701 * and choose # of regs based on category.
702 */
703 return ir3_instr_create2(block, category, opc, 4);
704 }
705
706 struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr)
707 {
708 struct ir3_instruction *new_instr = instr_create(instr->block,
709 instr->regs_count);
710 struct ir3_register **regs;
711 unsigned i;
712
713 regs = new_instr->regs;
714 *new_instr = *instr;
715 new_instr->regs = regs;
716
717 insert_instr(instr->block, new_instr);
718
719 /* clone registers: */
720 new_instr->regs_count = 0;
721 for (i = 0; i < instr->regs_count; i++) {
722 struct ir3_register *reg = instr->regs[i];
723 struct ir3_register *new_reg =
724 ir3_reg_create(new_instr, reg->num, reg->flags);
725 *new_reg = *reg;
726 }
727
728 return new_instr;
729 }
730
731 struct ir3_register * ir3_reg_create(struct ir3_instruction *instr,
732 int num, int flags)
733 {
734 struct ir3 *shader = instr->block->shader;
735 struct ir3_register *reg = reg_create(shader, num, flags);
736 #ifdef DEBUG
737 debug_assert(instr->regs_count < instr->regs_max);
738 #endif
739 instr->regs[instr->regs_count++] = reg;
740 return reg;
741 }
742
743 struct ir3_register * ir3_reg_clone(struct ir3 *shader,
744 struct ir3_register *reg)
745 {
746 struct ir3_register *new_reg = reg_create(shader, 0, 0);
747 *new_reg = *reg;
748 return new_reg;
749 }
750
751 void
752 ir3_instr_set_address(struct ir3_instruction *instr,
753 struct ir3_instruction *addr)
754 {
755 if (instr->address != addr) {
756 struct ir3 *ir = instr->block->shader;
757 instr->address = addr;
758 array_insert(ir->indirects, instr);
759 }
760 }
761
762 void
763 ir3_block_clear_mark(struct ir3_block *block)
764 {
765 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node)
766 instr->flags &= ~IR3_INSTR_MARK;
767 }
768
769 void
770 ir3_clear_mark(struct ir3 *ir)
771 {
772 list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
773 ir3_block_clear_mark(block);
774 }
775 }
776
777 /* note: this will destroy instr->depth, don't do it until after sched! */
778 unsigned
779 ir3_count_instructions(struct ir3 *ir)
780 {
781 unsigned cnt = 0;
782 list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
783 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
784 instr->ip = cnt++;
785 }
786 block->start_ip = list_first_entry(&block->instr_list, struct ir3_instruction, node)->ip;
787 block->end_ip = list_last_entry(&block->instr_list, struct ir3_instruction, node)->ip;
788 }
789 return cnt;
790 }
791
792 struct ir3_array *
793 ir3_lookup_array(struct ir3 *ir, unsigned id)
794 {
795 list_for_each_entry (struct ir3_array, arr, &ir->array_list, node)
796 if (arr->id == id)
797 return arr;
798 return NULL;
799 }