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[mesa.git] / src / gallium / drivers / freedreno / ir3 / ir3.h
1 /*
2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #ifndef IR3_H_
25 #define IR3_H_
26
27 #include <stdint.h>
28 #include <stdbool.h>
29
30 #include "util/u_debug.h"
31 #include "util/list.h"
32
33 #include "instr-a3xx.h"
34 #include "disasm.h" /* TODO move 'enum shader_t' somewhere else.. */
35
36 /* low level intermediate representation of an adreno shader program */
37
38 struct ir3_compiler;
39 struct ir3;
40 struct ir3_instruction;
41 struct ir3_block;
42
43 struct ir3_info {
44 uint32_t gpu_id;
45 uint16_t sizedwords;
46 uint16_t instrs_count; /* expanded to account for rpt's */
47 /* NOTE: max_reg, etc, does not include registers not touched
48 * by the shader (ie. vertex fetched via VFD_DECODE but not
49 * touched by shader)
50 */
51 int8_t max_reg; /* highest GPR # used by shader */
52 int8_t max_half_reg;
53 int16_t max_const;
54 };
55
56 struct ir3_register {
57 enum {
58 IR3_REG_CONST = 0x001,
59 IR3_REG_IMMED = 0x002,
60 IR3_REG_HALF = 0x004,
61 /* high registers are used for some things in compute shaders,
62 * for example. Seems to be for things that are global to all
63 * threads in a wave, so possibly these are global/shared by
64 * all the threads in the wave?
65 */
66 IR3_REG_HIGH = 0x008,
67 IR3_REG_RELATIV= 0x010,
68 IR3_REG_R = 0x020,
69 /* Most instructions, it seems, can do float abs/neg but not
70 * integer. The CP pass needs to know what is intended (int or
71 * float) in order to do the right thing. For this reason the
72 * abs/neg flags are split out into float and int variants. In
73 * addition, .b (bitwise) operations, the negate is actually a
74 * bitwise not, so split that out into a new flag to make it
75 * more clear.
76 */
77 IR3_REG_FNEG = 0x040,
78 IR3_REG_FABS = 0x080,
79 IR3_REG_SNEG = 0x100,
80 IR3_REG_SABS = 0x200,
81 IR3_REG_BNOT = 0x400,
82 IR3_REG_EVEN = 0x800,
83 IR3_REG_POS_INF= 0x1000,
84 /* (ei) flag, end-input? Set on last bary, presumably to signal
85 * that the shader needs no more input:
86 */
87 IR3_REG_EI = 0x2000,
88 /* meta-flags, for intermediate stages of IR, ie.
89 * before register assignment is done:
90 */
91 IR3_REG_SSA = 0x4000, /* 'instr' is ptr to assigning instr */
92 IR3_REG_ARRAY = 0x8000,
93 IR3_REG_PHI_SRC= 0x10000, /* phi src, regs[0]->instr points to phi */
94
95 } flags;
96 union {
97 /* normal registers:
98 * the component is in the low two bits of the reg #, so
99 * rN.x becomes: (N << 2) | x
100 */
101 int num;
102 /* immediate: */
103 int32_t iim_val;
104 uint32_t uim_val;
105 float fim_val;
106 /* relative: */
107 struct {
108 uint16_t id;
109 int16_t offset;
110 } array;
111 };
112
113 /* For IR3_REG_SSA, src registers contain ptr back to assigning
114 * instruction.
115 *
116 * For IR3_REG_ARRAY, the pointer is back to the last dependent
117 * array access (although the net effect is the same, it points
118 * back to a previous instruction that we depend on).
119 */
120 struct ir3_instruction *instr;
121
122 union {
123 /* used for cat5 instructions, but also for internal/IR level
124 * tracking of what registers are read/written by an instruction.
125 * wrmask may be a bad name since it is used to represent both
126 * src and dst that touch multiple adjacent registers.
127 */
128 unsigned wrmask;
129 /* for relative addressing, 32bits for array size is too small,
130 * but otoh we don't need to deal with disjoint sets, so instead
131 * use a simple size field (number of scalar components).
132 */
133 unsigned size;
134 };
135 };
136
137 /*
138 * Stupid/simple growable array implementation:
139 */
140 #define DECLARE_ARRAY(type, name) \
141 unsigned name ## _count, name ## _sz; \
142 type * name;
143
144 #define array_insert(ctx, arr, val) do { \
145 if (arr ## _count == arr ## _sz) { \
146 arr ## _sz = MAX2(2 * arr ## _sz, 16); \
147 arr = reralloc_size(ctx, arr, arr ## _sz * sizeof(arr[0])); \
148 } \
149 arr[arr ##_count++] = val; \
150 } while (0)
151
152 struct ir3_instruction {
153 struct ir3_block *block;
154 opc_t opc;
155 enum {
156 /* (sy) flag is set on first instruction, and after sample
157 * instructions (probably just on RAW hazard).
158 */
159 IR3_INSTR_SY = 0x001,
160 /* (ss) flag is set on first instruction, and first instruction
161 * to depend on the result of "long" instructions (RAW hazard):
162 *
163 * rcp, rsq, log2, exp2, sin, cos, sqrt
164 *
165 * It seems to synchronize until all in-flight instructions are
166 * completed, for example:
167 *
168 * rsq hr1.w, hr1.w
169 * add.f hr2.z, (neg)hr2.z, hc0.y
170 * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
171 * rsq hr2.x, hr2.x
172 * (rpt1)nop
173 * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
174 * nop
175 * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
176 * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
177 * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
178 *
179 * The last mul.f does not have (ss) set, presumably because the
180 * (ss) on the previous instruction does the job.
181 *
182 * The blob driver also seems to set it on WAR hazards, although
183 * not really clear if this is needed or just blob compiler being
184 * sloppy. So far I haven't found a case where removing the (ss)
185 * causes problems for WAR hazard, but I could just be getting
186 * lucky:
187 *
188 * rcp r1.y, r3.y
189 * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
190 *
191 */
192 IR3_INSTR_SS = 0x002,
193 /* (jp) flag is set on jump targets:
194 */
195 IR3_INSTR_JP = 0x004,
196 IR3_INSTR_UL = 0x008,
197 IR3_INSTR_3D = 0x010,
198 IR3_INSTR_A = 0x020,
199 IR3_INSTR_O = 0x040,
200 IR3_INSTR_P = 0x080,
201 IR3_INSTR_S = 0x100,
202 IR3_INSTR_S2EN = 0x200,
203 IR3_INSTR_G = 0x400,
204 /* meta-flags, for intermediate stages of IR, ie.
205 * before register assignment is done:
206 */
207 IR3_INSTR_MARK = 0x1000,
208 IR3_INSTR_UNUSED= 0x2000,
209 } flags;
210 int repeat;
211 #ifdef DEBUG
212 unsigned regs_max;
213 #endif
214 unsigned regs_count;
215 struct ir3_register **regs;
216 union {
217 struct {
218 char inv;
219 char comp;
220 int immed;
221 struct ir3_block *target;
222 } cat0;
223 struct {
224 type_t src_type, dst_type;
225 } cat1;
226 struct {
227 enum {
228 IR3_COND_LT = 0,
229 IR3_COND_LE = 1,
230 IR3_COND_GT = 2,
231 IR3_COND_GE = 3,
232 IR3_COND_EQ = 4,
233 IR3_COND_NE = 5,
234 } condition;
235 } cat2;
236 struct {
237 unsigned samp, tex;
238 type_t type;
239 } cat5;
240 struct {
241 type_t type;
242 int src_offset;
243 int dst_offset;
244 int iim_val : 3; /* for ldgb/stgb, # of components */
245 int d : 3;
246 bool typed : 1;
247 } cat6;
248 struct {
249 unsigned w : 1; /* write */
250 unsigned r : 1; /* read */
251 unsigned l : 1; /* local */
252 unsigned g : 1; /* global */
253 } cat7;
254 /* for meta-instructions, just used to hold extra data
255 * before instruction scheduling, etc
256 */
257 struct {
258 int off; /* component/offset */
259 } fo;
260 struct {
261 /* used to temporarily hold reference to nir_phi_instr
262 * until we resolve the phi srcs
263 */
264 void *nphi;
265 } phi;
266 struct {
267 struct ir3_block *block;
268 } inout;
269 };
270
271 /* transient values used during various algorithms: */
272 union {
273 /* The instruction depth is the max dependency distance to output.
274 *
275 * You can also think of it as the "cost", if we did any sort of
276 * optimization for register footprint. Ie. a value that is just
277 * result of moving a const to a reg would have a low cost, so to
278 * it could make sense to duplicate the instruction at various
279 * points where the result is needed to reduce register footprint.
280 */
281 unsigned depth;
282 /* When we get to the RA stage, we no longer need depth, but
283 * we do need instruction's position/name:
284 */
285 struct {
286 uint16_t ip;
287 uint16_t name;
288 };
289 };
290
291 /* used for per-pass extra instruction data.
292 */
293 void *data;
294
295 /* Used during CP and RA stages. For fanin and shader inputs/
296 * outputs where we need a sequence of consecutive registers,
297 * keep track of each src instructions left (ie 'n-1') and right
298 * (ie 'n+1') neighbor. The front-end must insert enough mov's
299 * to ensure that each instruction has at most one left and at
300 * most one right neighbor. During the copy-propagation pass,
301 * we only remove mov's when we can preserve this constraint.
302 * And during the RA stage, we use the neighbor information to
303 * allocate a block of registers in one shot.
304 *
305 * TODO: maybe just add something like:
306 * struct ir3_instruction_ref {
307 * struct ir3_instruction *instr;
308 * unsigned cnt;
309 * }
310 *
311 * Or can we get away without the refcnt stuff? It seems like
312 * it should be overkill.. the problem is if, potentially after
313 * already eliminating some mov's, if you have a single mov that
314 * needs to be grouped with it's neighbors in two different
315 * places (ex. shader output and a fanin).
316 */
317 struct {
318 struct ir3_instruction *left, *right;
319 uint16_t left_cnt, right_cnt;
320 } cp;
321
322 /* an instruction can reference at most one address register amongst
323 * it's src/dst registers. Beyond that, you need to insert mov's.
324 *
325 * NOTE: do not write this directly, use ir3_instr_set_address()
326 */
327 struct ir3_instruction *address;
328
329 /* Entry in ir3_block's instruction list: */
330 struct list_head node;
331
332 #ifdef DEBUG
333 uint32_t serialno;
334 #endif
335 };
336
337 static inline struct ir3_instruction *
338 ir3_neighbor_first(struct ir3_instruction *instr)
339 {
340 int cnt = 0;
341 while (instr->cp.left) {
342 instr = instr->cp.left;
343 if (++cnt > 0xffff) {
344 debug_assert(0);
345 break;
346 }
347 }
348 return instr;
349 }
350
351 static inline int ir3_neighbor_count(struct ir3_instruction *instr)
352 {
353 int num = 1;
354
355 debug_assert(!instr->cp.left);
356
357 while (instr->cp.right) {
358 num++;
359 instr = instr->cp.right;
360 if (num > 0xffff) {
361 debug_assert(0);
362 break;
363 }
364 }
365
366 return num;
367 }
368
369 struct ir3 {
370 struct ir3_compiler *compiler;
371
372 unsigned ninputs, noutputs;
373 struct ir3_instruction **inputs;
374 struct ir3_instruction **outputs;
375
376 /* Track bary.f (and ldlv) instructions.. this is needed in
377 * scheduling to ensure that all varying fetches happen before
378 * any potential kill instructions. The hw gets grumpy if all
379 * threads in a group are killed before the last bary.f gets
380 * a chance to signal end of input (ei).
381 */
382 DECLARE_ARRAY(struct ir3_instruction *, baryfs);
383
384 /* Track all indirect instructions (read and write). To avoid
385 * deadlock scenario where an address register gets scheduled,
386 * but other dependent src instructions cannot be scheduled due
387 * to dependency on a *different* address register value, the
388 * scheduler needs to ensure that all dependencies other than
389 * the instruction other than the address register are scheduled
390 * before the one that writes the address register. Having a
391 * convenient list of instructions that reference some address
392 * register simplifies this.
393 */
394 DECLARE_ARRAY(struct ir3_instruction *, indirects);
395
396 /* and same for instructions that consume predicate register: */
397 DECLARE_ARRAY(struct ir3_instruction *, predicates);
398
399 /* Track texture sample instructions which need texture state
400 * patched in (for astc-srgb workaround):
401 */
402 DECLARE_ARRAY(struct ir3_instruction *, astc_srgb);
403
404 /* List of blocks: */
405 struct list_head block_list;
406
407 /* List of ir3_array's: */
408 struct list_head array_list;
409 };
410
411 typedef struct nir_register nir_register;
412
413 struct ir3_array {
414 struct list_head node;
415 unsigned length;
416 unsigned id;
417
418 nir_register *r;
419
420 /* We track the last write and last access (read or write) to
421 * setup dependencies on instructions that read or write the
422 * array. Reads can be re-ordered wrt. other reads, but should
423 * not be re-ordered wrt. to writes. Writes cannot be reordered
424 * wrt. any other access to the array.
425 *
426 * So array reads depend on last write, and array writes depend
427 * on the last access.
428 */
429 struct ir3_instruction *last_write, *last_access;
430
431 /* extra stuff used in RA pass: */
432 unsigned base; /* base vreg name */
433 unsigned reg; /* base physical reg */
434 uint16_t start_ip, end_ip;
435 };
436
437 struct ir3_array * ir3_lookup_array(struct ir3 *ir, unsigned id);
438
439 typedef struct nir_block nir_block;
440
441 struct ir3_block {
442 struct list_head node;
443 struct ir3 *shader;
444
445 nir_block *nblock;
446
447 struct list_head instr_list; /* list of ir3_instruction */
448
449 /* each block has either one or two successors.. in case of
450 * two successors, 'condition' decides which one to follow.
451 * A block preceding an if/else has two successors.
452 */
453 struct ir3_instruction *condition;
454 struct ir3_block *successors[2];
455
456 uint16_t start_ip, end_ip;
457
458 /* Track instructions which do not write a register but other-
459 * wise must not be discarded (such as kill, stg, etc)
460 */
461 DECLARE_ARRAY(struct ir3_instruction *, keeps);
462
463 /* used for per-pass extra block data. Mainly used right
464 * now in RA step to track livein/liveout.
465 */
466 void *data;
467
468 #ifdef DEBUG
469 uint32_t serialno;
470 #endif
471 };
472
473 static inline uint32_t
474 block_id(struct ir3_block *block)
475 {
476 #ifdef DEBUG
477 return block->serialno;
478 #else
479 return (uint32_t)(unsigned long)block;
480 #endif
481 }
482
483 struct ir3 * ir3_create(struct ir3_compiler *compiler,
484 unsigned nin, unsigned nout);
485 void ir3_destroy(struct ir3 *shader);
486 void * ir3_assemble(struct ir3 *shader,
487 struct ir3_info *info, uint32_t gpu_id);
488 void * ir3_alloc(struct ir3 *shader, int sz);
489
490 struct ir3_block * ir3_block_create(struct ir3 *shader);
491
492 struct ir3_instruction * ir3_instr_create(struct ir3_block *block, opc_t opc);
493 struct ir3_instruction * ir3_instr_create2(struct ir3_block *block,
494 opc_t opc, int nreg);
495 struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr);
496 const char *ir3_instr_name(struct ir3_instruction *instr);
497
498 struct ir3_register * ir3_reg_create(struct ir3_instruction *instr,
499 int num, int flags);
500 struct ir3_register * ir3_reg_clone(struct ir3 *shader,
501 struct ir3_register *reg);
502
503 void ir3_instr_set_address(struct ir3_instruction *instr,
504 struct ir3_instruction *addr);
505
506 static inline bool ir3_instr_check_mark(struct ir3_instruction *instr)
507 {
508 if (instr->flags & IR3_INSTR_MARK)
509 return true; /* already visited */
510 instr->flags |= IR3_INSTR_MARK;
511 return false;
512 }
513
514 void ir3_block_clear_mark(struct ir3_block *block);
515 void ir3_clear_mark(struct ir3 *shader);
516
517 unsigned ir3_count_instructions(struct ir3 *ir);
518
519 static inline int ir3_instr_regno(struct ir3_instruction *instr,
520 struct ir3_register *reg)
521 {
522 unsigned i;
523 for (i = 0; i < instr->regs_count; i++)
524 if (reg == instr->regs[i])
525 return i;
526 return -1;
527 }
528
529
530 #define MAX_ARRAYS 16
531
532 /* comp:
533 * 0 - x
534 * 1 - y
535 * 2 - z
536 * 3 - w
537 */
538 static inline uint32_t regid(int num, int comp)
539 {
540 return (num << 2) | (comp & 0x3);
541 }
542
543 static inline uint32_t reg_num(struct ir3_register *reg)
544 {
545 return reg->num >> 2;
546 }
547
548 static inline uint32_t reg_comp(struct ir3_register *reg)
549 {
550 return reg->num & 0x3;
551 }
552
553 static inline bool is_flow(struct ir3_instruction *instr)
554 {
555 return (opc_cat(instr->opc) == 0);
556 }
557
558 static inline bool is_kill(struct ir3_instruction *instr)
559 {
560 return instr->opc == OPC_KILL;
561 }
562
563 static inline bool is_nop(struct ir3_instruction *instr)
564 {
565 return instr->opc == OPC_NOP;
566 }
567
568 /* Is it a non-transformative (ie. not type changing) mov? This can
569 * also include absneg.s/absneg.f, which for the most part can be
570 * treated as a mov (single src argument).
571 */
572 static inline bool is_same_type_mov(struct ir3_instruction *instr)
573 {
574 struct ir3_register *dst;
575
576 switch (instr->opc) {
577 case OPC_MOV:
578 if (instr->cat1.src_type != instr->cat1.dst_type)
579 return false;
580 break;
581 case OPC_ABSNEG_F:
582 case OPC_ABSNEG_S:
583 break;
584 default:
585 return false;
586 }
587
588 dst = instr->regs[0];
589
590 /* mov's that write to a0.x or p0.x are special: */
591 if (dst->num == regid(REG_P0, 0))
592 return false;
593 if (dst->num == regid(REG_A0, 0))
594 return false;
595
596 if (dst->flags & (IR3_REG_RELATIV | IR3_REG_ARRAY))
597 return false;
598
599 return true;
600 }
601
602 static inline bool is_alu(struct ir3_instruction *instr)
603 {
604 return (1 <= opc_cat(instr->opc)) && (opc_cat(instr->opc) <= 3);
605 }
606
607 static inline bool is_sfu(struct ir3_instruction *instr)
608 {
609 return (opc_cat(instr->opc) == 4);
610 }
611
612 static inline bool is_tex(struct ir3_instruction *instr)
613 {
614 return (opc_cat(instr->opc) == 5);
615 }
616
617 static inline bool is_mem(struct ir3_instruction *instr)
618 {
619 return (opc_cat(instr->opc) == 6);
620 }
621
622 static inline bool is_barrier(struct ir3_instruction *instr)
623 {
624 return (opc_cat(instr->opc) == 7);
625 }
626
627 static inline bool
628 is_store(struct ir3_instruction *instr)
629 {
630 /* these instructions, the "destination" register is
631 * actually a source, the address to store to.
632 */
633 switch (instr->opc) {
634 case OPC_STG:
635 case OPC_STGB:
636 case OPC_STIB:
637 case OPC_STP:
638 case OPC_STL:
639 case OPC_STLW:
640 case OPC_L2G:
641 case OPC_G2L:
642 return true;
643 default:
644 return false;
645 }
646 }
647
648 static inline bool is_load(struct ir3_instruction *instr)
649 {
650 switch (instr->opc) {
651 case OPC_LDG:
652 case OPC_LDGB:
653 case OPC_LDL:
654 case OPC_LDP:
655 case OPC_L2G:
656 case OPC_LDLW:
657 case OPC_LDC:
658 case OPC_LDLV:
659 /* probably some others too.. */
660 return true;
661 default:
662 return false;
663 }
664 }
665
666 static inline bool is_input(struct ir3_instruction *instr)
667 {
668 /* in some cases, ldlv is used to fetch varying without
669 * interpolation.. fortunately inloc is the first src
670 * register in either case
671 */
672 switch (instr->opc) {
673 case OPC_LDLV:
674 case OPC_BARY_F:
675 return true;
676 default:
677 return false;
678 }
679 }
680
681 static inline bool is_bool(struct ir3_instruction *instr)
682 {
683 switch (instr->opc) {
684 case OPC_CMPS_F:
685 case OPC_CMPS_S:
686 case OPC_CMPS_U:
687 return true;
688 default:
689 return false;
690 }
691 }
692
693 static inline bool is_meta(struct ir3_instruction *instr)
694 {
695 /* TODO how should we count PHI (and maybe fan-in/out) which
696 * might actually contribute some instructions to the final
697 * result?
698 */
699 return (opc_cat(instr->opc) == -1);
700 }
701
702 static inline bool writes_addr(struct ir3_instruction *instr)
703 {
704 if (instr->regs_count > 0) {
705 struct ir3_register *dst = instr->regs[0];
706 return reg_num(dst) == REG_A0;
707 }
708 return false;
709 }
710
711 static inline bool writes_pred(struct ir3_instruction *instr)
712 {
713 if (instr->regs_count > 0) {
714 struct ir3_register *dst = instr->regs[0];
715 return reg_num(dst) == REG_P0;
716 }
717 return false;
718 }
719
720 /* returns defining instruction for reg */
721 /* TODO better name */
722 static inline struct ir3_instruction *ssa(struct ir3_register *reg)
723 {
724 if (reg->flags & (IR3_REG_SSA | IR3_REG_ARRAY)) {
725 debug_assert(!(reg->instr && (reg->instr->flags & IR3_INSTR_UNUSED)));
726 return reg->instr;
727 }
728 return NULL;
729 }
730
731 static inline bool conflicts(struct ir3_instruction *a,
732 struct ir3_instruction *b)
733 {
734 return (a && b) && (a != b);
735 }
736
737 static inline bool reg_gpr(struct ir3_register *r)
738 {
739 if (r->flags & (IR3_REG_CONST | IR3_REG_IMMED))
740 return false;
741 if ((reg_num(r) == REG_A0) || (reg_num(r) == REG_P0))
742 return false;
743 return true;
744 }
745
746 static inline type_t half_type(type_t type)
747 {
748 switch (type) {
749 case TYPE_F32: return TYPE_F16;
750 case TYPE_U32: return TYPE_U16;
751 case TYPE_S32: return TYPE_S16;
752 case TYPE_F16:
753 case TYPE_U16:
754 case TYPE_S16:
755 return type;
756 default:
757 assert(0);
758 return ~0;
759 }
760 }
761
762 /* some cat2 instructions (ie. those which are not float) can embed an
763 * immediate:
764 */
765 static inline bool ir3_cat2_int(opc_t opc)
766 {
767 switch (opc) {
768 case OPC_ADD_U:
769 case OPC_ADD_S:
770 case OPC_SUB_U:
771 case OPC_SUB_S:
772 case OPC_CMPS_U:
773 case OPC_CMPS_S:
774 case OPC_MIN_U:
775 case OPC_MIN_S:
776 case OPC_MAX_U:
777 case OPC_MAX_S:
778 case OPC_CMPV_U:
779 case OPC_CMPV_S:
780 case OPC_MUL_U:
781 case OPC_MUL_S:
782 case OPC_MULL_U:
783 case OPC_CLZ_S:
784 case OPC_ABSNEG_S:
785 case OPC_AND_B:
786 case OPC_OR_B:
787 case OPC_NOT_B:
788 case OPC_XOR_B:
789 case OPC_BFREV_B:
790 case OPC_CLZ_B:
791 case OPC_SHL_B:
792 case OPC_SHR_B:
793 case OPC_ASHR_B:
794 case OPC_MGEN_B:
795 case OPC_GETBIT_B:
796 case OPC_CBITS_B:
797 case OPC_BARY_F:
798 return true;
799
800 default:
801 return false;
802 }
803 }
804
805
806 /* map cat2 instruction to valid abs/neg flags: */
807 static inline unsigned ir3_cat2_absneg(opc_t opc)
808 {
809 switch (opc) {
810 case OPC_ADD_F:
811 case OPC_MIN_F:
812 case OPC_MAX_F:
813 case OPC_MUL_F:
814 case OPC_SIGN_F:
815 case OPC_CMPS_F:
816 case OPC_ABSNEG_F:
817 case OPC_CMPV_F:
818 case OPC_FLOOR_F:
819 case OPC_CEIL_F:
820 case OPC_RNDNE_F:
821 case OPC_RNDAZ_F:
822 case OPC_TRUNC_F:
823 case OPC_BARY_F:
824 return IR3_REG_FABS | IR3_REG_FNEG;
825
826 case OPC_ADD_U:
827 case OPC_ADD_S:
828 case OPC_SUB_U:
829 case OPC_SUB_S:
830 case OPC_CMPS_U:
831 case OPC_CMPS_S:
832 case OPC_MIN_U:
833 case OPC_MIN_S:
834 case OPC_MAX_U:
835 case OPC_MAX_S:
836 case OPC_CMPV_U:
837 case OPC_CMPV_S:
838 case OPC_MUL_U:
839 case OPC_MUL_S:
840 case OPC_MULL_U:
841 case OPC_CLZ_S:
842 return 0;
843
844 case OPC_ABSNEG_S:
845 return IR3_REG_SABS | IR3_REG_SNEG;
846
847 case OPC_AND_B:
848 case OPC_OR_B:
849 case OPC_NOT_B:
850 case OPC_XOR_B:
851 case OPC_BFREV_B:
852 case OPC_CLZ_B:
853 case OPC_SHL_B:
854 case OPC_SHR_B:
855 case OPC_ASHR_B:
856 case OPC_MGEN_B:
857 case OPC_GETBIT_B:
858 case OPC_CBITS_B:
859 return IR3_REG_BNOT;
860
861 default:
862 return 0;
863 }
864 }
865
866 /* map cat3 instructions to valid abs/neg flags: */
867 static inline unsigned ir3_cat3_absneg(opc_t opc)
868 {
869 switch (opc) {
870 case OPC_MAD_F16:
871 case OPC_MAD_F32:
872 case OPC_SEL_F16:
873 case OPC_SEL_F32:
874 return IR3_REG_FNEG;
875
876 case OPC_MAD_U16:
877 case OPC_MADSH_U16:
878 case OPC_MAD_S16:
879 case OPC_MADSH_M16:
880 case OPC_MAD_U24:
881 case OPC_MAD_S24:
882 case OPC_SEL_S16:
883 case OPC_SEL_S32:
884 case OPC_SAD_S16:
885 case OPC_SAD_S32:
886 /* neg *may* work on 3rd src.. */
887
888 case OPC_SEL_B16:
889 case OPC_SEL_B32:
890
891 default:
892 return 0;
893 }
894 }
895
896 #define MASK(n) ((1 << (n)) - 1)
897
898 /* iterator for an instructions's sources (reg), also returns src #: */
899 #define foreach_src_n(__srcreg, __n, __instr) \
900 if ((__instr)->regs_count) \
901 for (unsigned __cnt = (__instr)->regs_count - 1, __n = 0; __n < __cnt; __n++) \
902 if ((__srcreg = (__instr)->regs[__n + 1]))
903
904 /* iterator for an instructions's sources (reg): */
905 #define foreach_src(__srcreg, __instr) \
906 foreach_src_n(__srcreg, __i, __instr)
907
908 static inline unsigned __ssa_src_cnt(struct ir3_instruction *instr)
909 {
910 if (instr->address)
911 return instr->regs_count + 1;
912 return instr->regs_count;
913 }
914
915 static inline struct ir3_instruction * __ssa_src_n(struct ir3_instruction *instr, unsigned n)
916 {
917 if (n == (instr->regs_count + 0))
918 return instr->address;
919 return ssa(instr->regs[n]);
920 }
921
922 #define __src_cnt(__instr) ((__instr)->address ? (__instr)->regs_count : (__instr)->regs_count - 1)
923
924 /* iterator for an instruction's SSA sources (instr), also returns src #: */
925 #define foreach_ssa_src_n(__srcinst, __n, __instr) \
926 if ((__instr)->regs_count) \
927 for (unsigned __cnt = __ssa_src_cnt(__instr), __n = 0; __n < __cnt; __n++) \
928 if ((__srcinst = __ssa_src_n(__instr, __n)))
929
930 /* iterator for an instruction's SSA sources (instr): */
931 #define foreach_ssa_src(__srcinst, __instr) \
932 foreach_ssa_src_n(__srcinst, __i, __instr)
933
934
935 /* dump: */
936 void ir3_print(struct ir3 *ir);
937 void ir3_print_instr(struct ir3_instruction *instr);
938
939 /* depth calculation: */
940 int ir3_delayslots(struct ir3_instruction *assigner,
941 struct ir3_instruction *consumer, unsigned n);
942 void ir3_insert_by_depth(struct ir3_instruction *instr, struct list_head *list);
943 void ir3_depth(struct ir3 *ir);
944
945 /* copy-propagate: */
946 struct ir3_shader_variant;
947 void ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so);
948
949 /* group neighbors and insert mov's to resolve conflicts: */
950 void ir3_group(struct ir3 *ir);
951
952 /* scheduling: */
953 int ir3_sched(struct ir3 *ir);
954
955 /* register assignment: */
956 struct ir3_ra_reg_set * ir3_ra_alloc_reg_set(void *memctx);
957 int ir3_ra(struct ir3 *ir3, enum shader_t type,
958 bool frag_coord, bool frag_face);
959
960 /* legalize: */
961 void ir3_legalize(struct ir3 *ir, bool *has_samp, bool *has_ssbo, int *max_bary);
962
963 /* ************************************************************************* */
964 /* instruction helpers */
965
966 static inline struct ir3_instruction *
967 ir3_MOV(struct ir3_block *block, struct ir3_instruction *src, type_t type)
968 {
969 struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOV);
970 ir3_reg_create(instr, 0, 0); /* dst */
971 if (src->regs[0]->flags & IR3_REG_ARRAY) {
972 struct ir3_register *src_reg =
973 ir3_reg_create(instr, 0, IR3_REG_ARRAY);
974 src_reg->array = src->regs[0]->array;
975 src_reg->instr = src;
976 } else {
977 ir3_reg_create(instr, 0, IR3_REG_SSA)->instr = src;
978 }
979 debug_assert(!(src->regs[0]->flags & IR3_REG_RELATIV));
980 instr->cat1.src_type = type;
981 instr->cat1.dst_type = type;
982 return instr;
983 }
984
985 static inline struct ir3_instruction *
986 ir3_COV(struct ir3_block *block, struct ir3_instruction *src,
987 type_t src_type, type_t dst_type)
988 {
989 struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOV);
990 ir3_reg_create(instr, 0, 0); /* dst */
991 ir3_reg_create(instr, 0, IR3_REG_SSA)->instr = src;
992 instr->cat1.src_type = src_type;
993 instr->cat1.dst_type = dst_type;
994 debug_assert(!(src->regs[0]->flags & IR3_REG_ARRAY));
995 return instr;
996 }
997
998 static inline struct ir3_instruction *
999 ir3_NOP(struct ir3_block *block)
1000 {
1001 return ir3_instr_create(block, OPC_NOP);
1002 }
1003
1004 #define INSTR0(name) \
1005 static inline struct ir3_instruction * \
1006 ir3_##name(struct ir3_block *block) \
1007 { \
1008 struct ir3_instruction *instr = \
1009 ir3_instr_create(block, OPC_##name); \
1010 return instr; \
1011 }
1012
1013 #define INSTR1(name) \
1014 static inline struct ir3_instruction * \
1015 ir3_##name(struct ir3_block *block, \
1016 struct ir3_instruction *a, unsigned aflags) \
1017 { \
1018 struct ir3_instruction *instr = \
1019 ir3_instr_create(block, OPC_##name); \
1020 ir3_reg_create(instr, 0, 0); /* dst */ \
1021 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
1022 return instr; \
1023 }
1024
1025 #define INSTR2(name) \
1026 static inline struct ir3_instruction * \
1027 ir3_##name(struct ir3_block *block, \
1028 struct ir3_instruction *a, unsigned aflags, \
1029 struct ir3_instruction *b, unsigned bflags) \
1030 { \
1031 struct ir3_instruction *instr = \
1032 ir3_instr_create(block, OPC_##name); \
1033 ir3_reg_create(instr, 0, 0); /* dst */ \
1034 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
1035 ir3_reg_create(instr, 0, IR3_REG_SSA | bflags)->instr = b; \
1036 return instr; \
1037 }
1038
1039 #define INSTR3(name) \
1040 static inline struct ir3_instruction * \
1041 ir3_##name(struct ir3_block *block, \
1042 struct ir3_instruction *a, unsigned aflags, \
1043 struct ir3_instruction *b, unsigned bflags, \
1044 struct ir3_instruction *c, unsigned cflags) \
1045 { \
1046 struct ir3_instruction *instr = \
1047 ir3_instr_create(block, OPC_##name); \
1048 ir3_reg_create(instr, 0, 0); /* dst */ \
1049 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
1050 ir3_reg_create(instr, 0, IR3_REG_SSA | bflags)->instr = b; \
1051 ir3_reg_create(instr, 0, IR3_REG_SSA | cflags)->instr = c; \
1052 return instr; \
1053 }
1054
1055 #define INSTR4(name) \
1056 static inline struct ir3_instruction * \
1057 ir3_##name(struct ir3_block *block, \
1058 struct ir3_instruction *a, unsigned aflags, \
1059 struct ir3_instruction *b, unsigned bflags, \
1060 struct ir3_instruction *c, unsigned cflags, \
1061 struct ir3_instruction *d, unsigned dflags) \
1062 { \
1063 struct ir3_instruction *instr = \
1064 ir3_instr_create2(block, OPC_##name, 5); \
1065 ir3_reg_create(instr, 0, 0); /* dst */ \
1066 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
1067 ir3_reg_create(instr, 0, IR3_REG_SSA | bflags)->instr = b; \
1068 ir3_reg_create(instr, 0, IR3_REG_SSA | cflags)->instr = c; \
1069 ir3_reg_create(instr, 0, IR3_REG_SSA | dflags)->instr = d; \
1070 return instr; \
1071 }
1072
1073 #define INSTR4F(f, name) \
1074 static inline struct ir3_instruction * \
1075 ir3_##name##_##f(struct ir3_block *block, \
1076 struct ir3_instruction *a, unsigned aflags, \
1077 struct ir3_instruction *b, unsigned bflags, \
1078 struct ir3_instruction *c, unsigned cflags, \
1079 struct ir3_instruction *d, unsigned dflags) \
1080 { \
1081 struct ir3_instruction *instr = \
1082 ir3_instr_create2(block, OPC_##name, 5); \
1083 ir3_reg_create(instr, 0, 0); /* dst */ \
1084 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
1085 ir3_reg_create(instr, 0, IR3_REG_SSA | bflags)->instr = b; \
1086 ir3_reg_create(instr, 0, IR3_REG_SSA | cflags)->instr = c; \
1087 ir3_reg_create(instr, 0, IR3_REG_SSA | dflags)->instr = d; \
1088 instr->flags |= IR3_INSTR_##f; \
1089 return instr; \
1090 }
1091
1092 /* cat0 instructions: */
1093 INSTR0(BR)
1094 INSTR0(JUMP)
1095 INSTR1(KILL)
1096 INSTR0(END)
1097
1098 /* cat2 instructions, most 2 src but some 1 src: */
1099 INSTR2(ADD_F)
1100 INSTR2(MIN_F)
1101 INSTR2(MAX_F)
1102 INSTR2(MUL_F)
1103 INSTR1(SIGN_F)
1104 INSTR2(CMPS_F)
1105 INSTR1(ABSNEG_F)
1106 INSTR2(CMPV_F)
1107 INSTR1(FLOOR_F)
1108 INSTR1(CEIL_F)
1109 INSTR1(RNDNE_F)
1110 INSTR1(RNDAZ_F)
1111 INSTR1(TRUNC_F)
1112 INSTR2(ADD_U)
1113 INSTR2(ADD_S)
1114 INSTR2(SUB_U)
1115 INSTR2(SUB_S)
1116 INSTR2(CMPS_U)
1117 INSTR2(CMPS_S)
1118 INSTR2(MIN_U)
1119 INSTR2(MIN_S)
1120 INSTR2(MAX_U)
1121 INSTR2(MAX_S)
1122 INSTR1(ABSNEG_S)
1123 INSTR2(AND_B)
1124 INSTR2(OR_B)
1125 INSTR1(NOT_B)
1126 INSTR2(XOR_B)
1127 INSTR2(CMPV_U)
1128 INSTR2(CMPV_S)
1129 INSTR2(MUL_U)
1130 INSTR2(MUL_S)
1131 INSTR2(MULL_U)
1132 INSTR1(BFREV_B)
1133 INSTR1(CLZ_S)
1134 INSTR1(CLZ_B)
1135 INSTR2(SHL_B)
1136 INSTR2(SHR_B)
1137 INSTR2(ASHR_B)
1138 INSTR2(BARY_F)
1139 INSTR2(MGEN_B)
1140 INSTR2(GETBIT_B)
1141 INSTR1(SETRM)
1142 INSTR1(CBITS_B)
1143 INSTR2(SHB)
1144 INSTR2(MSAD)
1145
1146 /* cat3 instructions: */
1147 INSTR3(MAD_U16)
1148 INSTR3(MADSH_U16)
1149 INSTR3(MAD_S16)
1150 INSTR3(MADSH_M16)
1151 INSTR3(MAD_U24)
1152 INSTR3(MAD_S24)
1153 INSTR3(MAD_F16)
1154 INSTR3(MAD_F32)
1155 INSTR3(SEL_B16)
1156 INSTR3(SEL_B32)
1157 INSTR3(SEL_S16)
1158 INSTR3(SEL_S32)
1159 INSTR3(SEL_F16)
1160 INSTR3(SEL_F32)
1161 INSTR3(SAD_S16)
1162 INSTR3(SAD_S32)
1163
1164 /* cat4 instructions: */
1165 INSTR1(RCP)
1166 INSTR1(RSQ)
1167 INSTR1(LOG2)
1168 INSTR1(EXP2)
1169 INSTR1(SIN)
1170 INSTR1(COS)
1171 INSTR1(SQRT)
1172
1173 /* cat5 instructions: */
1174 INSTR1(DSX)
1175 INSTR1(DSY)
1176
1177 static inline struct ir3_instruction *
1178 ir3_SAM(struct ir3_block *block, opc_t opc, type_t type,
1179 unsigned wrmask, unsigned flags, unsigned samp, unsigned tex,
1180 struct ir3_instruction *src0, struct ir3_instruction *src1)
1181 {
1182 struct ir3_instruction *sam;
1183 struct ir3_register *reg;
1184
1185 sam = ir3_instr_create(block, opc);
1186 sam->flags |= flags;
1187 ir3_reg_create(sam, 0, 0)->wrmask = wrmask;
1188 if (src0) {
1189 reg = ir3_reg_create(sam, 0, IR3_REG_SSA);
1190 reg->wrmask = (1 << (src0->regs_count - 1)) - 1;
1191 reg->instr = src0;
1192 }
1193 if (src1) {
1194 reg = ir3_reg_create(sam, 0, IR3_REG_SSA);
1195 reg->instr = src1;
1196 reg->wrmask = (1 << (src1->regs_count - 1)) - 1;
1197 }
1198 sam->cat5.samp = samp;
1199 sam->cat5.tex = tex;
1200 sam->cat5.type = type;
1201
1202 return sam;
1203 }
1204
1205 /* cat6 instructions: */
1206 INSTR2(LDLV)
1207 INSTR2(LDG)
1208 INSTR2(LDL)
1209 INSTR3(STG)
1210 INSTR3(STL)
1211 INSTR3(LDGB)
1212 INSTR4(STGB)
1213 INSTR4(STIB)
1214 INSTR1(RESINFO)
1215 INSTR1(RESFMT)
1216 INSTR2(ATOMIC_ADD)
1217 INSTR2(ATOMIC_SUB)
1218 INSTR2(ATOMIC_XCHG)
1219 INSTR2(ATOMIC_INC)
1220 INSTR2(ATOMIC_DEC)
1221 INSTR2(ATOMIC_CMPXCHG)
1222 INSTR2(ATOMIC_MIN)
1223 INSTR2(ATOMIC_MAX)
1224 INSTR2(ATOMIC_AND)
1225 INSTR2(ATOMIC_OR)
1226 INSTR2(ATOMIC_XOR)
1227 INSTR4F(G, ATOMIC_ADD)
1228 INSTR4F(G, ATOMIC_SUB)
1229 INSTR4F(G, ATOMIC_XCHG)
1230 INSTR4F(G, ATOMIC_INC)
1231 INSTR4F(G, ATOMIC_DEC)
1232 INSTR4F(G, ATOMIC_CMPXCHG)
1233 INSTR4F(G, ATOMIC_MIN)
1234 INSTR4F(G, ATOMIC_MAX)
1235 INSTR4F(G, ATOMIC_AND)
1236 INSTR4F(G, ATOMIC_OR)
1237 INSTR4F(G, ATOMIC_XOR)
1238
1239 /* cat7 instructions: */
1240 INSTR0(BAR)
1241 INSTR0(FENCE)
1242
1243 /* ************************************************************************* */
1244 /* split this out or find some helper to use.. like main/bitset.h.. */
1245
1246 #include <string.h>
1247
1248 #define MAX_REG 256
1249
1250 typedef uint8_t regmask_t[2 * MAX_REG / 8];
1251
1252 static inline unsigned regmask_idx(struct ir3_register *reg)
1253 {
1254 unsigned num = (reg->flags & IR3_REG_RELATIV) ? reg->array.offset : reg->num;
1255 debug_assert(num < MAX_REG);
1256 if (reg->flags & IR3_REG_HALF)
1257 num += MAX_REG;
1258 return num;
1259 }
1260
1261 static inline void regmask_init(regmask_t *regmask)
1262 {
1263 memset(regmask, 0, sizeof(*regmask));
1264 }
1265
1266 static inline void regmask_set(regmask_t *regmask, struct ir3_register *reg)
1267 {
1268 unsigned idx = regmask_idx(reg);
1269 if (reg->flags & IR3_REG_RELATIV) {
1270 unsigned i;
1271 for (i = 0; i < reg->size; i++, idx++)
1272 (*regmask)[idx / 8] |= 1 << (idx % 8);
1273 } else {
1274 unsigned mask;
1275 for (mask = reg->wrmask; mask; mask >>= 1, idx++)
1276 if (mask & 1)
1277 (*regmask)[idx / 8] |= 1 << (idx % 8);
1278 }
1279 }
1280
1281 static inline void regmask_or(regmask_t *dst, regmask_t *a, regmask_t *b)
1282 {
1283 unsigned i;
1284 for (i = 0; i < ARRAY_SIZE(*dst); i++)
1285 (*dst)[i] = (*a)[i] | (*b)[i];
1286 }
1287
1288 /* set bits in a if not set in b, conceptually:
1289 * a |= (reg & ~b)
1290 */
1291 static inline void regmask_set_if_not(regmask_t *a,
1292 struct ir3_register *reg, regmask_t *b)
1293 {
1294 unsigned idx = regmask_idx(reg);
1295 if (reg->flags & IR3_REG_RELATIV) {
1296 unsigned i;
1297 for (i = 0; i < reg->size; i++, idx++)
1298 if (!((*b)[idx / 8] & (1 << (idx % 8))))
1299 (*a)[idx / 8] |= 1 << (idx % 8);
1300 } else {
1301 unsigned mask;
1302 for (mask = reg->wrmask; mask; mask >>= 1, idx++)
1303 if (mask & 1)
1304 if (!((*b)[idx / 8] & (1 << (idx % 8))))
1305 (*a)[idx / 8] |= 1 << (idx % 8);
1306 }
1307 }
1308
1309 static inline bool regmask_get(regmask_t *regmask,
1310 struct ir3_register *reg)
1311 {
1312 unsigned idx = regmask_idx(reg);
1313 if (reg->flags & IR3_REG_RELATIV) {
1314 unsigned i;
1315 for (i = 0; i < reg->size; i++, idx++)
1316 if ((*regmask)[idx / 8] & (1 << (idx % 8)))
1317 return true;
1318 } else {
1319 unsigned mask;
1320 for (mask = reg->wrmask; mask; mask >>= 1, idx++)
1321 if (mask & 1)
1322 if ((*regmask)[idx / 8] & (1 << (idx % 8)))
1323 return true;
1324 }
1325 return false;
1326 }
1327
1328 /* ************************************************************************* */
1329
1330 #endif /* IR3_H_ */