2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 #include "util/u_debug.h"
31 #include "util/list.h"
33 #include "instr-a3xx.h"
34 #include "disasm.h" /* TODO move 'enum shader_t' somewhere else.. */
36 /* low level intermediate representation of an adreno shader program */
40 struct ir3_instruction
;
46 uint16_t instrs_count
; /* expanded to account for rpt's */
47 /* NOTE: max_reg, etc, does not include registers not touched
48 * by the shader (ie. vertex fetched via VFD_DECODE but not
51 int8_t max_reg
; /* highest GPR # used by shader */
58 IR3_REG_CONST
= 0x001,
59 IR3_REG_IMMED
= 0x002,
61 /* high registers are used for some things in compute shaders,
62 * for example. Seems to be for things that are global to all
63 * threads in a wave, so possibly these are global/shared by
64 * all the threads in the wave?
67 IR3_REG_RELATIV
= 0x010,
69 /* Most instructions, it seems, can do float abs/neg but not
70 * integer. The CP pass needs to know what is intended (int or
71 * float) in order to do the right thing. For this reason the
72 * abs/neg flags are split out into float and int variants. In
73 * addition, .b (bitwise) operations, the negate is actually a
74 * bitwise not, so split that out into a new flag to make it
83 IR3_REG_POS_INF
= 0x1000,
84 /* (ei) flag, end-input? Set on last bary, presumably to signal
85 * that the shader needs no more input:
88 /* meta-flags, for intermediate stages of IR, ie.
89 * before register assignment is done:
91 IR3_REG_SSA
= 0x4000, /* 'instr' is ptr to assigning instr */
92 IR3_REG_ARRAY
= 0x8000,
93 IR3_REG_PHI_SRC
= 0x10000, /* phi src, regs[0]->instr points to phi */
98 * the component is in the low two bits of the reg #, so
99 * rN.x becomes: (N << 2) | x
113 /* For IR3_REG_SSA, src registers contain ptr back to assigning
116 * For IR3_REG_ARRAY, the pointer is back to the last dependent
117 * array access (although the net effect is the same, it points
118 * back to a previous instruction that we depend on).
120 struct ir3_instruction
*instr
;
123 /* used for cat5 instructions, but also for internal/IR level
124 * tracking of what registers are read/written by an instruction.
125 * wrmask may be a bad name since it is used to represent both
126 * src and dst that touch multiple adjacent registers.
129 /* for relative addressing, 32bits for array size is too small,
130 * but otoh we don't need to deal with disjoint sets, so instead
131 * use a simple size field (number of scalar components).
137 struct ir3_instruction
{
138 struct ir3_block
*block
;
141 /* (sy) flag is set on first instruction, and after sample
142 * instructions (probably just on RAW hazard).
144 IR3_INSTR_SY
= 0x001,
145 /* (ss) flag is set on first instruction, and first instruction
146 * to depend on the result of "long" instructions (RAW hazard):
148 * rcp, rsq, log2, exp2, sin, cos, sqrt
150 * It seems to synchronize until all in-flight instructions are
151 * completed, for example:
154 * add.f hr2.z, (neg)hr2.z, hc0.y
155 * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
158 * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
160 * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
161 * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
162 * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
164 * The last mul.f does not have (ss) set, presumably because the
165 * (ss) on the previous instruction does the job.
167 * The blob driver also seems to set it on WAR hazards, although
168 * not really clear if this is needed or just blob compiler being
169 * sloppy. So far I haven't found a case where removing the (ss)
170 * causes problems for WAR hazard, but I could just be getting
174 * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
177 IR3_INSTR_SS
= 0x002,
178 /* (jp) flag is set on jump targets:
180 IR3_INSTR_JP
= 0x004,
181 IR3_INSTR_UL
= 0x008,
182 IR3_INSTR_3D
= 0x010,
187 IR3_INSTR_S2EN
= 0x200,
189 /* meta-flags, for intermediate stages of IR, ie.
190 * before register assignment is done:
192 IR3_INSTR_MARK
= 0x1000,
193 IR3_INSTR_UNUSED
= 0x2000,
200 struct ir3_register
**regs
;
206 struct ir3_block
*target
;
209 type_t src_type
, dst_type
;
229 int iim_val
; /* for ldgb/stgb, # of components */
231 /* for meta-instructions, just used to hold extra data
232 * before instruction scheduling, etc
235 int off
; /* component/offset */
238 /* used to temporarily hold reference to nir_phi_instr
239 * until we resolve the phi srcs
244 struct ir3_block
*block
;
248 /* transient values used during various algorithms: */
250 /* The instruction depth is the max dependency distance to output.
252 * You can also think of it as the "cost", if we did any sort of
253 * optimization for register footprint. Ie. a value that is just
254 * result of moving a const to a reg would have a low cost, so to
255 * it could make sense to duplicate the instruction at various
256 * points where the result is needed to reduce register footprint.
259 /* When we get to the RA stage, we no longer need depth, but
260 * we do need instruction's position/name:
268 /* used for per-pass extra instruction data.
272 /* Used during CP and RA stages. For fanin and shader inputs/
273 * outputs where we need a sequence of consecutive registers,
274 * keep track of each src instructions left (ie 'n-1') and right
275 * (ie 'n+1') neighbor. The front-end must insert enough mov's
276 * to ensure that each instruction has at most one left and at
277 * most one right neighbor. During the copy-propagation pass,
278 * we only remove mov's when we can preserve this constraint.
279 * And during the RA stage, we use the neighbor information to
280 * allocate a block of registers in one shot.
282 * TODO: maybe just add something like:
283 * struct ir3_instruction_ref {
284 * struct ir3_instruction *instr;
288 * Or can we get away without the refcnt stuff? It seems like
289 * it should be overkill.. the problem is if, potentially after
290 * already eliminating some mov's, if you have a single mov that
291 * needs to be grouped with it's neighbors in two different
292 * places (ex. shader output and a fanin).
295 struct ir3_instruction
*left
, *right
;
296 uint16_t left_cnt
, right_cnt
;
299 /* an instruction can reference at most one address register amongst
300 * it's src/dst registers. Beyond that, you need to insert mov's.
302 * NOTE: do not write this directly, use ir3_instr_set_address()
304 struct ir3_instruction
*address
;
306 /* Entry in ir3_block's instruction list: */
307 struct list_head node
;
314 static inline struct ir3_instruction
*
315 ir3_neighbor_first(struct ir3_instruction
*instr
)
318 while (instr
->cp
.left
) {
319 instr
= instr
->cp
.left
;
320 if (++cnt
> 0xffff) {
328 static inline int ir3_neighbor_count(struct ir3_instruction
*instr
)
332 debug_assert(!instr
->cp
.left
);
334 while (instr
->cp
.right
) {
336 instr
= instr
->cp
.right
;
347 struct ir3_compiler
*compiler
;
349 unsigned ninputs
, noutputs
;
350 struct ir3_instruction
**inputs
;
351 struct ir3_instruction
**outputs
;
353 /* Track bary.f (and ldlv) instructions.. this is needed in
354 * scheduling to ensure that all varying fetches happen before
355 * any potential kill instructions. The hw gets grumpy if all
356 * threads in a group are killed before the last bary.f gets
357 * a chance to signal end of input (ei).
359 unsigned baryfs_count
, baryfs_sz
;
360 struct ir3_instruction
**baryfs
;
362 /* Track all indirect instructions (read and write). To avoid
363 * deadlock scenario where an address register gets scheduled,
364 * but other dependent src instructions cannot be scheduled due
365 * to dependency on a *different* address register value, the
366 * scheduler needs to ensure that all dependencies other than
367 * the instruction other than the address register are scheduled
368 * before the one that writes the address register. Having a
369 * convenient list of instructions that reference some address
370 * register simplifies this.
372 unsigned indirects_count
, indirects_sz
;
373 struct ir3_instruction
**indirects
;
374 /* and same for instructions that consume predicate register: */
375 unsigned predicates_count
, predicates_sz
;
376 struct ir3_instruction
**predicates
;
378 /* Track texture sample instructions which need texture state
379 * patched in (for astc-srgb workaround):
381 unsigned astc_srgb_count
, astc_srgb_sz
;
382 struct ir3_instruction
**astc_srgb
;
384 /* List of blocks: */
385 struct list_head block_list
;
387 /* List of ir3_array's: */
388 struct list_head array_list
;
391 typedef struct nir_variable nir_variable
;
394 struct list_head node
;
400 /* We track the last write and last access (read or write) to
401 * setup dependencies on instructions that read or write the
402 * array. Reads can be re-ordered wrt. other reads, but should
403 * not be re-ordered wrt. to writes. Writes cannot be reordered
404 * wrt. any other access to the array.
406 * So array reads depend on last write, and array writes depend
407 * on the last access.
409 struct ir3_instruction
*last_write
, *last_access
;
411 /* extra stuff used in RA pass: */
412 unsigned base
; /* base vreg name */
413 unsigned reg
; /* base physical reg */
414 uint16_t start_ip
, end_ip
;
417 struct ir3_array
* ir3_lookup_array(struct ir3
*ir
, unsigned id
);
419 typedef struct nir_block nir_block
;
422 struct list_head node
;
427 struct list_head instr_list
; /* list of ir3_instruction */
429 /* each block has either one or two successors.. in case of
430 * two successors, 'condition' decides which one to follow.
431 * A block preceding an if/else has two successors.
433 struct ir3_instruction
*condition
;
434 struct ir3_block
*successors
[2];
436 uint16_t start_ip
, end_ip
;
438 /* Track instructions which do not write a register but other-
439 * wise must not be discarded (such as kill, stg, etc)
441 unsigned keeps_count
, keeps_sz
;
442 struct ir3_instruction
**keeps
;
444 /* used for per-pass extra block data. Mainly used right
445 * now in RA step to track livein/liveout.
454 static inline uint32_t
455 block_id(struct ir3_block
*block
)
458 return block
->serialno
;
460 return (uint32_t)(unsigned long)block
;
464 struct ir3
* ir3_create(struct ir3_compiler
*compiler
,
465 unsigned nin
, unsigned nout
);
466 void ir3_destroy(struct ir3
*shader
);
467 void * ir3_assemble(struct ir3
*shader
,
468 struct ir3_info
*info
, uint32_t gpu_id
);
469 void * ir3_alloc(struct ir3
*shader
, int sz
);
471 struct ir3_block
* ir3_block_create(struct ir3
*shader
);
473 struct ir3_instruction
* ir3_instr_create(struct ir3_block
*block
, opc_t opc
);
474 struct ir3_instruction
* ir3_instr_create2(struct ir3_block
*block
,
475 opc_t opc
, int nreg
);
476 struct ir3_instruction
* ir3_instr_clone(struct ir3_instruction
*instr
);
477 const char *ir3_instr_name(struct ir3_instruction
*instr
);
479 struct ir3_register
* ir3_reg_create(struct ir3_instruction
*instr
,
481 struct ir3_register
* ir3_reg_clone(struct ir3
*shader
,
482 struct ir3_register
*reg
);
484 void ir3_instr_set_address(struct ir3_instruction
*instr
,
485 struct ir3_instruction
*addr
);
487 static inline bool ir3_instr_check_mark(struct ir3_instruction
*instr
)
489 if (instr
->flags
& IR3_INSTR_MARK
)
490 return true; /* already visited */
491 instr
->flags
|= IR3_INSTR_MARK
;
495 void ir3_block_clear_mark(struct ir3_block
*block
);
496 void ir3_clear_mark(struct ir3
*shader
);
498 unsigned ir3_count_instructions(struct ir3
*ir
);
500 static inline int ir3_instr_regno(struct ir3_instruction
*instr
,
501 struct ir3_register
*reg
)
504 for (i
= 0; i
< instr
->regs_count
; i
++)
505 if (reg
== instr
->regs
[i
])
511 #define MAX_ARRAYS 16
519 static inline uint32_t regid(int num
, int comp
)
521 return (num
<< 2) | (comp
& 0x3);
524 static inline uint32_t reg_num(struct ir3_register
*reg
)
526 return reg
->num
>> 2;
529 static inline uint32_t reg_comp(struct ir3_register
*reg
)
531 return reg
->num
& 0x3;
534 static inline bool is_flow(struct ir3_instruction
*instr
)
536 return (opc_cat(instr
->opc
) == 0);
539 static inline bool is_kill(struct ir3_instruction
*instr
)
541 return instr
->opc
== OPC_KILL
;
544 static inline bool is_nop(struct ir3_instruction
*instr
)
546 return instr
->opc
== OPC_NOP
;
549 /* Is it a non-transformative (ie. not type changing) mov? This can
550 * also include absneg.s/absneg.f, which for the most part can be
551 * treated as a mov (single src argument).
553 static inline bool is_same_type_mov(struct ir3_instruction
*instr
)
555 struct ir3_register
*dst
= instr
->regs
[0];
557 /* mov's that write to a0.x or p0.x are special: */
558 if (dst
->num
== regid(REG_P0
, 0))
560 if (dst
->num
== regid(REG_A0
, 0))
563 if (dst
->flags
& (IR3_REG_RELATIV
| IR3_REG_ARRAY
))
566 switch (instr
->opc
) {
568 return instr
->cat1
.src_type
== instr
->cat1
.dst_type
;
577 static inline bool is_alu(struct ir3_instruction
*instr
)
579 return (1 <= opc_cat(instr
->opc
)) && (opc_cat(instr
->opc
) <= 3);
582 static inline bool is_sfu(struct ir3_instruction
*instr
)
584 return (opc_cat(instr
->opc
) == 4);
587 static inline bool is_tex(struct ir3_instruction
*instr
)
589 return (opc_cat(instr
->opc
) == 5);
592 static inline bool is_mem(struct ir3_instruction
*instr
)
594 return (opc_cat(instr
->opc
) == 6);
598 is_store(struct ir3_instruction
*instr
)
600 /* these instructions, the "destination" register is
601 * actually a source, the address to store to.
603 switch (instr
->opc
) {
617 static inline bool is_load(struct ir3_instruction
*instr
)
619 switch (instr
->opc
) {
628 /* probably some others too.. */
635 static inline bool is_input(struct ir3_instruction
*instr
)
637 /* in some cases, ldlv is used to fetch varying without
638 * interpolation.. fortunately inloc is the first src
639 * register in either case
641 switch (instr
->opc
) {
650 static inline bool is_bool(struct ir3_instruction
*instr
)
652 switch (instr
->opc
) {
662 static inline bool is_meta(struct ir3_instruction
*instr
)
664 /* TODO how should we count PHI (and maybe fan-in/out) which
665 * might actually contribute some instructions to the final
668 return (opc_cat(instr
->opc
) == -1);
671 static inline bool writes_addr(struct ir3_instruction
*instr
)
673 if (instr
->regs_count
> 0) {
674 struct ir3_register
*dst
= instr
->regs
[0];
675 return reg_num(dst
) == REG_A0
;
680 static inline bool writes_pred(struct ir3_instruction
*instr
)
682 if (instr
->regs_count
> 0) {
683 struct ir3_register
*dst
= instr
->regs
[0];
684 return reg_num(dst
) == REG_P0
;
689 /* returns defining instruction for reg */
690 /* TODO better name */
691 static inline struct ir3_instruction
*ssa(struct ir3_register
*reg
)
693 if (reg
->flags
& (IR3_REG_SSA
| IR3_REG_ARRAY
)) {
694 debug_assert(!(reg
->instr
&& (reg
->instr
->flags
& IR3_INSTR_UNUSED
)));
700 static inline bool conflicts(struct ir3_instruction
*a
,
701 struct ir3_instruction
*b
)
703 return (a
&& b
) && (a
!= b
);
706 static inline bool reg_gpr(struct ir3_register
*r
)
708 if (r
->flags
& (IR3_REG_CONST
| IR3_REG_IMMED
))
710 if ((reg_num(r
) == REG_A0
) || (reg_num(r
) == REG_P0
))
715 static inline type_t
half_type(type_t type
)
718 case TYPE_F32
: return TYPE_F16
;
719 case TYPE_U32
: return TYPE_U16
;
720 case TYPE_S32
: return TYPE_S16
;
731 /* some cat2 instructions (ie. those which are not float) can embed an
734 static inline bool ir3_cat2_int(opc_t opc
)
775 /* map cat2 instruction to valid abs/neg flags: */
776 static inline unsigned ir3_cat2_absneg(opc_t opc
)
793 return IR3_REG_FABS
| IR3_REG_FNEG
;
814 return IR3_REG_SABS
| IR3_REG_SNEG
;
835 /* map cat3 instructions to valid abs/neg flags: */
836 static inline unsigned ir3_cat3_absneg(opc_t opc
)
855 /* neg *may* work on 3rd src.. */
865 #define array_insert(ctx, arr, val) do { \
866 if (arr ## _count == arr ## _sz) { \
867 arr ## _sz = MAX2(2 * arr ## _sz, 16); \
868 arr = reralloc_size(ctx, arr, arr ## _sz * sizeof(arr[0])); \
870 arr[arr ##_count++] = val; \
873 /* iterator for an instructions's sources (reg), also returns src #: */
874 #define foreach_src_n(__srcreg, __n, __instr) \
875 if ((__instr)->regs_count) \
876 for (unsigned __cnt = (__instr)->regs_count - 1, __n = 0; __n < __cnt; __n++) \
877 if ((__srcreg = (__instr)->regs[__n + 1]))
879 /* iterator for an instructions's sources (reg): */
880 #define foreach_src(__srcreg, __instr) \
881 foreach_src_n(__srcreg, __i, __instr)
883 static inline unsigned __ssa_src_cnt(struct ir3_instruction
*instr
)
886 return instr
->regs_count
+ 1;
887 return instr
->regs_count
;
890 static inline struct ir3_instruction
* __ssa_src_n(struct ir3_instruction
*instr
, unsigned n
)
892 if (n
== (instr
->regs_count
+ 0))
893 return instr
->address
;
894 return ssa(instr
->regs
[n
]);
897 #define __src_cnt(__instr) ((__instr)->address ? (__instr)->regs_count : (__instr)->regs_count - 1)
899 /* iterator for an instruction's SSA sources (instr), also returns src #: */
900 #define foreach_ssa_src_n(__srcinst, __n, __instr) \
901 if ((__instr)->regs_count) \
902 for (unsigned __cnt = __ssa_src_cnt(__instr), __n = 0; __n < __cnt; __n++) \
903 if ((__srcinst = __ssa_src_n(__instr, __n)))
905 /* iterator for an instruction's SSA sources (instr): */
906 #define foreach_ssa_src(__srcinst, __instr) \
907 foreach_ssa_src_n(__srcinst, __i, __instr)
911 void ir3_print(struct ir3
*ir
);
912 void ir3_print_instr(struct ir3_instruction
*instr
);
914 /* depth calculation: */
915 int ir3_delayslots(struct ir3_instruction
*assigner
,
916 struct ir3_instruction
*consumer
, unsigned n
);
917 void ir3_insert_by_depth(struct ir3_instruction
*instr
, struct list_head
*list
);
918 void ir3_depth(struct ir3
*ir
);
920 /* copy-propagate: */
921 struct ir3_shader_variant
;
922 void ir3_cp(struct ir3
*ir
, struct ir3_shader_variant
*so
);
924 /* group neighbors and insert mov's to resolve conflicts: */
925 void ir3_group(struct ir3
*ir
);
928 int ir3_sched(struct ir3
*ir
);
930 /* register assignment: */
931 struct ir3_ra_reg_set
* ir3_ra_alloc_reg_set(void *memctx
);
932 int ir3_ra(struct ir3
*ir3
, enum shader_t type
,
933 bool frag_coord
, bool frag_face
);
936 void ir3_legalize(struct ir3
*ir
, bool *has_samp
, bool *has_ssbo
, int *max_bary
);
938 /* ************************************************************************* */
939 /* instruction helpers */
941 static inline struct ir3_instruction
*
942 ir3_MOV(struct ir3_block
*block
, struct ir3_instruction
*src
, type_t type
)
944 struct ir3_instruction
*instr
= ir3_instr_create(block
, OPC_MOV
);
945 ir3_reg_create(instr
, 0, 0); /* dst */
946 if (src
->regs
[0]->flags
& IR3_REG_ARRAY
) {
947 struct ir3_register
*src_reg
=
948 ir3_reg_create(instr
, 0, IR3_REG_ARRAY
);
949 src_reg
->array
= src
->regs
[0]->array
;
950 src_reg
->instr
= src
;
952 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
954 debug_assert(!(src
->regs
[0]->flags
& IR3_REG_RELATIV
));
955 instr
->cat1
.src_type
= type
;
956 instr
->cat1
.dst_type
= type
;
960 static inline struct ir3_instruction
*
961 ir3_COV(struct ir3_block
*block
, struct ir3_instruction
*src
,
962 type_t src_type
, type_t dst_type
)
964 struct ir3_instruction
*instr
= ir3_instr_create(block
, OPC_MOV
);
965 ir3_reg_create(instr
, 0, 0); /* dst */
966 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
967 instr
->cat1
.src_type
= src_type
;
968 instr
->cat1
.dst_type
= dst_type
;
969 debug_assert(!(src
->regs
[0]->flags
& IR3_REG_ARRAY
));
973 static inline struct ir3_instruction
*
974 ir3_NOP(struct ir3_block
*block
)
976 return ir3_instr_create(block
, OPC_NOP
);
979 #define INSTR0(name) \
980 static inline struct ir3_instruction * \
981 ir3_##name(struct ir3_block *block) \
983 struct ir3_instruction *instr = \
984 ir3_instr_create(block, OPC_##name); \
988 #define INSTR1(name) \
989 static inline struct ir3_instruction * \
990 ir3_##name(struct ir3_block *block, \
991 struct ir3_instruction *a, unsigned aflags) \
993 struct ir3_instruction *instr = \
994 ir3_instr_create(block, OPC_##name); \
995 ir3_reg_create(instr, 0, 0); /* dst */ \
996 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
1000 #define INSTR2(name) \
1001 static inline struct ir3_instruction * \
1002 ir3_##name(struct ir3_block *block, \
1003 struct ir3_instruction *a, unsigned aflags, \
1004 struct ir3_instruction *b, unsigned bflags) \
1006 struct ir3_instruction *instr = \
1007 ir3_instr_create(block, OPC_##name); \
1008 ir3_reg_create(instr, 0, 0); /* dst */ \
1009 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
1010 ir3_reg_create(instr, 0, IR3_REG_SSA | bflags)->instr = b; \
1014 #define INSTR3(name) \
1015 static inline struct ir3_instruction * \
1016 ir3_##name(struct ir3_block *block, \
1017 struct ir3_instruction *a, unsigned aflags, \
1018 struct ir3_instruction *b, unsigned bflags, \
1019 struct ir3_instruction *c, unsigned cflags) \
1021 struct ir3_instruction *instr = \
1022 ir3_instr_create(block, OPC_##name); \
1023 ir3_reg_create(instr, 0, 0); /* dst */ \
1024 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
1025 ir3_reg_create(instr, 0, IR3_REG_SSA | bflags)->instr = b; \
1026 ir3_reg_create(instr, 0, IR3_REG_SSA | cflags)->instr = c; \
1030 #define INSTR4(name) \
1031 static inline struct ir3_instruction * \
1032 ir3_##name(struct ir3_block *block, \
1033 struct ir3_instruction *a, unsigned aflags, \
1034 struct ir3_instruction *b, unsigned bflags, \
1035 struct ir3_instruction *c, unsigned cflags, \
1036 struct ir3_instruction *d, unsigned dflags) \
1038 struct ir3_instruction *instr = \
1039 ir3_instr_create2(block, OPC_##name, 5); \
1040 ir3_reg_create(instr, 0, 0); /* dst */ \
1041 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
1042 ir3_reg_create(instr, 0, IR3_REG_SSA | bflags)->instr = b; \
1043 ir3_reg_create(instr, 0, IR3_REG_SSA | cflags)->instr = c; \
1044 ir3_reg_create(instr, 0, IR3_REG_SSA | dflags)->instr = d; \
1048 /* cat0 instructions: */
1054 /* cat2 instructions, most 2 src but some 1 src: */
1102 /* cat3 instructions: */
1120 /* cat4 instructions: */
1129 /* cat5 instructions: */
1133 static inline struct ir3_instruction
*
1134 ir3_SAM(struct ir3_block
*block
, opc_t opc
, type_t type
,
1135 unsigned wrmask
, unsigned flags
, unsigned samp
, unsigned tex
,
1136 struct ir3_instruction
*src0
, struct ir3_instruction
*src1
)
1138 struct ir3_instruction
*sam
;
1139 struct ir3_register
*reg
;
1141 sam
= ir3_instr_create(block
, opc
);
1142 sam
->flags
|= flags
;
1143 ir3_reg_create(sam
, 0, 0)->wrmask
= wrmask
;
1145 reg
= ir3_reg_create(sam
, 0, IR3_REG_SSA
);
1146 reg
->wrmask
= (1 << (src0
->regs_count
- 1)) - 1;
1150 reg
= ir3_reg_create(sam
, 0, IR3_REG_SSA
);
1152 reg
->wrmask
= (1 << (src1
->regs_count
- 1)) - 1;
1154 sam
->cat5
.samp
= samp
;
1155 sam
->cat5
.tex
= tex
;
1156 sam
->cat5
.type
= type
;
1161 /* cat6 instructions: */
1169 INSTR4(ATOMIC_XCHG
);
1172 INSTR4(ATOMIC_CMPXCHG
);
1179 /* ************************************************************************* */
1180 /* split this out or find some helper to use.. like main/bitset.h.. */
1186 typedef uint8_t regmask_t
[2 * MAX_REG
/ 8];
1188 static inline unsigned regmask_idx(struct ir3_register
*reg
)
1190 unsigned num
= (reg
->flags
& IR3_REG_RELATIV
) ? reg
->array
.offset
: reg
->num
;
1191 debug_assert(num
< MAX_REG
);
1192 if (reg
->flags
& IR3_REG_HALF
)
1197 static inline void regmask_init(regmask_t
*regmask
)
1199 memset(regmask
, 0, sizeof(*regmask
));
1202 static inline void regmask_set(regmask_t
*regmask
, struct ir3_register
*reg
)
1204 unsigned idx
= regmask_idx(reg
);
1205 if (reg
->flags
& IR3_REG_RELATIV
) {
1207 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1208 (*regmask
)[idx
/ 8] |= 1 << (idx
% 8);
1211 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1213 (*regmask
)[idx
/ 8] |= 1 << (idx
% 8);
1217 static inline void regmask_or(regmask_t
*dst
, regmask_t
*a
, regmask_t
*b
)
1220 for (i
= 0; i
< ARRAY_SIZE(*dst
); i
++)
1221 (*dst
)[i
] = (*a
)[i
] | (*b
)[i
];
1224 /* set bits in a if not set in b, conceptually:
1227 static inline void regmask_set_if_not(regmask_t
*a
,
1228 struct ir3_register
*reg
, regmask_t
*b
)
1230 unsigned idx
= regmask_idx(reg
);
1231 if (reg
->flags
& IR3_REG_RELATIV
) {
1233 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1234 if (!((*b
)[idx
/ 8] & (1 << (idx
% 8))))
1235 (*a
)[idx
/ 8] |= 1 << (idx
% 8);
1238 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1240 if (!((*b
)[idx
/ 8] & (1 << (idx
% 8))))
1241 (*a
)[idx
/ 8] |= 1 << (idx
% 8);
1245 static inline bool regmask_get(regmask_t
*regmask
,
1246 struct ir3_register
*reg
)
1248 unsigned idx
= regmask_idx(reg
);
1249 if (reg
->flags
& IR3_REG_RELATIV
) {
1251 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1252 if ((*regmask
)[idx
/ 8] & (1 << (idx
% 8)))
1256 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1258 if ((*regmask
)[idx
/ 8] & (1 << (idx
% 8)))
1264 /* ************************************************************************* */