src/gallium/drivers/freedreno/ir3/ir3.h

   1 /*
   2  * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #ifndef IR3_H_
  25 #define IR3_H_
  26
  27 #include <stdint.h>
  28 #include <stdbool.h>
  29
  30 #include "instr-a3xx.h"
  31 #include "disasm.h"  /* TODO move 'enum shader_t' somewhere else.. */
  32
  33 /* low level intermediate representation of an adreno shader program */
  34
  35 struct ir3;
  36 struct ir3_instruction;
  37 struct ir3_block;
  38
  39 struct ir3 * fd_asm_parse(const char *src);
  40
  41 struct ir3_info {
  42         uint16_t sizedwords;
  43         uint16_t instrs_count;   /* expanded to account for rpt's */
  44         /* NOTE: max_reg, etc, does not include registers not touched
  45          * by the shader (ie. vertex fetched via VFD_DECODE but not
  46          * touched by shader)
  47          */
  48         int8_t   max_reg;   /* highest GPR # used by shader */
  49         int8_t   max_half_reg;
  50         int16_t  max_const;
  51 };
  52
  53 struct ir3_register {
  54         enum {
  55                 IR3_REG_CONST  = 0x001,
  56                 IR3_REG_IMMED  = 0x002,
  57                 IR3_REG_HALF   = 0x004,
  58                 IR3_REG_RELATIV= 0x008,
  59                 IR3_REG_R      = 0x010,
  60                 IR3_REG_NEGATE = 0x020,
  61                 IR3_REG_ABS    = 0x040,
  62                 IR3_REG_EVEN   = 0x080,
  63                 IR3_REG_POS_INF= 0x100,
  64                 /* (ei) flag, end-input?  Set on last bary, presumably to signal
  65                  * that the shader needs no more input:
  66                  */
  67                 IR3_REG_EI     = 0x200,
  68                 /* meta-flags, for intermediate stages of IR, ie.
  69                  * before register assignment is done:
  70                  */
  71                 IR3_REG_SSA    = 0x1000,   /* 'instr' is ptr to assigning instr */
  72                 IR3_REG_IA     = 0x2000,   /* meta-input dst is "assigned" */
  73                 IR3_REG_ADDR   = 0x4000,   /* register is a0.x */
  74         } flags;
  75         union {
  76                 /* normal registers:
  77                  * the component is in the low two bits of the reg #, so
  78                  * rN.x becomes: (N << 2) | x
  79                  */
  80                 int num;
  81                 /* immediate: */
  82                 int     iim_val;
  83                 float   fim_val;
  84                 /* relative: */
  85                 int offset;
  86                 /* for IR3_REG_SSA, src registers contain ptr back to
  87                  * assigning instruction.
  88                  */
  89                 struct ir3_instruction *instr;
  90         };
  91
  92         /* used for cat5 instructions, but also for internal/IR level
  93          * tracking of what registers are read/written by an instruction.
  94          * wrmask may be a bad name since it is used to represent both
  95          * src and dst that touch multiple adjacent registers.
  96          */
  97         int wrmask;
  98 };
  99
 100 #define IR3_INSTR_SRCS 10
 101
 102 struct ir3_instruction {
 103         struct ir3_block *block;
 104         int category;
 105         opc_t opc;
 106         enum {
 107                 /* (sy) flag is set on first instruction, and after sample
 108                  * instructions (probably just on RAW hazard).
 109                  */
 110                 IR3_INSTR_SY    = 0x001,
 111                 /* (ss) flag is set on first instruction, and first instruction
 112                  * to depend on the result of "long" instructions (RAW hazard):
 113                  *
 114                  *   rcp, rsq, log2, exp2, sin, cos, sqrt
 115                  *
 116                  * It seems to synchronize until all in-flight instructions are
 117                  * completed, for example:
 118                  *
 119                  *   rsq hr1.w, hr1.w
 120                  *   add.f hr2.z, (neg)hr2.z, hc0.y
 121                  *   mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
 122                  *   rsq hr2.x, hr2.x
 123                  *   (rpt1)nop
 124                  *   mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
 125                  *   nop
 126                  *   mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
 127                  *   (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
 128                  *   (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
 129                  *
 130                  * The last mul.f does not have (ss) set, presumably because the
 131                  * (ss) on the previous instruction does the job.
 132                  *
 133                  * The blob driver also seems to set it on WAR hazards, although
 134                  * not really clear if this is needed or just blob compiler being
 135                  * sloppy.  So far I haven't found a case where removing the (ss)
 136                  * causes problems for WAR hazard, but I could just be getting
 137                  * lucky:
 138                  *
 139                  *   rcp r1.y, r3.y
 140                  *   (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
 141                  *
 142                  */
 143                 IR3_INSTR_SS    = 0x002,
 144                 /* (jp) flag is set on jump targets:
 145                  */
 146                 IR3_INSTR_JP    = 0x004,
 147                 IR3_INSTR_UL    = 0x008,
 148                 IR3_INSTR_3D    = 0x010,
 149                 IR3_INSTR_A     = 0x020,
 150                 IR3_INSTR_O     = 0x040,
 151                 IR3_INSTR_P     = 0x080,
 152                 IR3_INSTR_S     = 0x100,
 153                 IR3_INSTR_S2EN  = 0x200,
 154                 /* meta-flags, for intermediate stages of IR, ie.
 155                  * before register assignment is done:
 156                  */
 157                 IR3_INSTR_MARK  = 0x1000,
 158         } flags;
 159         int repeat;
 160         unsigned regs_count;
 161         struct ir3_register *regs[1 + IR3_INSTR_SRCS];
 162         union {
 163                 struct {
 164                         char inv;
 165                         char comp;
 166                         int  immed;
 167                 } cat0;
 168                 struct {
 169                         type_t src_type, dst_type;
 170                 } cat1;
 171                 struct {
 172                         enum {
 173                                 IR3_COND_LT = 0,
 174                                 IR3_COND_LE = 1,
 175                                 IR3_COND_GT = 2,
 176                                 IR3_COND_GE = 3,
 177                                 IR3_COND_EQ = 4,
 178                                 IR3_COND_NE = 5,
 179                         } condition;
 180                 } cat2;
 181                 struct {
 182                         unsigned samp, tex;
 183                         type_t type;
 184                 } cat5;
 185                 struct {
 186                         type_t type;
 187                         int offset;
 188                         int iim_val;
 189                 } cat6;
 190                 /* for meta-instructions, just used to hold extra data
 191                  * before instruction scheduling, etc
 192                  */
 193                 struct {
 194                         int off;              /* component/offset */
 195                 } fo;
 196                 struct {
 197                         struct ir3_block *if_block, *else_block;
 198                 } flow;
 199                 struct {
 200                         struct ir3_block *block;
 201                 } inout;
 202         };
 203
 204         /* transient values used during various algorithms: */
 205         union {
 206                 /* The instruction depth is the max dependency distance to output.
 207                  *
 208                  * You can also think of it as the "cost", if we did any sort of
 209                  * optimization for register footprint.  Ie. a value that is  just
 210                  * result of moving a const to a reg would have a low cost,  so to
 211                  * it could make sense to duplicate the instruction at various
 212                  * points where the result is needed to reduce register footprint.
 213                  */
 214                 unsigned depth;
 215         };
 216         struct ir3_instruction *next;
 217 #ifdef DEBUG
 218         uint32_t serialno;
 219 #endif
 220 };
 221
 222 struct ir3_heap_chunk;
 223
 224 struct ir3 {
 225         unsigned instrs_count, instrs_sz;
 226         struct ir3_instruction **instrs;
 227         unsigned heap_idx;
 228         struct ir3_heap_chunk *chunk;
 229 };
 230
 231 struct ir3_block {
 232         struct ir3 *shader;
 233         unsigned ntemporaries, ninputs, noutputs;
 234         /* maps TGSI_FILE_TEMPORARY index back to the assigning instruction: */
 235         struct ir3_instruction **temporaries;
 236         struct ir3_instruction **inputs;
 237         struct ir3_instruction **outputs;
 238         /* only a single address register: */
 239         struct ir3_instruction *address;
 240         struct ir3_block *parent;
 241         struct ir3_instruction *head;
 242 };
 243
 244 struct ir3 * ir3_create(void);
 245 void ir3_destroy(struct ir3 *shader);
 246 void * ir3_assemble(struct ir3 *shader,
 247                 struct ir3_info *info);
 248 void * ir3_alloc(struct ir3 *shader, int sz);
 249
 250 struct ir3_block * ir3_block_create(struct ir3 *shader,
 251                 unsigned ntmp, unsigned nin, unsigned nout);
 252
 253 struct ir3_instruction * ir3_instr_create(struct ir3_block *block,
 254                 int category, opc_t opc);
 255 struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr);
 256 const char *ir3_instr_name(struct ir3_instruction *instr);
 257
 258 struct ir3_register * ir3_reg_create(struct ir3_instruction *instr,
 259                 int num, int flags);
 260
 261
 262 static inline bool ir3_instr_check_mark(struct ir3_instruction *instr)
 263 {
 264         if (instr->flags & IR3_INSTR_MARK)
 265                 return true;  /* already visited */
 266         instr->flags ^= IR3_INSTR_MARK;
 267         return false;
 268 }
 269
 270 static inline void ir3_clear_mark(struct ir3 *shader)
 271 {
 272         /* TODO would be nice to drop the instruction array.. for
 273          * new compiler, _clear_mark() is all we use it for, and
 274          * we could probably manage a linked list instead..
 275          */
 276         unsigned i;
 277         for (i = 0; i < shader->instrs_count; i++) {
 278                 struct ir3_instruction *instr = shader->instrs[i];
 279                 instr->flags &= ~IR3_INSTR_MARK;
 280         }
 281 }
 282
 283 static inline int ir3_instr_regno(struct ir3_instruction *instr,
 284                 struct ir3_register *reg)
 285 {
 286         unsigned i;
 287         for (i = 0; i < instr->regs_count; i++)
 288                 if (reg == instr->regs[i])
 289                         return i;
 290         return -1;
 291 }
 292
 293
 294 /* comp:
 295  *   0 - x
 296  *   1 - y
 297  *   2 - z
 298  *   3 - w
 299  */
 300 static inline uint32_t regid(int num, int comp)
 301 {
 302         return (num << 2) | (comp & 0x3);
 303 }
 304
 305 static inline uint32_t reg_num(struct ir3_register *reg)
 306 {
 307         return reg->num >> 2;
 308 }
 309
 310 static inline uint32_t reg_comp(struct ir3_register *reg)
 311 {
 312         return reg->num & 0x3;
 313 }
 314
 315 static inline bool is_flow(struct ir3_instruction *instr)
 316 {
 317         return (instr->category == 0);
 318 }
 319
 320 static inline bool is_kill(struct ir3_instruction *instr)
 321 {
 322         return is_flow(instr) && (instr->opc == OPC_KILL);
 323 }
 324
 325 static inline bool is_nop(struct ir3_instruction *instr)
 326 {
 327         return is_flow(instr) && (instr->opc == OPC_NOP);
 328 }
 329
 330 static inline bool is_alu(struct ir3_instruction *instr)
 331 {
 332         return (1 <= instr->category) && (instr->category <= 3);
 333 }
 334
 335 static inline bool is_sfu(struct ir3_instruction *instr)
 336 {
 337         return (instr->category == 4);
 338 }
 339
 340 static inline bool is_tex(struct ir3_instruction *instr)
 341 {
 342         return (instr->category == 5);
 343 }
 344
 345 static inline bool is_input(struct ir3_instruction *instr)
 346 {
 347         return (instr->category == 2) && (instr->opc == OPC_BARY_F);
 348 }
 349
 350 static inline bool is_meta(struct ir3_instruction *instr)
 351 {
 352         /* TODO how should we count PHI (and maybe fan-in/out) which
 353          * might actually contribute some instructions to the final
 354          * result?
 355          */
 356         return (instr->category == -1);
 357 }
 358
 359 static inline bool is_addr(struct ir3_instruction *instr)
 360 {
 361         return is_meta(instr) && (instr->opc == OPC_META_DEREF);
 362 }
 363
 364 static inline bool writes_addr(struct ir3_instruction *instr)
 365 {
 366         if (instr->regs_count > 0) {
 367                 struct ir3_register *dst = instr->regs[0];
 368                 return !!(dst->flags & IR3_REG_ADDR);
 369         }
 370         return false;
 371 }
 372
 373 static inline bool writes_pred(struct ir3_instruction *instr)
 374 {
 375         if (instr->regs_count > 0) {
 376                 struct ir3_register *dst = instr->regs[0];
 377                 return reg_num(dst) == REG_P0;
 378         }
 379         return false;
 380 }
 381
 382 static inline bool reg_gpr(struct ir3_register *r)
 383 {
 384         if (r->flags & (IR3_REG_CONST | IR3_REG_IMMED | IR3_REG_RELATIV | IR3_REG_SSA | IR3_REG_ADDR))
 385                 return false;
 386         if ((reg_num(r) == REG_A0) || (reg_num(r) == REG_P0))
 387                 return false;
 388         return true;
 389 }
 390
 391 /* dump: */
 392 #include <stdio.h>
 393 void ir3_dump(struct ir3 *shader, const char *name,
 394                 struct ir3_block *block /* XXX maybe 'block' ptr should move to ir3? */,
 395                 FILE *f);
 396 void ir3_dump_instr_single(struct ir3_instruction *instr);
 397 void ir3_dump_instr_list(struct ir3_instruction *instr);
 398
 399 /* flatten if/else: */
 400 int ir3_block_flatten(struct ir3_block *block);
 401
 402 /* depth calculation: */
 403 int ir3_delayslots(struct ir3_instruction *assigner,
 404                 struct ir3_instruction *consumer, unsigned n);
 405 void ir3_block_depth(struct ir3_block *block);
 406
 407 /* copy-propagate: */
 408 void ir3_block_cp(struct ir3_block *block);
 409
 410 /* scheduling: */
 411 int ir3_block_sched(struct ir3_block *block);
 412
 413 /* register assignment: */
 414 int ir3_block_ra(struct ir3_block *block, enum shader_t type,
 415                 bool half_precision, bool frag_coord, bool frag_face,
 416                 bool *has_samp, int *max_bary);
 417
 418 #ifndef ARRAY_SIZE
 419 #  define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
 420 #endif
 421
 422 /* ************************************************************************* */
 423 /* split this out or find some helper to use.. like main/bitset.h.. */
 424
 425 #include <string.h>
 426
 427 #define MAX_REG 256
 428
 429 typedef uint8_t regmask_t[2 * MAX_REG / 8];
 430
 431 static inline unsigned regmask_idx(struct ir3_register *reg)
 432 {
 433         unsigned num = reg->num;
 434         assert(num < MAX_REG);
 435         if (reg->flags & IR3_REG_HALF)
 436                 num += MAX_REG;
 437         return num;
 438 }
 439
 440 static inline void regmask_init(regmask_t *regmask)
 441 {
 442         memset(regmask, 0, sizeof(*regmask));
 443 }
 444
 445 static inline void regmask_set(regmask_t *regmask, struct ir3_register *reg)
 446 {
 447         unsigned idx = regmask_idx(reg);
 448         unsigned i;
 449         for (i = 0; i < IR3_INSTR_SRCS; i++, idx++)
 450                 if (reg->wrmask & (1 << i))
 451                         (*regmask)[idx / 8] |= 1 << (idx % 8);
 452 }
 453
 454 /* set bits in a if not set in b, conceptually:
 455  *   a |= (reg & ~b)
 456  */
 457 static inline void regmask_set_if_not(regmask_t *a,
 458                 struct ir3_register *reg, regmask_t *b)
 459 {
 460         unsigned idx = regmask_idx(reg);
 461         unsigned i;
 462         for (i = 0; i < IR3_INSTR_SRCS; i++, idx++)
 463                 if (reg->wrmask & (1 << i))
 464                         if (!((*b)[idx / 8] & (1 << (idx % 8))))
 465                                 (*a)[idx / 8] |= 1 << (idx % 8);
 466 }
 467
 468 static inline unsigned regmask_get(regmask_t *regmask,
 469                 struct ir3_register *reg)
 470 {
 471         unsigned idx = regmask_idx(reg);
 472         unsigned i;
 473         for (i = 0; i < IR3_INSTR_SRCS; i++, idx++)
 474                 if (reg->wrmask & (1 << i))
 475                         if ((*regmask)[idx / 8] & (1 << (idx % 8)))
 476                                 return true;
 477         return false;
 478 }
 479
 480 /* ************************************************************************* */
 481
 482 #endif /* IR3_H_ */