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freedreno/ir3: start dealing with half-precision
[mesa.git] / src / gallium / drivers / freedreno / ir3 / ir3.h
1 /*
2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #ifndef IR3_H_
25 #define IR3_H_
26
27 #include <stdint.h>
28 #include <stdbool.h>
29
30 #include "util/u_debug.h"
31 #include "util/list.h"
32
33 #include "instr-a3xx.h"
34 #include "disasm.h" /* TODO move 'enum shader_t' somewhere else.. */
35
36 /* low level intermediate representation of an adreno shader program */
37
38 struct ir3_compiler;
39 struct ir3;
40 struct ir3_instruction;
41 struct ir3_block;
42
43 struct ir3_info {
44 uint32_t gpu_id;
45 uint16_t sizedwords;
46 uint16_t instrs_count; /* expanded to account for rpt's */
47 /* NOTE: max_reg, etc, does not include registers not touched
48 * by the shader (ie. vertex fetched via VFD_DECODE but not
49 * touched by shader)
50 */
51 int8_t max_reg; /* highest GPR # used by shader */
52 int8_t max_half_reg;
53 int16_t max_const;
54
55 /* number of sync bits: */
56 uint16_t ss, sy;
57 };
58
59 struct ir3_register {
60 enum {
61 IR3_REG_CONST = 0x001,
62 IR3_REG_IMMED = 0x002,
63 IR3_REG_HALF = 0x004,
64 /* high registers are used for some things in compute shaders,
65 * for example. Seems to be for things that are global to all
66 * threads in a wave, so possibly these are global/shared by
67 * all the threads in the wave?
68 */
69 IR3_REG_HIGH = 0x008,
70 IR3_REG_RELATIV= 0x010,
71 IR3_REG_R = 0x020,
72 /* Most instructions, it seems, can do float abs/neg but not
73 * integer. The CP pass needs to know what is intended (int or
74 * float) in order to do the right thing. For this reason the
75 * abs/neg flags are split out into float and int variants. In
76 * addition, .b (bitwise) operations, the negate is actually a
77 * bitwise not, so split that out into a new flag to make it
78 * more clear.
79 */
80 IR3_REG_FNEG = 0x040,
81 IR3_REG_FABS = 0x080,
82 IR3_REG_SNEG = 0x100,
83 IR3_REG_SABS = 0x200,
84 IR3_REG_BNOT = 0x400,
85 IR3_REG_EVEN = 0x800,
86 IR3_REG_POS_INF= 0x1000,
87 /* (ei) flag, end-input? Set on last bary, presumably to signal
88 * that the shader needs no more input:
89 */
90 IR3_REG_EI = 0x2000,
91 /* meta-flags, for intermediate stages of IR, ie.
92 * before register assignment is done:
93 */
94 IR3_REG_SSA = 0x4000, /* 'instr' is ptr to assigning instr */
95 IR3_REG_ARRAY = 0x8000,
96
97 } flags;
98 union {
99 /* normal registers:
100 * the component is in the low two bits of the reg #, so
101 * rN.x becomes: (N << 2) | x
102 */
103 int num;
104 /* immediate: */
105 int32_t iim_val;
106 uint32_t uim_val;
107 float fim_val;
108 /* relative: */
109 struct {
110 uint16_t id;
111 int16_t offset;
112 } array;
113 };
114
115 /* For IR3_REG_SSA, src registers contain ptr back to assigning
116 * instruction.
117 *
118 * For IR3_REG_ARRAY, the pointer is back to the last dependent
119 * array access (although the net effect is the same, it points
120 * back to a previous instruction that we depend on).
121 */
122 struct ir3_instruction *instr;
123
124 union {
125 /* used for cat5 instructions, but also for internal/IR level
126 * tracking of what registers are read/written by an instruction.
127 * wrmask may be a bad name since it is used to represent both
128 * src and dst that touch multiple adjacent registers.
129 */
130 unsigned wrmask;
131 /* for relative addressing, 32bits for array size is too small,
132 * but otoh we don't need to deal with disjoint sets, so instead
133 * use a simple size field (number of scalar components).
134 */
135 unsigned size;
136 };
137 };
138
139 /*
140 * Stupid/simple growable array implementation:
141 */
142 #define DECLARE_ARRAY(type, name) \
143 unsigned name ## _count, name ## _sz; \
144 type * name;
145
146 #define array_insert(ctx, arr, val) do { \
147 if (arr ## _count == arr ## _sz) { \
148 arr ## _sz = MAX2(2 * arr ## _sz, 16); \
149 arr = reralloc_size(ctx, arr, arr ## _sz * sizeof(arr[0])); \
150 } \
151 arr[arr ##_count++] = val; \
152 } while (0)
153
154 struct ir3_instruction {
155 struct ir3_block *block;
156 opc_t opc;
157 enum {
158 /* (sy) flag is set on first instruction, and after sample
159 * instructions (probably just on RAW hazard).
160 */
161 IR3_INSTR_SY = 0x001,
162 /* (ss) flag is set on first instruction, and first instruction
163 * to depend on the result of "long" instructions (RAW hazard):
164 *
165 * rcp, rsq, log2, exp2, sin, cos, sqrt
166 *
167 * It seems to synchronize until all in-flight instructions are
168 * completed, for example:
169 *
170 * rsq hr1.w, hr1.w
171 * add.f hr2.z, (neg)hr2.z, hc0.y
172 * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
173 * rsq hr2.x, hr2.x
174 * (rpt1)nop
175 * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
176 * nop
177 * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
178 * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
179 * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
180 *
181 * The last mul.f does not have (ss) set, presumably because the
182 * (ss) on the previous instruction does the job.
183 *
184 * The blob driver also seems to set it on WAR hazards, although
185 * not really clear if this is needed or just blob compiler being
186 * sloppy. So far I haven't found a case where removing the (ss)
187 * causes problems for WAR hazard, but I could just be getting
188 * lucky:
189 *
190 * rcp r1.y, r3.y
191 * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
192 *
193 */
194 IR3_INSTR_SS = 0x002,
195 /* (jp) flag is set on jump targets:
196 */
197 IR3_INSTR_JP = 0x004,
198 IR3_INSTR_UL = 0x008,
199 IR3_INSTR_3D = 0x010,
200 IR3_INSTR_A = 0x020,
201 IR3_INSTR_O = 0x040,
202 IR3_INSTR_P = 0x080,
203 IR3_INSTR_S = 0x100,
204 IR3_INSTR_S2EN = 0x200,
205 IR3_INSTR_G = 0x400,
206 IR3_INSTR_SAT = 0x800,
207 /* meta-flags, for intermediate stages of IR, ie.
208 * before register assignment is done:
209 */
210 IR3_INSTR_MARK = 0x1000,
211 IR3_INSTR_UNUSED= 0x2000,
212 } flags;
213 int repeat;
214 #ifdef DEBUG
215 unsigned regs_max;
216 #endif
217 unsigned regs_count;
218 struct ir3_register **regs;
219 union {
220 struct {
221 char inv;
222 char comp;
223 int immed;
224 struct ir3_block *target;
225 } cat0;
226 struct {
227 type_t src_type, dst_type;
228 } cat1;
229 struct {
230 enum {
231 IR3_COND_LT = 0,
232 IR3_COND_LE = 1,
233 IR3_COND_GT = 2,
234 IR3_COND_GE = 3,
235 IR3_COND_EQ = 4,
236 IR3_COND_NE = 5,
237 } condition;
238 } cat2;
239 struct {
240 unsigned samp, tex;
241 type_t type;
242 } cat5;
243 struct {
244 type_t type;
245 int src_offset;
246 int dst_offset;
247 int iim_val : 3; /* for ldgb/stgb, # of components */
248 int d : 3;
249 bool typed : 1;
250 } cat6;
251 struct {
252 unsigned w : 1; /* write */
253 unsigned r : 1; /* read */
254 unsigned l : 1; /* local */
255 unsigned g : 1; /* global */
256 } cat7;
257 /* for meta-instructions, just used to hold extra data
258 * before instruction scheduling, etc
259 */
260 struct {
261 int off; /* component/offset */
262 } fo;
263 struct {
264 struct ir3_block *block;
265 } inout;
266 };
267
268 /* transient values used during various algorithms: */
269 union {
270 /* The instruction depth is the max dependency distance to output.
271 *
272 * You can also think of it as the "cost", if we did any sort of
273 * optimization for register footprint. Ie. a value that is just
274 * result of moving a const to a reg would have a low cost, so to
275 * it could make sense to duplicate the instruction at various
276 * points where the result is needed to reduce register footprint.
277 */
278 unsigned depth;
279 /* When we get to the RA stage, we no longer need depth, but
280 * we do need instruction's position/name:
281 */
282 struct {
283 uint16_t ip;
284 uint16_t name;
285 };
286 };
287
288 /* used for per-pass extra instruction data.
289 */
290 void *data;
291
292 /* Used during CP and RA stages. For fanin and shader inputs/
293 * outputs where we need a sequence of consecutive registers,
294 * keep track of each src instructions left (ie 'n-1') and right
295 * (ie 'n+1') neighbor. The front-end must insert enough mov's
296 * to ensure that each instruction has at most one left and at
297 * most one right neighbor. During the copy-propagation pass,
298 * we only remove mov's when we can preserve this constraint.
299 * And during the RA stage, we use the neighbor information to
300 * allocate a block of registers in one shot.
301 *
302 * TODO: maybe just add something like:
303 * struct ir3_instruction_ref {
304 * struct ir3_instruction *instr;
305 * unsigned cnt;
306 * }
307 *
308 * Or can we get away without the refcnt stuff? It seems like
309 * it should be overkill.. the problem is if, potentially after
310 * already eliminating some mov's, if you have a single mov that
311 * needs to be grouped with it's neighbors in two different
312 * places (ex. shader output and a fanin).
313 */
314 struct {
315 struct ir3_instruction *left, *right;
316 uint16_t left_cnt, right_cnt;
317 } cp;
318
319 /* an instruction can reference at most one address register amongst
320 * it's src/dst registers. Beyond that, you need to insert mov's.
321 *
322 * NOTE: do not write this directly, use ir3_instr_set_address()
323 */
324 struct ir3_instruction *address;
325
326 /* Tracking for additional dependent instructions. Used to handle
327 * barriers, WAR hazards for arrays/SSBOs/etc.
328 */
329 DECLARE_ARRAY(struct ir3_instruction *, deps);
330
331 /*
332 * From PoV of instruction scheduling, not execution (ie. ignores global/
333 * local distinction):
334 * shared image atomic SSBO everything
335 * barrier()/ - R/W R/W R/W R/W X
336 * groupMemoryBarrier()
337 * memoryBarrier() - R/W R/W
338 * (but only images declared coherent?)
339 * memoryBarrierAtomic() - R/W
340 * memoryBarrierBuffer() - R/W
341 * memoryBarrierImage() - R/W
342 * memoryBarrierShared() - R/W
343 *
344 * TODO I think for SSBO/image/shared, in cases where we can determine
345 * which variable is accessed, we don't need to care about accesses to
346 * different variables (unless declared coherent??)
347 */
348 enum {
349 IR3_BARRIER_EVERYTHING = 1 << 0,
350 IR3_BARRIER_SHARED_R = 1 << 1,
351 IR3_BARRIER_SHARED_W = 1 << 2,
352 IR3_BARRIER_IMAGE_R = 1 << 3,
353 IR3_BARRIER_IMAGE_W = 1 << 4,
354 IR3_BARRIER_BUFFER_R = 1 << 5,
355 IR3_BARRIER_BUFFER_W = 1 << 6,
356 IR3_BARRIER_ARRAY_R = 1 << 7,
357 IR3_BARRIER_ARRAY_W = 1 << 8,
358 } barrier_class, barrier_conflict;
359
360 /* Entry in ir3_block's instruction list: */
361 struct list_head node;
362
363 int use_count; /* currently just updated/used by cp */
364
365 #ifdef DEBUG
366 uint32_t serialno;
367 #endif
368 };
369
370 static inline struct ir3_instruction *
371 ir3_neighbor_first(struct ir3_instruction *instr)
372 {
373 int cnt = 0;
374 while (instr->cp.left) {
375 instr = instr->cp.left;
376 if (++cnt > 0xffff) {
377 debug_assert(0);
378 break;
379 }
380 }
381 return instr;
382 }
383
384 static inline int ir3_neighbor_count(struct ir3_instruction *instr)
385 {
386 int num = 1;
387
388 debug_assert(!instr->cp.left);
389
390 while (instr->cp.right) {
391 num++;
392 instr = instr->cp.right;
393 if (num > 0xffff) {
394 debug_assert(0);
395 break;
396 }
397 }
398
399 return num;
400 }
401
402 struct ir3 {
403 struct ir3_compiler *compiler;
404
405 unsigned ninputs, noutputs;
406 struct ir3_instruction **inputs;
407 struct ir3_instruction **outputs;
408
409 /* Track bary.f (and ldlv) instructions.. this is needed in
410 * scheduling to ensure that all varying fetches happen before
411 * any potential kill instructions. The hw gets grumpy if all
412 * threads in a group are killed before the last bary.f gets
413 * a chance to signal end of input (ei).
414 */
415 DECLARE_ARRAY(struct ir3_instruction *, baryfs);
416
417 /* Track all indirect instructions (read and write). To avoid
418 * deadlock scenario where an address register gets scheduled,
419 * but other dependent src instructions cannot be scheduled due
420 * to dependency on a *different* address register value, the
421 * scheduler needs to ensure that all dependencies other than
422 * the instruction other than the address register are scheduled
423 * before the one that writes the address register. Having a
424 * convenient list of instructions that reference some address
425 * register simplifies this.
426 */
427 DECLARE_ARRAY(struct ir3_instruction *, indirects);
428
429 /* and same for instructions that consume predicate register: */
430 DECLARE_ARRAY(struct ir3_instruction *, predicates);
431
432 /* Track texture sample instructions which need texture state
433 * patched in (for astc-srgb workaround):
434 */
435 DECLARE_ARRAY(struct ir3_instruction *, astc_srgb);
436
437 /* List of blocks: */
438 struct list_head block_list;
439
440 /* List of ir3_array's: */
441 struct list_head array_list;
442
443 #ifdef DEBUG
444 unsigned block_count, instr_count;
445 #endif
446 };
447
448 typedef struct nir_register nir_register;
449
450 struct ir3_array {
451 struct list_head node;
452 unsigned length;
453 unsigned id;
454
455 nir_register *r;
456
457 /* To avoid array write's from getting DCE'd, keep track of the
458 * most recent write. Any array access depends on the most
459 * recent write. This way, nothing depends on writes after the
460 * last read. But all the writes that happen before that have
461 * something depending on them
462 */
463 struct ir3_instruction *last_write;
464
465 /* extra stuff used in RA pass: */
466 unsigned base; /* base vreg name */
467 unsigned reg; /* base physical reg */
468 uint16_t start_ip, end_ip;
469 };
470
471 struct ir3_array * ir3_lookup_array(struct ir3 *ir, unsigned id);
472
473 typedef struct nir_block nir_block;
474
475 struct ir3_block {
476 struct list_head node;
477 struct ir3 *shader;
478
479 const nir_block *nblock;
480
481 struct list_head instr_list; /* list of ir3_instruction */
482
483 /* each block has either one or two successors.. in case of
484 * two successors, 'condition' decides which one to follow.
485 * A block preceding an if/else has two successors.
486 */
487 struct ir3_instruction *condition;
488 struct ir3_block *successors[2];
489
490 unsigned predecessors_count;
491 struct ir3_block **predecessors;
492
493 uint16_t start_ip, end_ip;
494
495 /* Track instructions which do not write a register but other-
496 * wise must not be discarded (such as kill, stg, etc)
497 */
498 DECLARE_ARRAY(struct ir3_instruction *, keeps);
499
500 /* used for per-pass extra block data. Mainly used right
501 * now in RA step to track livein/liveout.
502 */
503 void *data;
504
505 #ifdef DEBUG
506 uint32_t serialno;
507 #endif
508 };
509
510 static inline uint32_t
511 block_id(struct ir3_block *block)
512 {
513 #ifdef DEBUG
514 return block->serialno;
515 #else
516 return (uint32_t)(unsigned long)block;
517 #endif
518 }
519
520 struct ir3 * ir3_create(struct ir3_compiler *compiler,
521 unsigned nin, unsigned nout);
522 void ir3_destroy(struct ir3 *shader);
523 void * ir3_assemble(struct ir3 *shader,
524 struct ir3_info *info, uint32_t gpu_id);
525 void * ir3_alloc(struct ir3 *shader, int sz);
526
527 struct ir3_block * ir3_block_create(struct ir3 *shader);
528
529 struct ir3_instruction * ir3_instr_create(struct ir3_block *block, opc_t opc);
530 struct ir3_instruction * ir3_instr_create2(struct ir3_block *block,
531 opc_t opc, int nreg);
532 struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr);
533 void ir3_instr_add_dep(struct ir3_instruction *instr, struct ir3_instruction *dep);
534 const char *ir3_instr_name(struct ir3_instruction *instr);
535
536 struct ir3_register * ir3_reg_create(struct ir3_instruction *instr,
537 int num, int flags);
538 struct ir3_register * ir3_reg_clone(struct ir3 *shader,
539 struct ir3_register *reg);
540
541 void ir3_instr_set_address(struct ir3_instruction *instr,
542 struct ir3_instruction *addr);
543
544 static inline bool ir3_instr_check_mark(struct ir3_instruction *instr)
545 {
546 if (instr->flags & IR3_INSTR_MARK)
547 return true; /* already visited */
548 instr->flags |= IR3_INSTR_MARK;
549 return false;
550 }
551
552 void ir3_block_clear_mark(struct ir3_block *block);
553 void ir3_clear_mark(struct ir3 *shader);
554
555 unsigned ir3_count_instructions(struct ir3 *ir);
556
557 static inline int ir3_instr_regno(struct ir3_instruction *instr,
558 struct ir3_register *reg)
559 {
560 unsigned i;
561 for (i = 0; i < instr->regs_count; i++)
562 if (reg == instr->regs[i])
563 return i;
564 return -1;
565 }
566
567
568 #define MAX_ARRAYS 16
569
570 /* comp:
571 * 0 - x
572 * 1 - y
573 * 2 - z
574 * 3 - w
575 */
576 static inline uint32_t regid(int num, int comp)
577 {
578 return (num << 2) | (comp & 0x3);
579 }
580
581 static inline uint32_t reg_num(struct ir3_register *reg)
582 {
583 return reg->num >> 2;
584 }
585
586 static inline uint32_t reg_comp(struct ir3_register *reg)
587 {
588 return reg->num & 0x3;
589 }
590
591 static inline bool is_flow(struct ir3_instruction *instr)
592 {
593 return (opc_cat(instr->opc) == 0);
594 }
595
596 static inline bool is_kill(struct ir3_instruction *instr)
597 {
598 return instr->opc == OPC_KILL;
599 }
600
601 static inline bool is_nop(struct ir3_instruction *instr)
602 {
603 return instr->opc == OPC_NOP;
604 }
605
606 /* Is it a non-transformative (ie. not type changing) mov? This can
607 * also include absneg.s/absneg.f, which for the most part can be
608 * treated as a mov (single src argument).
609 */
610 static inline bool is_same_type_mov(struct ir3_instruction *instr)
611 {
612 struct ir3_register *dst;
613
614 switch (instr->opc) {
615 case OPC_MOV:
616 if (instr->cat1.src_type != instr->cat1.dst_type)
617 return false;
618 break;
619 case OPC_ABSNEG_F:
620 case OPC_ABSNEG_S:
621 if (instr->flags & IR3_INSTR_SAT)
622 return false;
623 break;
624 default:
625 return false;
626 }
627
628 dst = instr->regs[0];
629
630 /* mov's that write to a0.x or p0.x are special: */
631 if (dst->num == regid(REG_P0, 0))
632 return false;
633 if (dst->num == regid(REG_A0, 0))
634 return false;
635
636 if (dst->flags & (IR3_REG_RELATIV | IR3_REG_ARRAY))
637 return false;
638
639 return true;
640 }
641
642 static inline bool is_alu(struct ir3_instruction *instr)
643 {
644 return (1 <= opc_cat(instr->opc)) && (opc_cat(instr->opc) <= 3);
645 }
646
647 static inline bool is_sfu(struct ir3_instruction *instr)
648 {
649 return (opc_cat(instr->opc) == 4);
650 }
651
652 static inline bool is_tex(struct ir3_instruction *instr)
653 {
654 return (opc_cat(instr->opc) == 5);
655 }
656
657 static inline bool is_mem(struct ir3_instruction *instr)
658 {
659 return (opc_cat(instr->opc) == 6);
660 }
661
662 static inline bool is_barrier(struct ir3_instruction *instr)
663 {
664 return (opc_cat(instr->opc) == 7);
665 }
666
667 static inline bool
668 is_store(struct ir3_instruction *instr)
669 {
670 /* these instructions, the "destination" register is
671 * actually a source, the address to store to.
672 */
673 switch (instr->opc) {
674 case OPC_STG:
675 case OPC_STGB:
676 case OPC_STIB:
677 case OPC_STP:
678 case OPC_STL:
679 case OPC_STLW:
680 case OPC_L2G:
681 case OPC_G2L:
682 return true;
683 default:
684 return false;
685 }
686 }
687
688 static inline bool is_load(struct ir3_instruction *instr)
689 {
690 switch (instr->opc) {
691 case OPC_LDG:
692 case OPC_LDGB:
693 case OPC_LDL:
694 case OPC_LDP:
695 case OPC_L2G:
696 case OPC_LDLW:
697 case OPC_LDC:
698 case OPC_LDLV:
699 /* probably some others too.. */
700 return true;
701 default:
702 return false;
703 }
704 }
705
706 static inline bool is_input(struct ir3_instruction *instr)
707 {
708 /* in some cases, ldlv is used to fetch varying without
709 * interpolation.. fortunately inloc is the first src
710 * register in either case
711 */
712 switch (instr->opc) {
713 case OPC_LDLV:
714 case OPC_BARY_F:
715 return true;
716 default:
717 return false;
718 }
719 }
720
721 static inline bool is_bool(struct ir3_instruction *instr)
722 {
723 switch (instr->opc) {
724 case OPC_CMPS_F:
725 case OPC_CMPS_S:
726 case OPC_CMPS_U:
727 return true;
728 default:
729 return false;
730 }
731 }
732
733 static inline bool is_meta(struct ir3_instruction *instr)
734 {
735 /* TODO how should we count PHI (and maybe fan-in/out) which
736 * might actually contribute some instructions to the final
737 * result?
738 */
739 return (opc_cat(instr->opc) == -1);
740 }
741
742 static inline bool writes_addr(struct ir3_instruction *instr)
743 {
744 if (instr->regs_count > 0) {
745 struct ir3_register *dst = instr->regs[0];
746 return reg_num(dst) == REG_A0;
747 }
748 return false;
749 }
750
751 static inline bool writes_pred(struct ir3_instruction *instr)
752 {
753 if (instr->regs_count > 0) {
754 struct ir3_register *dst = instr->regs[0];
755 return reg_num(dst) == REG_P0;
756 }
757 return false;
758 }
759
760 /* returns defining instruction for reg */
761 /* TODO better name */
762 static inline struct ir3_instruction *ssa(struct ir3_register *reg)
763 {
764 if (reg->flags & (IR3_REG_SSA | IR3_REG_ARRAY)) {
765 debug_assert(!(reg->instr && (reg->instr->flags & IR3_INSTR_UNUSED)));
766 return reg->instr;
767 }
768 return NULL;
769 }
770
771 static inline bool conflicts(struct ir3_instruction *a,
772 struct ir3_instruction *b)
773 {
774 return (a && b) && (a != b);
775 }
776
777 static inline bool reg_gpr(struct ir3_register *r)
778 {
779 if (r->flags & (IR3_REG_CONST | IR3_REG_IMMED))
780 return false;
781 if ((reg_num(r) == REG_A0) || (reg_num(r) == REG_P0))
782 return false;
783 return true;
784 }
785
786 static inline type_t half_type(type_t type)
787 {
788 switch (type) {
789 case TYPE_F32: return TYPE_F16;
790 case TYPE_U32: return TYPE_U16;
791 case TYPE_S32: return TYPE_S16;
792 case TYPE_F16:
793 case TYPE_U16:
794 case TYPE_S16:
795 return type;
796 default:
797 assert(0);
798 return ~0;
799 }
800 }
801
802 /* some cat2 instructions (ie. those which are not float) can embed an
803 * immediate:
804 */
805 static inline bool ir3_cat2_int(opc_t opc)
806 {
807 switch (opc) {
808 case OPC_ADD_U:
809 case OPC_ADD_S:
810 case OPC_SUB_U:
811 case OPC_SUB_S:
812 case OPC_CMPS_U:
813 case OPC_CMPS_S:
814 case OPC_MIN_U:
815 case OPC_MIN_S:
816 case OPC_MAX_U:
817 case OPC_MAX_S:
818 case OPC_CMPV_U:
819 case OPC_CMPV_S:
820 case OPC_MUL_U:
821 case OPC_MUL_S:
822 case OPC_MULL_U:
823 case OPC_CLZ_S:
824 case OPC_ABSNEG_S:
825 case OPC_AND_B:
826 case OPC_OR_B:
827 case OPC_NOT_B:
828 case OPC_XOR_B:
829 case OPC_BFREV_B:
830 case OPC_CLZ_B:
831 case OPC_SHL_B:
832 case OPC_SHR_B:
833 case OPC_ASHR_B:
834 case OPC_MGEN_B:
835 case OPC_GETBIT_B:
836 case OPC_CBITS_B:
837 case OPC_BARY_F:
838 return true;
839
840 default:
841 return false;
842 }
843 }
844
845
846 /* map cat2 instruction to valid abs/neg flags: */
847 static inline unsigned ir3_cat2_absneg(opc_t opc)
848 {
849 switch (opc) {
850 case OPC_ADD_F:
851 case OPC_MIN_F:
852 case OPC_MAX_F:
853 case OPC_MUL_F:
854 case OPC_SIGN_F:
855 case OPC_CMPS_F:
856 case OPC_ABSNEG_F:
857 case OPC_CMPV_F:
858 case OPC_FLOOR_F:
859 case OPC_CEIL_F:
860 case OPC_RNDNE_F:
861 case OPC_RNDAZ_F:
862 case OPC_TRUNC_F:
863 case OPC_BARY_F:
864 return IR3_REG_FABS | IR3_REG_FNEG;
865
866 case OPC_ADD_U:
867 case OPC_ADD_S:
868 case OPC_SUB_U:
869 case OPC_SUB_S:
870 case OPC_CMPS_U:
871 case OPC_CMPS_S:
872 case OPC_MIN_U:
873 case OPC_MIN_S:
874 case OPC_MAX_U:
875 case OPC_MAX_S:
876 case OPC_CMPV_U:
877 case OPC_CMPV_S:
878 case OPC_MUL_U:
879 case OPC_MUL_S:
880 case OPC_MULL_U:
881 case OPC_CLZ_S:
882 return 0;
883
884 case OPC_ABSNEG_S:
885 return IR3_REG_SABS | IR3_REG_SNEG;
886
887 case OPC_AND_B:
888 case OPC_OR_B:
889 case OPC_NOT_B:
890 case OPC_XOR_B:
891 case OPC_BFREV_B:
892 case OPC_CLZ_B:
893 case OPC_SHL_B:
894 case OPC_SHR_B:
895 case OPC_ASHR_B:
896 case OPC_MGEN_B:
897 case OPC_GETBIT_B:
898 case OPC_CBITS_B:
899 return IR3_REG_BNOT;
900
901 default:
902 return 0;
903 }
904 }
905
906 /* map cat3 instructions to valid abs/neg flags: */
907 static inline unsigned ir3_cat3_absneg(opc_t opc)
908 {
909 switch (opc) {
910 case OPC_MAD_F16:
911 case OPC_MAD_F32:
912 case OPC_SEL_F16:
913 case OPC_SEL_F32:
914 return IR3_REG_FNEG;
915
916 case OPC_MAD_U16:
917 case OPC_MADSH_U16:
918 case OPC_MAD_S16:
919 case OPC_MADSH_M16:
920 case OPC_MAD_U24:
921 case OPC_MAD_S24:
922 case OPC_SEL_S16:
923 case OPC_SEL_S32:
924 case OPC_SAD_S16:
925 case OPC_SAD_S32:
926 /* neg *may* work on 3rd src.. */
927
928 case OPC_SEL_B16:
929 case OPC_SEL_B32:
930
931 default:
932 return 0;
933 }
934 }
935
936 #define MASK(n) ((1 << (n)) - 1)
937
938 /* iterator for an instructions's sources (reg), also returns src #: */
939 #define foreach_src_n(__srcreg, __n, __instr) \
940 if ((__instr)->regs_count) \
941 for (unsigned __cnt = (__instr)->regs_count - 1, __n = 0; __n < __cnt; __n++) \
942 if ((__srcreg = (__instr)->regs[__n + 1]))
943
944 /* iterator for an instructions's sources (reg): */
945 #define foreach_src(__srcreg, __instr) \
946 foreach_src_n(__srcreg, __i, __instr)
947
948 static inline unsigned __ssa_src_cnt(struct ir3_instruction *instr)
949 {
950 unsigned cnt = instr->regs_count + instr->deps_count;
951 if (instr->address)
952 cnt++;
953 return cnt;
954 }
955
956 static inline struct ir3_instruction * __ssa_src_n(struct ir3_instruction *instr, unsigned n)
957 {
958 if (n == (instr->regs_count + instr->deps_count))
959 return instr->address;
960 if (n >= instr->regs_count)
961 return instr->deps[n - instr->regs_count];
962 return ssa(instr->regs[n]);
963 }
964
965 static inline bool __is_false_dep(struct ir3_instruction *instr, unsigned n)
966 {
967 if (n == (instr->regs_count + instr->deps_count))
968 return false;
969 if (n >= instr->regs_count)
970 return true;
971 return false;
972 }
973
974 #define __src_cnt(__instr) ((__instr)->address ? (__instr)->regs_count : (__instr)->regs_count - 1)
975
976 /* iterator for an instruction's SSA sources (instr), also returns src #: */
977 #define foreach_ssa_src_n(__srcinst, __n, __instr) \
978 for (unsigned __cnt = __ssa_src_cnt(__instr), __n = 0; __n < __cnt; __n++) \
979 if ((__srcinst = __ssa_src_n(__instr, __n)))
980
981 /* iterator for an instruction's SSA sources (instr): */
982 #define foreach_ssa_src(__srcinst, __instr) \
983 foreach_ssa_src_n(__srcinst, __i, __instr)
984
985
986 /* dump: */
987 void ir3_print(struct ir3 *ir);
988 void ir3_print_instr(struct ir3_instruction *instr);
989
990 /* depth calculation: */
991 int ir3_delayslots(struct ir3_instruction *assigner,
992 struct ir3_instruction *consumer, unsigned n);
993 void ir3_insert_by_depth(struct ir3_instruction *instr, struct list_head *list);
994 void ir3_depth(struct ir3 *ir);
995
996 /* copy-propagate: */
997 struct ir3_shader_variant;
998 void ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so);
999
1000 /* group neighbors and insert mov's to resolve conflicts: */
1001 void ir3_group(struct ir3 *ir);
1002
1003 /* scheduling: */
1004 void ir3_sched_add_deps(struct ir3 *ir);
1005 int ir3_sched(struct ir3 *ir);
1006
1007 /* register assignment: */
1008 struct ir3_ra_reg_set * ir3_ra_alloc_reg_set(void *memctx);
1009 int ir3_ra(struct ir3 *ir3, enum shader_t type,
1010 bool frag_coord, bool frag_face);
1011
1012 /* legalize: */
1013 void ir3_legalize(struct ir3 *ir, bool *has_samp, bool *has_ssbo, int *max_bary);
1014
1015 /* ************************************************************************* */
1016 /* instruction helpers */
1017
1018 /* creates SSA src of correct type (ie. half vs full precision) */
1019 static inline struct ir3_register * __ssa_src(struct ir3_instruction *instr,
1020 struct ir3_instruction *src, unsigned flags)
1021 {
1022 struct ir3_register *reg;
1023 if (src->regs[0]->flags & IR3_REG_HALF)
1024 flags |= IR3_REG_HALF;
1025 reg = ir3_reg_create(instr, 0, IR3_REG_SSA | flags);
1026 reg->instr = src;
1027 return reg;
1028 }
1029
1030 static inline struct ir3_instruction *
1031 ir3_MOV(struct ir3_block *block, struct ir3_instruction *src, type_t type)
1032 {
1033 struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOV);
1034 ir3_reg_create(instr, 0, 0); /* dst */
1035 if (src->regs[0]->flags & IR3_REG_ARRAY) {
1036 struct ir3_register *src_reg = __ssa_src(instr, src, IR3_REG_ARRAY);
1037 src_reg->array = src->regs[0]->array;
1038 } else {
1039 __ssa_src(instr, src, 0);
1040 }
1041 debug_assert(!(src->regs[0]->flags & IR3_REG_RELATIV));
1042 instr->cat1.src_type = type;
1043 instr->cat1.dst_type = type;
1044 return instr;
1045 }
1046
1047 static inline struct ir3_instruction *
1048 ir3_COV(struct ir3_block *block, struct ir3_instruction *src,
1049 type_t src_type, type_t dst_type)
1050 {
1051 struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOV);
1052 ir3_reg_create(instr, 0, 0); /* dst */
1053 __ssa_src(instr, src, 0);
1054 instr->cat1.src_type = src_type;
1055 instr->cat1.dst_type = dst_type;
1056 debug_assert(!(src->regs[0]->flags & IR3_REG_ARRAY));
1057 return instr;
1058 }
1059
1060 static inline struct ir3_instruction *
1061 ir3_NOP(struct ir3_block *block)
1062 {
1063 return ir3_instr_create(block, OPC_NOP);
1064 }
1065
1066 #define INSTR0(name) \
1067 static inline struct ir3_instruction * \
1068 ir3_##name(struct ir3_block *block) \
1069 { \
1070 struct ir3_instruction *instr = \
1071 ir3_instr_create(block, OPC_##name); \
1072 return instr; \
1073 }
1074
1075 #define INSTR1(name) \
1076 static inline struct ir3_instruction * \
1077 ir3_##name(struct ir3_block *block, \
1078 struct ir3_instruction *a, unsigned aflags) \
1079 { \
1080 struct ir3_instruction *instr = \
1081 ir3_instr_create(block, OPC_##name); \
1082 ir3_reg_create(instr, 0, 0); /* dst */ \
1083 __ssa_src(instr, a, aflags); \
1084 return instr; \
1085 }
1086
1087 #define INSTR2(name) \
1088 static inline struct ir3_instruction * \
1089 ir3_##name(struct ir3_block *block, \
1090 struct ir3_instruction *a, unsigned aflags, \
1091 struct ir3_instruction *b, unsigned bflags) \
1092 { \
1093 struct ir3_instruction *instr = \
1094 ir3_instr_create(block, OPC_##name); \
1095 ir3_reg_create(instr, 0, 0); /* dst */ \
1096 __ssa_src(instr, a, aflags); \
1097 __ssa_src(instr, b, bflags); \
1098 return instr; \
1099 }
1100
1101 #define INSTR3(name) \
1102 static inline struct ir3_instruction * \
1103 ir3_##name(struct ir3_block *block, \
1104 struct ir3_instruction *a, unsigned aflags, \
1105 struct ir3_instruction *b, unsigned bflags, \
1106 struct ir3_instruction *c, unsigned cflags) \
1107 { \
1108 struct ir3_instruction *instr = \
1109 ir3_instr_create(block, OPC_##name); \
1110 ir3_reg_create(instr, 0, 0); /* dst */ \
1111 __ssa_src(instr, a, aflags); \
1112 __ssa_src(instr, b, bflags); \
1113 __ssa_src(instr, c, cflags); \
1114 return instr; \
1115 }
1116
1117 #define INSTR4(name) \
1118 static inline struct ir3_instruction * \
1119 ir3_##name(struct ir3_block *block, \
1120 struct ir3_instruction *a, unsigned aflags, \
1121 struct ir3_instruction *b, unsigned bflags, \
1122 struct ir3_instruction *c, unsigned cflags, \
1123 struct ir3_instruction *d, unsigned dflags) \
1124 { \
1125 struct ir3_instruction *instr = \
1126 ir3_instr_create2(block, OPC_##name, 5); \
1127 ir3_reg_create(instr, 0, 0); /* dst */ \
1128 __ssa_src(instr, a, aflags); \
1129 __ssa_src(instr, b, bflags); \
1130 __ssa_src(instr, c, cflags); \
1131 __ssa_src(instr, d, dflags); \
1132 return instr; \
1133 }
1134
1135 #define INSTR4F(f, name) \
1136 static inline struct ir3_instruction * \
1137 ir3_##name##_##f(struct ir3_block *block, \
1138 struct ir3_instruction *a, unsigned aflags, \
1139 struct ir3_instruction *b, unsigned bflags, \
1140 struct ir3_instruction *c, unsigned cflags, \
1141 struct ir3_instruction *d, unsigned dflags) \
1142 { \
1143 struct ir3_instruction *instr = \
1144 ir3_instr_create2(block, OPC_##name, 5); \
1145 ir3_reg_create(instr, 0, 0); /* dst */ \
1146 __ssa_src(instr, a, aflags); \
1147 __ssa_src(instr, b, bflags); \
1148 __ssa_src(instr, c, cflags); \
1149 __ssa_src(instr, d, dflags); \
1150 instr->flags |= IR3_INSTR_##f; \
1151 return instr; \
1152 }
1153
1154 /* cat0 instructions: */
1155 INSTR0(BR)
1156 INSTR0(JUMP)
1157 INSTR1(KILL)
1158 INSTR0(END)
1159
1160 /* cat2 instructions, most 2 src but some 1 src: */
1161 INSTR2(ADD_F)
1162 INSTR2(MIN_F)
1163 INSTR2(MAX_F)
1164 INSTR2(MUL_F)
1165 INSTR1(SIGN_F)
1166 INSTR2(CMPS_F)
1167 INSTR1(ABSNEG_F)
1168 INSTR2(CMPV_F)
1169 INSTR1(FLOOR_F)
1170 INSTR1(CEIL_F)
1171 INSTR1(RNDNE_F)
1172 INSTR1(RNDAZ_F)
1173 INSTR1(TRUNC_F)
1174 INSTR2(ADD_U)
1175 INSTR2(ADD_S)
1176 INSTR2(SUB_U)
1177 INSTR2(SUB_S)
1178 INSTR2(CMPS_U)
1179 INSTR2(CMPS_S)
1180 INSTR2(MIN_U)
1181 INSTR2(MIN_S)
1182 INSTR2(MAX_U)
1183 INSTR2(MAX_S)
1184 INSTR1(ABSNEG_S)
1185 INSTR2(AND_B)
1186 INSTR2(OR_B)
1187 INSTR1(NOT_B)
1188 INSTR2(XOR_B)
1189 INSTR2(CMPV_U)
1190 INSTR2(CMPV_S)
1191 INSTR2(MUL_U)
1192 INSTR2(MUL_S)
1193 INSTR2(MULL_U)
1194 INSTR1(BFREV_B)
1195 INSTR1(CLZ_S)
1196 INSTR1(CLZ_B)
1197 INSTR2(SHL_B)
1198 INSTR2(SHR_B)
1199 INSTR2(ASHR_B)
1200 INSTR2(BARY_F)
1201 INSTR2(MGEN_B)
1202 INSTR2(GETBIT_B)
1203 INSTR1(SETRM)
1204 INSTR1(CBITS_B)
1205 INSTR2(SHB)
1206 INSTR2(MSAD)
1207
1208 /* cat3 instructions: */
1209 INSTR3(MAD_U16)
1210 INSTR3(MADSH_U16)
1211 INSTR3(MAD_S16)
1212 INSTR3(MADSH_M16)
1213 INSTR3(MAD_U24)
1214 INSTR3(MAD_S24)
1215 INSTR3(MAD_F16)
1216 INSTR3(MAD_F32)
1217 INSTR3(SEL_B16)
1218 INSTR3(SEL_B32)
1219 INSTR3(SEL_S16)
1220 INSTR3(SEL_S32)
1221 INSTR3(SEL_F16)
1222 INSTR3(SEL_F32)
1223 INSTR3(SAD_S16)
1224 INSTR3(SAD_S32)
1225
1226 /* cat4 instructions: */
1227 INSTR1(RCP)
1228 INSTR1(RSQ)
1229 INSTR1(LOG2)
1230 INSTR1(EXP2)
1231 INSTR1(SIN)
1232 INSTR1(COS)
1233 INSTR1(SQRT)
1234
1235 /* cat5 instructions: */
1236 INSTR1(DSX)
1237 INSTR1(DSY)
1238
1239 static inline struct ir3_instruction *
1240 ir3_SAM(struct ir3_block *block, opc_t opc, type_t type,
1241 unsigned wrmask, unsigned flags, unsigned samp, unsigned tex,
1242 struct ir3_instruction *src0, struct ir3_instruction *src1)
1243 {
1244 struct ir3_instruction *sam;
1245 struct ir3_register *reg;
1246
1247 sam = ir3_instr_create(block, opc);
1248 sam->flags |= flags;
1249 ir3_reg_create(sam, 0, 0)->wrmask = wrmask;
1250 if (src0) {
1251 reg = ir3_reg_create(sam, 0, IR3_REG_SSA);
1252 reg->wrmask = (1 << (src0->regs_count - 1)) - 1;
1253 reg->instr = src0;
1254 }
1255 if (src1) {
1256 reg = ir3_reg_create(sam, 0, IR3_REG_SSA);
1257 reg->instr = src1;
1258 reg->wrmask = (1 << (src1->regs_count - 1)) - 1;
1259 }
1260 sam->cat5.samp = samp;
1261 sam->cat5.tex = tex;
1262 sam->cat5.type = type;
1263
1264 return sam;
1265 }
1266
1267 /* cat6 instructions: */
1268 INSTR2(LDLV)
1269 INSTR2(LDG)
1270 INSTR2(LDL)
1271 INSTR3(STG)
1272 INSTR3(STL)
1273 INSTR3(LDGB)
1274 INSTR4(STGB)
1275 INSTR4(STIB)
1276 INSTR1(RESINFO)
1277 INSTR1(RESFMT)
1278 INSTR2(ATOMIC_ADD)
1279 INSTR2(ATOMIC_SUB)
1280 INSTR2(ATOMIC_XCHG)
1281 INSTR2(ATOMIC_INC)
1282 INSTR2(ATOMIC_DEC)
1283 INSTR2(ATOMIC_CMPXCHG)
1284 INSTR2(ATOMIC_MIN)
1285 INSTR2(ATOMIC_MAX)
1286 INSTR2(ATOMIC_AND)
1287 INSTR2(ATOMIC_OR)
1288 INSTR2(ATOMIC_XOR)
1289 INSTR4F(G, ATOMIC_ADD)
1290 INSTR4F(G, ATOMIC_SUB)
1291 INSTR4F(G, ATOMIC_XCHG)
1292 INSTR4F(G, ATOMIC_INC)
1293 INSTR4F(G, ATOMIC_DEC)
1294 INSTR4F(G, ATOMIC_CMPXCHG)
1295 INSTR4F(G, ATOMIC_MIN)
1296 INSTR4F(G, ATOMIC_MAX)
1297 INSTR4F(G, ATOMIC_AND)
1298 INSTR4F(G, ATOMIC_OR)
1299 INSTR4F(G, ATOMIC_XOR)
1300
1301 /* cat7 instructions: */
1302 INSTR0(BAR)
1303 INSTR0(FENCE)
1304
1305 /* ************************************************************************* */
1306 /* split this out or find some helper to use.. like main/bitset.h.. */
1307
1308 #include <string.h>
1309
1310 #define MAX_REG 256
1311
1312 typedef uint8_t regmask_t[2 * MAX_REG / 8];
1313
1314 static inline unsigned regmask_idx(struct ir3_register *reg)
1315 {
1316 unsigned num = (reg->flags & IR3_REG_RELATIV) ? reg->array.offset : reg->num;
1317 debug_assert(num < MAX_REG);
1318 if (reg->flags & IR3_REG_HALF)
1319 num += MAX_REG;
1320 return num;
1321 }
1322
1323 static inline void regmask_init(regmask_t *regmask)
1324 {
1325 memset(regmask, 0, sizeof(*regmask));
1326 }
1327
1328 static inline void regmask_set(regmask_t *regmask, struct ir3_register *reg)
1329 {
1330 unsigned idx = regmask_idx(reg);
1331 if (reg->flags & IR3_REG_RELATIV) {
1332 unsigned i;
1333 for (i = 0; i < reg->size; i++, idx++)
1334 (*regmask)[idx / 8] |= 1 << (idx % 8);
1335 } else {
1336 unsigned mask;
1337 for (mask = reg->wrmask; mask; mask >>= 1, idx++)
1338 if (mask & 1)
1339 (*regmask)[idx / 8] |= 1 << (idx % 8);
1340 }
1341 }
1342
1343 static inline void regmask_or(regmask_t *dst, regmask_t *a, regmask_t *b)
1344 {
1345 unsigned i;
1346 for (i = 0; i < ARRAY_SIZE(*dst); i++)
1347 (*dst)[i] = (*a)[i] | (*b)[i];
1348 }
1349
1350 /* set bits in a if not set in b, conceptually:
1351 * a |= (reg & ~b)
1352 */
1353 static inline void regmask_set_if_not(regmask_t *a,
1354 struct ir3_register *reg, regmask_t *b)
1355 {
1356 unsigned idx = regmask_idx(reg);
1357 if (reg->flags & IR3_REG_RELATIV) {
1358 unsigned i;
1359 for (i = 0; i < reg->size; i++, idx++)
1360 if (!((*b)[idx / 8] & (1 << (idx % 8))))
1361 (*a)[idx / 8] |= 1 << (idx % 8);
1362 } else {
1363 unsigned mask;
1364 for (mask = reg->wrmask; mask; mask >>= 1, idx++)
1365 if (mask & 1)
1366 if (!((*b)[idx / 8] & (1 << (idx % 8))))
1367 (*a)[idx / 8] |= 1 << (idx % 8);
1368 }
1369 }
1370
1371 static inline bool regmask_get(regmask_t *regmask,
1372 struct ir3_register *reg)
1373 {
1374 unsigned idx = regmask_idx(reg);
1375 if (reg->flags & IR3_REG_RELATIV) {
1376 unsigned i;
1377 for (i = 0; i < reg->size; i++, idx++)
1378 if ((*regmask)[idx / 8] & (1 << (idx % 8)))
1379 return true;
1380 } else {
1381 unsigned mask;
1382 for (mask = reg->wrmask; mask; mask >>= 1, idx++)
1383 if (mask & 1)
1384 if ((*regmask)[idx / 8] & (1 << (idx % 8)))
1385 return true;
1386 }
1387 return false;
1388 }
1389
1390 /* ************************************************************************* */
1391
1392 #endif /* IR3_H_ */