2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 #include "util/u_debug.h"
31 #include "util/list.h"
33 #include "instr-a3xx.h"
34 #include "disasm.h" /* TODO move 'enum shader_t' somewhere else.. */
36 /* low level intermediate representation of an adreno shader program */
40 struct ir3_instruction
;
46 uint16_t instrs_count
; /* expanded to account for rpt's */
47 /* NOTE: max_reg, etc, does not include registers not touched
48 * by the shader (ie. vertex fetched via VFD_DECODE but not
51 int8_t max_reg
; /* highest GPR # used by shader */
58 IR3_REG_CONST
= 0x001,
59 IR3_REG_IMMED
= 0x002,
61 IR3_REG_RELATIV
= 0x008,
63 /* Most instructions, it seems, can do float abs/neg but not
64 * integer. The CP pass needs to know what is intended (int or
65 * float) in order to do the right thing. For this reason the
66 * abs/neg flags are split out into float and int variants. In
67 * addition, .b (bitwise) operations, the negate is actually a
68 * bitwise not, so split that out into a new flag to make it
77 IR3_REG_POS_INF
= 0x800,
78 /* (ei) flag, end-input? Set on last bary, presumably to signal
79 * that the shader needs no more input:
82 /* meta-flags, for intermediate stages of IR, ie.
83 * before register assignment is done:
85 IR3_REG_SSA
= 0x2000, /* 'instr' is ptr to assigning instr */
86 IR3_REG_PHI_SRC
= 0x4000, /* phi src, regs[0]->instr points to phi */
91 * the component is in the low two bits of the reg #, so
92 * rN.x becomes: (N << 2) | x
103 /* for IR3_REG_SSA, src registers contain ptr back to
104 * assigning instruction.
106 struct ir3_instruction
*instr
;
109 /* used for cat5 instructions, but also for internal/IR level
110 * tracking of what registers are read/written by an instruction.
111 * wrmask may be a bad name since it is used to represent both
112 * src and dst that touch multiple adjacent registers.
115 /* for relative addressing, 32bits for array size is too small,
116 * but otoh we don't need to deal with disjoint sets, so instead
117 * use a simple size field (number of scalar components).
123 struct ir3_instruction
{
124 struct ir3_block
*block
;
128 /* (sy) flag is set on first instruction, and after sample
129 * instructions (probably just on RAW hazard).
131 IR3_INSTR_SY
= 0x001,
132 /* (ss) flag is set on first instruction, and first instruction
133 * to depend on the result of "long" instructions (RAW hazard):
135 * rcp, rsq, log2, exp2, sin, cos, sqrt
137 * It seems to synchronize until all in-flight instructions are
138 * completed, for example:
141 * add.f hr2.z, (neg)hr2.z, hc0.y
142 * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
145 * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
147 * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
148 * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
149 * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
151 * The last mul.f does not have (ss) set, presumably because the
152 * (ss) on the previous instruction does the job.
154 * The blob driver also seems to set it on WAR hazards, although
155 * not really clear if this is needed or just blob compiler being
156 * sloppy. So far I haven't found a case where removing the (ss)
157 * causes problems for WAR hazard, but I could just be getting
161 * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
164 IR3_INSTR_SS
= 0x002,
165 /* (jp) flag is set on jump targets:
167 IR3_INSTR_JP
= 0x004,
168 IR3_INSTR_UL
= 0x008,
169 IR3_INSTR_3D
= 0x010,
174 IR3_INSTR_S2EN
= 0x200,
175 /* meta-flags, for intermediate stages of IR, ie.
176 * before register assignment is done:
178 IR3_INSTR_MARK
= 0x1000,
185 struct ir3_register
**regs
;
191 struct ir3_block
*target
;
194 type_t src_type
, dst_type
;
215 /* for meta-instructions, just used to hold extra data
216 * before instruction scheduling, etc
219 int off
; /* component/offset */
225 /* used to temporarily hold reference to nir_phi_instr
226 * until we resolve the phi srcs
231 struct ir3_block
*block
;
235 /* transient values used during various algorithms: */
237 /* The instruction depth is the max dependency distance to output.
239 * You can also think of it as the "cost", if we did any sort of
240 * optimization for register footprint. Ie. a value that is just
241 * result of moving a const to a reg would have a low cost, so to
242 * it could make sense to duplicate the instruction at various
243 * points where the result is needed to reduce register footprint.
245 * DEPTH_UNUSED used to mark unused instructions after depth
248 #define DEPTH_UNUSED ~0
250 /* When we get to the RA stage, we no longer need depth, but
251 * we do need instruction's position/name:
259 /* Used during CP and RA stages. For fanin and shader inputs/
260 * outputs where we need a sequence of consecutive registers,
261 * keep track of each src instructions left (ie 'n-1') and right
262 * (ie 'n+1') neighbor. The front-end must insert enough mov's
263 * to ensure that each instruction has at most one left and at
264 * most one right neighbor. During the copy-propagation pass,
265 * we only remove mov's when we can preserve this constraint.
266 * And during the RA stage, we use the neighbor information to
267 * allocate a block of registers in one shot.
269 * TODO: maybe just add something like:
270 * struct ir3_instruction_ref {
271 * struct ir3_instruction *instr;
275 * Or can we get away without the refcnt stuff? It seems like
276 * it should be overkill.. the problem is if, potentially after
277 * already eliminating some mov's, if you have a single mov that
278 * needs to be grouped with it's neighbors in two different
279 * places (ex. shader output and a fanin).
282 struct ir3_instruction
*left
, *right
;
283 uint16_t left_cnt
, right_cnt
;
286 /* an instruction can reference at most one address register amongst
287 * it's src/dst registers. Beyond that, you need to insert mov's.
289 struct ir3_instruction
*address
;
291 /* in case of a instruction with relative dst instruction, we need to
292 * capture the dependency on the fanin for the previous values of
293 * the array elements. Since we don't know at compile time actually
294 * which array elements are written, this serves to preserve the
295 * unconditional write to array elements prior to the conditional
298 * TODO only cat1 can do indirect write.. we could maybe move this
299 * into instr->cat1.fanin (but would require the frontend to insert
302 struct ir3_instruction
*fanin
;
304 /* Entry in ir3_block's instruction list: */
305 struct list_head node
;
312 static inline struct ir3_instruction
*
313 ir3_neighbor_first(struct ir3_instruction
*instr
)
315 while (instr
->cp
.left
)
316 instr
= instr
->cp
.left
;
320 static inline int ir3_neighbor_count(struct ir3_instruction
*instr
)
324 debug_assert(!instr
->cp
.left
);
326 while (instr
->cp
.right
) {
328 instr
= instr
->cp
.right
;
334 struct ir3_heap_chunk
;
337 struct ir3_compiler
*compiler
;
339 unsigned ninputs
, noutputs
;
340 struct ir3_instruction
**inputs
;
341 struct ir3_instruction
**outputs
;
343 /* Track bary.f (and ldlv) instructions.. this is needed in
344 * scheduling to ensure that all varying fetches happen before
345 * any potential kill instructions. The hw gets grumpy if all
346 * threads in a group are killed before the last bary.f gets
347 * a chance to signal end of input (ei).
349 unsigned baryfs_count
, baryfs_sz
;
350 struct ir3_instruction
**baryfs
;
352 /* Track all indirect instructions (read and write). To avoid
353 * deadlock scenario where an address register gets scheduled,
354 * but other dependent src instructions cannot be scheduled due
355 * to dependency on a *different* address register value, the
356 * scheduler needs to ensure that all dependencies other than
357 * the instruction other than the address register are scheduled
358 * before the one that writes the address register. Having a
359 * convenient list of instructions that reference some address
360 * register simplifies this.
362 unsigned indirects_count
, indirects_sz
;
363 struct ir3_instruction
**indirects
;
364 /* and same for instructions that consume predicate register: */
365 unsigned predicates_count
, predicates_sz
;
366 struct ir3_instruction
**predicates
;
368 /* List of blocks: */
369 struct list_head block_list
;
372 struct ir3_heap_chunk
*chunk
;
375 typedef struct nir_block nir_block
;
378 struct list_head node
;
383 struct list_head instr_list
; /* list of ir3_instruction */
385 /* each block has either one or two successors.. in case of
386 * two successors, 'condition' decides which one to follow.
387 * A block preceding an if/else has two successors.
389 struct ir3_instruction
*condition
;
390 struct ir3_block
*successors
[2];
392 uint16_t start_ip
, end_ip
;
394 /* used for per-pass extra block data. Mainly used right
395 * now in RA step to track livein/liveout.
404 struct ir3
* ir3_create(struct ir3_compiler
*compiler
,
405 unsigned nin
, unsigned nout
);
406 void ir3_destroy(struct ir3
*shader
);
407 void * ir3_assemble(struct ir3
*shader
,
408 struct ir3_info
*info
, uint32_t gpu_id
);
409 void * ir3_alloc(struct ir3
*shader
, int sz
);
411 struct ir3_block
* ir3_block_create(struct ir3
*shader
);
413 struct ir3_instruction
* ir3_instr_create(struct ir3_block
*block
,
414 int category
, opc_t opc
);
415 struct ir3_instruction
* ir3_instr_create2(struct ir3_block
*block
,
416 int category
, opc_t opc
, int nreg
);
417 struct ir3_instruction
* ir3_instr_clone(struct ir3_instruction
*instr
);
418 const char *ir3_instr_name(struct ir3_instruction
*instr
);
420 struct ir3_register
* ir3_reg_create(struct ir3_instruction
*instr
,
423 static inline bool ir3_instr_check_mark(struct ir3_instruction
*instr
)
425 if (instr
->flags
& IR3_INSTR_MARK
)
426 return true; /* already visited */
427 instr
->flags
|= IR3_INSTR_MARK
;
431 void ir3_block_clear_mark(struct ir3_block
*block
);
432 void ir3_clear_mark(struct ir3
*shader
);
434 unsigned ir3_count_instructions(struct ir3
*ir
);
436 static inline int ir3_instr_regno(struct ir3_instruction
*instr
,
437 struct ir3_register
*reg
)
440 for (i
= 0; i
< instr
->regs_count
; i
++)
441 if (reg
== instr
->regs
[i
])
447 #define MAX_ARRAYS 16
455 static inline uint32_t regid(int num
, int comp
)
457 return (num
<< 2) | (comp
& 0x3);
460 static inline uint32_t reg_num(struct ir3_register
*reg
)
462 return reg
->num
>> 2;
465 static inline uint32_t reg_comp(struct ir3_register
*reg
)
467 return reg
->num
& 0x3;
470 static inline bool is_flow(struct ir3_instruction
*instr
)
472 return (instr
->category
== 0);
475 static inline bool is_kill(struct ir3_instruction
*instr
)
477 return is_flow(instr
) && (instr
->opc
== OPC_KILL
);
480 static inline bool is_nop(struct ir3_instruction
*instr
)
482 return is_flow(instr
) && (instr
->opc
== OPC_NOP
);
485 /* Is it a non-transformative (ie. not type changing) mov? This can
486 * also include absneg.s/absneg.f, which for the most part can be
487 * treated as a mov (single src argument).
489 static inline bool is_same_type_mov(struct ir3_instruction
*instr
)
491 struct ir3_register
*dst
= instr
->regs
[0];
493 /* mov's that write to a0.x or p0.x are special: */
494 if (dst
->num
== regid(REG_P0
, 0))
496 if (dst
->num
== regid(REG_A0
, 0))
499 if ((instr
->category
== 1) &&
500 (instr
->cat1
.src_type
== instr
->cat1
.dst_type
))
502 if ((instr
->category
== 2) && ((instr
->opc
== OPC_ABSNEG_F
) ||
503 (instr
->opc
== OPC_ABSNEG_S
)))
508 static inline bool is_alu(struct ir3_instruction
*instr
)
510 return (1 <= instr
->category
) && (instr
->category
<= 3);
513 static inline bool is_sfu(struct ir3_instruction
*instr
)
515 return (instr
->category
== 4);
518 static inline bool is_tex(struct ir3_instruction
*instr
)
520 return (instr
->category
== 5);
523 static inline bool is_mem(struct ir3_instruction
*instr
)
525 return (instr
->category
== 6);
529 is_store(struct ir3_instruction
*instr
)
532 /* these instructions, the "destination" register is
533 * actually a source, the address to store to.
535 switch (instr
->opc
) {
550 static inline bool is_input(struct ir3_instruction
*instr
)
552 /* in some cases, ldlv is used to fetch varying without
553 * interpolation.. fortunately inloc is the first src
554 * register in either case
556 if (is_mem(instr
) && (instr
->opc
== OPC_LDLV
))
558 return (instr
->category
== 2) && (instr
->opc
== OPC_BARY_F
);
561 static inline bool is_meta(struct ir3_instruction
*instr
)
563 /* TODO how should we count PHI (and maybe fan-in/out) which
564 * might actually contribute some instructions to the final
567 return (instr
->category
== -1);
570 static inline bool writes_addr(struct ir3_instruction
*instr
)
572 if (instr
->regs_count
> 0) {
573 struct ir3_register
*dst
= instr
->regs
[0];
574 return reg_num(dst
) == REG_A0
;
579 static inline bool writes_pred(struct ir3_instruction
*instr
)
581 if (instr
->regs_count
> 0) {
582 struct ir3_register
*dst
= instr
->regs
[0];
583 return reg_num(dst
) == REG_P0
;
588 /* returns defining instruction for reg */
589 /* TODO better name */
590 static inline struct ir3_instruction
*ssa(struct ir3_register
*reg
)
592 if (reg
->flags
& IR3_REG_SSA
)
597 static inline bool conflicts(struct ir3_instruction
*a
,
598 struct ir3_instruction
*b
)
600 return (a
&& b
) && (a
!= b
);
603 static inline bool reg_gpr(struct ir3_register
*r
)
605 if (r
->flags
& (IR3_REG_CONST
| IR3_REG_IMMED
))
607 if ((reg_num(r
) == REG_A0
) || (reg_num(r
) == REG_P0
))
612 static inline type_t
half_type(type_t type
)
615 case TYPE_F32
: return TYPE_F16
;
616 case TYPE_U32
: return TYPE_U16
;
617 case TYPE_S32
: return TYPE_S16
;
628 /* some cat2 instructions (ie. those which are not float) can embed an
631 static inline bool ir3_cat2_int(opc_t opc
)
672 /* map cat2 instruction to valid abs/neg flags: */
673 static inline unsigned ir3_cat2_absneg(opc_t opc
)
690 return IR3_REG_FABS
| IR3_REG_FNEG
;
711 return IR3_REG_SABS
| IR3_REG_SNEG
;
732 /* map cat3 instructions to valid abs/neg flags: */
733 static inline unsigned ir3_cat3_absneg(opc_t opc
)
752 /* neg *may* work on 3rd src.. */
762 #define array_insert(arr, val) do { \
763 if (arr ## _count == arr ## _sz) { \
764 arr ## _sz = MAX2(2 * arr ## _sz, 16); \
765 arr = realloc(arr, arr ## _sz * sizeof(arr[0])); \
767 arr[arr ##_count++] = val; \
770 /* iterator for an instructions's sources (reg), also returns src #: */
771 #define foreach_src_n(__srcreg, __n, __instr) \
772 if ((__instr)->regs_count) \
773 for (unsigned __cnt = (__instr)->regs_count - 1, __n = 0; __n < __cnt; __n++) \
774 if ((__srcreg = (__instr)->regs[__n + 1]))
776 /* iterator for an instructions's sources (reg): */
777 #define foreach_src(__srcreg, __instr) \
778 foreach_src_n(__srcreg, __i, __instr)
780 static inline unsigned __ssa_src_cnt(struct ir3_instruction
*instr
)
783 return instr
->regs_count
+ 2;
785 return instr
->regs_count
+ 1;
786 return instr
->regs_count
;
789 static inline struct ir3_instruction
* __ssa_src_n(struct ir3_instruction
*instr
, unsigned n
)
791 if (n
== (instr
->regs_count
+ 1))
793 if (n
== (instr
->regs_count
+ 0))
794 return instr
->address
;
795 return ssa(instr
->regs
[n
]);
798 #define __src_cnt(__instr) ((__instr)->address ? (__instr)->regs_count : (__instr)->regs_count - 1)
800 /* iterator for an instruction's SSA sources (instr), also returns src #: */
801 #define foreach_ssa_src_n(__srcinst, __n, __instr) \
802 if ((__instr)->regs_count) \
803 for (unsigned __cnt = __ssa_src_cnt(__instr) - 1, __n = 0; __n < __cnt; __n++) \
804 if ((__srcinst = __ssa_src_n(__instr, __n + 1)))
806 /* iterator for an instruction's SSA sources (instr): */
807 #define foreach_ssa_src(__srcinst, __instr) \
808 foreach_ssa_src_n(__srcinst, __i, __instr)
812 void ir3_print(struct ir3
*ir
);
813 void ir3_print_instr(struct ir3_instruction
*instr
);
815 /* depth calculation: */
816 int ir3_delayslots(struct ir3_instruction
*assigner
,
817 struct ir3_instruction
*consumer
, unsigned n
);
818 void ir3_insert_by_depth(struct ir3_instruction
*instr
, struct list_head
*list
);
819 void ir3_depth(struct ir3
*ir
);
821 /* copy-propagate: */
822 void ir3_cp(struct ir3
*ir
);
824 /* group neighbors and insert mov's to resolve conflicts: */
825 void ir3_group(struct ir3
*ir
);
828 int ir3_sched(struct ir3
*ir
);
830 /* register assignment: */
831 struct ir3_ra_reg_set
* ir3_ra_alloc_reg_set(void *memctx
);
832 int ir3_ra(struct ir3
*ir3
, enum shader_t type
,
833 bool frag_coord
, bool frag_face
);
836 void ir3_legalize(struct ir3
*ir
, bool *has_samp
, int *max_bary
);
838 /* ************************************************************************* */
839 /* instruction helpers */
841 static inline struct ir3_instruction
*
842 ir3_MOV(struct ir3_block
*block
, struct ir3_instruction
*src
, type_t type
)
844 struct ir3_instruction
*instr
=
845 ir3_instr_create(block
, 1, 0);
846 ir3_reg_create(instr
, 0, 0); /* dst */
847 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
848 instr
->cat1
.src_type
= type
;
849 instr
->cat1
.dst_type
= type
;
853 static inline struct ir3_instruction
*
854 ir3_COV(struct ir3_block
*block
, struct ir3_instruction
*src
,
855 type_t src_type
, type_t dst_type
)
857 struct ir3_instruction
*instr
=
858 ir3_instr_create(block
, 1, 0);
859 ir3_reg_create(instr
, 0, 0); /* dst */
860 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
861 instr
->cat1
.src_type
= src_type
;
862 instr
->cat1
.dst_type
= dst_type
;
866 static inline struct ir3_instruction
*
867 ir3_NOP(struct ir3_block
*block
)
869 return ir3_instr_create(block
, 0, OPC_NOP
);
872 #define INSTR0(CAT, name) \
873 static inline struct ir3_instruction * \
874 ir3_##name(struct ir3_block *block) \
876 struct ir3_instruction *instr = \
877 ir3_instr_create(block, CAT, OPC_##name); \
881 #define INSTR1(CAT, name) \
882 static inline struct ir3_instruction * \
883 ir3_##name(struct ir3_block *block, \
884 struct ir3_instruction *a, unsigned aflags) \
886 struct ir3_instruction *instr = \
887 ir3_instr_create(block, CAT, OPC_##name); \
888 ir3_reg_create(instr, 0, 0); /* dst */ \
889 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
893 #define INSTR2(CAT, name) \
894 static inline struct ir3_instruction * \
895 ir3_##name(struct ir3_block *block, \
896 struct ir3_instruction *a, unsigned aflags, \
897 struct ir3_instruction *b, unsigned bflags) \
899 struct ir3_instruction *instr = \
900 ir3_instr_create(block, CAT, OPC_##name); \
901 ir3_reg_create(instr, 0, 0); /* dst */ \
902 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
903 ir3_reg_create(instr, 0, IR3_REG_SSA | bflags)->instr = b; \
907 #define INSTR3(CAT, name) \
908 static inline struct ir3_instruction * \
909 ir3_##name(struct ir3_block *block, \
910 struct ir3_instruction *a, unsigned aflags, \
911 struct ir3_instruction *b, unsigned bflags, \
912 struct ir3_instruction *c, unsigned cflags) \
914 struct ir3_instruction *instr = \
915 ir3_instr_create(block, CAT, OPC_##name); \
916 ir3_reg_create(instr, 0, 0); /* dst */ \
917 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
918 ir3_reg_create(instr, 0, IR3_REG_SSA | bflags)->instr = b; \
919 ir3_reg_create(instr, 0, IR3_REG_SSA | cflags)->instr = c; \
923 /* cat0 instructions: */
929 /* cat2 instructions, most 2 src but some 1 src: */
977 /* cat3 instructions: */
995 /* cat4 instructions: */
1004 /* cat5 instructions: */
1008 static inline struct ir3_instruction
*
1009 ir3_SAM(struct ir3_block
*block
, opc_t opc
, type_t type
,
1010 unsigned wrmask
, unsigned flags
, unsigned samp
, unsigned tex
,
1011 struct ir3_instruction
*src0
, struct ir3_instruction
*src1
)
1013 struct ir3_instruction
*sam
;
1014 struct ir3_register
*reg
;
1016 sam
= ir3_instr_create(block
, 5, opc
);
1017 sam
->flags
|= flags
;
1018 ir3_reg_create(sam
, 0, 0)->wrmask
= wrmask
;
1020 reg
= ir3_reg_create(sam
, 0, IR3_REG_SSA
);
1021 reg
->wrmask
= (1 << (src0
->regs_count
- 1)) - 1;
1025 reg
= ir3_reg_create(sam
, 0, IR3_REG_SSA
);
1027 reg
->wrmask
= (1 << (src1
->regs_count
- 1)) - 1;
1029 sam
->cat5
.samp
= samp
;
1030 sam
->cat5
.tex
= tex
;
1031 sam
->cat5
.type
= type
;
1036 /* cat6 instructions: */
1040 /* ************************************************************************* */
1041 /* split this out or find some helper to use.. like main/bitset.h.. */
1047 typedef uint8_t regmask_t
[2 * MAX_REG
/ 8];
1049 static inline unsigned regmask_idx(struct ir3_register
*reg
)
1051 unsigned num
= reg
->num
;
1052 debug_assert(num
< MAX_REG
);
1053 if (reg
->flags
& IR3_REG_HALF
)
1058 static inline void regmask_init(regmask_t
*regmask
)
1060 memset(regmask
, 0, sizeof(*regmask
));
1063 static inline void regmask_set(regmask_t
*regmask
, struct ir3_register
*reg
)
1065 unsigned idx
= regmask_idx(reg
);
1066 if (reg
->flags
& IR3_REG_RELATIV
) {
1068 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1069 (*regmask
)[idx
/ 8] |= 1 << (idx
% 8);
1072 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1074 (*regmask
)[idx
/ 8] |= 1 << (idx
% 8);
1078 static inline void regmask_or(regmask_t
*dst
, regmask_t
*a
, regmask_t
*b
)
1081 for (i
= 0; i
< ARRAY_SIZE(*dst
); i
++)
1082 (*dst
)[i
] = (*a
)[i
] | (*b
)[i
];
1085 /* set bits in a if not set in b, conceptually:
1088 static inline void regmask_set_if_not(regmask_t
*a
,
1089 struct ir3_register
*reg
, regmask_t
*b
)
1091 unsigned idx
= regmask_idx(reg
);
1092 if (reg
->flags
& IR3_REG_RELATIV
) {
1094 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1095 if (!((*b
)[idx
/ 8] & (1 << (idx
% 8))))
1096 (*a
)[idx
/ 8] |= 1 << (idx
% 8);
1099 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1101 if (!((*b
)[idx
/ 8] & (1 << (idx
% 8))))
1102 (*a
)[idx
/ 8] |= 1 << (idx
% 8);
1106 static inline bool regmask_get(regmask_t
*regmask
,
1107 struct ir3_register
*reg
)
1109 unsigned idx
= regmask_idx(reg
);
1110 if (reg
->flags
& IR3_REG_RELATIV
) {
1112 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1113 if ((*regmask
)[idx
/ 8] & (1 << (idx
% 8)))
1117 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1119 if ((*regmask
)[idx
/ 8] & (1 << (idx
% 8)))
1125 /* ************************************************************************* */