2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 #include "util/u_debug.h"
32 #include "instr-a3xx.h"
33 #include "disasm.h" /* TODO move 'enum shader_t' somewhere else.. */
35 /* low level intermediate representation of an adreno shader program */
38 struct ir3_instruction
;
43 uint16_t instrs_count
; /* expanded to account for rpt's */
44 /* NOTE: max_reg, etc, does not include registers not touched
45 * by the shader (ie. vertex fetched via VFD_DECODE but not
48 int8_t max_reg
; /* highest GPR # used by shader */
55 IR3_REG_CONST
= 0x001,
56 IR3_REG_IMMED
= 0x002,
58 IR3_REG_RELATIV
= 0x008,
60 /* Most instructions, it seems, can do float abs/neg but not
61 * integer. The CP pass needs to know what is intended (int or
62 * float) in order to do the right thing. For this reason the
63 * abs/neg flags are split out into float and int variants. In
64 * addition, .b (bitwise) operations, the negate is actually a
65 * bitwise not, so split that out into a new flag to make it
74 IR3_REG_POS_INF
= 0x800,
75 /* (ei) flag, end-input? Set on last bary, presumably to signal
76 * that the shader needs no more input:
79 /* meta-flags, for intermediate stages of IR, ie.
80 * before register assignment is done:
82 IR3_REG_SSA
= 0x2000, /* 'instr' is ptr to assigning instr */
83 IR3_REG_IA
= 0x4000, /* meta-input dst is "assigned" */
84 IR3_REG_ADDR
= 0x8000, /* register is a0.x */
88 * the component is in the low two bits of the reg #, so
89 * rN.x becomes: (N << 2) | x
100 /* for IR3_REG_SSA, src registers contain ptr back to
101 * assigning instruction.
103 struct ir3_instruction
*instr
;
106 /* used for cat5 instructions, but also for internal/IR level
107 * tracking of what registers are read/written by an instruction.
108 * wrmask may be a bad name since it is used to represent both
109 * src and dst that touch multiple adjacent registers.
112 /* for relative addressing, 32bits for array size is too small,
113 * but otoh we don't need to deal with disjoint sets, so instead
114 * use a simple size field (number of scalar components).
120 struct ir3_instruction
{
121 struct ir3_block
*block
;
125 /* (sy) flag is set on first instruction, and after sample
126 * instructions (probably just on RAW hazard).
128 IR3_INSTR_SY
= 0x001,
129 /* (ss) flag is set on first instruction, and first instruction
130 * to depend on the result of "long" instructions (RAW hazard):
132 * rcp, rsq, log2, exp2, sin, cos, sqrt
134 * It seems to synchronize until all in-flight instructions are
135 * completed, for example:
138 * add.f hr2.z, (neg)hr2.z, hc0.y
139 * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
142 * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
144 * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
145 * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
146 * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
148 * The last mul.f does not have (ss) set, presumably because the
149 * (ss) on the previous instruction does the job.
151 * The blob driver also seems to set it on WAR hazards, although
152 * not really clear if this is needed or just blob compiler being
153 * sloppy. So far I haven't found a case where removing the (ss)
154 * causes problems for WAR hazard, but I could just be getting
158 * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
161 IR3_INSTR_SS
= 0x002,
162 /* (jp) flag is set on jump targets:
164 IR3_INSTR_JP
= 0x004,
165 IR3_INSTR_UL
= 0x008,
166 IR3_INSTR_3D
= 0x010,
171 IR3_INSTR_S2EN
= 0x200,
172 /* meta-flags, for intermediate stages of IR, ie.
173 * before register assignment is done:
175 IR3_INSTR_MARK
= 0x1000,
182 struct ir3_register
**regs
;
190 type_t src_type
, dst_type
;
211 /* for meta-instructions, just used to hold extra data
212 * before instruction scheduling, etc
215 int off
; /* component/offset */
221 struct ir3_block
*if_block
, *else_block
;
224 struct ir3_block
*block
;
227 /* XXX keep this as big as all other union members! */
231 /* transient values used during various algorithms: */
233 /* The instruction depth is the max dependency distance to output.
235 * You can also think of it as the "cost", if we did any sort of
236 * optimization for register footprint. Ie. a value that is just
237 * result of moving a const to a reg would have a low cost, so to
238 * it could make sense to duplicate the instruction at various
239 * points where the result is needed to reduce register footprint.
241 * DEPTH_UNUSED used to mark unused instructions after depth
244 #define DEPTH_UNUSED ~0
248 /* Used during CP and RA stages. For fanin and shader inputs/
249 * outputs where we need a sequence of consecutive registers,
250 * keep track of each src instructions left (ie 'n-1') and right
251 * (ie 'n+1') neighbor. The front-end must insert enough mov's
252 * to ensure that each instruction has at most one left and at
253 * most one right neighbor. During the copy-propagation pass,
254 * we only remove mov's when we can preserve this constraint.
255 * And during the RA stage, we use the neighbor information to
256 * allocate a block of registers in one shot.
258 * TODO: maybe just add something like:
259 * struct ir3_instruction_ref {
260 * struct ir3_instruction *instr;
264 * Or can we get away without the refcnt stuff? It seems like
265 * it should be overkill.. the problem is if, potentially after
266 * already eliminating some mov's, if you have a single mov that
267 * needs to be grouped with it's neighbors in two different
268 * places (ex. shader output and a fanin).
271 struct ir3_instruction
*left
, *right
;
272 uint16_t left_cnt
, right_cnt
;
275 /* an instruction can reference at most one address register amongst
276 * it's src/dst registers. Beyond that, you need to insert mov's.
278 struct ir3_instruction
*address
;
280 /* in case of a instruction with relative dst instruction, we need to
281 * capture the dependency on the fanin for the previous values of
282 * the array elements. Since we don't know at compile time actually
283 * which array elements are written, this serves to preserve the
284 * unconditional write to array elements prior to the conditional
287 * TODO only cat1 can do indirect write.. we could maybe move this
288 * into instr->cat1.fanin (but would require the frontend to insert
291 struct ir3_instruction
*fanin
;
293 struct ir3_instruction
*next
;
299 static inline struct ir3_instruction
*
300 ir3_neighbor_first(struct ir3_instruction
*instr
)
302 while (instr
->cp
.left
)
303 instr
= instr
->cp
.left
;
307 static inline int ir3_neighbor_count(struct ir3_instruction
*instr
)
311 debug_assert(!instr
->cp
.left
);
313 while (instr
->cp
.right
) {
315 instr
= instr
->cp
.right
;
321 struct ir3_heap_chunk
;
324 unsigned instrs_count
, instrs_sz
;
325 struct ir3_instruction
**instrs
;
327 /* Track bary.f (and ldlv) instructions.. this is needed in
328 * scheduling to ensure that all varying fetches happen before
329 * any potential kill instructions. The hw gets grumpy if all
330 * threads in a group are killed before the last bary.f gets
331 * a chance to signal end of input (ei).
333 unsigned baryfs_count
, baryfs_sz
;
334 struct ir3_instruction
**baryfs
;
336 /* Track all indirect instructions (read and write). To avoid
337 * deadlock scenario where an address register gets scheduled,
338 * but other dependent src instructions cannot be scheduled due
339 * to dependency on a *different* address register value, the
340 * scheduler needs to ensure that all dependencies other than
341 * the instruction other than the address register are scheduled
342 * before the one that writes the address register. Having a
343 * convenient list of instructions that reference some address
344 * register simplifies this.
346 unsigned indirects_count
, indirects_sz
;
347 struct ir3_instruction
**indirects
;
349 struct ir3_block
*block
;
351 struct ir3_heap_chunk
*chunk
;
356 unsigned ntemporaries
, ninputs
, noutputs
;
357 /* maps TGSI_FILE_TEMPORARY index back to the assigning instruction: */
358 struct ir3_instruction
**temporaries
;
359 struct ir3_instruction
**inputs
;
360 struct ir3_instruction
**outputs
;
361 /* only a single address register: */
362 struct ir3_instruction
*address
;
363 struct ir3_block
*parent
;
364 struct ir3_instruction
*head
;
367 struct ir3
* ir3_create(void);
368 void ir3_destroy(struct ir3
*shader
);
369 void * ir3_assemble(struct ir3
*shader
,
370 struct ir3_info
*info
, uint32_t gpu_id
);
371 void * ir3_alloc(struct ir3
*shader
, int sz
);
373 struct ir3_block
* ir3_block_create(struct ir3
*shader
,
374 unsigned ntmp
, unsigned nin
, unsigned nout
);
376 struct ir3_instruction
* ir3_instr_create(struct ir3_block
*block
,
377 int category
, opc_t opc
);
378 struct ir3_instruction
* ir3_instr_create2(struct ir3_block
*block
,
379 int category
, opc_t opc
, int nreg
);
380 struct ir3_instruction
* ir3_instr_clone(struct ir3_instruction
*instr
);
381 const char *ir3_instr_name(struct ir3_instruction
*instr
);
383 struct ir3_register
* ir3_reg_create(struct ir3_instruction
*instr
,
387 static inline bool ir3_instr_check_mark(struct ir3_instruction
*instr
)
389 if (instr
->flags
& IR3_INSTR_MARK
)
390 return true; /* already visited */
391 instr
->flags
|= IR3_INSTR_MARK
;
395 static inline void ir3_clear_mark(struct ir3
*shader
)
397 /* TODO would be nice to drop the instruction array.. for
398 * new compiler, _clear_mark() is all we use it for, and
399 * we could probably manage a linked list instead..
401 * Also, we'll probably want to mark instructions within
402 * a block, so tracking the list of instrs globally is
403 * unlikely to be what we want.
406 for (i
= 0; i
< shader
->instrs_count
; i
++) {
407 struct ir3_instruction
*instr
= shader
->instrs
[i
];
408 instr
->flags
&= ~IR3_INSTR_MARK
;
412 static inline int ir3_instr_regno(struct ir3_instruction
*instr
,
413 struct ir3_register
*reg
)
416 for (i
= 0; i
< instr
->regs_count
; i
++)
417 if (reg
== instr
->regs
[i
])
423 #define MAX_ARRAYS 16
431 static inline uint32_t regid(int num
, int comp
)
433 return (num
<< 2) | (comp
& 0x3);
436 static inline uint32_t reg_num(struct ir3_register
*reg
)
438 return reg
->num
>> 2;
441 static inline uint32_t reg_comp(struct ir3_register
*reg
)
443 return reg
->num
& 0x3;
446 static inline bool is_flow(struct ir3_instruction
*instr
)
448 return (instr
->category
== 0);
451 static inline bool is_kill(struct ir3_instruction
*instr
)
453 return is_flow(instr
) && (instr
->opc
== OPC_KILL
);
456 static inline bool is_nop(struct ir3_instruction
*instr
)
458 return is_flow(instr
) && (instr
->opc
== OPC_NOP
);
461 static inline bool is_alu(struct ir3_instruction
*instr
)
463 return (1 <= instr
->category
) && (instr
->category
<= 3);
466 static inline bool is_sfu(struct ir3_instruction
*instr
)
468 return (instr
->category
== 4);
471 static inline bool is_tex(struct ir3_instruction
*instr
)
473 return (instr
->category
== 5);
476 static inline bool is_mem(struct ir3_instruction
*instr
)
478 return (instr
->category
== 6);
481 static inline bool is_input(struct ir3_instruction
*instr
)
483 /* in some cases, ldlv is used to fetch varying without
484 * interpolation.. fortunately inloc is the first src
485 * register in either case
487 if (is_mem(instr
) && (instr
->opc
== OPC_LDLV
))
489 return (instr
->category
== 2) && (instr
->opc
== OPC_BARY_F
);
492 static inline bool is_meta(struct ir3_instruction
*instr
)
494 /* TODO how should we count PHI (and maybe fan-in/out) which
495 * might actually contribute some instructions to the final
498 return (instr
->category
== -1);
501 static inline bool writes_addr(struct ir3_instruction
*instr
)
503 if (instr
->regs_count
> 0) {
504 struct ir3_register
*dst
= instr
->regs
[0];
505 return !!(dst
->flags
& IR3_REG_ADDR
);
510 static inline bool writes_pred(struct ir3_instruction
*instr
)
512 if (instr
->regs_count
> 0) {
513 struct ir3_register
*dst
= instr
->regs
[0];
514 return reg_num(dst
) == REG_P0
;
519 /* returns defining instruction for reg */
520 /* TODO better name */
521 static inline struct ir3_instruction
*ssa(struct ir3_register
*reg
)
523 if (reg
->flags
& IR3_REG_SSA
)
528 static inline bool reg_gpr(struct ir3_register
*r
)
530 if (r
->flags
& (IR3_REG_CONST
| IR3_REG_IMMED
| IR3_REG_ADDR
))
532 if ((reg_num(r
) == REG_A0
) || (reg_num(r
) == REG_P0
))
537 /* some cat2 instructions (ie. those which are not float can embed an
540 static inline bool ir3_cat2_immed(opc_t opc
)
581 /* map cat2 instruction to valid abs/neg flags: */
582 static inline unsigned ir3_cat2_absneg(opc_t opc
)
599 return IR3_REG_FABS
| IR3_REG_FNEG
;
620 return IR3_REG_SABS
| IR3_REG_SNEG
;
641 /* map cat3 instructions to valid abs/neg flags: */
642 static inline unsigned ir3_cat3_absneg(opc_t opc
)
661 /* neg *may* work on 3rd src.. */
671 #define array_insert(arr, val) do { \
672 if (arr ## _count == arr ## _sz) { \
673 arr ## _sz = MAX2(2 * arr ## _sz, 16); \
674 arr = realloc(arr, arr ## _sz * sizeof(arr[0])); \
676 arr[arr ##_count++] = val; \
679 /* iterator for an instructions's sources (reg), also returns src #: */
680 #define foreach_src_n(__srcreg, __n, __instr) \
681 if ((__instr)->regs_count) \
682 for (unsigned __cnt = (__instr)->regs_count - 1, __n = 0; __n < __cnt; __n++) \
683 if ((__srcreg = (__instr)->regs[__n + 1]))
685 /* iterator for an instructions's sources (reg): */
686 #define foreach_src(__srcreg, __instr) \
687 foreach_src_n(__srcreg, __i, __instr)
689 static inline unsigned __ssa_src_cnt(struct ir3_instruction
*instr
)
692 return instr
->regs_count
+ 2;
694 return instr
->regs_count
+ 1;
695 return instr
->regs_count
;
698 static inline struct ir3_instruction
* __ssa_src_n(struct ir3_instruction
*instr
, unsigned n
)
700 if (n
== (instr
->regs_count
+ 1))
702 if (n
== (instr
->regs_count
+ 0))
703 return instr
->address
;
704 return ssa(instr
->regs
[n
]);
707 #define __src_cnt(__instr) ((__instr)->address ? (__instr)->regs_count : (__instr)->regs_count - 1)
709 /* iterator for an instruction's SSA sources (instr), also returns src #: */
710 #define foreach_ssa_src_n(__srcinst, __n, __instr) \
711 if ((__instr)->regs_count) \
712 for (unsigned __cnt = __ssa_src_cnt(__instr) - 1, __n = 0; __n < __cnt; __n++) \
713 if ((__srcinst = __ssa_src_n(__instr, __n + 1)))
715 /* iterator for an instruction's SSA sources (instr): */
716 #define foreach_ssa_src(__srcinst, __instr) \
717 foreach_ssa_src_n(__srcinst, __i, __instr)
722 void ir3_dump(struct ir3
*shader
, const char *name
,
723 struct ir3_block
*block
/* XXX maybe 'block' ptr should move to ir3? */,
725 void ir3_dump_instr_single(struct ir3_instruction
*instr
);
726 void ir3_dump_instr_list(struct ir3_instruction
*instr
);
728 /* flatten if/else: */
729 int ir3_block_flatten(struct ir3_block
*block
);
731 /* depth calculation: */
732 int ir3_delayslots(struct ir3_instruction
*assigner
,
733 struct ir3_instruction
*consumer
, unsigned n
);
734 void ir3_block_depth(struct ir3_block
*block
);
736 /* copy-propagate: */
737 void ir3_block_cp(struct ir3_block
*block
);
739 /* group neightbors and insert mov's to resolve conflicts: */
740 void ir3_block_group(struct ir3_block
*block
);
743 int ir3_block_sched(struct ir3_block
*block
);
745 /* register assignment: */
746 int ir3_block_ra(struct ir3_block
*block
, enum shader_t type
,
747 bool frag_coord
, bool frag_face
);
750 void ir3_block_legalize(struct ir3_block
*block
,
751 bool *has_samp
, int *max_bary
);
753 /* ************************************************************************* */
754 /* instruction helpers */
756 static inline struct ir3_instruction
*
757 ir3_MOV(struct ir3_block
*block
, struct ir3_instruction
*src
, type_t type
)
759 struct ir3_instruction
*instr
=
760 ir3_instr_create(block
, 1, 0);
761 ir3_reg_create(instr
, 0, 0); /* dst */
762 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
763 instr
->cat1
.src_type
= type
;
764 instr
->cat1
.dst_type
= type
;
768 static inline struct ir3_instruction
*
769 ir3_COV(struct ir3_block
*block
, struct ir3_instruction
*src
,
770 type_t src_type
, type_t dst_type
)
772 struct ir3_instruction
*instr
=
773 ir3_instr_create(block
, 1, 0);
774 ir3_reg_create(instr
, 0, 0); /* dst */
775 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
776 instr
->cat1
.src_type
= src_type
;
777 instr
->cat1
.dst_type
= dst_type
;
781 #define INSTR1(CAT, name) \
782 static inline struct ir3_instruction * \
783 ir3_##name(struct ir3_block *block, \
784 struct ir3_instruction *a, unsigned aflags) \
786 struct ir3_instruction *instr = \
787 ir3_instr_create(block, CAT, OPC_##name); \
788 ir3_reg_create(instr, 0, 0); /* dst */ \
789 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
793 #define INSTR2(CAT, name) \
794 static inline struct ir3_instruction * \
795 ir3_##name(struct ir3_block *block, \
796 struct ir3_instruction *a, unsigned aflags, \
797 struct ir3_instruction *b, unsigned bflags) \
799 struct ir3_instruction *instr = \
800 ir3_instr_create(block, CAT, OPC_##name); \
801 ir3_reg_create(instr, 0, 0); /* dst */ \
802 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
803 ir3_reg_create(instr, 0, IR3_REG_SSA | bflags)->instr = b; \
807 #define INSTR3(CAT, name) \
808 static inline struct ir3_instruction * \
809 ir3_##name(struct ir3_block *block, \
810 struct ir3_instruction *a, unsigned aflags, \
811 struct ir3_instruction *b, unsigned bflags, \
812 struct ir3_instruction *c, unsigned cflags) \
814 struct ir3_instruction *instr = \
815 ir3_instr_create(block, CAT, OPC_##name); \
816 ir3_reg_create(instr, 0, 0); /* dst */ \
817 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
818 ir3_reg_create(instr, 0, IR3_REG_SSA | bflags)->instr = b; \
819 ir3_reg_create(instr, 0, IR3_REG_SSA | cflags)->instr = c; \
823 /* cat0 instructions: */
826 /* cat2 instructions, most 2 src but some 1 src: */
874 /* cat3 instructions: */
892 /* cat4 instructions: */
901 /* cat5 instructions: */
905 /* cat6 instructions: */
908 /* ************************************************************************* */
909 /* split this out or find some helper to use.. like main/bitset.h.. */
915 typedef uint8_t regmask_t
[2 * MAX_REG
/ 8];
917 static inline unsigned regmask_idx(struct ir3_register
*reg
)
919 unsigned num
= reg
->num
;
920 debug_assert(num
< MAX_REG
);
921 if (reg
->flags
& IR3_REG_HALF
)
926 static inline void regmask_init(regmask_t
*regmask
)
928 memset(regmask
, 0, sizeof(*regmask
));
931 static inline void regmask_set(regmask_t
*regmask
, struct ir3_register
*reg
)
933 unsigned idx
= regmask_idx(reg
);
934 if (reg
->flags
& IR3_REG_RELATIV
) {
936 for (i
= 0; i
< reg
->size
; i
++, idx
++)
937 (*regmask
)[idx
/ 8] |= 1 << (idx
% 8);
940 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
942 (*regmask
)[idx
/ 8] |= 1 << (idx
% 8);
946 static inline void regmask_or(regmask_t
*dst
, regmask_t
*a
, regmask_t
*b
)
949 for (i
= 0; i
< ARRAY_SIZE(*dst
); i
++)
950 (*dst
)[i
] = (*a
)[i
] | (*b
)[i
];
953 /* set bits in a if not set in b, conceptually:
956 static inline void regmask_set_if_not(regmask_t
*a
,
957 struct ir3_register
*reg
, regmask_t
*b
)
959 unsigned idx
= regmask_idx(reg
);
960 if (reg
->flags
& IR3_REG_RELATIV
) {
962 for (i
= 0; i
< reg
->size
; i
++, idx
++)
963 if (!((*b
)[idx
/ 8] & (1 << (idx
% 8))))
964 (*a
)[idx
/ 8] |= 1 << (idx
% 8);
967 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
969 if (!((*b
)[idx
/ 8] & (1 << (idx
% 8))))
970 (*a
)[idx
/ 8] |= 1 << (idx
% 8);
974 static inline bool regmask_get(regmask_t
*regmask
,
975 struct ir3_register
*reg
)
977 unsigned idx
= regmask_idx(reg
);
978 if (reg
->flags
& IR3_REG_RELATIV
) {
980 for (i
= 0; i
< reg
->size
; i
++, idx
++)
981 if ((*regmask
)[idx
/ 8] & (1 << (idx
% 8)))
985 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
987 if ((*regmask
)[idx
/ 8] & (1 << (idx
% 8)))
993 /* ************************************************************************* */