src/gallium/drivers/freedreno/ir3/ir3.h

   1 /*
   2  * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #ifndef IR3_H_
  25 #define IR3_H_
  26
  27 #include <stdint.h>
  28 #include <stdbool.h>
  29
  30 #include "util/u_debug.h"
  31
  32 #include "instr-a3xx.h"
  33 #include "disasm.h"  /* TODO move 'enum shader_t' somewhere else.. */
  34
  35 /* low level intermediate representation of an adreno shader program */
  36
  37 struct ir3;
  38 struct ir3_instruction;
  39 struct ir3_block;
  40
  41 struct ir3 * fd_asm_parse(const char *src);
  42
  43 struct ir3_info {
  44         uint16_t sizedwords;
  45         uint16_t instrs_count;   /* expanded to account for rpt's */
  46         /* NOTE: max_reg, etc, does not include registers not touched
  47          * by the shader (ie. vertex fetched via VFD_DECODE but not
  48          * touched by shader)
  49          */
  50         int8_t   max_reg;   /* highest GPR # used by shader */
  51         int8_t   max_half_reg;
  52         int16_t  max_const;
  53 };
  54
  55 struct ir3_register {
  56         enum {
  57                 IR3_REG_CONST  = 0x001,
  58                 IR3_REG_IMMED  = 0x002,
  59                 IR3_REG_HALF   = 0x004,
  60                 IR3_REG_RELATIV= 0x008,
  61                 IR3_REG_R      = 0x010,
  62                 IR3_REG_NEGATE = 0x020,
  63                 IR3_REG_ABS    = 0x040,
  64                 IR3_REG_EVEN   = 0x080,
  65                 IR3_REG_POS_INF= 0x100,
  66                 /* (ei) flag, end-input?  Set on last bary, presumably to signal
  67                  * that the shader needs no more input:
  68                  */
  69                 IR3_REG_EI     = 0x200,
  70                 /* meta-flags, for intermediate stages of IR, ie.
  71                  * before register assignment is done:
  72                  */
  73                 IR3_REG_SSA    = 0x1000,   /* 'instr' is ptr to assigning instr */
  74                 IR3_REG_IA     = 0x2000,   /* meta-input dst is "assigned" */
  75                 IR3_REG_ADDR   = 0x4000,   /* register is a0.x */
  76         } flags;
  77         union {
  78                 /* normal registers:
  79                  * the component is in the low two bits of the reg #, so
  80                  * rN.x becomes: (N << 2) | x
  81                  */
  82                 int num;
  83                 /* immediate: */
  84                 int     iim_val;
  85                 float   fim_val;
  86                 /* relative: */
  87                 int offset;
  88                 /* for IR3_REG_SSA, src registers contain ptr back to
  89                  * assigning instruction.
  90                  */
  91                 struct ir3_instruction *instr;
  92         };
  93
  94         union {
  95                 /* used for cat5 instructions, but also for internal/IR level
  96                  * tracking of what registers are read/written by an instruction.
  97                  * wrmask may be a bad name since it is used to represent both
  98                  * src and dst that touch multiple adjacent registers.
  99                  */
 100                 unsigned wrmask;
 101                 /* for relative addressing, 32bits for array size is too small,
 102                  * but otoh we don't need to deal with disjoint sets, so instead
 103                  * use a simple size field (number of scalar components).
 104                  */
 105                 unsigned size;
 106         };
 107 };
 108
 109 struct ir3_instruction {
 110         struct ir3_block *block;
 111         int category;
 112         opc_t opc;
 113         enum {
 114                 /* (sy) flag is set on first instruction, and after sample
 115                  * instructions (probably just on RAW hazard).
 116                  */
 117                 IR3_INSTR_SY    = 0x001,
 118                 /* (ss) flag is set on first instruction, and first instruction
 119                  * to depend on the result of "long" instructions (RAW hazard):
 120                  *
 121                  *   rcp, rsq, log2, exp2, sin, cos, sqrt
 122                  *
 123                  * It seems to synchronize until all in-flight instructions are
 124                  * completed, for example:
 125                  *
 126                  *   rsq hr1.w, hr1.w
 127                  *   add.f hr2.z, (neg)hr2.z, hc0.y
 128                  *   mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
 129                  *   rsq hr2.x, hr2.x
 130                  *   (rpt1)nop
 131                  *   mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
 132                  *   nop
 133                  *   mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
 134                  *   (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
 135                  *   (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
 136                  *
 137                  * The last mul.f does not have (ss) set, presumably because the
 138                  * (ss) on the previous instruction does the job.
 139                  *
 140                  * The blob driver also seems to set it on WAR hazards, although
 141                  * not really clear if this is needed or just blob compiler being
 142                  * sloppy.  So far I haven't found a case where removing the (ss)
 143                  * causes problems for WAR hazard, but I could just be getting
 144                  * lucky:
 145                  *
 146                  *   rcp r1.y, r3.y
 147                  *   (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
 148                  *
 149                  */
 150                 IR3_INSTR_SS    = 0x002,
 151                 /* (jp) flag is set on jump targets:
 152                  */
 153                 IR3_INSTR_JP    = 0x004,
 154                 IR3_INSTR_UL    = 0x008,
 155                 IR3_INSTR_3D    = 0x010,
 156                 IR3_INSTR_A     = 0x020,
 157                 IR3_INSTR_O     = 0x040,
 158                 IR3_INSTR_P     = 0x080,
 159                 IR3_INSTR_S     = 0x100,
 160                 IR3_INSTR_S2EN  = 0x200,
 161                 /* meta-flags, for intermediate stages of IR, ie.
 162                  * before register assignment is done:
 163                  */
 164                 IR3_INSTR_MARK  = 0x1000,
 165         } flags;
 166         int repeat;
 167 #ifdef DEBUG
 168         unsigned regs_max;
 169 #endif
 170         unsigned regs_count;
 171         struct ir3_register **regs;
 172         union {
 173                 struct {
 174                         char inv;
 175                         char comp;
 176                         int  immed;
 177                 } cat0;
 178                 struct {
 179                         type_t src_type, dst_type;
 180                 } cat1;
 181                 struct {
 182                         enum {
 183                                 IR3_COND_LT = 0,
 184                                 IR3_COND_LE = 1,
 185                                 IR3_COND_GT = 2,
 186                                 IR3_COND_GE = 3,
 187                                 IR3_COND_EQ = 4,
 188                                 IR3_COND_NE = 5,
 189                         } condition;
 190                 } cat2;
 191                 struct {
 192                         unsigned samp, tex;
 193                         type_t type;
 194                 } cat5;
 195                 struct {
 196                         type_t type;
 197                         int offset;
 198                         int iim_val;
 199                 } cat6;
 200                 /* for meta-instructions, just used to hold extra data
 201                  * before instruction scheduling, etc
 202                  */
 203                 struct {
 204                         int off;              /* component/offset */
 205                 } fo;
 206                 struct {
 207                         struct ir3_block *if_block, *else_block;
 208                 } flow;
 209                 struct {
 210                         struct ir3_block *block;
 211                 } inout;
 212                 struct {
 213                         int off;              /* offset relative to addr reg */
 214                 } deref;
 215
 216                 /* XXX keep this as big as all other union members! */
 217                 uint32_t info[3];
 218         };
 219
 220         /* transient values used during various algorithms: */
 221         union {
 222                 /* The instruction depth is the max dependency distance to output.
 223                  *
 224                  * You can also think of it as the "cost", if we did any sort of
 225                  * optimization for register footprint.  Ie. a value that is  just
 226                  * result of moving a const to a reg would have a low cost,  so to
 227                  * it could make sense to duplicate the instruction at various
 228                  * points where the result is needed to reduce register footprint.
 229                  *
 230                  * DEPTH_UNUSED used to mark unused instructions after depth
 231                  * calculation pass.
 232                  */
 233 #define DEPTH_UNUSED  ~0
 234                 unsigned depth;
 235         };
 236
 237         /* Used during CP and RA stages.  For fanin and shader inputs/
 238          * outputs where we need a sequence of consecutive registers,
 239          * keep track of each src instructions left (ie 'n-1') and right
 240          * (ie 'n+1') neighbor.  The front-end must insert enough mov's
 241          * to ensure that each instruction has at most one left and at
 242          * most one right neighbor.  During the copy-propagation pass,
 243          * we only remove mov's when we can preserve this constraint.
 244          * And during the RA stage, we use the neighbor information to
 245          * allocate a block of registers in one shot.
 246          *
 247          * TODO: maybe just add something like:
 248          *   struct ir3_instruction_ref {
 249          *       struct ir3_instruction *instr;
 250          *       unsigned cnt;
 251          *   }
 252          *
 253          * Or can we get away without the refcnt stuff?  It seems like
 254          * it should be overkill..  the problem is if, potentially after
 255          * already eliminating some mov's, if you have a single mov that
 256          * needs to be grouped with it's neighbors in two different
 257          * places (ex. shader output and a fanin).
 258          */
 259         struct {
 260                 struct ir3_instruction *left, *right;
 261                 uint16_t left_cnt, right_cnt;
 262         } cp;
 263         struct ir3_instruction *next;
 264 #ifdef DEBUG
 265         uint32_t serialno;
 266 #endif
 267 };
 268
 269 static inline struct ir3_instruction *
 270 ir3_neighbor_first(struct ir3_instruction *instr)
 271 {
 272         while (instr->cp.left)
 273                 instr = instr->cp.left;
 274         return instr;
 275 }
 276
 277 static inline int ir3_neighbor_count(struct ir3_instruction *instr)
 278 {
 279         int num = 1;
 280
 281         debug_assert(!instr->cp.left);
 282
 283         while (instr->cp.right) {
 284                 num++;
 285                 instr = instr->cp.right;
 286         }
 287
 288         return num;
 289 }
 290
 291 struct ir3_heap_chunk;
 292
 293 struct ir3 {
 294         unsigned instrs_count, instrs_sz;
 295         struct ir3_instruction **instrs;
 296         unsigned baryfs_count, baryfs_sz;
 297         struct ir3_instruction **baryfs;
 298         struct ir3_block *block;
 299         unsigned heap_idx;
 300         struct ir3_heap_chunk *chunk;
 301 };
 302
 303 struct ir3_block {
 304         struct ir3 *shader;
 305         unsigned ntemporaries, ninputs, noutputs;
 306         /* maps TGSI_FILE_TEMPORARY index back to the assigning instruction: */
 307         struct ir3_instruction **temporaries;
 308         struct ir3_instruction **inputs;
 309         struct ir3_instruction **outputs;
 310         /* only a single address register: */
 311         struct ir3_instruction *address;
 312         struct ir3_block *parent;
 313         struct ir3_instruction *head;
 314 };
 315
 316 struct ir3 * ir3_create(void);
 317 void ir3_destroy(struct ir3 *shader);
 318 void * ir3_assemble(struct ir3 *shader,
 319                 struct ir3_info *info, uint32_t gpu_id);
 320 void * ir3_alloc(struct ir3 *shader, int sz);
 321
 322 struct ir3_block * ir3_block_create(struct ir3 *shader,
 323                 unsigned ntmp, unsigned nin, unsigned nout);
 324
 325 struct ir3_instruction * ir3_instr_create(struct ir3_block *block,
 326                 int category, opc_t opc);
 327 struct ir3_instruction * ir3_instr_create2(struct ir3_block *block,
 328                 int category, opc_t opc, int nreg);
 329 struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr);
 330 const char *ir3_instr_name(struct ir3_instruction *instr);
 331
 332 struct ir3_register * ir3_reg_create(struct ir3_instruction *instr,
 333                 int num, int flags);
 334
 335
 336 static inline bool ir3_instr_check_mark(struct ir3_instruction *instr)
 337 {
 338         if (instr->flags & IR3_INSTR_MARK)
 339                 return true;  /* already visited */
 340         instr->flags |= IR3_INSTR_MARK;
 341         return false;
 342 }
 343
 344 static inline void ir3_clear_mark(struct ir3 *shader)
 345 {
 346         /* TODO would be nice to drop the instruction array.. for
 347          * new compiler, _clear_mark() is all we use it for, and
 348          * we could probably manage a linked list instead..
 349          *
 350          * Also, we'll probably want to mark instructions within
 351          * a block, so tracking the list of instrs globally is
 352          * unlikely to be what we want.
 353          */
 354         unsigned i;
 355         for (i = 0; i < shader->instrs_count; i++) {
 356                 struct ir3_instruction *instr = shader->instrs[i];
 357                 instr->flags &= ~IR3_INSTR_MARK;
 358         }
 359 }
 360
 361 static inline int ir3_instr_regno(struct ir3_instruction *instr,
 362                 struct ir3_register *reg)
 363 {
 364         unsigned i;
 365         for (i = 0; i < instr->regs_count; i++)
 366                 if (reg == instr->regs[i])
 367                         return i;
 368         return -1;
 369 }
 370
 371
 372 /* comp:
 373  *   0 - x
 374  *   1 - y
 375  *   2 - z
 376  *   3 - w
 377  */
 378 static inline uint32_t regid(int num, int comp)
 379 {
 380         return (num << 2) | (comp & 0x3);
 381 }
 382
 383 static inline uint32_t reg_num(struct ir3_register *reg)
 384 {
 385         return reg->num >> 2;
 386 }
 387
 388 static inline uint32_t reg_comp(struct ir3_register *reg)
 389 {
 390         return reg->num & 0x3;
 391 }
 392
 393 static inline bool is_flow(struct ir3_instruction *instr)
 394 {
 395         return (instr->category == 0);
 396 }
 397
 398 static inline bool is_kill(struct ir3_instruction *instr)
 399 {
 400         return is_flow(instr) && (instr->opc == OPC_KILL);
 401 }
 402
 403 static inline bool is_nop(struct ir3_instruction *instr)
 404 {
 405         return is_flow(instr) && (instr->opc == OPC_NOP);
 406 }
 407
 408 static inline bool is_alu(struct ir3_instruction *instr)
 409 {
 410         return (1 <= instr->category) && (instr->category <= 3);
 411 }
 412
 413 static inline bool is_sfu(struct ir3_instruction *instr)
 414 {
 415         return (instr->category == 4);
 416 }
 417
 418 static inline bool is_tex(struct ir3_instruction *instr)
 419 {
 420         return (instr->category == 5);
 421 }
 422
 423 static inline bool is_input(struct ir3_instruction *instr)
 424 {
 425         return (instr->category == 2) && (instr->opc == OPC_BARY_F);
 426 }
 427
 428 static inline bool is_meta(struct ir3_instruction *instr)
 429 {
 430         /* TODO how should we count PHI (and maybe fan-in/out) which
 431          * might actually contribute some instructions to the final
 432          * result?
 433          */
 434         return (instr->category == -1);
 435 }
 436
 437 static inline bool is_addr(struct ir3_instruction *instr)
 438 {
 439         return is_meta(instr) && (instr->opc == OPC_META_DEREF);
 440 }
 441
 442 static inline bool writes_addr(struct ir3_instruction *instr)
 443 {
 444         if (instr->regs_count > 0) {
 445                 struct ir3_register *dst = instr->regs[0];
 446                 return !!(dst->flags & IR3_REG_ADDR);
 447         }
 448         return false;
 449 }
 450
 451 static inline bool writes_pred(struct ir3_instruction *instr)
 452 {
 453         if (instr->regs_count > 0) {
 454                 struct ir3_register *dst = instr->regs[0];
 455                 return reg_num(dst) == REG_P0;
 456         }
 457         return false;
 458 }
 459
 460 /* returns defining instruction for reg */
 461 /* TODO better name */
 462 static inline struct ir3_instruction *ssa(struct ir3_register *reg)
 463 {
 464         if (reg->flags & IR3_REG_SSA)
 465                 return reg->instr;
 466         return NULL;
 467 }
 468
 469 static inline bool reg_gpr(struct ir3_register *r)
 470 {
 471         if (r->flags & (IR3_REG_CONST | IR3_REG_IMMED | IR3_REG_ADDR))
 472                 return false;
 473         if ((reg_num(r) == REG_A0) || (reg_num(r) == REG_P0))
 474                 return false;
 475         return true;
 476 }
 477
 478 /* dump: */
 479 #include <stdio.h>
 480 void ir3_dump(struct ir3 *shader, const char *name,
 481                 struct ir3_block *block /* XXX maybe 'block' ptr should move to ir3? */,
 482                 FILE *f);
 483 void ir3_dump_instr_single(struct ir3_instruction *instr);
 484 void ir3_dump_instr_list(struct ir3_instruction *instr);
 485
 486 /* flatten if/else: */
 487 int ir3_block_flatten(struct ir3_block *block);
 488
 489 /* depth calculation: */
 490 int ir3_delayslots(struct ir3_instruction *assigner,
 491                 struct ir3_instruction *consumer, unsigned n);
 492 void ir3_block_depth(struct ir3_block *block);
 493
 494 /* copy-propagate: */
 495 void ir3_block_cp(struct ir3_block *block);
 496
 497 /* group neightbors and insert mov's to resolve conflicts: */
 498 void ir3_block_group(struct ir3_block *block);
 499
 500 /* scheduling: */
 501 int ir3_block_sched(struct ir3_block *block);
 502
 503 /* register assignment: */
 504 int ir3_block_ra(struct ir3_block *block, enum shader_t type,
 505                 bool frag_coord, bool frag_face);
 506
 507 /* legalize: */
 508 void ir3_block_legalize(struct ir3_block *block,
 509                 bool *has_samp, int *max_bary);
 510
 511 #ifndef ARRAY_SIZE
 512 #  define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
 513 #endif
 514
 515 /* ************************************************************************* */
 516 /* split this out or find some helper to use.. like main/bitset.h.. */
 517
 518 #include <string.h>
 519
 520 #define MAX_REG 256
 521
 522 typedef uint8_t regmask_t[2 * MAX_REG / 8];
 523
 524 static inline unsigned regmask_idx(struct ir3_register *reg)
 525 {
 526         unsigned num = reg->num;
 527         debug_assert(num < MAX_REG);
 528         if (reg->flags & IR3_REG_HALF)
 529                 num += MAX_REG;
 530         return num;
 531 }
 532
 533 static inline void regmask_init(regmask_t *regmask)
 534 {
 535         memset(regmask, 0, sizeof(*regmask));
 536 }
 537
 538 static inline void regmask_set(regmask_t *regmask, struct ir3_register *reg)
 539 {
 540         unsigned idx = regmask_idx(reg);
 541         if (reg->flags & IR3_REG_RELATIV) {
 542                 unsigned i;
 543                 for (i = 0; i < reg->size; i++, idx++)
 544                         (*regmask)[idx / 8] |= 1 << (idx % 8);
 545         } else {
 546                 unsigned mask;
 547                 for (mask = reg->wrmask; mask; mask >>= 1, idx++)
 548                         if (mask & 1)
 549                                 (*regmask)[idx / 8] |= 1 << (idx % 8);
 550         }
 551 }
 552
 553 static inline void regmask_or(regmask_t *dst, regmask_t *a, regmask_t *b)
 554 {
 555         unsigned i;
 556         for (i = 0; i < ARRAY_SIZE(*dst); i++)
 557                 (*dst)[i] = (*a)[i] | (*b)[i];
 558 }
 559
 560 /* set bits in a if not set in b, conceptually:
 561  *   a |= (reg & ~b)
 562  */
 563 static inline void regmask_set_if_not(regmask_t *a,
 564                 struct ir3_register *reg, regmask_t *b)
 565 {
 566         unsigned idx = regmask_idx(reg);
 567         if (reg->flags & IR3_REG_RELATIV) {
 568                 unsigned i;
 569                 for (i = 0; i < reg->size; i++, idx++)
 570                         if (!((*b)[idx / 8] & (1 << (idx % 8))))
 571                                 (*a)[idx / 8] |= 1 << (idx % 8);
 572         } else {
 573                 unsigned mask;
 574                 for (mask = reg->wrmask; mask; mask >>= 1, idx++)
 575                         if (mask & 1)
 576                                 if (!((*b)[idx / 8] & (1 << (idx % 8))))
 577                                         (*a)[idx / 8] |= 1 << (idx % 8);
 578         }
 579 }
 580
 581 static inline bool regmask_get(regmask_t *regmask,
 582                 struct ir3_register *reg)
 583 {
 584         unsigned idx = regmask_idx(reg);
 585         if (reg->flags & IR3_REG_RELATIV) {
 586                 unsigned i;
 587                 for (i = 0; i < reg->size; i++, idx++)
 588                         if ((*regmask)[idx / 8] & (1 << (idx % 8)))
 589                                 return true;
 590         } else {
 591                 unsigned mask;
 592                 for (mask = reg->wrmask; mask; mask >>= 1, idx++)
 593                         if (mask & 1)
 594                                 if ((*regmask)[idx / 8] & (1 << (idx % 8)))
 595                                         return true;
 596         }
 597         return false;
 598 }
 599
 600 /* ************************************************************************* */
 601
 602 #endif /* IR3_H_ */