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freedreno/ir3: make block/instruction serialno per-shader
[mesa.git] / src / gallium / drivers / freedreno / ir3 / ir3.h
1 /*
2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #ifndef IR3_H_
25 #define IR3_H_
26
27 #include <stdint.h>
28 #include <stdbool.h>
29
30 #include "util/u_debug.h"
31 #include "util/list.h"
32
33 #include "instr-a3xx.h"
34 #include "disasm.h" /* TODO move 'enum shader_t' somewhere else.. */
35
36 /* low level intermediate representation of an adreno shader program */
37
38 struct ir3_compiler;
39 struct ir3;
40 struct ir3_instruction;
41 struct ir3_block;
42
43 struct ir3_info {
44 uint32_t gpu_id;
45 uint16_t sizedwords;
46 uint16_t instrs_count; /* expanded to account for rpt's */
47 /* NOTE: max_reg, etc, does not include registers not touched
48 * by the shader (ie. vertex fetched via VFD_DECODE but not
49 * touched by shader)
50 */
51 int8_t max_reg; /* highest GPR # used by shader */
52 int8_t max_half_reg;
53 int16_t max_const;
54
55 /* number of sync bits: */
56 uint16_t ss, sy;
57 };
58
59 struct ir3_register {
60 enum {
61 IR3_REG_CONST = 0x001,
62 IR3_REG_IMMED = 0x002,
63 IR3_REG_HALF = 0x004,
64 /* high registers are used for some things in compute shaders,
65 * for example. Seems to be for things that are global to all
66 * threads in a wave, so possibly these are global/shared by
67 * all the threads in the wave?
68 */
69 IR3_REG_HIGH = 0x008,
70 IR3_REG_RELATIV= 0x010,
71 IR3_REG_R = 0x020,
72 /* Most instructions, it seems, can do float abs/neg but not
73 * integer. The CP pass needs to know what is intended (int or
74 * float) in order to do the right thing. For this reason the
75 * abs/neg flags are split out into float and int variants. In
76 * addition, .b (bitwise) operations, the negate is actually a
77 * bitwise not, so split that out into a new flag to make it
78 * more clear.
79 */
80 IR3_REG_FNEG = 0x040,
81 IR3_REG_FABS = 0x080,
82 IR3_REG_SNEG = 0x100,
83 IR3_REG_SABS = 0x200,
84 IR3_REG_BNOT = 0x400,
85 IR3_REG_EVEN = 0x800,
86 IR3_REG_POS_INF= 0x1000,
87 /* (ei) flag, end-input? Set on last bary, presumably to signal
88 * that the shader needs no more input:
89 */
90 IR3_REG_EI = 0x2000,
91 /* meta-flags, for intermediate stages of IR, ie.
92 * before register assignment is done:
93 */
94 IR3_REG_SSA = 0x4000, /* 'instr' is ptr to assigning instr */
95 IR3_REG_ARRAY = 0x8000,
96 IR3_REG_PHI_SRC= 0x10000, /* phi src, regs[0]->instr points to phi */
97
98 } flags;
99 union {
100 /* normal registers:
101 * the component is in the low two bits of the reg #, so
102 * rN.x becomes: (N << 2) | x
103 */
104 int num;
105 /* immediate: */
106 int32_t iim_val;
107 uint32_t uim_val;
108 float fim_val;
109 /* relative: */
110 struct {
111 uint16_t id;
112 int16_t offset;
113 } array;
114 };
115
116 /* For IR3_REG_SSA, src registers contain ptr back to assigning
117 * instruction.
118 *
119 * For IR3_REG_ARRAY, the pointer is back to the last dependent
120 * array access (although the net effect is the same, it points
121 * back to a previous instruction that we depend on).
122 */
123 struct ir3_instruction *instr;
124
125 union {
126 /* used for cat5 instructions, but also for internal/IR level
127 * tracking of what registers are read/written by an instruction.
128 * wrmask may be a bad name since it is used to represent both
129 * src and dst that touch multiple adjacent registers.
130 */
131 unsigned wrmask;
132 /* for relative addressing, 32bits for array size is too small,
133 * but otoh we don't need to deal with disjoint sets, so instead
134 * use a simple size field (number of scalar components).
135 */
136 unsigned size;
137 };
138 };
139
140 /*
141 * Stupid/simple growable array implementation:
142 */
143 #define DECLARE_ARRAY(type, name) \
144 unsigned name ## _count, name ## _sz; \
145 type * name;
146
147 #define array_insert(ctx, arr, val) do { \
148 if (arr ## _count == arr ## _sz) { \
149 arr ## _sz = MAX2(2 * arr ## _sz, 16); \
150 arr = reralloc_size(ctx, arr, arr ## _sz * sizeof(arr[0])); \
151 } \
152 arr[arr ##_count++] = val; \
153 } while (0)
154
155 struct ir3_instruction {
156 struct ir3_block *block;
157 opc_t opc;
158 enum {
159 /* (sy) flag is set on first instruction, and after sample
160 * instructions (probably just on RAW hazard).
161 */
162 IR3_INSTR_SY = 0x001,
163 /* (ss) flag is set on first instruction, and first instruction
164 * to depend on the result of "long" instructions (RAW hazard):
165 *
166 * rcp, rsq, log2, exp2, sin, cos, sqrt
167 *
168 * It seems to synchronize until all in-flight instructions are
169 * completed, for example:
170 *
171 * rsq hr1.w, hr1.w
172 * add.f hr2.z, (neg)hr2.z, hc0.y
173 * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
174 * rsq hr2.x, hr2.x
175 * (rpt1)nop
176 * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
177 * nop
178 * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
179 * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
180 * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
181 *
182 * The last mul.f does not have (ss) set, presumably because the
183 * (ss) on the previous instruction does the job.
184 *
185 * The blob driver also seems to set it on WAR hazards, although
186 * not really clear if this is needed or just blob compiler being
187 * sloppy. So far I haven't found a case where removing the (ss)
188 * causes problems for WAR hazard, but I could just be getting
189 * lucky:
190 *
191 * rcp r1.y, r3.y
192 * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
193 *
194 */
195 IR3_INSTR_SS = 0x002,
196 /* (jp) flag is set on jump targets:
197 */
198 IR3_INSTR_JP = 0x004,
199 IR3_INSTR_UL = 0x008,
200 IR3_INSTR_3D = 0x010,
201 IR3_INSTR_A = 0x020,
202 IR3_INSTR_O = 0x040,
203 IR3_INSTR_P = 0x080,
204 IR3_INSTR_S = 0x100,
205 IR3_INSTR_S2EN = 0x200,
206 IR3_INSTR_G = 0x400,
207 IR3_INSTR_SAT = 0x800,
208 /* meta-flags, for intermediate stages of IR, ie.
209 * before register assignment is done:
210 */
211 IR3_INSTR_MARK = 0x1000,
212 IR3_INSTR_UNUSED= 0x2000,
213 } flags;
214 int repeat;
215 #ifdef DEBUG
216 unsigned regs_max;
217 #endif
218 unsigned regs_count;
219 struct ir3_register **regs;
220 union {
221 struct {
222 char inv;
223 char comp;
224 int immed;
225 struct ir3_block *target;
226 } cat0;
227 struct {
228 type_t src_type, dst_type;
229 } cat1;
230 struct {
231 enum {
232 IR3_COND_LT = 0,
233 IR3_COND_LE = 1,
234 IR3_COND_GT = 2,
235 IR3_COND_GE = 3,
236 IR3_COND_EQ = 4,
237 IR3_COND_NE = 5,
238 } condition;
239 } cat2;
240 struct {
241 unsigned samp, tex;
242 type_t type;
243 } cat5;
244 struct {
245 type_t type;
246 int src_offset;
247 int dst_offset;
248 int iim_val : 3; /* for ldgb/stgb, # of components */
249 int d : 3;
250 bool typed : 1;
251 } cat6;
252 struct {
253 unsigned w : 1; /* write */
254 unsigned r : 1; /* read */
255 unsigned l : 1; /* local */
256 unsigned g : 1; /* global */
257 } cat7;
258 /* for meta-instructions, just used to hold extra data
259 * before instruction scheduling, etc
260 */
261 struct {
262 int off; /* component/offset */
263 } fo;
264 struct {
265 /* used to temporarily hold reference to nir_phi_instr
266 * until we resolve the phi srcs
267 */
268 void *nphi;
269 } phi;
270 struct {
271 struct ir3_block *block;
272 } inout;
273 };
274
275 /* transient values used during various algorithms: */
276 union {
277 /* The instruction depth is the max dependency distance to output.
278 *
279 * You can also think of it as the "cost", if we did any sort of
280 * optimization for register footprint. Ie. a value that is just
281 * result of moving a const to a reg would have a low cost, so to
282 * it could make sense to duplicate the instruction at various
283 * points where the result is needed to reduce register footprint.
284 */
285 unsigned depth;
286 /* When we get to the RA stage, we no longer need depth, but
287 * we do need instruction's position/name:
288 */
289 struct {
290 uint16_t ip;
291 uint16_t name;
292 };
293 };
294
295 /* used for per-pass extra instruction data.
296 */
297 void *data;
298
299 /* Used during CP and RA stages. For fanin and shader inputs/
300 * outputs where we need a sequence of consecutive registers,
301 * keep track of each src instructions left (ie 'n-1') and right
302 * (ie 'n+1') neighbor. The front-end must insert enough mov's
303 * to ensure that each instruction has at most one left and at
304 * most one right neighbor. During the copy-propagation pass,
305 * we only remove mov's when we can preserve this constraint.
306 * And during the RA stage, we use the neighbor information to
307 * allocate a block of registers in one shot.
308 *
309 * TODO: maybe just add something like:
310 * struct ir3_instruction_ref {
311 * struct ir3_instruction *instr;
312 * unsigned cnt;
313 * }
314 *
315 * Or can we get away without the refcnt stuff? It seems like
316 * it should be overkill.. the problem is if, potentially after
317 * already eliminating some mov's, if you have a single mov that
318 * needs to be grouped with it's neighbors in two different
319 * places (ex. shader output and a fanin).
320 */
321 struct {
322 struct ir3_instruction *left, *right;
323 uint16_t left_cnt, right_cnt;
324 } cp;
325
326 /* an instruction can reference at most one address register amongst
327 * it's src/dst registers. Beyond that, you need to insert mov's.
328 *
329 * NOTE: do not write this directly, use ir3_instr_set_address()
330 */
331 struct ir3_instruction *address;
332
333 /* Tracking for additional dependent instructions. Used to handle
334 * barriers, WAR hazards for arrays/SSBOs/etc.
335 */
336 DECLARE_ARRAY(struct ir3_instruction *, deps);
337
338 /*
339 * From PoV of instruction scheduling, not execution (ie. ignores global/
340 * local distinction):
341 * shared image atomic SSBO everything
342 * barrier()/ - R/W R/W R/W R/W X
343 * groupMemoryBarrier()
344 * memoryBarrier() - R/W R/W
345 * (but only images declared coherent?)
346 * memoryBarrierAtomic() - R/W
347 * memoryBarrierBuffer() - R/W
348 * memoryBarrierImage() - R/W
349 * memoryBarrierShared() - R/W
350 *
351 * TODO I think for SSBO/image/shared, in cases where we can determine
352 * which variable is accessed, we don't need to care about accesses to
353 * different variables (unless declared coherent??)
354 */
355 enum {
356 IR3_BARRIER_EVERYTHING = 1 << 0,
357 IR3_BARRIER_SHARED_R = 1 << 1,
358 IR3_BARRIER_SHARED_W = 1 << 2,
359 IR3_BARRIER_IMAGE_R = 1 << 3,
360 IR3_BARRIER_IMAGE_W = 1 << 4,
361 IR3_BARRIER_BUFFER_R = 1 << 5,
362 IR3_BARRIER_BUFFER_W = 1 << 6,
363 IR3_BARRIER_ARRAY_R = 1 << 7,
364 IR3_BARRIER_ARRAY_W = 1 << 8,
365 } barrier_class, barrier_conflict;
366
367 /* Entry in ir3_block's instruction list: */
368 struct list_head node;
369
370 #ifdef DEBUG
371 uint32_t serialno;
372 #endif
373 };
374
375 static inline struct ir3_instruction *
376 ir3_neighbor_first(struct ir3_instruction *instr)
377 {
378 int cnt = 0;
379 while (instr->cp.left) {
380 instr = instr->cp.left;
381 if (++cnt > 0xffff) {
382 debug_assert(0);
383 break;
384 }
385 }
386 return instr;
387 }
388
389 static inline int ir3_neighbor_count(struct ir3_instruction *instr)
390 {
391 int num = 1;
392
393 debug_assert(!instr->cp.left);
394
395 while (instr->cp.right) {
396 num++;
397 instr = instr->cp.right;
398 if (num > 0xffff) {
399 debug_assert(0);
400 break;
401 }
402 }
403
404 return num;
405 }
406
407 struct ir3 {
408 struct ir3_compiler *compiler;
409
410 unsigned ninputs, noutputs;
411 struct ir3_instruction **inputs;
412 struct ir3_instruction **outputs;
413
414 /* Track bary.f (and ldlv) instructions.. this is needed in
415 * scheduling to ensure that all varying fetches happen before
416 * any potential kill instructions. The hw gets grumpy if all
417 * threads in a group are killed before the last bary.f gets
418 * a chance to signal end of input (ei).
419 */
420 DECLARE_ARRAY(struct ir3_instruction *, baryfs);
421
422 /* Track all indirect instructions (read and write). To avoid
423 * deadlock scenario where an address register gets scheduled,
424 * but other dependent src instructions cannot be scheduled due
425 * to dependency on a *different* address register value, the
426 * scheduler needs to ensure that all dependencies other than
427 * the instruction other than the address register are scheduled
428 * before the one that writes the address register. Having a
429 * convenient list of instructions that reference some address
430 * register simplifies this.
431 */
432 DECLARE_ARRAY(struct ir3_instruction *, indirects);
433
434 /* and same for instructions that consume predicate register: */
435 DECLARE_ARRAY(struct ir3_instruction *, predicates);
436
437 /* Track texture sample instructions which need texture state
438 * patched in (for astc-srgb workaround):
439 */
440 DECLARE_ARRAY(struct ir3_instruction *, astc_srgb);
441
442 /* List of blocks: */
443 struct list_head block_list;
444
445 /* List of ir3_array's: */
446 struct list_head array_list;
447
448 #ifdef DEBUG
449 unsigned block_count, instr_count;
450 #endif
451 };
452
453 typedef struct nir_register nir_register;
454
455 struct ir3_array {
456 struct list_head node;
457 unsigned length;
458 unsigned id;
459
460 nir_register *r;
461
462 /* To avoid array write's from getting DCE'd, keep track of the
463 * most recent write. Any array access depends on the most
464 * recent write. This way, nothing depends on writes after the
465 * last read. But all the writes that happen before that have
466 * something depending on them
467 */
468 struct ir3_instruction *last_write;
469
470 /* extra stuff used in RA pass: */
471 unsigned base; /* base vreg name */
472 unsigned reg; /* base physical reg */
473 uint16_t start_ip, end_ip;
474 };
475
476 struct ir3_array * ir3_lookup_array(struct ir3 *ir, unsigned id);
477
478 typedef struct nir_block nir_block;
479
480 struct ir3_block {
481 struct list_head node;
482 struct ir3 *shader;
483
484 nir_block *nblock;
485
486 struct list_head instr_list; /* list of ir3_instruction */
487
488 /* each block has either one or two successors.. in case of
489 * two successors, 'condition' decides which one to follow.
490 * A block preceding an if/else has two successors.
491 */
492 struct ir3_instruction *condition;
493 struct ir3_block *successors[2];
494
495 uint16_t start_ip, end_ip;
496
497 /* Track instructions which do not write a register but other-
498 * wise must not be discarded (such as kill, stg, etc)
499 */
500 DECLARE_ARRAY(struct ir3_instruction *, keeps);
501
502 /* used for per-pass extra block data. Mainly used right
503 * now in RA step to track livein/liveout.
504 */
505 void *data;
506
507 #ifdef DEBUG
508 uint32_t serialno;
509 #endif
510 };
511
512 static inline uint32_t
513 block_id(struct ir3_block *block)
514 {
515 #ifdef DEBUG
516 return block->serialno;
517 #else
518 return (uint32_t)(unsigned long)block;
519 #endif
520 }
521
522 struct ir3 * ir3_create(struct ir3_compiler *compiler,
523 unsigned nin, unsigned nout);
524 void ir3_destroy(struct ir3 *shader);
525 void * ir3_assemble(struct ir3 *shader,
526 struct ir3_info *info, uint32_t gpu_id);
527 void * ir3_alloc(struct ir3 *shader, int sz);
528
529 struct ir3_block * ir3_block_create(struct ir3 *shader);
530
531 struct ir3_instruction * ir3_instr_create(struct ir3_block *block, opc_t opc);
532 struct ir3_instruction * ir3_instr_create2(struct ir3_block *block,
533 opc_t opc, int nreg);
534 struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr);
535 void ir3_instr_add_dep(struct ir3_instruction *instr, struct ir3_instruction *dep);
536 const char *ir3_instr_name(struct ir3_instruction *instr);
537
538 struct ir3_register * ir3_reg_create(struct ir3_instruction *instr,
539 int num, int flags);
540 struct ir3_register * ir3_reg_clone(struct ir3 *shader,
541 struct ir3_register *reg);
542
543 void ir3_instr_set_address(struct ir3_instruction *instr,
544 struct ir3_instruction *addr);
545
546 static inline bool ir3_instr_check_mark(struct ir3_instruction *instr)
547 {
548 if (instr->flags & IR3_INSTR_MARK)
549 return true; /* already visited */
550 instr->flags |= IR3_INSTR_MARK;
551 return false;
552 }
553
554 void ir3_block_clear_mark(struct ir3_block *block);
555 void ir3_clear_mark(struct ir3 *shader);
556
557 unsigned ir3_count_instructions(struct ir3 *ir);
558
559 static inline int ir3_instr_regno(struct ir3_instruction *instr,
560 struct ir3_register *reg)
561 {
562 unsigned i;
563 for (i = 0; i < instr->regs_count; i++)
564 if (reg == instr->regs[i])
565 return i;
566 return -1;
567 }
568
569
570 #define MAX_ARRAYS 16
571
572 /* comp:
573 * 0 - x
574 * 1 - y
575 * 2 - z
576 * 3 - w
577 */
578 static inline uint32_t regid(int num, int comp)
579 {
580 return (num << 2) | (comp & 0x3);
581 }
582
583 static inline uint32_t reg_num(struct ir3_register *reg)
584 {
585 return reg->num >> 2;
586 }
587
588 static inline uint32_t reg_comp(struct ir3_register *reg)
589 {
590 return reg->num & 0x3;
591 }
592
593 static inline bool is_flow(struct ir3_instruction *instr)
594 {
595 return (opc_cat(instr->opc) == 0);
596 }
597
598 static inline bool is_kill(struct ir3_instruction *instr)
599 {
600 return instr->opc == OPC_KILL;
601 }
602
603 static inline bool is_nop(struct ir3_instruction *instr)
604 {
605 return instr->opc == OPC_NOP;
606 }
607
608 /* Is it a non-transformative (ie. not type changing) mov? This can
609 * also include absneg.s/absneg.f, which for the most part can be
610 * treated as a mov (single src argument).
611 */
612 static inline bool is_same_type_mov(struct ir3_instruction *instr)
613 {
614 struct ir3_register *dst;
615
616 switch (instr->opc) {
617 case OPC_MOV:
618 if (instr->cat1.src_type != instr->cat1.dst_type)
619 return false;
620 break;
621 case OPC_ABSNEG_F:
622 case OPC_ABSNEG_S:
623 if (instr->flags & IR3_INSTR_SAT)
624 return false;
625 break;
626 default:
627 return false;
628 }
629
630 dst = instr->regs[0];
631
632 /* mov's that write to a0.x or p0.x are special: */
633 if (dst->num == regid(REG_P0, 0))
634 return false;
635 if (dst->num == regid(REG_A0, 0))
636 return false;
637
638 if (dst->flags & (IR3_REG_RELATIV | IR3_REG_ARRAY))
639 return false;
640
641 return true;
642 }
643
644 static inline bool is_alu(struct ir3_instruction *instr)
645 {
646 return (1 <= opc_cat(instr->opc)) && (opc_cat(instr->opc) <= 3);
647 }
648
649 static inline bool is_sfu(struct ir3_instruction *instr)
650 {
651 return (opc_cat(instr->opc) == 4);
652 }
653
654 static inline bool is_tex(struct ir3_instruction *instr)
655 {
656 return (opc_cat(instr->opc) == 5);
657 }
658
659 static inline bool is_mem(struct ir3_instruction *instr)
660 {
661 return (opc_cat(instr->opc) == 6);
662 }
663
664 static inline bool is_barrier(struct ir3_instruction *instr)
665 {
666 return (opc_cat(instr->opc) == 7);
667 }
668
669 static inline bool
670 is_store(struct ir3_instruction *instr)
671 {
672 /* these instructions, the "destination" register is
673 * actually a source, the address to store to.
674 */
675 switch (instr->opc) {
676 case OPC_STG:
677 case OPC_STGB:
678 case OPC_STIB:
679 case OPC_STP:
680 case OPC_STL:
681 case OPC_STLW:
682 case OPC_L2G:
683 case OPC_G2L:
684 return true;
685 default:
686 return false;
687 }
688 }
689
690 static inline bool is_load(struct ir3_instruction *instr)
691 {
692 switch (instr->opc) {
693 case OPC_LDG:
694 case OPC_LDGB:
695 case OPC_LDL:
696 case OPC_LDP:
697 case OPC_L2G:
698 case OPC_LDLW:
699 case OPC_LDC:
700 case OPC_LDLV:
701 /* probably some others too.. */
702 return true;
703 default:
704 return false;
705 }
706 }
707
708 static inline bool is_input(struct ir3_instruction *instr)
709 {
710 /* in some cases, ldlv is used to fetch varying without
711 * interpolation.. fortunately inloc is the first src
712 * register in either case
713 */
714 switch (instr->opc) {
715 case OPC_LDLV:
716 case OPC_BARY_F:
717 return true;
718 default:
719 return false;
720 }
721 }
722
723 static inline bool is_bool(struct ir3_instruction *instr)
724 {
725 switch (instr->opc) {
726 case OPC_CMPS_F:
727 case OPC_CMPS_S:
728 case OPC_CMPS_U:
729 return true;
730 default:
731 return false;
732 }
733 }
734
735 static inline bool is_meta(struct ir3_instruction *instr)
736 {
737 /* TODO how should we count PHI (and maybe fan-in/out) which
738 * might actually contribute some instructions to the final
739 * result?
740 */
741 return (opc_cat(instr->opc) == -1);
742 }
743
744 static inline bool writes_addr(struct ir3_instruction *instr)
745 {
746 if (instr->regs_count > 0) {
747 struct ir3_register *dst = instr->regs[0];
748 return reg_num(dst) == REG_A0;
749 }
750 return false;
751 }
752
753 static inline bool writes_pred(struct ir3_instruction *instr)
754 {
755 if (instr->regs_count > 0) {
756 struct ir3_register *dst = instr->regs[0];
757 return reg_num(dst) == REG_P0;
758 }
759 return false;
760 }
761
762 /* returns defining instruction for reg */
763 /* TODO better name */
764 static inline struct ir3_instruction *ssa(struct ir3_register *reg)
765 {
766 if (reg->flags & (IR3_REG_SSA | IR3_REG_ARRAY)) {
767 debug_assert(!(reg->instr && (reg->instr->flags & IR3_INSTR_UNUSED)));
768 return reg->instr;
769 }
770 return NULL;
771 }
772
773 static inline bool conflicts(struct ir3_instruction *a,
774 struct ir3_instruction *b)
775 {
776 return (a && b) && (a != b);
777 }
778
779 static inline bool reg_gpr(struct ir3_register *r)
780 {
781 if (r->flags & (IR3_REG_CONST | IR3_REG_IMMED))
782 return false;
783 if ((reg_num(r) == REG_A0) || (reg_num(r) == REG_P0))
784 return false;
785 return true;
786 }
787
788 static inline type_t half_type(type_t type)
789 {
790 switch (type) {
791 case TYPE_F32: return TYPE_F16;
792 case TYPE_U32: return TYPE_U16;
793 case TYPE_S32: return TYPE_S16;
794 case TYPE_F16:
795 case TYPE_U16:
796 case TYPE_S16:
797 return type;
798 default:
799 assert(0);
800 return ~0;
801 }
802 }
803
804 /* some cat2 instructions (ie. those which are not float) can embed an
805 * immediate:
806 */
807 static inline bool ir3_cat2_int(opc_t opc)
808 {
809 switch (opc) {
810 case OPC_ADD_U:
811 case OPC_ADD_S:
812 case OPC_SUB_U:
813 case OPC_SUB_S:
814 case OPC_CMPS_U:
815 case OPC_CMPS_S:
816 case OPC_MIN_U:
817 case OPC_MIN_S:
818 case OPC_MAX_U:
819 case OPC_MAX_S:
820 case OPC_CMPV_U:
821 case OPC_CMPV_S:
822 case OPC_MUL_U:
823 case OPC_MUL_S:
824 case OPC_MULL_U:
825 case OPC_CLZ_S:
826 case OPC_ABSNEG_S:
827 case OPC_AND_B:
828 case OPC_OR_B:
829 case OPC_NOT_B:
830 case OPC_XOR_B:
831 case OPC_BFREV_B:
832 case OPC_CLZ_B:
833 case OPC_SHL_B:
834 case OPC_SHR_B:
835 case OPC_ASHR_B:
836 case OPC_MGEN_B:
837 case OPC_GETBIT_B:
838 case OPC_CBITS_B:
839 case OPC_BARY_F:
840 return true;
841
842 default:
843 return false;
844 }
845 }
846
847
848 /* map cat2 instruction to valid abs/neg flags: */
849 static inline unsigned ir3_cat2_absneg(opc_t opc)
850 {
851 switch (opc) {
852 case OPC_ADD_F:
853 case OPC_MIN_F:
854 case OPC_MAX_F:
855 case OPC_MUL_F:
856 case OPC_SIGN_F:
857 case OPC_CMPS_F:
858 case OPC_ABSNEG_F:
859 case OPC_CMPV_F:
860 case OPC_FLOOR_F:
861 case OPC_CEIL_F:
862 case OPC_RNDNE_F:
863 case OPC_RNDAZ_F:
864 case OPC_TRUNC_F:
865 case OPC_BARY_F:
866 return IR3_REG_FABS | IR3_REG_FNEG;
867
868 case OPC_ADD_U:
869 case OPC_ADD_S:
870 case OPC_SUB_U:
871 case OPC_SUB_S:
872 case OPC_CMPS_U:
873 case OPC_CMPS_S:
874 case OPC_MIN_U:
875 case OPC_MIN_S:
876 case OPC_MAX_U:
877 case OPC_MAX_S:
878 case OPC_CMPV_U:
879 case OPC_CMPV_S:
880 case OPC_MUL_U:
881 case OPC_MUL_S:
882 case OPC_MULL_U:
883 case OPC_CLZ_S:
884 return 0;
885
886 case OPC_ABSNEG_S:
887 return IR3_REG_SABS | IR3_REG_SNEG;
888
889 case OPC_AND_B:
890 case OPC_OR_B:
891 case OPC_NOT_B:
892 case OPC_XOR_B:
893 case OPC_BFREV_B:
894 case OPC_CLZ_B:
895 case OPC_SHL_B:
896 case OPC_SHR_B:
897 case OPC_ASHR_B:
898 case OPC_MGEN_B:
899 case OPC_GETBIT_B:
900 case OPC_CBITS_B:
901 return IR3_REG_BNOT;
902
903 default:
904 return 0;
905 }
906 }
907
908 /* map cat3 instructions to valid abs/neg flags: */
909 static inline unsigned ir3_cat3_absneg(opc_t opc)
910 {
911 switch (opc) {
912 case OPC_MAD_F16:
913 case OPC_MAD_F32:
914 case OPC_SEL_F16:
915 case OPC_SEL_F32:
916 return IR3_REG_FNEG;
917
918 case OPC_MAD_U16:
919 case OPC_MADSH_U16:
920 case OPC_MAD_S16:
921 case OPC_MADSH_M16:
922 case OPC_MAD_U24:
923 case OPC_MAD_S24:
924 case OPC_SEL_S16:
925 case OPC_SEL_S32:
926 case OPC_SAD_S16:
927 case OPC_SAD_S32:
928 /* neg *may* work on 3rd src.. */
929
930 case OPC_SEL_B16:
931 case OPC_SEL_B32:
932
933 default:
934 return 0;
935 }
936 }
937
938 #define MASK(n) ((1 << (n)) - 1)
939
940 /* iterator for an instructions's sources (reg), also returns src #: */
941 #define foreach_src_n(__srcreg, __n, __instr) \
942 if ((__instr)->regs_count) \
943 for (unsigned __cnt = (__instr)->regs_count - 1, __n = 0; __n < __cnt; __n++) \
944 if ((__srcreg = (__instr)->regs[__n + 1]))
945
946 /* iterator for an instructions's sources (reg): */
947 #define foreach_src(__srcreg, __instr) \
948 foreach_src_n(__srcreg, __i, __instr)
949
950 static inline unsigned __ssa_src_cnt(struct ir3_instruction *instr)
951 {
952 unsigned cnt = instr->regs_count + instr->deps_count;
953 if (instr->address)
954 cnt++;
955 return cnt;
956 }
957
958 static inline struct ir3_instruction * __ssa_src_n(struct ir3_instruction *instr, unsigned n)
959 {
960 if (n == (instr->regs_count + instr->deps_count))
961 return instr->address;
962 if (n >= instr->regs_count)
963 return instr->deps[n - instr->regs_count];
964 return ssa(instr->regs[n]);
965 }
966
967 static inline bool __is_false_dep(struct ir3_instruction *instr, unsigned n)
968 {
969 if (n == (instr->regs_count + instr->deps_count))
970 return false;
971 if (n >= instr->regs_count)
972 return true;
973 return false;
974 }
975
976 #define __src_cnt(__instr) ((__instr)->address ? (__instr)->regs_count : (__instr)->regs_count - 1)
977
978 /* iterator for an instruction's SSA sources (instr), also returns src #: */
979 #define foreach_ssa_src_n(__srcinst, __n, __instr) \
980 for (unsigned __cnt = __ssa_src_cnt(__instr), __n = 0; __n < __cnt; __n++) \
981 if ((__srcinst = __ssa_src_n(__instr, __n)))
982
983 /* iterator for an instruction's SSA sources (instr): */
984 #define foreach_ssa_src(__srcinst, __instr) \
985 foreach_ssa_src_n(__srcinst, __i, __instr)
986
987
988 /* dump: */
989 void ir3_print(struct ir3 *ir);
990 void ir3_print_instr(struct ir3_instruction *instr);
991
992 /* depth calculation: */
993 int ir3_delayslots(struct ir3_instruction *assigner,
994 struct ir3_instruction *consumer, unsigned n);
995 void ir3_insert_by_depth(struct ir3_instruction *instr, struct list_head *list);
996 void ir3_depth(struct ir3 *ir);
997
998 /* copy-propagate: */
999 struct ir3_shader_variant;
1000 void ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so);
1001
1002 /* group neighbors and insert mov's to resolve conflicts: */
1003 void ir3_group(struct ir3 *ir);
1004
1005 /* scheduling: */
1006 void ir3_sched_add_deps(struct ir3 *ir);
1007 int ir3_sched(struct ir3 *ir);
1008
1009 /* register assignment: */
1010 struct ir3_ra_reg_set * ir3_ra_alloc_reg_set(void *memctx);
1011 int ir3_ra(struct ir3 *ir3, enum shader_t type,
1012 bool frag_coord, bool frag_face);
1013
1014 /* legalize: */
1015 void ir3_legalize(struct ir3 *ir, bool *has_samp, bool *has_ssbo, int *max_bary);
1016
1017 /* ************************************************************************* */
1018 /* instruction helpers */
1019
1020 static inline struct ir3_instruction *
1021 ir3_MOV(struct ir3_block *block, struct ir3_instruction *src, type_t type)
1022 {
1023 struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOV);
1024 ir3_reg_create(instr, 0, 0); /* dst */
1025 if (src->regs[0]->flags & IR3_REG_ARRAY) {
1026 struct ir3_register *src_reg =
1027 ir3_reg_create(instr, 0, IR3_REG_ARRAY);
1028 src_reg->array = src->regs[0]->array;
1029 src_reg->instr = src;
1030 } else {
1031 ir3_reg_create(instr, 0, IR3_REG_SSA)->instr = src;
1032 }
1033 debug_assert(!(src->regs[0]->flags & IR3_REG_RELATIV));
1034 instr->cat1.src_type = type;
1035 instr->cat1.dst_type = type;
1036 return instr;
1037 }
1038
1039 static inline struct ir3_instruction *
1040 ir3_COV(struct ir3_block *block, struct ir3_instruction *src,
1041 type_t src_type, type_t dst_type)
1042 {
1043 struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOV);
1044 ir3_reg_create(instr, 0, 0); /* dst */
1045 ir3_reg_create(instr, 0, IR3_REG_SSA)->instr = src;
1046 instr->cat1.src_type = src_type;
1047 instr->cat1.dst_type = dst_type;
1048 debug_assert(!(src->regs[0]->flags & IR3_REG_ARRAY));
1049 return instr;
1050 }
1051
1052 static inline struct ir3_instruction *
1053 ir3_NOP(struct ir3_block *block)
1054 {
1055 return ir3_instr_create(block, OPC_NOP);
1056 }
1057
1058 #define INSTR0(name) \
1059 static inline struct ir3_instruction * \
1060 ir3_##name(struct ir3_block *block) \
1061 { \
1062 struct ir3_instruction *instr = \
1063 ir3_instr_create(block, OPC_##name); \
1064 return instr; \
1065 }
1066
1067 #define INSTR1(name) \
1068 static inline struct ir3_instruction * \
1069 ir3_##name(struct ir3_block *block, \
1070 struct ir3_instruction *a, unsigned aflags) \
1071 { \
1072 struct ir3_instruction *instr = \
1073 ir3_instr_create(block, OPC_##name); \
1074 ir3_reg_create(instr, 0, 0); /* dst */ \
1075 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
1076 return instr; \
1077 }
1078
1079 #define INSTR2(name) \
1080 static inline struct ir3_instruction * \
1081 ir3_##name(struct ir3_block *block, \
1082 struct ir3_instruction *a, unsigned aflags, \
1083 struct ir3_instruction *b, unsigned bflags) \
1084 { \
1085 struct ir3_instruction *instr = \
1086 ir3_instr_create(block, OPC_##name); \
1087 ir3_reg_create(instr, 0, 0); /* dst */ \
1088 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
1089 ir3_reg_create(instr, 0, IR3_REG_SSA | bflags)->instr = b; \
1090 return instr; \
1091 }
1092
1093 #define INSTR3(name) \
1094 static inline struct ir3_instruction * \
1095 ir3_##name(struct ir3_block *block, \
1096 struct ir3_instruction *a, unsigned aflags, \
1097 struct ir3_instruction *b, unsigned bflags, \
1098 struct ir3_instruction *c, unsigned cflags) \
1099 { \
1100 struct ir3_instruction *instr = \
1101 ir3_instr_create(block, OPC_##name); \
1102 ir3_reg_create(instr, 0, 0); /* dst */ \
1103 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
1104 ir3_reg_create(instr, 0, IR3_REG_SSA | bflags)->instr = b; \
1105 ir3_reg_create(instr, 0, IR3_REG_SSA | cflags)->instr = c; \
1106 return instr; \
1107 }
1108
1109 #define INSTR4(name) \
1110 static inline struct ir3_instruction * \
1111 ir3_##name(struct ir3_block *block, \
1112 struct ir3_instruction *a, unsigned aflags, \
1113 struct ir3_instruction *b, unsigned bflags, \
1114 struct ir3_instruction *c, unsigned cflags, \
1115 struct ir3_instruction *d, unsigned dflags) \
1116 { \
1117 struct ir3_instruction *instr = \
1118 ir3_instr_create2(block, OPC_##name, 5); \
1119 ir3_reg_create(instr, 0, 0); /* dst */ \
1120 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
1121 ir3_reg_create(instr, 0, IR3_REG_SSA | bflags)->instr = b; \
1122 ir3_reg_create(instr, 0, IR3_REG_SSA | cflags)->instr = c; \
1123 ir3_reg_create(instr, 0, IR3_REG_SSA | dflags)->instr = d; \
1124 return instr; \
1125 }
1126
1127 #define INSTR4F(f, name) \
1128 static inline struct ir3_instruction * \
1129 ir3_##name##_##f(struct ir3_block *block, \
1130 struct ir3_instruction *a, unsigned aflags, \
1131 struct ir3_instruction *b, unsigned bflags, \
1132 struct ir3_instruction *c, unsigned cflags, \
1133 struct ir3_instruction *d, unsigned dflags) \
1134 { \
1135 struct ir3_instruction *instr = \
1136 ir3_instr_create2(block, OPC_##name, 5); \
1137 ir3_reg_create(instr, 0, 0); /* dst */ \
1138 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
1139 ir3_reg_create(instr, 0, IR3_REG_SSA | bflags)->instr = b; \
1140 ir3_reg_create(instr, 0, IR3_REG_SSA | cflags)->instr = c; \
1141 ir3_reg_create(instr, 0, IR3_REG_SSA | dflags)->instr = d; \
1142 instr->flags |= IR3_INSTR_##f; \
1143 return instr; \
1144 }
1145
1146 /* cat0 instructions: */
1147 INSTR0(BR)
1148 INSTR0(JUMP)
1149 INSTR1(KILL)
1150 INSTR0(END)
1151
1152 /* cat2 instructions, most 2 src but some 1 src: */
1153 INSTR2(ADD_F)
1154 INSTR2(MIN_F)
1155 INSTR2(MAX_F)
1156 INSTR2(MUL_F)
1157 INSTR1(SIGN_F)
1158 INSTR2(CMPS_F)
1159 INSTR1(ABSNEG_F)
1160 INSTR2(CMPV_F)
1161 INSTR1(FLOOR_F)
1162 INSTR1(CEIL_F)
1163 INSTR1(RNDNE_F)
1164 INSTR1(RNDAZ_F)
1165 INSTR1(TRUNC_F)
1166 INSTR2(ADD_U)
1167 INSTR2(ADD_S)
1168 INSTR2(SUB_U)
1169 INSTR2(SUB_S)
1170 INSTR2(CMPS_U)
1171 INSTR2(CMPS_S)
1172 INSTR2(MIN_U)
1173 INSTR2(MIN_S)
1174 INSTR2(MAX_U)
1175 INSTR2(MAX_S)
1176 INSTR1(ABSNEG_S)
1177 INSTR2(AND_B)
1178 INSTR2(OR_B)
1179 INSTR1(NOT_B)
1180 INSTR2(XOR_B)
1181 INSTR2(CMPV_U)
1182 INSTR2(CMPV_S)
1183 INSTR2(MUL_U)
1184 INSTR2(MUL_S)
1185 INSTR2(MULL_U)
1186 INSTR1(BFREV_B)
1187 INSTR1(CLZ_S)
1188 INSTR1(CLZ_B)
1189 INSTR2(SHL_B)
1190 INSTR2(SHR_B)
1191 INSTR2(ASHR_B)
1192 INSTR2(BARY_F)
1193 INSTR2(MGEN_B)
1194 INSTR2(GETBIT_B)
1195 INSTR1(SETRM)
1196 INSTR1(CBITS_B)
1197 INSTR2(SHB)
1198 INSTR2(MSAD)
1199
1200 /* cat3 instructions: */
1201 INSTR3(MAD_U16)
1202 INSTR3(MADSH_U16)
1203 INSTR3(MAD_S16)
1204 INSTR3(MADSH_M16)
1205 INSTR3(MAD_U24)
1206 INSTR3(MAD_S24)
1207 INSTR3(MAD_F16)
1208 INSTR3(MAD_F32)
1209 INSTR3(SEL_B16)
1210 INSTR3(SEL_B32)
1211 INSTR3(SEL_S16)
1212 INSTR3(SEL_S32)
1213 INSTR3(SEL_F16)
1214 INSTR3(SEL_F32)
1215 INSTR3(SAD_S16)
1216 INSTR3(SAD_S32)
1217
1218 /* cat4 instructions: */
1219 INSTR1(RCP)
1220 INSTR1(RSQ)
1221 INSTR1(LOG2)
1222 INSTR1(EXP2)
1223 INSTR1(SIN)
1224 INSTR1(COS)
1225 INSTR1(SQRT)
1226
1227 /* cat5 instructions: */
1228 INSTR1(DSX)
1229 INSTR1(DSY)
1230
1231 static inline struct ir3_instruction *
1232 ir3_SAM(struct ir3_block *block, opc_t opc, type_t type,
1233 unsigned wrmask, unsigned flags, unsigned samp, unsigned tex,
1234 struct ir3_instruction *src0, struct ir3_instruction *src1)
1235 {
1236 struct ir3_instruction *sam;
1237 struct ir3_register *reg;
1238
1239 sam = ir3_instr_create(block, opc);
1240 sam->flags |= flags;
1241 ir3_reg_create(sam, 0, 0)->wrmask = wrmask;
1242 if (src0) {
1243 reg = ir3_reg_create(sam, 0, IR3_REG_SSA);
1244 reg->wrmask = (1 << (src0->regs_count - 1)) - 1;
1245 reg->instr = src0;
1246 }
1247 if (src1) {
1248 reg = ir3_reg_create(sam, 0, IR3_REG_SSA);
1249 reg->instr = src1;
1250 reg->wrmask = (1 << (src1->regs_count - 1)) - 1;
1251 }
1252 sam->cat5.samp = samp;
1253 sam->cat5.tex = tex;
1254 sam->cat5.type = type;
1255
1256 return sam;
1257 }
1258
1259 /* cat6 instructions: */
1260 INSTR2(LDLV)
1261 INSTR2(LDG)
1262 INSTR2(LDL)
1263 INSTR3(STG)
1264 INSTR3(STL)
1265 INSTR3(LDGB)
1266 INSTR4(STGB)
1267 INSTR4(STIB)
1268 INSTR1(RESINFO)
1269 INSTR1(RESFMT)
1270 INSTR2(ATOMIC_ADD)
1271 INSTR2(ATOMIC_SUB)
1272 INSTR2(ATOMIC_XCHG)
1273 INSTR2(ATOMIC_INC)
1274 INSTR2(ATOMIC_DEC)
1275 INSTR2(ATOMIC_CMPXCHG)
1276 INSTR2(ATOMIC_MIN)
1277 INSTR2(ATOMIC_MAX)
1278 INSTR2(ATOMIC_AND)
1279 INSTR2(ATOMIC_OR)
1280 INSTR2(ATOMIC_XOR)
1281 INSTR4F(G, ATOMIC_ADD)
1282 INSTR4F(G, ATOMIC_SUB)
1283 INSTR4F(G, ATOMIC_XCHG)
1284 INSTR4F(G, ATOMIC_INC)
1285 INSTR4F(G, ATOMIC_DEC)
1286 INSTR4F(G, ATOMIC_CMPXCHG)
1287 INSTR4F(G, ATOMIC_MIN)
1288 INSTR4F(G, ATOMIC_MAX)
1289 INSTR4F(G, ATOMIC_AND)
1290 INSTR4F(G, ATOMIC_OR)
1291 INSTR4F(G, ATOMIC_XOR)
1292
1293 /* cat7 instructions: */
1294 INSTR0(BAR)
1295 INSTR0(FENCE)
1296
1297 /* ************************************************************************* */
1298 /* split this out or find some helper to use.. like main/bitset.h.. */
1299
1300 #include <string.h>
1301
1302 #define MAX_REG 256
1303
1304 typedef uint8_t regmask_t[2 * MAX_REG / 8];
1305
1306 static inline unsigned regmask_idx(struct ir3_register *reg)
1307 {
1308 unsigned num = (reg->flags & IR3_REG_RELATIV) ? reg->array.offset : reg->num;
1309 debug_assert(num < MAX_REG);
1310 if (reg->flags & IR3_REG_HALF)
1311 num += MAX_REG;
1312 return num;
1313 }
1314
1315 static inline void regmask_init(regmask_t *regmask)
1316 {
1317 memset(regmask, 0, sizeof(*regmask));
1318 }
1319
1320 static inline void regmask_set(regmask_t *regmask, struct ir3_register *reg)
1321 {
1322 unsigned idx = regmask_idx(reg);
1323 if (reg->flags & IR3_REG_RELATIV) {
1324 unsigned i;
1325 for (i = 0; i < reg->size; i++, idx++)
1326 (*regmask)[idx / 8] |= 1 << (idx % 8);
1327 } else {
1328 unsigned mask;
1329 for (mask = reg->wrmask; mask; mask >>= 1, idx++)
1330 if (mask & 1)
1331 (*regmask)[idx / 8] |= 1 << (idx % 8);
1332 }
1333 }
1334
1335 static inline void regmask_or(regmask_t *dst, regmask_t *a, regmask_t *b)
1336 {
1337 unsigned i;
1338 for (i = 0; i < ARRAY_SIZE(*dst); i++)
1339 (*dst)[i] = (*a)[i] | (*b)[i];
1340 }
1341
1342 /* set bits in a if not set in b, conceptually:
1343 * a |= (reg & ~b)
1344 */
1345 static inline void regmask_set_if_not(regmask_t *a,
1346 struct ir3_register *reg, regmask_t *b)
1347 {
1348 unsigned idx = regmask_idx(reg);
1349 if (reg->flags & IR3_REG_RELATIV) {
1350 unsigned i;
1351 for (i = 0; i < reg->size; i++, idx++)
1352 if (!((*b)[idx / 8] & (1 << (idx % 8))))
1353 (*a)[idx / 8] |= 1 << (idx % 8);
1354 } else {
1355 unsigned mask;
1356 for (mask = reg->wrmask; mask; mask >>= 1, idx++)
1357 if (mask & 1)
1358 if (!((*b)[idx / 8] & (1 << (idx % 8))))
1359 (*a)[idx / 8] |= 1 << (idx % 8);
1360 }
1361 }
1362
1363 static inline bool regmask_get(regmask_t *regmask,
1364 struct ir3_register *reg)
1365 {
1366 unsigned idx = regmask_idx(reg);
1367 if (reg->flags & IR3_REG_RELATIV) {
1368 unsigned i;
1369 for (i = 0; i < reg->size; i++, idx++)
1370 if ((*regmask)[idx / 8] & (1 << (idx % 8)))
1371 return true;
1372 } else {
1373 unsigned mask;
1374 for (mask = reg->wrmask; mask; mask >>= 1, idx++)
1375 if (mask & 1)
1376 if ((*regmask)[idx / 8] & (1 << (idx % 8)))
1377 return true;
1378 }
1379 return false;
1380 }
1381
1382 /* ************************************************************************* */
1383
1384 #endif /* IR3_H_ */