2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 #include "util/u_debug.h"
31 #include "util/list.h"
33 #include "instr-a3xx.h"
34 #include "disasm.h" /* TODO move 'enum shader_t' somewhere else.. */
36 /* low level intermediate representation of an adreno shader program */
40 struct ir3_instruction
;
45 uint16_t instrs_count
; /* expanded to account for rpt's */
46 /* NOTE: max_reg, etc, does not include registers not touched
47 * by the shader (ie. vertex fetched via VFD_DECODE but not
50 int8_t max_reg
; /* highest GPR # used by shader */
57 IR3_REG_CONST
= 0x001,
58 IR3_REG_IMMED
= 0x002,
60 IR3_REG_RELATIV
= 0x008,
62 /* Most instructions, it seems, can do float abs/neg but not
63 * integer. The CP pass needs to know what is intended (int or
64 * float) in order to do the right thing. For this reason the
65 * abs/neg flags are split out into float and int variants. In
66 * addition, .b (bitwise) operations, the negate is actually a
67 * bitwise not, so split that out into a new flag to make it
76 IR3_REG_POS_INF
= 0x800,
77 /* (ei) flag, end-input? Set on last bary, presumably to signal
78 * that the shader needs no more input:
81 /* meta-flags, for intermediate stages of IR, ie.
82 * before register assignment is done:
84 IR3_REG_SSA
= 0x2000, /* 'instr' is ptr to assigning instr */
85 IR3_REG_IA
= 0x4000, /* meta-input dst is "assigned" */
86 IR3_REG_ADDR
= 0x8000, /* register is a0.x */
90 * the component is in the low two bits of the reg #, so
91 * rN.x becomes: (N << 2) | x
102 /* for IR3_REG_SSA, src registers contain ptr back to
103 * assigning instruction.
105 struct ir3_instruction
*instr
;
108 /* used for cat5 instructions, but also for internal/IR level
109 * tracking of what registers are read/written by an instruction.
110 * wrmask may be a bad name since it is used to represent both
111 * src and dst that touch multiple adjacent registers.
114 /* for relative addressing, 32bits for array size is too small,
115 * but otoh we don't need to deal with disjoint sets, so instead
116 * use a simple size field (number of scalar components).
122 struct ir3_instruction
{
123 struct ir3_block
*block
;
127 /* (sy) flag is set on first instruction, and after sample
128 * instructions (probably just on RAW hazard).
130 IR3_INSTR_SY
= 0x001,
131 /* (ss) flag is set on first instruction, and first instruction
132 * to depend on the result of "long" instructions (RAW hazard):
134 * rcp, rsq, log2, exp2, sin, cos, sqrt
136 * It seems to synchronize until all in-flight instructions are
137 * completed, for example:
140 * add.f hr2.z, (neg)hr2.z, hc0.y
141 * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
144 * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
146 * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
147 * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
148 * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
150 * The last mul.f does not have (ss) set, presumably because the
151 * (ss) on the previous instruction does the job.
153 * The blob driver also seems to set it on WAR hazards, although
154 * not really clear if this is needed or just blob compiler being
155 * sloppy. So far I haven't found a case where removing the (ss)
156 * causes problems for WAR hazard, but I could just be getting
160 * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
163 IR3_INSTR_SS
= 0x002,
164 /* (jp) flag is set on jump targets:
166 IR3_INSTR_JP
= 0x004,
167 IR3_INSTR_UL
= 0x008,
168 IR3_INSTR_3D
= 0x010,
173 IR3_INSTR_S2EN
= 0x200,
174 /* meta-flags, for intermediate stages of IR, ie.
175 * before register assignment is done:
177 IR3_INSTR_MARK
= 0x1000,
184 struct ir3_register
**regs
;
192 type_t src_type
, dst_type
;
213 /* for meta-instructions, just used to hold extra data
214 * before instruction scheduling, etc
217 int off
; /* component/offset */
223 struct ir3_block
*if_block
, *else_block
;
226 struct ir3_block
*block
;
229 /* XXX keep this as big as all other union members! */
233 /* transient values used during various algorithms: */
235 /* The instruction depth is the max dependency distance to output.
237 * You can also think of it as the "cost", if we did any sort of
238 * optimization for register footprint. Ie. a value that is just
239 * result of moving a const to a reg would have a low cost, so to
240 * it could make sense to duplicate the instruction at various
241 * points where the result is needed to reduce register footprint.
243 * DEPTH_UNUSED used to mark unused instructions after depth
246 #define DEPTH_UNUSED ~0
250 /* Used during CP and RA stages. For fanin and shader inputs/
251 * outputs where we need a sequence of consecutive registers,
252 * keep track of each src instructions left (ie 'n-1') and right
253 * (ie 'n+1') neighbor. The front-end must insert enough mov's
254 * to ensure that each instruction has at most one left and at
255 * most one right neighbor. During the copy-propagation pass,
256 * we only remove mov's when we can preserve this constraint.
257 * And during the RA stage, we use the neighbor information to
258 * allocate a block of registers in one shot.
260 * TODO: maybe just add something like:
261 * struct ir3_instruction_ref {
262 * struct ir3_instruction *instr;
266 * Or can we get away without the refcnt stuff? It seems like
267 * it should be overkill.. the problem is if, potentially after
268 * already eliminating some mov's, if you have a single mov that
269 * needs to be grouped with it's neighbors in two different
270 * places (ex. shader output and a fanin).
273 struct ir3_instruction
*left
, *right
;
274 uint16_t left_cnt
, right_cnt
;
277 /* an instruction can reference at most one address register amongst
278 * it's src/dst registers. Beyond that, you need to insert mov's.
280 struct ir3_instruction
*address
;
282 /* in case of a instruction with relative dst instruction, we need to
283 * capture the dependency on the fanin for the previous values of
284 * the array elements. Since we don't know at compile time actually
285 * which array elements are written, this serves to preserve the
286 * unconditional write to array elements prior to the conditional
289 * TODO only cat1 can do indirect write.. we could maybe move this
290 * into instr->cat1.fanin (but would require the frontend to insert
293 struct ir3_instruction
*fanin
;
295 /* Entry in ir3_block's instruction list: */
296 struct list_head node
;
303 static inline struct ir3_instruction
*
304 ir3_neighbor_first(struct ir3_instruction
*instr
)
306 while (instr
->cp
.left
)
307 instr
= instr
->cp
.left
;
311 static inline int ir3_neighbor_count(struct ir3_instruction
*instr
)
315 debug_assert(!instr
->cp
.left
);
317 while (instr
->cp
.right
) {
319 instr
= instr
->cp
.right
;
325 struct ir3_heap_chunk
;
328 struct ir3_compiler
*compiler
;
330 /* Track bary.f (and ldlv) instructions.. this is needed in
331 * scheduling to ensure that all varying fetches happen before
332 * any potential kill instructions. The hw gets grumpy if all
333 * threads in a group are killed before the last bary.f gets
334 * a chance to signal end of input (ei).
336 unsigned baryfs_count
, baryfs_sz
;
337 struct ir3_instruction
**baryfs
;
339 /* Track all indirect instructions (read and write). To avoid
340 * deadlock scenario where an address register gets scheduled,
341 * but other dependent src instructions cannot be scheduled due
342 * to dependency on a *different* address register value, the
343 * scheduler needs to ensure that all dependencies other than
344 * the instruction other than the address register are scheduled
345 * before the one that writes the address register. Having a
346 * convenient list of instructions that reference some address
347 * register simplifies this.
349 unsigned indirects_count
, indirects_sz
;
350 struct ir3_instruction
**indirects
;
351 /* and same for instructions that consume predicate register: */
352 unsigned predicates_count
, predicates_sz
;
353 struct ir3_instruction
**predicates
;
355 struct ir3_block
*block
;
357 struct ir3_heap_chunk
*chunk
;
362 unsigned ntemporaries
, ninputs
, noutputs
;
363 /* maps TGSI_FILE_TEMPORARY index back to the assigning instruction: */
364 struct ir3_instruction
**temporaries
;
365 struct ir3_instruction
**inputs
;
366 struct ir3_instruction
**outputs
;
367 /* only a single address register: */
368 struct ir3_instruction
*address
;
369 struct list_head instr_list
;
372 struct ir3
* ir3_create(struct ir3_compiler
*compiler
);
373 void ir3_destroy(struct ir3
*shader
);
374 void * ir3_assemble(struct ir3
*shader
,
375 struct ir3_info
*info
, uint32_t gpu_id
);
376 void * ir3_alloc(struct ir3
*shader
, int sz
);
378 struct ir3_block
* ir3_block_create(struct ir3
*shader
,
379 unsigned ntmp
, unsigned nin
, unsigned nout
);
381 struct ir3_instruction
* ir3_instr_create(struct ir3_block
*block
,
382 int category
, opc_t opc
);
383 struct ir3_instruction
* ir3_instr_create2(struct ir3_block
*block
,
384 int category
, opc_t opc
, int nreg
);
385 struct ir3_instruction
* ir3_instr_clone(struct ir3_instruction
*instr
);
386 const char *ir3_instr_name(struct ir3_instruction
*instr
);
388 struct ir3_register
* ir3_reg_create(struct ir3_instruction
*instr
,
392 static inline bool ir3_instr_check_mark(struct ir3_instruction
*instr
)
394 if (instr
->flags
& IR3_INSTR_MARK
)
395 return true; /* already visited */
396 instr
->flags
|= IR3_INSTR_MARK
;
400 static inline void ir3_clear_mark(struct ir3
*shader
)
402 /* TODO would be nice to drop the instruction array.. for
403 * new compiler, _clear_mark() is all we use it for, and
404 * we could probably manage a linked list instead..
406 * Also, we'll probably want to mark instructions within
407 * a block, so tracking the list of instrs globally is
408 * unlikely to be what we want.
410 list_for_each_entry (struct ir3_instruction
, instr
, &shader
->block
->instr_list
, node
)
411 instr
->flags
&= ~IR3_INSTR_MARK
;
414 static inline int ir3_instr_regno(struct ir3_instruction
*instr
,
415 struct ir3_register
*reg
)
418 for (i
= 0; i
< instr
->regs_count
; i
++)
419 if (reg
== instr
->regs
[i
])
425 #define MAX_ARRAYS 16
433 static inline uint32_t regid(int num
, int comp
)
435 return (num
<< 2) | (comp
& 0x3);
438 static inline uint32_t reg_num(struct ir3_register
*reg
)
440 return reg
->num
>> 2;
443 static inline uint32_t reg_comp(struct ir3_register
*reg
)
445 return reg
->num
& 0x3;
448 static inline bool is_flow(struct ir3_instruction
*instr
)
450 return (instr
->category
== 0);
453 static inline bool is_kill(struct ir3_instruction
*instr
)
455 return is_flow(instr
) && (instr
->opc
== OPC_KILL
);
458 static inline bool is_nop(struct ir3_instruction
*instr
)
460 return is_flow(instr
) && (instr
->opc
== OPC_NOP
);
463 /* Is it a non-transformative (ie. not type changing) mov? This can
464 * also include absneg.s/absneg.f, which for the most part can be
465 * treated as a mov (single src argument).
467 static inline bool is_same_type_mov(struct ir3_instruction
*instr
)
469 struct ir3_register
*dst
= instr
->regs
[0];
471 /* mov's that write to a0.x or p0.x are special: */
472 if (dst
->num
== regid(REG_P0
, 0))
474 if (dst
->num
== regid(REG_A0
, 0))
477 if ((instr
->category
== 1) &&
478 (instr
->cat1
.src_type
== instr
->cat1
.dst_type
))
480 if ((instr
->category
== 2) && ((instr
->opc
== OPC_ABSNEG_F
) ||
481 (instr
->opc
== OPC_ABSNEG_S
)))
486 static inline bool is_alu(struct ir3_instruction
*instr
)
488 return (1 <= instr
->category
) && (instr
->category
<= 3);
491 static inline bool is_sfu(struct ir3_instruction
*instr
)
493 return (instr
->category
== 4);
496 static inline bool is_tex(struct ir3_instruction
*instr
)
498 return (instr
->category
== 5);
501 static inline bool is_mem(struct ir3_instruction
*instr
)
503 return (instr
->category
== 6);
506 static inline bool is_input(struct ir3_instruction
*instr
)
508 /* in some cases, ldlv is used to fetch varying without
509 * interpolation.. fortunately inloc is the first src
510 * register in either case
512 if (is_mem(instr
) && (instr
->opc
== OPC_LDLV
))
514 return (instr
->category
== 2) && (instr
->opc
== OPC_BARY_F
);
517 static inline bool is_meta(struct ir3_instruction
*instr
)
519 /* TODO how should we count PHI (and maybe fan-in/out) which
520 * might actually contribute some instructions to the final
523 return (instr
->category
== -1);
526 static inline bool writes_addr(struct ir3_instruction
*instr
)
528 if (instr
->regs_count
> 0) {
529 struct ir3_register
*dst
= instr
->regs
[0];
530 return !!(dst
->flags
& IR3_REG_ADDR
);
535 static inline bool writes_pred(struct ir3_instruction
*instr
)
537 if (instr
->regs_count
> 0) {
538 struct ir3_register
*dst
= instr
->regs
[0];
539 return reg_num(dst
) == REG_P0
;
544 /* returns defining instruction for reg */
545 /* TODO better name */
546 static inline struct ir3_instruction
*ssa(struct ir3_register
*reg
)
548 if (reg
->flags
& IR3_REG_SSA
)
553 static inline bool conflicts(struct ir3_instruction
*a
,
554 struct ir3_instruction
*b
)
556 return (a
&& b
) && (a
!= b
);
559 static inline bool reg_gpr(struct ir3_register
*r
)
561 if (r
->flags
& (IR3_REG_CONST
| IR3_REG_IMMED
| IR3_REG_ADDR
))
563 if ((reg_num(r
) == REG_A0
) || (reg_num(r
) == REG_P0
))
568 /* some cat2 instructions (ie. those which are not float) can embed an
571 static inline bool ir3_cat2_int(opc_t opc
)
612 /* map cat2 instruction to valid abs/neg flags: */
613 static inline unsigned ir3_cat2_absneg(opc_t opc
)
630 return IR3_REG_FABS
| IR3_REG_FNEG
;
651 return IR3_REG_SABS
| IR3_REG_SNEG
;
672 /* map cat3 instructions to valid abs/neg flags: */
673 static inline unsigned ir3_cat3_absneg(opc_t opc
)
692 /* neg *may* work on 3rd src.. */
702 #define array_insert(arr, val) do { \
703 if (arr ## _count == arr ## _sz) { \
704 arr ## _sz = MAX2(2 * arr ## _sz, 16); \
705 arr = realloc(arr, arr ## _sz * sizeof(arr[0])); \
707 arr[arr ##_count++] = val; \
710 /* iterator for an instructions's sources (reg), also returns src #: */
711 #define foreach_src_n(__srcreg, __n, __instr) \
712 if ((__instr)->regs_count) \
713 for (unsigned __cnt = (__instr)->regs_count - 1, __n = 0; __n < __cnt; __n++) \
714 if ((__srcreg = (__instr)->regs[__n + 1]))
716 /* iterator for an instructions's sources (reg): */
717 #define foreach_src(__srcreg, __instr) \
718 foreach_src_n(__srcreg, __i, __instr)
720 static inline unsigned __ssa_src_cnt(struct ir3_instruction
*instr
)
723 return instr
->regs_count
+ 2;
725 return instr
->regs_count
+ 1;
726 return instr
->regs_count
;
729 static inline struct ir3_instruction
* __ssa_src_n(struct ir3_instruction
*instr
, unsigned n
)
731 if (n
== (instr
->regs_count
+ 1))
733 if (n
== (instr
->regs_count
+ 0))
734 return instr
->address
;
735 return ssa(instr
->regs
[n
]);
738 #define __src_cnt(__instr) ((__instr)->address ? (__instr)->regs_count : (__instr)->regs_count - 1)
740 /* iterator for an instruction's SSA sources (instr), also returns src #: */
741 #define foreach_ssa_src_n(__srcinst, __n, __instr) \
742 if ((__instr)->regs_count) \
743 for (unsigned __cnt = __ssa_src_cnt(__instr) - 1, __n = 0; __n < __cnt; __n++) \
744 if ((__srcinst = __ssa_src_n(__instr, __n + 1)))
746 /* iterator for an instruction's SSA sources (instr): */
747 #define foreach_ssa_src(__srcinst, __instr) \
748 foreach_ssa_src_n(__srcinst, __i, __instr)
752 void ir3_print(struct ir3
*ir
);
753 void ir3_print_instr(struct ir3_instruction
*instr
);
755 /* flatten if/else: */
756 int ir3_block_flatten(struct ir3_block
*block
);
758 /* depth calculation: */
759 int ir3_delayslots(struct ir3_instruction
*assigner
,
760 struct ir3_instruction
*consumer
, unsigned n
);
761 void ir3_insert_by_depth(struct ir3_instruction
*instr
, struct list_head
*list
);
762 void ir3_block_depth(struct ir3_block
*block
);
764 /* copy-propagate: */
765 void ir3_block_cp(struct ir3_block
*block
);
767 /* group neighbors and insert mov's to resolve conflicts: */
768 void ir3_block_group(struct ir3_block
*block
);
771 int ir3_block_sched(struct ir3_block
*block
);
773 /* register assignment: */
774 int ir3_block_ra(struct ir3_block
*block
, enum shader_t type
,
775 bool frag_coord
, bool frag_face
);
778 void ir3_block_legalize(struct ir3_block
*block
,
779 bool *has_samp
, int *max_bary
);
781 /* ************************************************************************* */
782 /* instruction helpers */
784 static inline struct ir3_instruction
*
785 ir3_MOV(struct ir3_block
*block
, struct ir3_instruction
*src
, type_t type
)
787 struct ir3_instruction
*instr
=
788 ir3_instr_create(block
, 1, 0);
789 ir3_reg_create(instr
, 0, 0); /* dst */
790 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
791 instr
->cat1
.src_type
= type
;
792 instr
->cat1
.dst_type
= type
;
796 static inline struct ir3_instruction
*
797 ir3_COV(struct ir3_block
*block
, struct ir3_instruction
*src
,
798 type_t src_type
, type_t dst_type
)
800 struct ir3_instruction
*instr
=
801 ir3_instr_create(block
, 1, 0);
802 ir3_reg_create(instr
, 0, 0); /* dst */
803 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
804 instr
->cat1
.src_type
= src_type
;
805 instr
->cat1
.dst_type
= dst_type
;
809 static inline struct ir3_instruction
*
810 ir3_NOP(struct ir3_block
*block
)
812 return ir3_instr_create(block
, 0, OPC_NOP
);
815 #define INSTR1(CAT, name) \
816 static inline struct ir3_instruction * \
817 ir3_##name(struct ir3_block *block, \
818 struct ir3_instruction *a, unsigned aflags) \
820 struct ir3_instruction *instr = \
821 ir3_instr_create(block, CAT, OPC_##name); \
822 ir3_reg_create(instr, 0, 0); /* dst */ \
823 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
827 #define INSTR2(CAT, name) \
828 static inline struct ir3_instruction * \
829 ir3_##name(struct ir3_block *block, \
830 struct ir3_instruction *a, unsigned aflags, \
831 struct ir3_instruction *b, unsigned bflags) \
833 struct ir3_instruction *instr = \
834 ir3_instr_create(block, CAT, OPC_##name); \
835 ir3_reg_create(instr, 0, 0); /* dst */ \
836 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
837 ir3_reg_create(instr, 0, IR3_REG_SSA | bflags)->instr = b; \
841 #define INSTR3(CAT, name) \
842 static inline struct ir3_instruction * \
843 ir3_##name(struct ir3_block *block, \
844 struct ir3_instruction *a, unsigned aflags, \
845 struct ir3_instruction *b, unsigned bflags, \
846 struct ir3_instruction *c, unsigned cflags) \
848 struct ir3_instruction *instr = \
849 ir3_instr_create(block, CAT, OPC_##name); \
850 ir3_reg_create(instr, 0, 0); /* dst */ \
851 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
852 ir3_reg_create(instr, 0, IR3_REG_SSA | bflags)->instr = b; \
853 ir3_reg_create(instr, 0, IR3_REG_SSA | cflags)->instr = c; \
857 /* cat0 instructions: */
860 /* cat2 instructions, most 2 src but some 1 src: */
908 /* cat3 instructions: */
926 /* cat4 instructions: */
935 /* cat5 instructions: */
939 static inline struct ir3_instruction
*
940 ir3_SAM(struct ir3_block
*block
, opc_t opc
, type_t type
,
941 unsigned wrmask
, unsigned flags
, unsigned samp
, unsigned tex
,
942 struct ir3_instruction
*src0
, struct ir3_instruction
*src1
)
944 struct ir3_instruction
*sam
;
945 struct ir3_register
*reg
;
947 sam
= ir3_instr_create(block
, 5, opc
);
949 ir3_reg_create(sam
, 0, 0)->wrmask
= wrmask
;
951 reg
= ir3_reg_create(sam
, 0, IR3_REG_SSA
);
952 reg
->wrmask
= (1 << (src0
->regs_count
- 1)) - 1;
956 reg
= ir3_reg_create(sam
, 0, IR3_REG_SSA
);
958 reg
->wrmask
= (1 << (src1
->regs_count
- 1)) - 1;
960 sam
->cat5
.samp
= samp
;
962 sam
->cat5
.type
= type
;
967 /* cat6 instructions: */
971 /* ************************************************************************* */
972 /* split this out or find some helper to use.. like main/bitset.h.. */
978 typedef uint8_t regmask_t
[2 * MAX_REG
/ 8];
980 static inline unsigned regmask_idx(struct ir3_register
*reg
)
982 unsigned num
= reg
->num
;
983 debug_assert(num
< MAX_REG
);
984 if (reg
->flags
& IR3_REG_HALF
)
989 static inline void regmask_init(regmask_t
*regmask
)
991 memset(regmask
, 0, sizeof(*regmask
));
994 static inline void regmask_set(regmask_t
*regmask
, struct ir3_register
*reg
)
996 unsigned idx
= regmask_idx(reg
);
997 if (reg
->flags
& IR3_REG_RELATIV
) {
999 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1000 (*regmask
)[idx
/ 8] |= 1 << (idx
% 8);
1003 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1005 (*regmask
)[idx
/ 8] |= 1 << (idx
% 8);
1009 static inline void regmask_or(regmask_t
*dst
, regmask_t
*a
, regmask_t
*b
)
1012 for (i
= 0; i
< ARRAY_SIZE(*dst
); i
++)
1013 (*dst
)[i
] = (*a
)[i
] | (*b
)[i
];
1016 /* set bits in a if not set in b, conceptually:
1019 static inline void regmask_set_if_not(regmask_t
*a
,
1020 struct ir3_register
*reg
, regmask_t
*b
)
1022 unsigned idx
= regmask_idx(reg
);
1023 if (reg
->flags
& IR3_REG_RELATIV
) {
1025 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1026 if (!((*b
)[idx
/ 8] & (1 << (idx
% 8))))
1027 (*a
)[idx
/ 8] |= 1 << (idx
% 8);
1030 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1032 if (!((*b
)[idx
/ 8] & (1 << (idx
% 8))))
1033 (*a
)[idx
/ 8] |= 1 << (idx
% 8);
1037 static inline bool regmask_get(regmask_t
*regmask
,
1038 struct ir3_register
*reg
)
1040 unsigned idx
= regmask_idx(reg
);
1041 if (reg
->flags
& IR3_REG_RELATIV
) {
1043 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1044 if ((*regmask
)[idx
/ 8] & (1 << (idx
% 8)))
1048 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1050 if ((*regmask
)[idx
/ 8] & (1 << (idx
% 8)))
1056 /* ************************************************************************* */