2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 #include "util/u_debug.h"
31 #include "util/list.h"
33 #include "instr-a3xx.h"
34 #include "disasm.h" /* TODO move 'enum shader_t' somewhere else.. */
36 /* low level intermediate representation of an adreno shader program */
40 struct ir3_instruction
;
46 uint16_t instrs_count
; /* expanded to account for rpt's */
47 /* NOTE: max_reg, etc, does not include registers not touched
48 * by the shader (ie. vertex fetched via VFD_DECODE but not
51 int8_t max_reg
; /* highest GPR # used by shader */
58 IR3_REG_CONST
= 0x001,
59 IR3_REG_IMMED
= 0x002,
61 IR3_REG_RELATIV
= 0x008,
63 /* Most instructions, it seems, can do float abs/neg but not
64 * integer. The CP pass needs to know what is intended (int or
65 * float) in order to do the right thing. For this reason the
66 * abs/neg flags are split out into float and int variants. In
67 * addition, .b (bitwise) operations, the negate is actually a
68 * bitwise not, so split that out into a new flag to make it
77 IR3_REG_POS_INF
= 0x800,
78 /* (ei) flag, end-input? Set on last bary, presumably to signal
79 * that the shader needs no more input:
82 /* meta-flags, for intermediate stages of IR, ie.
83 * before register assignment is done:
85 IR3_REG_SSA
= 0x2000, /* 'instr' is ptr to assigning instr */
86 IR3_REG_ARRAY
= 0x4000,
87 IR3_REG_PHI_SRC
= 0x8000, /* phi src, regs[0]->instr points to phi */
92 * the component is in the low two bits of the reg #, so
93 * rN.x becomes: (N << 2) | x
107 /* For IR3_REG_SSA, src registers contain ptr back to assigning
110 * For IR3_REG_ARRAY, the pointer is back to the last dependent
111 * array access (although the net effect is the same, it points
112 * back to a previous instruction that we depend on).
114 struct ir3_instruction
*instr
;
117 /* used for cat5 instructions, but also for internal/IR level
118 * tracking of what registers are read/written by an instruction.
119 * wrmask may be a bad name since it is used to represent both
120 * src and dst that touch multiple adjacent registers.
123 /* for relative addressing, 32bits for array size is too small,
124 * but otoh we don't need to deal with disjoint sets, so instead
125 * use a simple size field (number of scalar components).
131 struct ir3_instruction
{
132 struct ir3_block
*block
;
136 /* (sy) flag is set on first instruction, and after sample
137 * instructions (probably just on RAW hazard).
139 IR3_INSTR_SY
= 0x001,
140 /* (ss) flag is set on first instruction, and first instruction
141 * to depend on the result of "long" instructions (RAW hazard):
143 * rcp, rsq, log2, exp2, sin, cos, sqrt
145 * It seems to synchronize until all in-flight instructions are
146 * completed, for example:
149 * add.f hr2.z, (neg)hr2.z, hc0.y
150 * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
153 * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
155 * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
156 * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
157 * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
159 * The last mul.f does not have (ss) set, presumably because the
160 * (ss) on the previous instruction does the job.
162 * The blob driver also seems to set it on WAR hazards, although
163 * not really clear if this is needed or just blob compiler being
164 * sloppy. So far I haven't found a case where removing the (ss)
165 * causes problems for WAR hazard, but I could just be getting
169 * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
172 IR3_INSTR_SS
= 0x002,
173 /* (jp) flag is set on jump targets:
175 IR3_INSTR_JP
= 0x004,
176 IR3_INSTR_UL
= 0x008,
177 IR3_INSTR_3D
= 0x010,
182 IR3_INSTR_S2EN
= 0x200,
184 /* meta-flags, for intermediate stages of IR, ie.
185 * before register assignment is done:
187 IR3_INSTR_MARK
= 0x1000,
188 IR3_INSTR_UNUSED
= 0x2000,
195 struct ir3_register
**regs
;
201 struct ir3_block
*target
;
204 type_t src_type
, dst_type
;
226 /* for meta-instructions, just used to hold extra data
227 * before instruction scheduling, etc
230 int off
; /* component/offset */
233 /* used to temporarily hold reference to nir_phi_instr
234 * until we resolve the phi srcs
239 struct ir3_block
*block
;
243 /* transient values used during various algorithms: */
245 /* The instruction depth is the max dependency distance to output.
247 * You can also think of it as the "cost", if we did any sort of
248 * optimization for register footprint. Ie. a value that is just
249 * result of moving a const to a reg would have a low cost, so to
250 * it could make sense to duplicate the instruction at various
251 * points where the result is needed to reduce register footprint.
254 /* When we get to the RA stage, we no longer need depth, but
255 * we do need instruction's position/name:
263 /* used for per-pass extra instruction data.
267 /* Used during CP and RA stages. For fanin and shader inputs/
268 * outputs where we need a sequence of consecutive registers,
269 * keep track of each src instructions left (ie 'n-1') and right
270 * (ie 'n+1') neighbor. The front-end must insert enough mov's
271 * to ensure that each instruction has at most one left and at
272 * most one right neighbor. During the copy-propagation pass,
273 * we only remove mov's when we can preserve this constraint.
274 * And during the RA stage, we use the neighbor information to
275 * allocate a block of registers in one shot.
277 * TODO: maybe just add something like:
278 * struct ir3_instruction_ref {
279 * struct ir3_instruction *instr;
283 * Or can we get away without the refcnt stuff? It seems like
284 * it should be overkill.. the problem is if, potentially after
285 * already eliminating some mov's, if you have a single mov that
286 * needs to be grouped with it's neighbors in two different
287 * places (ex. shader output and a fanin).
290 struct ir3_instruction
*left
, *right
;
291 uint16_t left_cnt
, right_cnt
;
294 /* an instruction can reference at most one address register amongst
295 * it's src/dst registers. Beyond that, you need to insert mov's.
297 * NOTE: do not write this directly, use ir3_instr_set_address()
299 struct ir3_instruction
*address
;
301 /* Entry in ir3_block's instruction list: */
302 struct list_head node
;
309 static inline struct ir3_instruction
*
310 ir3_neighbor_first(struct ir3_instruction
*instr
)
312 while (instr
->cp
.left
)
313 instr
= instr
->cp
.left
;
317 static inline int ir3_neighbor_count(struct ir3_instruction
*instr
)
321 debug_assert(!instr
->cp
.left
);
323 while (instr
->cp
.right
) {
325 instr
= instr
->cp
.right
;
331 struct ir3_heap_chunk
;
334 struct ir3_compiler
*compiler
;
336 unsigned ninputs
, noutputs
;
337 struct ir3_instruction
**inputs
;
338 struct ir3_instruction
**outputs
;
340 /* Track bary.f (and ldlv) instructions.. this is needed in
341 * scheduling to ensure that all varying fetches happen before
342 * any potential kill instructions. The hw gets grumpy if all
343 * threads in a group are killed before the last bary.f gets
344 * a chance to signal end of input (ei).
346 unsigned baryfs_count
, baryfs_sz
;
347 struct ir3_instruction
**baryfs
;
349 /* Track all indirect instructions (read and write). To avoid
350 * deadlock scenario where an address register gets scheduled,
351 * but other dependent src instructions cannot be scheduled due
352 * to dependency on a *different* address register value, the
353 * scheduler needs to ensure that all dependencies other than
354 * the instruction other than the address register are scheduled
355 * before the one that writes the address register. Having a
356 * convenient list of instructions that reference some address
357 * register simplifies this.
359 unsigned indirects_count
, indirects_sz
;
360 struct ir3_instruction
**indirects
;
361 /* and same for instructions that consume predicate register: */
362 unsigned predicates_count
, predicates_sz
;
363 struct ir3_instruction
**predicates
;
365 /* Track instructions which do not write a register but other-
366 * wise must not be discarded (such as kill, stg, etc)
368 unsigned keeps_count
, keeps_sz
;
369 struct ir3_instruction
**keeps
;
371 /* List of blocks: */
372 struct list_head block_list
;
374 /* List of ir3_array's: */
375 struct list_head array_list
;
378 struct ir3_heap_chunk
*chunk
;
381 typedef struct nir_variable nir_variable
;
384 struct list_head node
;
390 /* We track the last write and last access (read or write) to
391 * setup dependencies on instructions that read or write the
392 * array. Reads can be re-ordered wrt. other reads, but should
393 * not be re-ordered wrt. to writes. Writes cannot be reordered
394 * wrt. any other access to the array.
396 * So array reads depend on last write, and array writes depend
397 * on the last access.
399 struct ir3_instruction
*last_write
, *last_access
;
401 /* extra stuff used in RA pass: */
402 unsigned base
; /* base vreg name */
403 unsigned reg
; /* base physical reg */
404 uint16_t start_ip
, end_ip
;
407 struct ir3_array
* ir3_lookup_array(struct ir3
*ir
, unsigned id
);
409 typedef struct nir_block nir_block
;
412 struct list_head node
;
417 struct list_head instr_list
; /* list of ir3_instruction */
419 /* each block has either one or two successors.. in case of
420 * two successors, 'condition' decides which one to follow.
421 * A block preceding an if/else has two successors.
423 struct ir3_instruction
*condition
;
424 struct ir3_block
*successors
[2];
426 uint16_t start_ip
, end_ip
;
428 /* used for per-pass extra block data. Mainly used right
429 * now in RA step to track livein/liveout.
438 struct ir3
* ir3_create(struct ir3_compiler
*compiler
,
439 unsigned nin
, unsigned nout
);
440 void ir3_destroy(struct ir3
*shader
);
441 void * ir3_assemble(struct ir3
*shader
,
442 struct ir3_info
*info
, uint32_t gpu_id
);
443 void * ir3_alloc(struct ir3
*shader
, int sz
);
445 struct ir3_block
* ir3_block_create(struct ir3
*shader
);
447 struct ir3_instruction
* ir3_instr_create(struct ir3_block
*block
,
448 int category
, opc_t opc
);
449 struct ir3_instruction
* ir3_instr_create2(struct ir3_block
*block
,
450 int category
, opc_t opc
, int nreg
);
451 struct ir3_instruction
* ir3_instr_clone(struct ir3_instruction
*instr
);
452 const char *ir3_instr_name(struct ir3_instruction
*instr
);
454 struct ir3_register
* ir3_reg_create(struct ir3_instruction
*instr
,
456 struct ir3_register
* ir3_reg_clone(struct ir3
*shader
,
457 struct ir3_register
*reg
);
459 void ir3_instr_set_address(struct ir3_instruction
*instr
,
460 struct ir3_instruction
*addr
);
462 static inline bool ir3_instr_check_mark(struct ir3_instruction
*instr
)
464 if (instr
->flags
& IR3_INSTR_MARK
)
465 return true; /* already visited */
466 instr
->flags
|= IR3_INSTR_MARK
;
470 void ir3_block_clear_mark(struct ir3_block
*block
);
471 void ir3_clear_mark(struct ir3
*shader
);
473 unsigned ir3_count_instructions(struct ir3
*ir
);
475 static inline int ir3_instr_regno(struct ir3_instruction
*instr
,
476 struct ir3_register
*reg
)
479 for (i
= 0; i
< instr
->regs_count
; i
++)
480 if (reg
== instr
->regs
[i
])
486 #define MAX_ARRAYS 16
494 static inline uint32_t regid(int num
, int comp
)
496 return (num
<< 2) | (comp
& 0x3);
499 static inline uint32_t reg_num(struct ir3_register
*reg
)
501 return reg
->num
>> 2;
504 static inline uint32_t reg_comp(struct ir3_register
*reg
)
506 return reg
->num
& 0x3;
509 static inline bool is_flow(struct ir3_instruction
*instr
)
511 return (instr
->category
== 0);
514 static inline bool is_kill(struct ir3_instruction
*instr
)
516 return is_flow(instr
) && (instr
->opc
== OPC_KILL
);
519 static inline bool is_nop(struct ir3_instruction
*instr
)
521 return is_flow(instr
) && (instr
->opc
== OPC_NOP
);
524 /* Is it a non-transformative (ie. not type changing) mov? This can
525 * also include absneg.s/absneg.f, which for the most part can be
526 * treated as a mov (single src argument).
528 static inline bool is_same_type_mov(struct ir3_instruction
*instr
)
530 struct ir3_register
*dst
= instr
->regs
[0];
532 /* mov's that write to a0.x or p0.x are special: */
533 if (dst
->num
== regid(REG_P0
, 0))
535 if (dst
->num
== regid(REG_A0
, 0))
538 if (dst
->flags
& (IR3_REG_RELATIV
| IR3_REG_ARRAY
))
541 if ((instr
->category
== 1) &&
542 (instr
->cat1
.src_type
== instr
->cat1
.dst_type
))
544 if ((instr
->category
== 2) && ((instr
->opc
== OPC_ABSNEG_F
) ||
545 (instr
->opc
== OPC_ABSNEG_S
)))
550 static inline bool is_alu(struct ir3_instruction
*instr
)
552 return (1 <= instr
->category
) && (instr
->category
<= 3);
555 static inline bool is_sfu(struct ir3_instruction
*instr
)
557 return (instr
->category
== 4);
560 static inline bool is_tex(struct ir3_instruction
*instr
)
562 return (instr
->category
== 5);
565 static inline bool is_mem(struct ir3_instruction
*instr
)
567 return (instr
->category
== 6);
571 is_store(struct ir3_instruction
*instr
)
574 /* these instructions, the "destination" register is
575 * actually a source, the address to store to.
577 switch (instr
->opc
) {
592 static inline bool is_load(struct ir3_instruction
*instr
)
595 switch (instr
->opc
) {
603 /* probably some others too.. */
612 static inline bool is_input(struct ir3_instruction
*instr
)
614 /* in some cases, ldlv is used to fetch varying without
615 * interpolation.. fortunately inloc is the first src
616 * register in either case
618 if (is_mem(instr
) && (instr
->opc
== OPC_LDLV
))
620 return (instr
->category
== 2) && (instr
->opc
== OPC_BARY_F
);
623 static inline bool is_meta(struct ir3_instruction
*instr
)
625 /* TODO how should we count PHI (and maybe fan-in/out) which
626 * might actually contribute some instructions to the final
629 return (instr
->category
== -1);
632 static inline bool writes_addr(struct ir3_instruction
*instr
)
634 if (instr
->regs_count
> 0) {
635 struct ir3_register
*dst
= instr
->regs
[0];
636 return reg_num(dst
) == REG_A0
;
641 static inline bool writes_pred(struct ir3_instruction
*instr
)
643 if (instr
->regs_count
> 0) {
644 struct ir3_register
*dst
= instr
->regs
[0];
645 return reg_num(dst
) == REG_P0
;
650 /* returns defining instruction for reg */
651 /* TODO better name */
652 static inline struct ir3_instruction
*ssa(struct ir3_register
*reg
)
654 if (reg
->flags
& (IR3_REG_SSA
| IR3_REG_ARRAY
)) {
655 debug_assert(!(reg
->instr
&& (reg
->instr
->flags
& IR3_INSTR_UNUSED
)));
661 static inline bool conflicts(struct ir3_instruction
*a
,
662 struct ir3_instruction
*b
)
664 return (a
&& b
) && (a
!= b
);
667 static inline bool reg_gpr(struct ir3_register
*r
)
669 if (r
->flags
& (IR3_REG_CONST
| IR3_REG_IMMED
))
671 if ((reg_num(r
) == REG_A0
) || (reg_num(r
) == REG_P0
))
676 static inline type_t
half_type(type_t type
)
679 case TYPE_F32
: return TYPE_F16
;
680 case TYPE_U32
: return TYPE_U16
;
681 case TYPE_S32
: return TYPE_S16
;
692 /* some cat2 instructions (ie. those which are not float) can embed an
695 static inline bool ir3_cat2_int(opc_t opc
)
736 /* map cat2 instruction to valid abs/neg flags: */
737 static inline unsigned ir3_cat2_absneg(opc_t opc
)
754 return IR3_REG_FABS
| IR3_REG_FNEG
;
775 return IR3_REG_SABS
| IR3_REG_SNEG
;
796 /* map cat3 instructions to valid abs/neg flags: */
797 static inline unsigned ir3_cat3_absneg(opc_t opc
)
816 /* neg *may* work on 3rd src.. */
826 #define array_insert(arr, val) do { \
827 if (arr ## _count == arr ## _sz) { \
828 arr ## _sz = MAX2(2 * arr ## _sz, 16); \
829 arr = realloc(arr, arr ## _sz * sizeof(arr[0])); \
831 arr[arr ##_count++] = val; \
834 /* iterator for an instructions's sources (reg), also returns src #: */
835 #define foreach_src_n(__srcreg, __n, __instr) \
836 if ((__instr)->regs_count) \
837 for (unsigned __cnt = (__instr)->regs_count - 1, __n = 0; __n < __cnt; __n++) \
838 if ((__srcreg = (__instr)->regs[__n + 1]))
840 /* iterator for an instructions's sources (reg): */
841 #define foreach_src(__srcreg, __instr) \
842 foreach_src_n(__srcreg, __i, __instr)
844 static inline unsigned __ssa_src_cnt(struct ir3_instruction
*instr
)
847 return instr
->regs_count
+ 1;
848 return instr
->regs_count
;
851 static inline struct ir3_instruction
* __ssa_src_n(struct ir3_instruction
*instr
, unsigned n
)
853 if (n
== (instr
->regs_count
+ 0))
854 return instr
->address
;
855 return ssa(instr
->regs
[n
]);
858 #define __src_cnt(__instr) ((__instr)->address ? (__instr)->regs_count : (__instr)->regs_count - 1)
860 /* iterator for an instruction's SSA sources (instr), also returns src #: */
861 #define foreach_ssa_src_n(__srcinst, __n, __instr) \
862 if ((__instr)->regs_count) \
863 for (unsigned __cnt = __ssa_src_cnt(__instr), __n = 0; __n < __cnt; __n++) \
864 if ((__srcinst = __ssa_src_n(__instr, __n)))
866 /* iterator for an instruction's SSA sources (instr): */
867 #define foreach_ssa_src(__srcinst, __instr) \
868 foreach_ssa_src_n(__srcinst, __i, __instr)
872 void ir3_print(struct ir3
*ir
);
873 void ir3_print_instr(struct ir3_instruction
*instr
);
875 /* depth calculation: */
876 int ir3_delayslots(struct ir3_instruction
*assigner
,
877 struct ir3_instruction
*consumer
, unsigned n
);
878 void ir3_insert_by_depth(struct ir3_instruction
*instr
, struct list_head
*list
);
879 void ir3_depth(struct ir3
*ir
);
881 /* copy-propagate: */
882 void ir3_cp(struct ir3
*ir
);
884 /* group neighbors and insert mov's to resolve conflicts: */
885 void ir3_group(struct ir3
*ir
);
888 int ir3_sched(struct ir3
*ir
);
890 /* register assignment: */
891 struct ir3_ra_reg_set
* ir3_ra_alloc_reg_set(void *memctx
);
892 int ir3_ra(struct ir3
*ir3
, enum shader_t type
,
893 bool frag_coord
, bool frag_face
);
896 void ir3_legalize(struct ir3
*ir
, bool *has_samp
, int *max_bary
);
898 /* ************************************************************************* */
899 /* instruction helpers */
901 static inline struct ir3_instruction
*
902 ir3_MOV(struct ir3_block
*block
, struct ir3_instruction
*src
, type_t type
)
904 struct ir3_instruction
*instr
=
905 ir3_instr_create(block
, 1, OPC_MOV
);
906 ir3_reg_create(instr
, 0, 0); /* dst */
907 if (src
->regs
[0]->flags
& IR3_REG_ARRAY
) {
908 struct ir3_register
*src_reg
=
909 ir3_reg_create(instr
, 0, IR3_REG_ARRAY
);
910 src_reg
->array
= src
->regs
[0]->array
;
911 src_reg
->instr
= src
;
913 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
915 debug_assert(!(src
->regs
[0]->flags
& IR3_REG_RELATIV
));
916 instr
->cat1
.src_type
= type
;
917 instr
->cat1
.dst_type
= type
;
921 static inline struct ir3_instruction
*
922 ir3_COV(struct ir3_block
*block
, struct ir3_instruction
*src
,
923 type_t src_type
, type_t dst_type
)
925 struct ir3_instruction
*instr
=
926 ir3_instr_create(block
, 1, OPC_MOV
);
927 ir3_reg_create(instr
, 0, 0); /* dst */
928 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
929 instr
->cat1
.src_type
= src_type
;
930 instr
->cat1
.dst_type
= dst_type
;
931 debug_assert(!(src
->regs
[0]->flags
& IR3_REG_ARRAY
));
935 static inline struct ir3_instruction
*
936 ir3_NOP(struct ir3_block
*block
)
938 return ir3_instr_create(block
, 0, OPC_NOP
);
941 #define INSTR0(CAT, name) \
942 static inline struct ir3_instruction * \
943 ir3_##name(struct ir3_block *block) \
945 struct ir3_instruction *instr = \
946 ir3_instr_create(block, CAT, OPC_##name); \
950 #define INSTR1(CAT, name) \
951 static inline struct ir3_instruction * \
952 ir3_##name(struct ir3_block *block, \
953 struct ir3_instruction *a, unsigned aflags) \
955 struct ir3_instruction *instr = \
956 ir3_instr_create(block, CAT, OPC_##name); \
957 ir3_reg_create(instr, 0, 0); /* dst */ \
958 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
962 #define INSTR2(CAT, name) \
963 static inline struct ir3_instruction * \
964 ir3_##name(struct ir3_block *block, \
965 struct ir3_instruction *a, unsigned aflags, \
966 struct ir3_instruction *b, unsigned bflags) \
968 struct ir3_instruction *instr = \
969 ir3_instr_create(block, CAT, OPC_##name); \
970 ir3_reg_create(instr, 0, 0); /* dst */ \
971 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
972 ir3_reg_create(instr, 0, IR3_REG_SSA | bflags)->instr = b; \
976 #define INSTR3(CAT, name) \
977 static inline struct ir3_instruction * \
978 ir3_##name(struct ir3_block *block, \
979 struct ir3_instruction *a, unsigned aflags, \
980 struct ir3_instruction *b, unsigned bflags, \
981 struct ir3_instruction *c, unsigned cflags) \
983 struct ir3_instruction *instr = \
984 ir3_instr_create(block, CAT, OPC_##name); \
985 ir3_reg_create(instr, 0, 0); /* dst */ \
986 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
987 ir3_reg_create(instr, 0, IR3_REG_SSA | bflags)->instr = b; \
988 ir3_reg_create(instr, 0, IR3_REG_SSA | cflags)->instr = c; \
992 /* cat0 instructions: */
998 /* cat2 instructions, most 2 src but some 1 src: */
1046 /* cat3 instructions: */
1048 INSTR3(3, MADSH_U16
)
1050 INSTR3(3, MADSH_M16
)
1064 /* cat4 instructions: */
1073 /* cat5 instructions: */
1077 static inline struct ir3_instruction
*
1078 ir3_SAM(struct ir3_block
*block
, opc_t opc
, type_t type
,
1079 unsigned wrmask
, unsigned flags
, unsigned samp
, unsigned tex
,
1080 struct ir3_instruction
*src0
, struct ir3_instruction
*src1
)
1082 struct ir3_instruction
*sam
;
1083 struct ir3_register
*reg
;
1085 sam
= ir3_instr_create(block
, 5, opc
);
1086 sam
->flags
|= flags
;
1087 ir3_reg_create(sam
, 0, 0)->wrmask
= wrmask
;
1089 reg
= ir3_reg_create(sam
, 0, IR3_REG_SSA
);
1090 reg
->wrmask
= (1 << (src0
->regs_count
- 1)) - 1;
1094 reg
= ir3_reg_create(sam
, 0, IR3_REG_SSA
);
1096 reg
->wrmask
= (1 << (src1
->regs_count
- 1)) - 1;
1098 sam
->cat5
.samp
= samp
;
1099 sam
->cat5
.tex
= tex
;
1100 sam
->cat5
.type
= type
;
1105 /* cat6 instructions: */
1110 /* ************************************************************************* */
1111 /* split this out or find some helper to use.. like main/bitset.h.. */
1117 typedef uint8_t regmask_t
[2 * MAX_REG
/ 8];
1119 static inline unsigned regmask_idx(struct ir3_register
*reg
)
1121 unsigned num
= (reg
->flags
& IR3_REG_RELATIV
) ? reg
->array
.offset
: reg
->num
;
1122 debug_assert(num
< MAX_REG
);
1123 if (reg
->flags
& IR3_REG_HALF
)
1128 static inline void regmask_init(regmask_t
*regmask
)
1130 memset(regmask
, 0, sizeof(*regmask
));
1133 static inline void regmask_set(regmask_t
*regmask
, struct ir3_register
*reg
)
1135 unsigned idx
= regmask_idx(reg
);
1136 if (reg
->flags
& IR3_REG_RELATIV
) {
1138 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1139 (*regmask
)[idx
/ 8] |= 1 << (idx
% 8);
1142 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1144 (*regmask
)[idx
/ 8] |= 1 << (idx
% 8);
1148 static inline void regmask_or(regmask_t
*dst
, regmask_t
*a
, regmask_t
*b
)
1151 for (i
= 0; i
< ARRAY_SIZE(*dst
); i
++)
1152 (*dst
)[i
] = (*a
)[i
] | (*b
)[i
];
1155 /* set bits in a if not set in b, conceptually:
1158 static inline void regmask_set_if_not(regmask_t
*a
,
1159 struct ir3_register
*reg
, regmask_t
*b
)
1161 unsigned idx
= regmask_idx(reg
);
1162 if (reg
->flags
& IR3_REG_RELATIV
) {
1164 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1165 if (!((*b
)[idx
/ 8] & (1 << (idx
% 8))))
1166 (*a
)[idx
/ 8] |= 1 << (idx
% 8);
1169 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1171 if (!((*b
)[idx
/ 8] & (1 << (idx
% 8))))
1172 (*a
)[idx
/ 8] |= 1 << (idx
% 8);
1176 static inline bool regmask_get(regmask_t
*regmask
,
1177 struct ir3_register
*reg
)
1179 unsigned idx
= regmask_idx(reg
);
1180 if (reg
->flags
& IR3_REG_RELATIV
) {
1182 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1183 if ((*regmask
)[idx
/ 8] & (1 << (idx
% 8)))
1187 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1189 if ((*regmask
)[idx
/ 8] & (1 << (idx
% 8)))
1195 /* ************************************************************************* */