2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 #include "util/u_debug.h"
32 #include "instr-a3xx.h"
33 #include "disasm.h" /* TODO move 'enum shader_t' somewhere else.. */
35 /* low level intermediate representation of an adreno shader program */
38 struct ir3_instruction
;
43 uint16_t instrs_count
; /* expanded to account for rpt's */
44 /* NOTE: max_reg, etc, does not include registers not touched
45 * by the shader (ie. vertex fetched via VFD_DECODE but not
48 int8_t max_reg
; /* highest GPR # used by shader */
55 IR3_REG_CONST
= 0x001,
56 IR3_REG_IMMED
= 0x002,
58 IR3_REG_RELATIV
= 0x008,
60 IR3_REG_NEGATE
= 0x020,
63 IR3_REG_POS_INF
= 0x100,
64 /* (ei) flag, end-input? Set on last bary, presumably to signal
65 * that the shader needs no more input:
68 /* meta-flags, for intermediate stages of IR, ie.
69 * before register assignment is done:
71 IR3_REG_SSA
= 0x1000, /* 'instr' is ptr to assigning instr */
72 IR3_REG_IA
= 0x2000, /* meta-input dst is "assigned" */
73 IR3_REG_ADDR
= 0x4000, /* register is a0.x */
77 * the component is in the low two bits of the reg #, so
78 * rN.x becomes: (N << 2) | x
88 /* for IR3_REG_SSA, src registers contain ptr back to
89 * assigning instruction.
91 struct ir3_instruction
*instr
;
94 /* used for cat5 instructions, but also for internal/IR level
95 * tracking of what registers are read/written by an instruction.
96 * wrmask may be a bad name since it is used to represent both
97 * src and dst that touch multiple adjacent registers.
100 /* for relative addressing, 32bits for array size is too small,
101 * but otoh we don't need to deal with disjoint sets, so instead
102 * use a simple size field (number of scalar components).
108 struct ir3_instruction
{
109 struct ir3_block
*block
;
113 /* (sy) flag is set on first instruction, and after sample
114 * instructions (probably just on RAW hazard).
116 IR3_INSTR_SY
= 0x001,
117 /* (ss) flag is set on first instruction, and first instruction
118 * to depend on the result of "long" instructions (RAW hazard):
120 * rcp, rsq, log2, exp2, sin, cos, sqrt
122 * It seems to synchronize until all in-flight instructions are
123 * completed, for example:
126 * add.f hr2.z, (neg)hr2.z, hc0.y
127 * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
130 * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
132 * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
133 * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
134 * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
136 * The last mul.f does not have (ss) set, presumably because the
137 * (ss) on the previous instruction does the job.
139 * The blob driver also seems to set it on WAR hazards, although
140 * not really clear if this is needed or just blob compiler being
141 * sloppy. So far I haven't found a case where removing the (ss)
142 * causes problems for WAR hazard, but I could just be getting
146 * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
149 IR3_INSTR_SS
= 0x002,
150 /* (jp) flag is set on jump targets:
152 IR3_INSTR_JP
= 0x004,
153 IR3_INSTR_UL
= 0x008,
154 IR3_INSTR_3D
= 0x010,
159 IR3_INSTR_S2EN
= 0x200,
160 /* meta-flags, for intermediate stages of IR, ie.
161 * before register assignment is done:
163 IR3_INSTR_MARK
= 0x1000,
170 struct ir3_register
**regs
;
178 type_t src_type
, dst_type
;
199 /* for meta-instructions, just used to hold extra data
200 * before instruction scheduling, etc
203 int off
; /* component/offset */
209 struct ir3_block
*if_block
, *else_block
;
212 struct ir3_block
*block
;
215 /* XXX keep this as big as all other union members! */
219 /* transient values used during various algorithms: */
221 /* The instruction depth is the max dependency distance to output.
223 * You can also think of it as the "cost", if we did any sort of
224 * optimization for register footprint. Ie. a value that is just
225 * result of moving a const to a reg would have a low cost, so to
226 * it could make sense to duplicate the instruction at various
227 * points where the result is needed to reduce register footprint.
229 * DEPTH_UNUSED used to mark unused instructions after depth
232 #define DEPTH_UNUSED ~0
236 /* Used during CP and RA stages. For fanin and shader inputs/
237 * outputs where we need a sequence of consecutive registers,
238 * keep track of each src instructions left (ie 'n-1') and right
239 * (ie 'n+1') neighbor. The front-end must insert enough mov's
240 * to ensure that each instruction has at most one left and at
241 * most one right neighbor. During the copy-propagation pass,
242 * we only remove mov's when we can preserve this constraint.
243 * And during the RA stage, we use the neighbor information to
244 * allocate a block of registers in one shot.
246 * TODO: maybe just add something like:
247 * struct ir3_instruction_ref {
248 * struct ir3_instruction *instr;
252 * Or can we get away without the refcnt stuff? It seems like
253 * it should be overkill.. the problem is if, potentially after
254 * already eliminating some mov's, if you have a single mov that
255 * needs to be grouped with it's neighbors in two different
256 * places (ex. shader output and a fanin).
259 struct ir3_instruction
*left
, *right
;
260 uint16_t left_cnt
, right_cnt
;
263 /* an instruction can reference at most one address register amongst
264 * it's src/dst registers. Beyond that, you need to insert mov's.
266 struct ir3_instruction
*address
;
268 /* in case of a instruction with relative dst instruction, we need to
269 * capture the dependency on the fanin for the previous values of
270 * the array elements. Since we don't know at compile time actually
271 * which array elements are written, this serves to preserve the
272 * unconditional write to array elements prior to the conditional
275 * TODO only cat1 can do indirect write.. we could maybe move this
276 * into instr->cat1.fanin (but would require the frontend to insert
279 struct ir3_instruction
*fanin
;
281 struct ir3_instruction
*next
;
287 static inline struct ir3_instruction
*
288 ir3_neighbor_first(struct ir3_instruction
*instr
)
290 while (instr
->cp
.left
)
291 instr
= instr
->cp
.left
;
295 static inline int ir3_neighbor_count(struct ir3_instruction
*instr
)
299 debug_assert(!instr
->cp
.left
);
301 while (instr
->cp
.right
) {
303 instr
= instr
->cp
.right
;
309 struct ir3_heap_chunk
;
312 unsigned instrs_count
, instrs_sz
;
313 struct ir3_instruction
**instrs
;
315 /* Track bary.f (and ldlv) instructions.. this is needed in
316 * scheduling to ensure that all varying fetches happen before
317 * any potential kill instructions. The hw gets grumpy if all
318 * threads in a group are killed before the last bary.f gets
319 * a chance to signal end of input (ei).
321 unsigned baryfs_count
, baryfs_sz
;
322 struct ir3_instruction
**baryfs
;
324 struct ir3_block
*block
;
326 struct ir3_heap_chunk
*chunk
;
331 unsigned ntemporaries
, ninputs
, noutputs
;
332 /* maps TGSI_FILE_TEMPORARY index back to the assigning instruction: */
333 struct ir3_instruction
**temporaries
;
334 struct ir3_instruction
**inputs
;
335 struct ir3_instruction
**outputs
;
336 /* only a single address register: */
337 struct ir3_instruction
*address
;
338 struct ir3_block
*parent
;
339 struct ir3_instruction
*head
;
342 struct ir3
* ir3_create(void);
343 void ir3_destroy(struct ir3
*shader
);
344 void * ir3_assemble(struct ir3
*shader
,
345 struct ir3_info
*info
, uint32_t gpu_id
);
346 void * ir3_alloc(struct ir3
*shader
, int sz
);
348 struct ir3_block
* ir3_block_create(struct ir3
*shader
,
349 unsigned ntmp
, unsigned nin
, unsigned nout
);
351 struct ir3_instruction
* ir3_instr_create(struct ir3_block
*block
,
352 int category
, opc_t opc
);
353 struct ir3_instruction
* ir3_instr_create2(struct ir3_block
*block
,
354 int category
, opc_t opc
, int nreg
);
355 struct ir3_instruction
* ir3_instr_clone(struct ir3_instruction
*instr
);
356 const char *ir3_instr_name(struct ir3_instruction
*instr
);
358 struct ir3_register
* ir3_reg_create(struct ir3_instruction
*instr
,
362 static inline bool ir3_instr_check_mark(struct ir3_instruction
*instr
)
364 if (instr
->flags
& IR3_INSTR_MARK
)
365 return true; /* already visited */
366 instr
->flags
|= IR3_INSTR_MARK
;
370 static inline void ir3_clear_mark(struct ir3
*shader
)
372 /* TODO would be nice to drop the instruction array.. for
373 * new compiler, _clear_mark() is all we use it for, and
374 * we could probably manage a linked list instead..
376 * Also, we'll probably want to mark instructions within
377 * a block, so tracking the list of instrs globally is
378 * unlikely to be what we want.
381 for (i
= 0; i
< shader
->instrs_count
; i
++) {
382 struct ir3_instruction
*instr
= shader
->instrs
[i
];
383 instr
->flags
&= ~IR3_INSTR_MARK
;
387 static inline int ir3_instr_regno(struct ir3_instruction
*instr
,
388 struct ir3_register
*reg
)
391 for (i
= 0; i
< instr
->regs_count
; i
++)
392 if (reg
== instr
->regs
[i
])
398 #define MAX_ARRAYS 16
406 static inline uint32_t regid(int num
, int comp
)
408 return (num
<< 2) | (comp
& 0x3);
411 static inline uint32_t reg_num(struct ir3_register
*reg
)
413 return reg
->num
>> 2;
416 static inline uint32_t reg_comp(struct ir3_register
*reg
)
418 return reg
->num
& 0x3;
421 static inline bool is_flow(struct ir3_instruction
*instr
)
423 return (instr
->category
== 0);
426 static inline bool is_kill(struct ir3_instruction
*instr
)
428 return is_flow(instr
) && (instr
->opc
== OPC_KILL
);
431 static inline bool is_nop(struct ir3_instruction
*instr
)
433 return is_flow(instr
) && (instr
->opc
== OPC_NOP
);
436 static inline bool is_alu(struct ir3_instruction
*instr
)
438 return (1 <= instr
->category
) && (instr
->category
<= 3);
441 static inline bool is_sfu(struct ir3_instruction
*instr
)
443 return (instr
->category
== 4);
446 static inline bool is_tex(struct ir3_instruction
*instr
)
448 return (instr
->category
== 5);
451 static inline bool is_mem(struct ir3_instruction
*instr
)
453 return (instr
->category
== 6);
456 static inline bool is_input(struct ir3_instruction
*instr
)
458 /* in some cases, ldlv is used to fetch varying without
459 * interpolation.. fortunately inloc is the first src
460 * register in either case
462 if (is_mem(instr
) && (instr
->opc
== OPC_LDLV
))
464 return (instr
->category
== 2) && (instr
->opc
== OPC_BARY_F
);
467 static inline bool is_meta(struct ir3_instruction
*instr
)
469 /* TODO how should we count PHI (and maybe fan-in/out) which
470 * might actually contribute some instructions to the final
473 return (instr
->category
== -1);
476 static inline bool writes_addr(struct ir3_instruction
*instr
)
478 if (instr
->regs_count
> 0) {
479 struct ir3_register
*dst
= instr
->regs
[0];
480 return !!(dst
->flags
& IR3_REG_ADDR
);
485 static inline bool writes_pred(struct ir3_instruction
*instr
)
487 if (instr
->regs_count
> 0) {
488 struct ir3_register
*dst
= instr
->regs
[0];
489 return reg_num(dst
) == REG_P0
;
494 /* returns defining instruction for reg */
495 /* TODO better name */
496 static inline struct ir3_instruction
*ssa(struct ir3_register
*reg
)
498 if (reg
->flags
& IR3_REG_SSA
)
503 static inline bool reg_gpr(struct ir3_register
*r
)
505 if (r
->flags
& (IR3_REG_CONST
| IR3_REG_IMMED
| IR3_REG_ADDR
))
507 if ((reg_num(r
) == REG_A0
) || (reg_num(r
) == REG_P0
))
512 #define array_insert(arr, val) do { \
513 if (arr ## _count == arr ## _sz) { \
514 arr ## _sz = MAX2(2 * arr ## _sz, 16); \
515 arr = realloc(arr, arr ## _sz * sizeof(arr[0])); \
517 arr[arr ##_count++] = val; \
520 /* iterator for an instructions's sources (reg), also returns src #: */
521 #define foreach_src_n(__srcreg, __n, __instr) \
522 if ((__instr)->regs_count) \
523 for (unsigned __cnt = (__instr)->regs_count - 1, __n = 0; __n < __cnt; __n++) \
524 if ((__srcreg = (__instr)->regs[__n + 1]))
526 /* iterator for an instructions's sources (reg): */
527 #define foreach_src(__srcreg, __instr) \
528 foreach_src_n(__srcreg, __i, __instr)
530 static inline unsigned __ssa_src_cnt(struct ir3_instruction
*instr
)
533 return instr
->regs_count
+ 2;
535 return instr
->regs_count
+ 1;
536 return instr
->regs_count
;
539 static inline struct ir3_instruction
* __ssa_src_n(struct ir3_instruction
*instr
, unsigned n
)
541 if (n
== (instr
->regs_count
+ 1))
543 if (n
== (instr
->regs_count
+ 0))
544 return instr
->address
;
545 return ssa(instr
->regs
[n
]);
548 #define __src_cnt(__instr) ((__instr)->address ? (__instr)->regs_count : (__instr)->regs_count - 1)
550 /* iterator for an instruction's SSA sources (instr), also returns src #: */
551 #define foreach_ssa_src_n(__srcinst, __n, __instr) \
552 if ((__instr)->regs_count) \
553 for (unsigned __cnt = __ssa_src_cnt(__instr) - 1, __n = 0; __n < __cnt; __n++) \
554 if ((__srcinst = __ssa_src_n(__instr, __n + 1)))
556 /* iterator for an instruction's SSA sources (instr): */
557 #define foreach_ssa_src(__srcinst, __instr) \
558 foreach_ssa_src_n(__srcinst, __i, __instr)
563 void ir3_dump(struct ir3
*shader
, const char *name
,
564 struct ir3_block
*block
/* XXX maybe 'block' ptr should move to ir3? */,
566 void ir3_dump_instr_single(struct ir3_instruction
*instr
);
567 void ir3_dump_instr_list(struct ir3_instruction
*instr
);
569 /* flatten if/else: */
570 int ir3_block_flatten(struct ir3_block
*block
);
572 /* depth calculation: */
573 int ir3_delayslots(struct ir3_instruction
*assigner
,
574 struct ir3_instruction
*consumer
, unsigned n
);
575 void ir3_block_depth(struct ir3_block
*block
);
577 /* copy-propagate: */
578 void ir3_block_cp(struct ir3_block
*block
);
580 /* group neightbors and insert mov's to resolve conflicts: */
581 void ir3_block_group(struct ir3_block
*block
);
584 int ir3_block_sched(struct ir3_block
*block
);
586 /* register assignment: */
587 int ir3_block_ra(struct ir3_block
*block
, enum shader_t type
,
588 bool frag_coord
, bool frag_face
);
591 void ir3_block_legalize(struct ir3_block
*block
,
592 bool *has_samp
, int *max_bary
);
595 /* ************************************************************************* */
596 /* split this out or find some helper to use.. like main/bitset.h.. */
602 typedef uint8_t regmask_t
[2 * MAX_REG
/ 8];
604 static inline unsigned regmask_idx(struct ir3_register
*reg
)
606 unsigned num
= reg
->num
;
607 debug_assert(num
< MAX_REG
);
608 if (reg
->flags
& IR3_REG_HALF
)
613 static inline void regmask_init(regmask_t
*regmask
)
615 memset(regmask
, 0, sizeof(*regmask
));
618 static inline void regmask_set(regmask_t
*regmask
, struct ir3_register
*reg
)
620 unsigned idx
= regmask_idx(reg
);
621 if (reg
->flags
& IR3_REG_RELATIV
) {
623 for (i
= 0; i
< reg
->size
; i
++, idx
++)
624 (*regmask
)[idx
/ 8] |= 1 << (idx
% 8);
627 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
629 (*regmask
)[idx
/ 8] |= 1 << (idx
% 8);
633 static inline void regmask_or(regmask_t
*dst
, regmask_t
*a
, regmask_t
*b
)
636 for (i
= 0; i
< ARRAY_SIZE(*dst
); i
++)
637 (*dst
)[i
] = (*a
)[i
] | (*b
)[i
];
640 /* set bits in a if not set in b, conceptually:
643 static inline void regmask_set_if_not(regmask_t
*a
,
644 struct ir3_register
*reg
, regmask_t
*b
)
646 unsigned idx
= regmask_idx(reg
);
647 if (reg
->flags
& IR3_REG_RELATIV
) {
649 for (i
= 0; i
< reg
->size
; i
++, idx
++)
650 if (!((*b
)[idx
/ 8] & (1 << (idx
% 8))))
651 (*a
)[idx
/ 8] |= 1 << (idx
% 8);
654 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
656 if (!((*b
)[idx
/ 8] & (1 << (idx
% 8))))
657 (*a
)[idx
/ 8] |= 1 << (idx
% 8);
661 static inline bool regmask_get(regmask_t
*regmask
,
662 struct ir3_register
*reg
)
664 unsigned idx
= regmask_idx(reg
);
665 if (reg
->flags
& IR3_REG_RELATIV
) {
667 for (i
= 0; i
< reg
->size
; i
++, idx
++)
668 if ((*regmask
)[idx
/ 8] & (1 << (idx
% 8)))
672 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
674 if ((*regmask
)[idx
/ 8] & (1 << (idx
% 8)))
680 /* ************************************************************************* */