2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 #include "util/u_debug.h"
31 #include "util/list.h"
33 #include "instr-a3xx.h"
34 #include "disasm.h" /* TODO move 'enum shader_t' somewhere else.. */
36 /* low level intermediate representation of an adreno shader program */
40 struct ir3_instruction
;
46 uint16_t instrs_count
; /* expanded to account for rpt's */
47 /* NOTE: max_reg, etc, does not include registers not touched
48 * by the shader (ie. vertex fetched via VFD_DECODE but not
51 int8_t max_reg
; /* highest GPR # used by shader */
58 IR3_REG_CONST
= 0x001,
59 IR3_REG_IMMED
= 0x002,
61 IR3_REG_RELATIV
= 0x008,
63 /* Most instructions, it seems, can do float abs/neg but not
64 * integer. The CP pass needs to know what is intended (int or
65 * float) in order to do the right thing. For this reason the
66 * abs/neg flags are split out into float and int variants. In
67 * addition, .b (bitwise) operations, the negate is actually a
68 * bitwise not, so split that out into a new flag to make it
77 IR3_REG_POS_INF
= 0x800,
78 /* (ei) flag, end-input? Set on last bary, presumably to signal
79 * that the shader needs no more input:
82 /* meta-flags, for intermediate stages of IR, ie.
83 * before register assignment is done:
85 IR3_REG_SSA
= 0x2000, /* 'instr' is ptr to assigning instr */
86 IR3_REG_PHI_SRC
= 0x4000, /* phi src, regs[0]->instr points to phi */
91 * the component is in the low two bits of the reg #, so
92 * rN.x becomes: (N << 2) | x
103 /* for IR3_REG_SSA, src registers contain ptr back to
104 * assigning instruction.
106 struct ir3_instruction
*instr
;
109 /* used for cat5 instructions, but also for internal/IR level
110 * tracking of what registers are read/written by an instruction.
111 * wrmask may be a bad name since it is used to represent both
112 * src and dst that touch multiple adjacent registers.
115 /* for relative addressing, 32bits for array size is too small,
116 * but otoh we don't need to deal with disjoint sets, so instead
117 * use a simple size field (number of scalar components).
123 struct ir3_instruction
{
124 struct ir3_block
*block
;
128 /* (sy) flag is set on first instruction, and after sample
129 * instructions (probably just on RAW hazard).
131 IR3_INSTR_SY
= 0x001,
132 /* (ss) flag is set on first instruction, and first instruction
133 * to depend on the result of "long" instructions (RAW hazard):
135 * rcp, rsq, log2, exp2, sin, cos, sqrt
137 * It seems to synchronize until all in-flight instructions are
138 * completed, for example:
141 * add.f hr2.z, (neg)hr2.z, hc0.y
142 * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
145 * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
147 * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
148 * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
149 * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
151 * The last mul.f does not have (ss) set, presumably because the
152 * (ss) on the previous instruction does the job.
154 * The blob driver also seems to set it on WAR hazards, although
155 * not really clear if this is needed or just blob compiler being
156 * sloppy. So far I haven't found a case where removing the (ss)
157 * causes problems for WAR hazard, but I could just be getting
161 * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
164 IR3_INSTR_SS
= 0x002,
165 /* (jp) flag is set on jump targets:
167 IR3_INSTR_JP
= 0x004,
168 IR3_INSTR_UL
= 0x008,
169 IR3_INSTR_3D
= 0x010,
174 IR3_INSTR_S2EN
= 0x200,
176 /* meta-flags, for intermediate stages of IR, ie.
177 * before register assignment is done:
179 IR3_INSTR_MARK
= 0x1000,
180 IR3_INSTR_UNUSED
= 0x2000,
187 struct ir3_register
**regs
;
193 struct ir3_block
*target
;
196 type_t src_type
, dst_type
;
218 /* for meta-instructions, just used to hold extra data
219 * before instruction scheduling, etc
222 int off
; /* component/offset */
228 /* used to temporarily hold reference to nir_phi_instr
229 * until we resolve the phi srcs
234 struct ir3_block
*block
;
238 /* transient values used during various algorithms: */
240 /* The instruction depth is the max dependency distance to output.
242 * You can also think of it as the "cost", if we did any sort of
243 * optimization for register footprint. Ie. a value that is just
244 * result of moving a const to a reg would have a low cost, so to
245 * it could make sense to duplicate the instruction at various
246 * points where the result is needed to reduce register footprint.
249 /* When we get to the RA stage, we no longer need depth, but
250 * we do need instruction's position/name:
258 /* Used during CP and RA stages. For fanin and shader inputs/
259 * outputs where we need a sequence of consecutive registers,
260 * keep track of each src instructions left (ie 'n-1') and right
261 * (ie 'n+1') neighbor. The front-end must insert enough mov's
262 * to ensure that each instruction has at most one left and at
263 * most one right neighbor. During the copy-propagation pass,
264 * we only remove mov's when we can preserve this constraint.
265 * And during the RA stage, we use the neighbor information to
266 * allocate a block of registers in one shot.
268 * TODO: maybe just add something like:
269 * struct ir3_instruction_ref {
270 * struct ir3_instruction *instr;
274 * Or can we get away without the refcnt stuff? It seems like
275 * it should be overkill.. the problem is if, potentially after
276 * already eliminating some mov's, if you have a single mov that
277 * needs to be grouped with it's neighbors in two different
278 * places (ex. shader output and a fanin).
281 struct ir3_instruction
*left
, *right
;
282 uint16_t left_cnt
, right_cnt
;
285 /* an instruction can reference at most one address register amongst
286 * it's src/dst registers. Beyond that, you need to insert mov's.
288 * NOTE: do not write this directly, use ir3_instr_set_address()
290 struct ir3_instruction
*address
;
292 /* in case of a instruction with relative dst instruction, we need to
293 * capture the dependency on the fanin for the previous values of
294 * the array elements. Since we don't know at compile time actually
295 * which array elements are written, this serves to preserve the
296 * unconditional write to array elements prior to the conditional
299 * TODO only cat1 can do indirect write.. we could maybe move this
300 * into instr->cat1.fanin (but would require the frontend to insert
303 struct ir3_instruction
*fanin
;
305 /* Entry in ir3_block's instruction list: */
306 struct list_head node
;
313 static inline struct ir3_instruction
*
314 ir3_neighbor_first(struct ir3_instruction
*instr
)
316 while (instr
->cp
.left
)
317 instr
= instr
->cp
.left
;
321 static inline int ir3_neighbor_count(struct ir3_instruction
*instr
)
325 debug_assert(!instr
->cp
.left
);
327 while (instr
->cp
.right
) {
329 instr
= instr
->cp
.right
;
335 struct ir3_heap_chunk
;
338 struct ir3_compiler
*compiler
;
340 unsigned ninputs
, noutputs
;
341 struct ir3_instruction
**inputs
;
342 struct ir3_instruction
**outputs
;
344 /* Track bary.f (and ldlv) instructions.. this is needed in
345 * scheduling to ensure that all varying fetches happen before
346 * any potential kill instructions. The hw gets grumpy if all
347 * threads in a group are killed before the last bary.f gets
348 * a chance to signal end of input (ei).
350 unsigned baryfs_count
, baryfs_sz
;
351 struct ir3_instruction
**baryfs
;
353 /* Track all indirect instructions (read and write). To avoid
354 * deadlock scenario where an address register gets scheduled,
355 * but other dependent src instructions cannot be scheduled due
356 * to dependency on a *different* address register value, the
357 * scheduler needs to ensure that all dependencies other than
358 * the instruction other than the address register are scheduled
359 * before the one that writes the address register. Having a
360 * convenient list of instructions that reference some address
361 * register simplifies this.
363 unsigned indirects_count
, indirects_sz
;
364 struct ir3_instruction
**indirects
;
365 /* and same for instructions that consume predicate register: */
366 unsigned predicates_count
, predicates_sz
;
367 struct ir3_instruction
**predicates
;
369 /* Track instructions which do not write a register but other-
370 * wise must not be discarded (such as kill, stg, etc)
372 unsigned keeps_count
, keeps_sz
;
373 struct ir3_instruction
**keeps
;
375 /* List of blocks: */
376 struct list_head block_list
;
379 struct ir3_heap_chunk
*chunk
;
382 typedef struct nir_block nir_block
;
385 struct list_head node
;
390 struct list_head instr_list
; /* list of ir3_instruction */
392 /* each block has either one or two successors.. in case of
393 * two successors, 'condition' decides which one to follow.
394 * A block preceding an if/else has two successors.
396 struct ir3_instruction
*condition
;
397 struct ir3_block
*successors
[2];
399 uint16_t start_ip
, end_ip
;
401 /* used for per-pass extra block data. Mainly used right
402 * now in RA step to track livein/liveout.
411 struct ir3
* ir3_create(struct ir3_compiler
*compiler
,
412 unsigned nin
, unsigned nout
);
413 void ir3_destroy(struct ir3
*shader
);
414 void * ir3_assemble(struct ir3
*shader
,
415 struct ir3_info
*info
, uint32_t gpu_id
);
416 void * ir3_alloc(struct ir3
*shader
, int sz
);
418 struct ir3_block
* ir3_block_create(struct ir3
*shader
);
420 struct ir3_instruction
* ir3_instr_create(struct ir3_block
*block
,
421 int category
, opc_t opc
);
422 struct ir3_instruction
* ir3_instr_create2(struct ir3_block
*block
,
423 int category
, opc_t opc
, int nreg
);
424 struct ir3_instruction
* ir3_instr_clone(struct ir3_instruction
*instr
);
425 const char *ir3_instr_name(struct ir3_instruction
*instr
);
427 struct ir3_register
* ir3_reg_create(struct ir3_instruction
*instr
,
430 void ir3_instr_set_address(struct ir3_instruction
*instr
,
431 struct ir3_instruction
*addr
);
433 static inline bool ir3_instr_check_mark(struct ir3_instruction
*instr
)
435 if (instr
->flags
& IR3_INSTR_MARK
)
436 return true; /* already visited */
437 instr
->flags
|= IR3_INSTR_MARK
;
441 void ir3_block_clear_mark(struct ir3_block
*block
);
442 void ir3_clear_mark(struct ir3
*shader
);
444 unsigned ir3_count_instructions(struct ir3
*ir
);
446 static inline int ir3_instr_regno(struct ir3_instruction
*instr
,
447 struct ir3_register
*reg
)
450 for (i
= 0; i
< instr
->regs_count
; i
++)
451 if (reg
== instr
->regs
[i
])
457 #define MAX_ARRAYS 16
465 static inline uint32_t regid(int num
, int comp
)
467 return (num
<< 2) | (comp
& 0x3);
470 static inline uint32_t reg_num(struct ir3_register
*reg
)
472 return reg
->num
>> 2;
475 static inline uint32_t reg_comp(struct ir3_register
*reg
)
477 return reg
->num
& 0x3;
480 static inline bool is_flow(struct ir3_instruction
*instr
)
482 return (instr
->category
== 0);
485 static inline bool is_kill(struct ir3_instruction
*instr
)
487 return is_flow(instr
) && (instr
->opc
== OPC_KILL
);
490 static inline bool is_nop(struct ir3_instruction
*instr
)
492 return is_flow(instr
) && (instr
->opc
== OPC_NOP
);
495 /* Is it a non-transformative (ie. not type changing) mov? This can
496 * also include absneg.s/absneg.f, which for the most part can be
497 * treated as a mov (single src argument).
499 static inline bool is_same_type_mov(struct ir3_instruction
*instr
)
501 struct ir3_register
*dst
= instr
->regs
[0];
503 /* mov's that write to a0.x or p0.x are special: */
504 if (dst
->num
== regid(REG_P0
, 0))
506 if (dst
->num
== regid(REG_A0
, 0))
509 if ((instr
->category
== 1) &&
510 (instr
->cat1
.src_type
== instr
->cat1
.dst_type
))
512 if ((instr
->category
== 2) && ((instr
->opc
== OPC_ABSNEG_F
) ||
513 (instr
->opc
== OPC_ABSNEG_S
)))
518 static inline bool is_alu(struct ir3_instruction
*instr
)
520 return (1 <= instr
->category
) && (instr
->category
<= 3);
523 static inline bool is_sfu(struct ir3_instruction
*instr
)
525 return (instr
->category
== 4);
528 static inline bool is_tex(struct ir3_instruction
*instr
)
530 return (instr
->category
== 5);
533 static inline bool is_mem(struct ir3_instruction
*instr
)
535 return (instr
->category
== 6);
539 is_store(struct ir3_instruction
*instr
)
542 /* these instructions, the "destination" register is
543 * actually a source, the address to store to.
545 switch (instr
->opc
) {
560 static inline bool is_load(struct ir3_instruction
*instr
)
563 switch (instr
->opc
) {
571 /* probably some others too.. */
580 static inline bool is_input(struct ir3_instruction
*instr
)
582 /* in some cases, ldlv is used to fetch varying without
583 * interpolation.. fortunately inloc is the first src
584 * register in either case
586 if (is_mem(instr
) && (instr
->opc
== OPC_LDLV
))
588 return (instr
->category
== 2) && (instr
->opc
== OPC_BARY_F
);
591 static inline bool is_meta(struct ir3_instruction
*instr
)
593 /* TODO how should we count PHI (and maybe fan-in/out) which
594 * might actually contribute some instructions to the final
597 return (instr
->category
== -1);
600 static inline bool writes_addr(struct ir3_instruction
*instr
)
602 if (instr
->regs_count
> 0) {
603 struct ir3_register
*dst
= instr
->regs
[0];
604 return reg_num(dst
) == REG_A0
;
609 static inline bool writes_pred(struct ir3_instruction
*instr
)
611 if (instr
->regs_count
> 0) {
612 struct ir3_register
*dst
= instr
->regs
[0];
613 return reg_num(dst
) == REG_P0
;
618 /* returns defining instruction for reg */
619 /* TODO better name */
620 static inline struct ir3_instruction
*ssa(struct ir3_register
*reg
)
622 if (reg
->flags
& IR3_REG_SSA
)
627 static inline bool conflicts(struct ir3_instruction
*a
,
628 struct ir3_instruction
*b
)
630 return (a
&& b
) && (a
!= b
);
633 static inline bool reg_gpr(struct ir3_register
*r
)
635 if (r
->flags
& (IR3_REG_CONST
| IR3_REG_IMMED
))
637 if ((reg_num(r
) == REG_A0
) || (reg_num(r
) == REG_P0
))
642 static inline type_t
half_type(type_t type
)
645 case TYPE_F32
: return TYPE_F16
;
646 case TYPE_U32
: return TYPE_U16
;
647 case TYPE_S32
: return TYPE_S16
;
658 /* some cat2 instructions (ie. those which are not float) can embed an
661 static inline bool ir3_cat2_int(opc_t opc
)
702 /* map cat2 instruction to valid abs/neg flags: */
703 static inline unsigned ir3_cat2_absneg(opc_t opc
)
720 return IR3_REG_FABS
| IR3_REG_FNEG
;
741 return IR3_REG_SABS
| IR3_REG_SNEG
;
762 /* map cat3 instructions to valid abs/neg flags: */
763 static inline unsigned ir3_cat3_absneg(opc_t opc
)
782 /* neg *may* work on 3rd src.. */
792 #define array_insert(arr, val) do { \
793 if (arr ## _count == arr ## _sz) { \
794 arr ## _sz = MAX2(2 * arr ## _sz, 16); \
795 arr = realloc(arr, arr ## _sz * sizeof(arr[0])); \
797 arr[arr ##_count++] = val; \
800 /* iterator for an instructions's sources (reg), also returns src #: */
801 #define foreach_src_n(__srcreg, __n, __instr) \
802 if ((__instr)->regs_count) \
803 for (unsigned __cnt = (__instr)->regs_count - 1, __n = 0; __n < __cnt; __n++) \
804 if ((__srcreg = (__instr)->regs[__n + 1]))
806 /* iterator for an instructions's sources (reg): */
807 #define foreach_src(__srcreg, __instr) \
808 foreach_src_n(__srcreg, __i, __instr)
810 static inline unsigned __ssa_src_cnt(struct ir3_instruction
*instr
)
813 return instr
->regs_count
+ 2;
815 return instr
->regs_count
+ 1;
816 return instr
->regs_count
;
819 static inline struct ir3_instruction
* __ssa_src_n(struct ir3_instruction
*instr
, unsigned n
)
821 if (n
== (instr
->regs_count
+ 1))
823 if (n
== (instr
->regs_count
+ 0))
824 return instr
->address
;
825 return ssa(instr
->regs
[n
]);
828 #define __src_cnt(__instr) ((__instr)->address ? (__instr)->regs_count : (__instr)->regs_count - 1)
830 /* iterator for an instruction's SSA sources (instr), also returns src #: */
831 #define foreach_ssa_src_n(__srcinst, __n, __instr) \
832 if ((__instr)->regs_count) \
833 for (unsigned __cnt = __ssa_src_cnt(__instr) - 1, __n = 0; __n < __cnt; __n++) \
834 if ((__srcinst = __ssa_src_n(__instr, __n + 1)))
836 /* iterator for an instruction's SSA sources (instr): */
837 #define foreach_ssa_src(__srcinst, __instr) \
838 foreach_ssa_src_n(__srcinst, __i, __instr)
842 void ir3_print(struct ir3
*ir
);
843 void ir3_print_instr(struct ir3_instruction
*instr
);
845 /* depth calculation: */
846 int ir3_delayslots(struct ir3_instruction
*assigner
,
847 struct ir3_instruction
*consumer
, unsigned n
);
848 void ir3_insert_by_depth(struct ir3_instruction
*instr
, struct list_head
*list
);
849 void ir3_depth(struct ir3
*ir
);
851 /* copy-propagate: */
852 void ir3_cp(struct ir3
*ir
);
854 /* group neighbors and insert mov's to resolve conflicts: */
855 void ir3_group(struct ir3
*ir
);
858 int ir3_sched(struct ir3
*ir
);
860 /* register assignment: */
861 struct ir3_ra_reg_set
* ir3_ra_alloc_reg_set(void *memctx
);
862 int ir3_ra(struct ir3
*ir3
, enum shader_t type
,
863 bool frag_coord
, bool frag_face
);
866 void ir3_legalize(struct ir3
*ir
, bool *has_samp
, int *max_bary
);
868 /* ************************************************************************* */
869 /* instruction helpers */
871 static inline struct ir3_instruction
*
872 ir3_MOV(struct ir3_block
*block
, struct ir3_instruction
*src
, type_t type
)
874 struct ir3_instruction
*instr
=
875 ir3_instr_create(block
, 1, 0);
876 ir3_reg_create(instr
, 0, 0); /* dst */
877 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
878 instr
->cat1
.src_type
= type
;
879 instr
->cat1
.dst_type
= type
;
883 static inline struct ir3_instruction
*
884 ir3_COV(struct ir3_block
*block
, struct ir3_instruction
*src
,
885 type_t src_type
, type_t dst_type
)
887 struct ir3_instruction
*instr
=
888 ir3_instr_create(block
, 1, 0);
889 ir3_reg_create(instr
, 0, 0); /* dst */
890 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
891 instr
->cat1
.src_type
= src_type
;
892 instr
->cat1
.dst_type
= dst_type
;
896 static inline struct ir3_instruction
*
897 ir3_NOP(struct ir3_block
*block
)
899 return ir3_instr_create(block
, 0, OPC_NOP
);
902 #define INSTR0(CAT, name) \
903 static inline struct ir3_instruction * \
904 ir3_##name(struct ir3_block *block) \
906 struct ir3_instruction *instr = \
907 ir3_instr_create(block, CAT, OPC_##name); \
911 #define INSTR1(CAT, name) \
912 static inline struct ir3_instruction * \
913 ir3_##name(struct ir3_block *block, \
914 struct ir3_instruction *a, unsigned aflags) \
916 struct ir3_instruction *instr = \
917 ir3_instr_create(block, CAT, OPC_##name); \
918 ir3_reg_create(instr, 0, 0); /* dst */ \
919 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
923 #define INSTR2(CAT, name) \
924 static inline struct ir3_instruction * \
925 ir3_##name(struct ir3_block *block, \
926 struct ir3_instruction *a, unsigned aflags, \
927 struct ir3_instruction *b, unsigned bflags) \
929 struct ir3_instruction *instr = \
930 ir3_instr_create(block, CAT, OPC_##name); \
931 ir3_reg_create(instr, 0, 0); /* dst */ \
932 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
933 ir3_reg_create(instr, 0, IR3_REG_SSA | bflags)->instr = b; \
937 #define INSTR3(CAT, name) \
938 static inline struct ir3_instruction * \
939 ir3_##name(struct ir3_block *block, \
940 struct ir3_instruction *a, unsigned aflags, \
941 struct ir3_instruction *b, unsigned bflags, \
942 struct ir3_instruction *c, unsigned cflags) \
944 struct ir3_instruction *instr = \
945 ir3_instr_create(block, CAT, OPC_##name); \
946 ir3_reg_create(instr, 0, 0); /* dst */ \
947 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
948 ir3_reg_create(instr, 0, IR3_REG_SSA | bflags)->instr = b; \
949 ir3_reg_create(instr, 0, IR3_REG_SSA | cflags)->instr = c; \
953 /* cat0 instructions: */
959 /* cat2 instructions, most 2 src but some 1 src: */
1007 /* cat3 instructions: */
1009 INSTR3(3, MADSH_U16
)
1011 INSTR3(3, MADSH_M16
)
1025 /* cat4 instructions: */
1034 /* cat5 instructions: */
1038 static inline struct ir3_instruction
*
1039 ir3_SAM(struct ir3_block
*block
, opc_t opc
, type_t type
,
1040 unsigned wrmask
, unsigned flags
, unsigned samp
, unsigned tex
,
1041 struct ir3_instruction
*src0
, struct ir3_instruction
*src1
)
1043 struct ir3_instruction
*sam
;
1044 struct ir3_register
*reg
;
1046 sam
= ir3_instr_create(block
, 5, opc
);
1047 sam
->flags
|= flags
;
1048 ir3_reg_create(sam
, 0, 0)->wrmask
= wrmask
;
1050 reg
= ir3_reg_create(sam
, 0, IR3_REG_SSA
);
1051 reg
->wrmask
= (1 << (src0
->regs_count
- 1)) - 1;
1055 reg
= ir3_reg_create(sam
, 0, IR3_REG_SSA
);
1057 reg
->wrmask
= (1 << (src1
->regs_count
- 1)) - 1;
1059 sam
->cat5
.samp
= samp
;
1060 sam
->cat5
.tex
= tex
;
1061 sam
->cat5
.type
= type
;
1066 /* cat6 instructions: */
1071 /* ************************************************************************* */
1072 /* split this out or find some helper to use.. like main/bitset.h.. */
1078 typedef uint8_t regmask_t
[2 * MAX_REG
/ 8];
1080 static inline unsigned regmask_idx(struct ir3_register
*reg
)
1082 unsigned num
= reg
->num
;
1083 debug_assert(num
< MAX_REG
);
1084 if (reg
->flags
& IR3_REG_HALF
)
1089 static inline void regmask_init(regmask_t
*regmask
)
1091 memset(regmask
, 0, sizeof(*regmask
));
1094 static inline void regmask_set(regmask_t
*regmask
, struct ir3_register
*reg
)
1096 unsigned idx
= regmask_idx(reg
);
1097 if (reg
->flags
& IR3_REG_RELATIV
) {
1099 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1100 (*regmask
)[idx
/ 8] |= 1 << (idx
% 8);
1103 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1105 (*regmask
)[idx
/ 8] |= 1 << (idx
% 8);
1109 static inline void regmask_or(regmask_t
*dst
, regmask_t
*a
, regmask_t
*b
)
1112 for (i
= 0; i
< ARRAY_SIZE(*dst
); i
++)
1113 (*dst
)[i
] = (*a
)[i
] | (*b
)[i
];
1116 /* set bits in a if not set in b, conceptually:
1119 static inline void regmask_set_if_not(regmask_t
*a
,
1120 struct ir3_register
*reg
, regmask_t
*b
)
1122 unsigned idx
= regmask_idx(reg
);
1123 if (reg
->flags
& IR3_REG_RELATIV
) {
1125 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1126 if (!((*b
)[idx
/ 8] & (1 << (idx
% 8))))
1127 (*a
)[idx
/ 8] |= 1 << (idx
% 8);
1130 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1132 if (!((*b
)[idx
/ 8] & (1 << (idx
% 8))))
1133 (*a
)[idx
/ 8] |= 1 << (idx
% 8);
1137 static inline bool regmask_get(regmask_t
*regmask
,
1138 struct ir3_register
*reg
)
1140 unsigned idx
= regmask_idx(reg
);
1141 if (reg
->flags
& IR3_REG_RELATIV
) {
1143 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1144 if ((*regmask
)[idx
/ 8] & (1 << (idx
% 8)))
1148 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1150 if ((*regmask
)[idx
/ 8] & (1 << (idx
% 8)))
1156 /* ************************************************************************* */