2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 #include "instr-a3xx.h"
31 #include "disasm.h" /* TODO move 'enum shader_t' somewhere else.. */
33 /* low level intermediate representation of an adreno shader program */
36 struct ir3_instruction
;
39 struct ir3
* fd_asm_parse(const char *src
);
43 uint16_t instrs_count
; /* expanded to account for rpt's */
44 /* NOTE: max_reg, etc, does not include registers not touched
45 * by the shader (ie. vertex fetched via VFD_DECODE but not
48 int8_t max_reg
; /* highest GPR # used by shader */
55 IR3_REG_CONST
= 0x001,
56 IR3_REG_IMMED
= 0x002,
58 IR3_REG_RELATIV
= 0x008,
60 IR3_REG_NEGATE
= 0x020,
63 IR3_REG_POS_INF
= 0x100,
64 /* (ei) flag, end-input? Set on last bary, presumably to signal
65 * that the shader needs no more input:
68 /* meta-flags, for intermediate stages of IR, ie.
69 * before register assignment is done:
71 IR3_REG_SSA
= 0x1000, /* 'instr' is ptr to assigning instr */
72 IR3_REG_IA
= 0x2000, /* meta-input dst is "assigned" */
73 IR3_REG_ADDR
= 0x4000, /* register is a0.x */
77 * the component is in the low two bits of the reg #, so
78 * rN.x becomes: (N << 2) | x
86 /* for IR3_REG_SSA, src registers contain ptr back to
87 * assigning instruction.
89 struct ir3_instruction
*instr
;
92 /* used for cat5 instructions, but also for internal/IR level
93 * tracking of what registers are read/written by an instruction.
94 * wrmask may be a bad name since it is used to represent both
95 * src and dst that touch multiple adjacent registers.
100 #define IR3_INSTR_SRCS 10
102 struct ir3_instruction
{
103 struct ir3_block
*block
;
107 /* (sy) flag is set on first instruction, and after sample
108 * instructions (probably just on RAW hazard).
110 IR3_INSTR_SY
= 0x001,
111 /* (ss) flag is set on first instruction, and first instruction
112 * to depend on the result of "long" instructions (RAW hazard):
114 * rcp, rsq, log2, exp2, sin, cos, sqrt
116 * It seems to synchronize until all in-flight instructions are
117 * completed, for example:
120 * add.f hr2.z, (neg)hr2.z, hc0.y
121 * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
124 * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
126 * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
127 * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
128 * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
130 * The last mul.f does not have (ss) set, presumably because the
131 * (ss) on the previous instruction does the job.
133 * The blob driver also seems to set it on WAR hazards, although
134 * not really clear if this is needed or just blob compiler being
135 * sloppy. So far I haven't found a case where removing the (ss)
136 * causes problems for WAR hazard, but I could just be getting
140 * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
143 IR3_INSTR_SS
= 0x002,
144 /* (jp) flag is set on jump targets:
146 IR3_INSTR_JP
= 0x004,
147 IR3_INSTR_UL
= 0x008,
148 IR3_INSTR_3D
= 0x010,
153 IR3_INSTR_S2EN
= 0x200,
154 /* meta-flags, for intermediate stages of IR, ie.
155 * before register assignment is done:
157 IR3_INSTR_MARK
= 0x1000,
161 struct ir3_register
*regs
[1 + IR3_INSTR_SRCS
];
169 type_t src_type
, dst_type
;
190 /* for meta-instructions, just used to hold extra data
191 * before instruction scheduling, etc
194 int off
; /* component/offset */
197 struct ir3_block
*if_block
, *else_block
;
200 struct ir3_block
*block
;
204 /* transient values used during various algorithms: */
206 /* The instruction depth is the max dependency distance to output.
208 * You can also think of it as the "cost", if we did any sort of
209 * optimization for register footprint. Ie. a value that is just
210 * result of moving a const to a reg would have a low cost, so to
211 * it could make sense to duplicate the instruction at various
212 * points where the result is needed to reduce register footprint.
216 struct ir3_instruction
*next
;
222 struct ir3_heap_chunk
;
225 unsigned instrs_count
, instrs_sz
;
226 struct ir3_instruction
**instrs
;
228 struct ir3_heap_chunk
*chunk
;
233 unsigned ntemporaries
, ninputs
, noutputs
;
234 /* maps TGSI_FILE_TEMPORARY index back to the assigning instruction: */
235 struct ir3_instruction
**temporaries
;
236 struct ir3_instruction
**inputs
;
237 struct ir3_instruction
**outputs
;
238 /* only a single address register: */
239 struct ir3_instruction
*address
;
240 struct ir3_block
*parent
;
241 struct ir3_instruction
*head
;
244 struct ir3
* ir3_create(void);
245 void ir3_destroy(struct ir3
*shader
);
246 void * ir3_assemble(struct ir3
*shader
,
247 struct ir3_info
*info
);
248 void * ir3_alloc(struct ir3
*shader
, int sz
);
250 struct ir3_block
* ir3_block_create(struct ir3
*shader
,
251 unsigned ntmp
, unsigned nin
, unsigned nout
);
253 struct ir3_instruction
* ir3_instr_create(struct ir3_block
*block
,
254 int category
, opc_t opc
);
255 struct ir3_instruction
* ir3_instr_clone(struct ir3_instruction
*instr
);
256 const char *ir3_instr_name(struct ir3_instruction
*instr
);
258 struct ir3_register
* ir3_reg_create(struct ir3_instruction
*instr
,
262 static inline bool ir3_instr_check_mark(struct ir3_instruction
*instr
)
264 if (instr
->flags
& IR3_INSTR_MARK
)
265 return true; /* already visited */
266 instr
->flags
^= IR3_INSTR_MARK
;
270 static inline void ir3_clear_mark(struct ir3
*shader
)
272 /* TODO would be nice to drop the instruction array.. for
273 * new compiler, _clear_mark() is all we use it for, and
274 * we could probably manage a linked list instead..
277 for (i
= 0; i
< shader
->instrs_count
; i
++) {
278 struct ir3_instruction
*instr
= shader
->instrs
[i
];
279 instr
->flags
&= ~IR3_INSTR_MARK
;
283 static inline int ir3_instr_regno(struct ir3_instruction
*instr
,
284 struct ir3_register
*reg
)
287 for (i
= 0; i
< instr
->regs_count
; i
++)
288 if (reg
== instr
->regs
[i
])
300 static inline uint32_t regid(int num
, int comp
)
302 return (num
<< 2) | (comp
& 0x3);
305 static inline uint32_t reg_num(struct ir3_register
*reg
)
307 return reg
->num
>> 2;
310 static inline uint32_t reg_comp(struct ir3_register
*reg
)
312 return reg
->num
& 0x3;
315 static inline bool is_flow(struct ir3_instruction
*instr
)
317 return (instr
->category
== 0);
320 static inline bool is_kill(struct ir3_instruction
*instr
)
322 return is_flow(instr
) && (instr
->opc
== OPC_KILL
);
325 static inline bool is_nop(struct ir3_instruction
*instr
)
327 return is_flow(instr
) && (instr
->opc
== OPC_NOP
);
330 static inline bool is_alu(struct ir3_instruction
*instr
)
332 return (1 <= instr
->category
) && (instr
->category
<= 3);
335 static inline bool is_sfu(struct ir3_instruction
*instr
)
337 return (instr
->category
== 4);
340 static inline bool is_tex(struct ir3_instruction
*instr
)
342 return (instr
->category
== 5);
345 static inline bool is_input(struct ir3_instruction
*instr
)
347 return (instr
->category
== 2) && (instr
->opc
== OPC_BARY_F
);
350 static inline bool is_meta(struct ir3_instruction
*instr
)
352 /* TODO how should we count PHI (and maybe fan-in/out) which
353 * might actually contribute some instructions to the final
356 return (instr
->category
== -1);
359 static inline bool is_addr(struct ir3_instruction
*instr
)
361 return is_meta(instr
) && (instr
->opc
== OPC_META_DEREF
);
364 static inline bool writes_addr(struct ir3_instruction
*instr
)
366 if (instr
->regs_count
> 0) {
367 struct ir3_register
*dst
= instr
->regs
[0];
368 return !!(dst
->flags
& IR3_REG_ADDR
);
373 static inline bool writes_pred(struct ir3_instruction
*instr
)
375 if (instr
->regs_count
> 0) {
376 struct ir3_register
*dst
= instr
->regs
[0];
377 return reg_num(dst
) == REG_P0
;
382 static inline bool reg_gpr(struct ir3_register
*r
)
384 if (r
->flags
& (IR3_REG_CONST
| IR3_REG_IMMED
| IR3_REG_RELATIV
| IR3_REG_SSA
| IR3_REG_ADDR
))
386 if ((reg_num(r
) == REG_A0
) || (reg_num(r
) == REG_P0
))
393 void ir3_dump(struct ir3
*shader
, const char *name
,
394 struct ir3_block
*block
/* XXX maybe 'block' ptr should move to ir3? */,
396 void ir3_dump_instr_single(struct ir3_instruction
*instr
);
397 void ir3_dump_instr_list(struct ir3_instruction
*instr
);
399 /* flatten if/else: */
400 int ir3_block_flatten(struct ir3_block
*block
);
402 /* depth calculation: */
403 int ir3_delayslots(struct ir3_instruction
*assigner
,
404 struct ir3_instruction
*consumer
, unsigned n
);
405 void ir3_block_depth(struct ir3_block
*block
);
407 /* copy-propagate: */
408 void ir3_block_cp(struct ir3_block
*block
);
411 int ir3_block_sched(struct ir3_block
*block
);
413 /* register assignment: */
414 int ir3_block_ra(struct ir3_block
*block
, enum shader_t type
,
415 bool half_precision
, bool frag_coord
, bool frag_face
,
416 bool *has_samp
, int *max_bary
);
419 # define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
422 /* ************************************************************************* */
423 /* split this out or find some helper to use.. like main/bitset.h.. */
429 typedef uint8_t regmask_t
[2 * MAX_REG
/ 8];
431 static inline unsigned regmask_idx(struct ir3_register
*reg
)
433 unsigned num
= reg
->num
;
434 assert(num
< MAX_REG
);
435 if (reg
->flags
& IR3_REG_HALF
)
440 static inline void regmask_init(regmask_t
*regmask
)
442 memset(regmask
, 0, sizeof(*regmask
));
445 static inline void regmask_set(regmask_t
*regmask
, struct ir3_register
*reg
)
447 unsigned idx
= regmask_idx(reg
);
449 for (i
= 0; i
< IR3_INSTR_SRCS
; i
++, idx
++)
450 if (reg
->wrmask
& (1 << i
))
451 (*regmask
)[idx
/ 8] |= 1 << (idx
% 8);
454 /* set bits in a if not set in b, conceptually:
457 static inline void regmask_set_if_not(regmask_t
*a
,
458 struct ir3_register
*reg
, regmask_t
*b
)
460 unsigned idx
= regmask_idx(reg
);
462 for (i
= 0; i
< IR3_INSTR_SRCS
; i
++, idx
++)
463 if (reg
->wrmask
& (1 << i
))
464 if (!((*b
)[idx
/ 8] & (1 << (idx
% 8))))
465 (*a
)[idx
/ 8] |= 1 << (idx
% 8);
468 static inline unsigned regmask_get(regmask_t
*regmask
,
469 struct ir3_register
*reg
)
471 unsigned idx
= regmask_idx(reg
);
473 for (i
= 0; i
< IR3_INSTR_SRCS
; i
++, idx
++)
474 if (reg
->wrmask
& (1 << i
))
475 if ((*regmask
)[idx
/ 8] & (1 << (idx
% 8)))
480 /* ************************************************************************* */