2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 #include "util/u_debug.h"
31 #include "util/list.h"
33 #include "instr-a3xx.h"
34 #include "disasm.h" /* TODO move 'enum shader_t' somewhere else.. */
36 /* low level intermediate representation of an adreno shader program */
40 struct ir3_instruction
;
45 uint16_t instrs_count
; /* expanded to account for rpt's */
46 /* NOTE: max_reg, etc, does not include registers not touched
47 * by the shader (ie. vertex fetched via VFD_DECODE but not
50 int8_t max_reg
; /* highest GPR # used by shader */
57 IR3_REG_CONST
= 0x001,
58 IR3_REG_IMMED
= 0x002,
60 IR3_REG_RELATIV
= 0x008,
62 /* Most instructions, it seems, can do float abs/neg but not
63 * integer. The CP pass needs to know what is intended (int or
64 * float) in order to do the right thing. For this reason the
65 * abs/neg flags are split out into float and int variants. In
66 * addition, .b (bitwise) operations, the negate is actually a
67 * bitwise not, so split that out into a new flag to make it
76 IR3_REG_POS_INF
= 0x800,
77 /* (ei) flag, end-input? Set on last bary, presumably to signal
78 * that the shader needs no more input:
81 /* meta-flags, for intermediate stages of IR, ie.
82 * before register assignment is done:
84 IR3_REG_SSA
= 0x2000, /* 'instr' is ptr to assigning instr */
85 IR3_REG_IA
= 0x4000, /* meta-input dst is "assigned" */
89 * the component is in the low two bits of the reg #, so
90 * rN.x becomes: (N << 2) | x
101 /* for IR3_REG_SSA, src registers contain ptr back to
102 * assigning instruction.
104 struct ir3_instruction
*instr
;
107 /* used for cat5 instructions, but also for internal/IR level
108 * tracking of what registers are read/written by an instruction.
109 * wrmask may be a bad name since it is used to represent both
110 * src and dst that touch multiple adjacent registers.
113 /* for relative addressing, 32bits for array size is too small,
114 * but otoh we don't need to deal with disjoint sets, so instead
115 * use a simple size field (number of scalar components).
121 struct ir3_instruction
{
122 struct ir3_block
*block
;
126 /* (sy) flag is set on first instruction, and after sample
127 * instructions (probably just on RAW hazard).
129 IR3_INSTR_SY
= 0x001,
130 /* (ss) flag is set on first instruction, and first instruction
131 * to depend on the result of "long" instructions (RAW hazard):
133 * rcp, rsq, log2, exp2, sin, cos, sqrt
135 * It seems to synchronize until all in-flight instructions are
136 * completed, for example:
139 * add.f hr2.z, (neg)hr2.z, hc0.y
140 * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
143 * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
145 * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
146 * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
147 * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
149 * The last mul.f does not have (ss) set, presumably because the
150 * (ss) on the previous instruction does the job.
152 * The blob driver also seems to set it on WAR hazards, although
153 * not really clear if this is needed or just blob compiler being
154 * sloppy. So far I haven't found a case where removing the (ss)
155 * causes problems for WAR hazard, but I could just be getting
159 * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
162 IR3_INSTR_SS
= 0x002,
163 /* (jp) flag is set on jump targets:
165 IR3_INSTR_JP
= 0x004,
166 IR3_INSTR_UL
= 0x008,
167 IR3_INSTR_3D
= 0x010,
172 IR3_INSTR_S2EN
= 0x200,
173 /* meta-flags, for intermediate stages of IR, ie.
174 * before register assignment is done:
176 IR3_INSTR_MARK
= 0x1000,
183 struct ir3_register
**regs
;
191 type_t src_type
, dst_type
;
212 /* for meta-instructions, just used to hold extra data
213 * before instruction scheduling, etc
216 int off
; /* component/offset */
222 struct ir3_block
*if_block
, *else_block
;
225 struct ir3_block
*block
;
228 /* XXX keep this as big as all other union members! */
232 /* transient values used during various algorithms: */
234 /* The instruction depth is the max dependency distance to output.
236 * You can also think of it as the "cost", if we did any sort of
237 * optimization for register footprint. Ie. a value that is just
238 * result of moving a const to a reg would have a low cost, so to
239 * it could make sense to duplicate the instruction at various
240 * points where the result is needed to reduce register footprint.
242 * DEPTH_UNUSED used to mark unused instructions after depth
245 #define DEPTH_UNUSED ~0
247 /* When we get to the RA stage, we no longer need depth, but
248 * we do need instruction's position/name:
256 /* Used during CP and RA stages. For fanin and shader inputs/
257 * outputs where we need a sequence of consecutive registers,
258 * keep track of each src instructions left (ie 'n-1') and right
259 * (ie 'n+1') neighbor. The front-end must insert enough mov's
260 * to ensure that each instruction has at most one left and at
261 * most one right neighbor. During the copy-propagation pass,
262 * we only remove mov's when we can preserve this constraint.
263 * And during the RA stage, we use the neighbor information to
264 * allocate a block of registers in one shot.
266 * TODO: maybe just add something like:
267 * struct ir3_instruction_ref {
268 * struct ir3_instruction *instr;
272 * Or can we get away without the refcnt stuff? It seems like
273 * it should be overkill.. the problem is if, potentially after
274 * already eliminating some mov's, if you have a single mov that
275 * needs to be grouped with it's neighbors in two different
276 * places (ex. shader output and a fanin).
279 struct ir3_instruction
*left
, *right
;
280 uint16_t left_cnt
, right_cnt
;
283 /* an instruction can reference at most one address register amongst
284 * it's src/dst registers. Beyond that, you need to insert mov's.
286 struct ir3_instruction
*address
;
288 /* in case of a instruction with relative dst instruction, we need to
289 * capture the dependency on the fanin for the previous values of
290 * the array elements. Since we don't know at compile time actually
291 * which array elements are written, this serves to preserve the
292 * unconditional write to array elements prior to the conditional
295 * TODO only cat1 can do indirect write.. we could maybe move this
296 * into instr->cat1.fanin (but would require the frontend to insert
299 struct ir3_instruction
*fanin
;
301 /* Entry in ir3_block's instruction list: */
302 struct list_head node
;
309 static inline struct ir3_instruction
*
310 ir3_neighbor_first(struct ir3_instruction
*instr
)
312 while (instr
->cp
.left
)
313 instr
= instr
->cp
.left
;
317 static inline int ir3_neighbor_count(struct ir3_instruction
*instr
)
321 debug_assert(!instr
->cp
.left
);
323 while (instr
->cp
.right
) {
325 instr
= instr
->cp
.right
;
331 struct ir3_heap_chunk
;
334 struct ir3_compiler
*compiler
;
336 unsigned ninputs
, noutputs
;
337 struct ir3_instruction
**inputs
;
338 struct ir3_instruction
**outputs
;
340 /* Track bary.f (and ldlv) instructions.. this is needed in
341 * scheduling to ensure that all varying fetches happen before
342 * any potential kill instructions. The hw gets grumpy if all
343 * threads in a group are killed before the last bary.f gets
344 * a chance to signal end of input (ei).
346 unsigned baryfs_count
, baryfs_sz
;
347 struct ir3_instruction
**baryfs
;
349 /* Track all indirect instructions (read and write). To avoid
350 * deadlock scenario where an address register gets scheduled,
351 * but other dependent src instructions cannot be scheduled due
352 * to dependency on a *different* address register value, the
353 * scheduler needs to ensure that all dependencies other than
354 * the instruction other than the address register are scheduled
355 * before the one that writes the address register. Having a
356 * convenient list of instructions that reference some address
357 * register simplifies this.
359 unsigned indirects_count
, indirects_sz
;
360 struct ir3_instruction
**indirects
;
361 /* and same for instructions that consume predicate register: */
362 unsigned predicates_count
, predicates_sz
;
363 struct ir3_instruction
**predicates
;
365 struct ir3_block
*block
;
367 struct ir3_heap_chunk
*chunk
;
372 /* only a single address register: */
373 struct ir3_instruction
*address
;
374 struct list_head instr_list
;
377 struct ir3
* ir3_create(struct ir3_compiler
*compiler
,
378 unsigned nin
, unsigned nout
);
379 void ir3_destroy(struct ir3
*shader
);
380 void * ir3_assemble(struct ir3
*shader
,
381 struct ir3_info
*info
, uint32_t gpu_id
);
382 void * ir3_alloc(struct ir3
*shader
, int sz
);
384 struct ir3_block
* ir3_block_create(struct ir3
*shader
);
386 struct ir3_instruction
* ir3_instr_create(struct ir3_block
*block
,
387 int category
, opc_t opc
);
388 struct ir3_instruction
* ir3_instr_create2(struct ir3_block
*block
,
389 int category
, opc_t opc
, int nreg
);
390 struct ir3_instruction
* ir3_instr_clone(struct ir3_instruction
*instr
);
391 const char *ir3_instr_name(struct ir3_instruction
*instr
);
393 struct ir3_register
* ir3_reg_create(struct ir3_instruction
*instr
,
397 static inline bool ir3_instr_check_mark(struct ir3_instruction
*instr
)
399 if (instr
->flags
& IR3_INSTR_MARK
)
400 return true; /* already visited */
401 instr
->flags
|= IR3_INSTR_MARK
;
405 static inline void ir3_clear_mark(struct ir3
*shader
)
407 /* TODO would be nice to drop the instruction array.. for
408 * new compiler, _clear_mark() is all we use it for, and
409 * we could probably manage a linked list instead..
411 * Also, we'll probably want to mark instructions within
412 * a block, so tracking the list of instrs globally is
413 * unlikely to be what we want.
415 list_for_each_entry (struct ir3_instruction
, instr
, &shader
->block
->instr_list
, node
)
416 instr
->flags
&= ~IR3_INSTR_MARK
;
419 static inline int ir3_instr_regno(struct ir3_instruction
*instr
,
420 struct ir3_register
*reg
)
423 for (i
= 0; i
< instr
->regs_count
; i
++)
424 if (reg
== instr
->regs
[i
])
430 #define MAX_ARRAYS 16
438 static inline uint32_t regid(int num
, int comp
)
440 return (num
<< 2) | (comp
& 0x3);
443 static inline uint32_t reg_num(struct ir3_register
*reg
)
445 return reg
->num
>> 2;
448 static inline uint32_t reg_comp(struct ir3_register
*reg
)
450 return reg
->num
& 0x3;
453 static inline bool is_flow(struct ir3_instruction
*instr
)
455 return (instr
->category
== 0);
458 static inline bool is_kill(struct ir3_instruction
*instr
)
460 return is_flow(instr
) && (instr
->opc
== OPC_KILL
);
463 static inline bool is_nop(struct ir3_instruction
*instr
)
465 return is_flow(instr
) && (instr
->opc
== OPC_NOP
);
468 /* Is it a non-transformative (ie. not type changing) mov? This can
469 * also include absneg.s/absneg.f, which for the most part can be
470 * treated as a mov (single src argument).
472 static inline bool is_same_type_mov(struct ir3_instruction
*instr
)
474 struct ir3_register
*dst
= instr
->regs
[0];
476 /* mov's that write to a0.x or p0.x are special: */
477 if (dst
->num
== regid(REG_P0
, 0))
479 if (dst
->num
== regid(REG_A0
, 0))
482 if ((instr
->category
== 1) &&
483 (instr
->cat1
.src_type
== instr
->cat1
.dst_type
))
485 if ((instr
->category
== 2) && ((instr
->opc
== OPC_ABSNEG_F
) ||
486 (instr
->opc
== OPC_ABSNEG_S
)))
491 static inline bool is_alu(struct ir3_instruction
*instr
)
493 return (1 <= instr
->category
) && (instr
->category
<= 3);
496 static inline bool is_sfu(struct ir3_instruction
*instr
)
498 return (instr
->category
== 4);
501 static inline bool is_tex(struct ir3_instruction
*instr
)
503 return (instr
->category
== 5);
506 static inline bool is_mem(struct ir3_instruction
*instr
)
508 return (instr
->category
== 6);
512 is_store(struct ir3_instruction
*instr
)
515 /* these instructions, the "destination" register is
516 * actually a source, the address to store to.
518 switch (instr
->opc
) {
533 static inline bool is_input(struct ir3_instruction
*instr
)
535 /* in some cases, ldlv is used to fetch varying without
536 * interpolation.. fortunately inloc is the first src
537 * register in either case
539 if (is_mem(instr
) && (instr
->opc
== OPC_LDLV
))
541 return (instr
->category
== 2) && (instr
->opc
== OPC_BARY_F
);
544 static inline bool is_meta(struct ir3_instruction
*instr
)
546 /* TODO how should we count PHI (and maybe fan-in/out) which
547 * might actually contribute some instructions to the final
550 return (instr
->category
== -1);
553 static inline bool writes_addr(struct ir3_instruction
*instr
)
555 if (instr
->regs_count
> 0) {
556 struct ir3_register
*dst
= instr
->regs
[0];
557 return reg_num(dst
) == REG_A0
;
562 static inline bool writes_pred(struct ir3_instruction
*instr
)
564 if (instr
->regs_count
> 0) {
565 struct ir3_register
*dst
= instr
->regs
[0];
566 return reg_num(dst
) == REG_P0
;
571 /* returns defining instruction for reg */
572 /* TODO better name */
573 static inline struct ir3_instruction
*ssa(struct ir3_register
*reg
)
575 if (reg
->flags
& IR3_REG_SSA
)
580 static inline bool conflicts(struct ir3_instruction
*a
,
581 struct ir3_instruction
*b
)
583 return (a
&& b
) && (a
!= b
);
586 static inline bool reg_gpr(struct ir3_register
*r
)
588 if (r
->flags
& (IR3_REG_CONST
| IR3_REG_IMMED
))
590 if ((reg_num(r
) == REG_A0
) || (reg_num(r
) == REG_P0
))
595 /* some cat2 instructions (ie. those which are not float) can embed an
598 static inline bool ir3_cat2_int(opc_t opc
)
639 /* map cat2 instruction to valid abs/neg flags: */
640 static inline unsigned ir3_cat2_absneg(opc_t opc
)
657 return IR3_REG_FABS
| IR3_REG_FNEG
;
678 return IR3_REG_SABS
| IR3_REG_SNEG
;
699 /* map cat3 instructions to valid abs/neg flags: */
700 static inline unsigned ir3_cat3_absneg(opc_t opc
)
719 /* neg *may* work on 3rd src.. */
729 #define array_insert(arr, val) do { \
730 if (arr ## _count == arr ## _sz) { \
731 arr ## _sz = MAX2(2 * arr ## _sz, 16); \
732 arr = realloc(arr, arr ## _sz * sizeof(arr[0])); \
734 arr[arr ##_count++] = val; \
737 /* iterator for an instructions's sources (reg), also returns src #: */
738 #define foreach_src_n(__srcreg, __n, __instr) \
739 if ((__instr)->regs_count) \
740 for (unsigned __cnt = (__instr)->regs_count - 1, __n = 0; __n < __cnt; __n++) \
741 if ((__srcreg = (__instr)->regs[__n + 1]))
743 /* iterator for an instructions's sources (reg): */
744 #define foreach_src(__srcreg, __instr) \
745 foreach_src_n(__srcreg, __i, __instr)
747 static inline unsigned __ssa_src_cnt(struct ir3_instruction
*instr
)
750 return instr
->regs_count
+ 2;
752 return instr
->regs_count
+ 1;
753 return instr
->regs_count
;
756 static inline struct ir3_instruction
* __ssa_src_n(struct ir3_instruction
*instr
, unsigned n
)
758 if (n
== (instr
->regs_count
+ 1))
760 if (n
== (instr
->regs_count
+ 0))
761 return instr
->address
;
762 return ssa(instr
->regs
[n
]);
765 #define __src_cnt(__instr) ((__instr)->address ? (__instr)->regs_count : (__instr)->regs_count - 1)
767 /* iterator for an instruction's SSA sources (instr), also returns src #: */
768 #define foreach_ssa_src_n(__srcinst, __n, __instr) \
769 if ((__instr)->regs_count) \
770 for (unsigned __cnt = __ssa_src_cnt(__instr) - 1, __n = 0; __n < __cnt; __n++) \
771 if ((__srcinst = __ssa_src_n(__instr, __n + 1)))
773 /* iterator for an instruction's SSA sources (instr): */
774 #define foreach_ssa_src(__srcinst, __instr) \
775 foreach_ssa_src_n(__srcinst, __i, __instr)
779 void ir3_print(struct ir3
*ir
);
780 void ir3_print_instr(struct ir3_instruction
*instr
);
782 /* depth calculation: */
783 int ir3_delayslots(struct ir3_instruction
*assigner
,
784 struct ir3_instruction
*consumer
, unsigned n
);
785 void ir3_insert_by_depth(struct ir3_instruction
*instr
, struct list_head
*list
);
786 void ir3_depth(struct ir3
*ir
);
788 /* copy-propagate: */
789 void ir3_cp(struct ir3
*ir
);
791 /* group neighbors and insert mov's to resolve conflicts: */
792 void ir3_group(struct ir3
*ir
);
795 int ir3_sched(struct ir3
*ir
);
797 /* register assignment: */
798 struct ir3_ra_reg_set
* ir3_ra_alloc_reg_set(void *memctx
);
799 int ir3_ra(struct ir3
*ir3
, enum shader_t type
,
800 bool frag_coord
, bool frag_face
);
803 void ir3_legalize(struct ir3
*ir
, bool *has_samp
, int *max_bary
);
805 /* ************************************************************************* */
806 /* instruction helpers */
808 static inline struct ir3_instruction
*
809 ir3_MOV(struct ir3_block
*block
, struct ir3_instruction
*src
, type_t type
)
811 struct ir3_instruction
*instr
=
812 ir3_instr_create(block
, 1, 0);
813 ir3_reg_create(instr
, 0, 0); /* dst */
814 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
815 instr
->cat1
.src_type
= type
;
816 instr
->cat1
.dst_type
= type
;
820 static inline struct ir3_instruction
*
821 ir3_COV(struct ir3_block
*block
, struct ir3_instruction
*src
,
822 type_t src_type
, type_t dst_type
)
824 struct ir3_instruction
*instr
=
825 ir3_instr_create(block
, 1, 0);
826 ir3_reg_create(instr
, 0, 0); /* dst */
827 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
828 instr
->cat1
.src_type
= src_type
;
829 instr
->cat1
.dst_type
= dst_type
;
833 static inline struct ir3_instruction
*
834 ir3_NOP(struct ir3_block
*block
)
836 return ir3_instr_create(block
, 0, OPC_NOP
);
839 #define INSTR1(CAT, name) \
840 static inline struct ir3_instruction * \
841 ir3_##name(struct ir3_block *block, \
842 struct ir3_instruction *a, unsigned aflags) \
844 struct ir3_instruction *instr = \
845 ir3_instr_create(block, CAT, OPC_##name); \
846 ir3_reg_create(instr, 0, 0); /* dst */ \
847 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
851 #define INSTR2(CAT, name) \
852 static inline struct ir3_instruction * \
853 ir3_##name(struct ir3_block *block, \
854 struct ir3_instruction *a, unsigned aflags, \
855 struct ir3_instruction *b, unsigned bflags) \
857 struct ir3_instruction *instr = \
858 ir3_instr_create(block, CAT, OPC_##name); \
859 ir3_reg_create(instr, 0, 0); /* dst */ \
860 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
861 ir3_reg_create(instr, 0, IR3_REG_SSA | bflags)->instr = b; \
865 #define INSTR3(CAT, name) \
866 static inline struct ir3_instruction * \
867 ir3_##name(struct ir3_block *block, \
868 struct ir3_instruction *a, unsigned aflags, \
869 struct ir3_instruction *b, unsigned bflags, \
870 struct ir3_instruction *c, unsigned cflags) \
872 struct ir3_instruction *instr = \
873 ir3_instr_create(block, CAT, OPC_##name); \
874 ir3_reg_create(instr, 0, 0); /* dst */ \
875 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
876 ir3_reg_create(instr, 0, IR3_REG_SSA | bflags)->instr = b; \
877 ir3_reg_create(instr, 0, IR3_REG_SSA | cflags)->instr = c; \
881 /* cat0 instructions: */
884 /* cat2 instructions, most 2 src but some 1 src: */
932 /* cat3 instructions: */
950 /* cat4 instructions: */
959 /* cat5 instructions: */
963 static inline struct ir3_instruction
*
964 ir3_SAM(struct ir3_block
*block
, opc_t opc
, type_t type
,
965 unsigned wrmask
, unsigned flags
, unsigned samp
, unsigned tex
,
966 struct ir3_instruction
*src0
, struct ir3_instruction
*src1
)
968 struct ir3_instruction
*sam
;
969 struct ir3_register
*reg
;
971 sam
= ir3_instr_create(block
, 5, opc
);
973 ir3_reg_create(sam
, 0, 0)->wrmask
= wrmask
;
975 reg
= ir3_reg_create(sam
, 0, IR3_REG_SSA
);
976 reg
->wrmask
= (1 << (src0
->regs_count
- 1)) - 1;
980 reg
= ir3_reg_create(sam
, 0, IR3_REG_SSA
);
982 reg
->wrmask
= (1 << (src1
->regs_count
- 1)) - 1;
984 sam
->cat5
.samp
= samp
;
986 sam
->cat5
.type
= type
;
991 /* cat6 instructions: */
995 /* ************************************************************************* */
996 /* split this out or find some helper to use.. like main/bitset.h.. */
1002 typedef uint8_t regmask_t
[2 * MAX_REG
/ 8];
1004 static inline unsigned regmask_idx(struct ir3_register
*reg
)
1006 unsigned num
= reg
->num
;
1007 debug_assert(num
< MAX_REG
);
1008 if (reg
->flags
& IR3_REG_HALF
)
1013 static inline void regmask_init(regmask_t
*regmask
)
1015 memset(regmask
, 0, sizeof(*regmask
));
1018 static inline void regmask_set(regmask_t
*regmask
, struct ir3_register
*reg
)
1020 unsigned idx
= regmask_idx(reg
);
1021 if (reg
->flags
& IR3_REG_RELATIV
) {
1023 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1024 (*regmask
)[idx
/ 8] |= 1 << (idx
% 8);
1027 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1029 (*regmask
)[idx
/ 8] |= 1 << (idx
% 8);
1033 static inline void regmask_or(regmask_t
*dst
, regmask_t
*a
, regmask_t
*b
)
1036 for (i
= 0; i
< ARRAY_SIZE(*dst
); i
++)
1037 (*dst
)[i
] = (*a
)[i
] | (*b
)[i
];
1040 /* set bits in a if not set in b, conceptually:
1043 static inline void regmask_set_if_not(regmask_t
*a
,
1044 struct ir3_register
*reg
, regmask_t
*b
)
1046 unsigned idx
= regmask_idx(reg
);
1047 if (reg
->flags
& IR3_REG_RELATIV
) {
1049 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1050 if (!((*b
)[idx
/ 8] & (1 << (idx
% 8))))
1051 (*a
)[idx
/ 8] |= 1 << (idx
% 8);
1054 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1056 if (!((*b
)[idx
/ 8] & (1 << (idx
% 8))))
1057 (*a
)[idx
/ 8] |= 1 << (idx
% 8);
1061 static inline bool regmask_get(regmask_t
*regmask
,
1062 struct ir3_register
*reg
)
1064 unsigned idx
= regmask_idx(reg
);
1065 if (reg
->flags
& IR3_REG_RELATIV
) {
1067 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1068 if ((*regmask
)[idx
/ 8] & (1 << (idx
% 8)))
1072 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1074 if ((*regmask
)[idx
/ 8] & (1 << (idx
% 8)))
1080 /* ************************************************************************* */