src/gallium/drivers/freedreno/ir3/ir3.h

   1 /*
   2  * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #ifndef IR3_H_
  25 #define IR3_H_
  26
  27 #include <stdint.h>
  28 #include <stdbool.h>
  29
  30 #include "instr-a3xx.h"
  31 #include "disasm.h"  /* TODO move 'enum shader_t' somewhere else.. */
  32
  33 /* low level intermediate representation of an adreno shader program */
  34
  35 struct ir3;
  36 struct ir3_instruction;
  37 struct ir3_block;
  38
  39 struct ir3 * fd_asm_parse(const char *src);
  40
  41 struct ir3_info {
  42         uint16_t sizedwords;
  43         uint16_t instrs_count;   /* expanded to account for rpt's */
  44         /* NOTE: max_reg, etc, does not include registers not touched
  45          * by the shader (ie. vertex fetched via VFD_DECODE but not
  46          * touched by shader)
  47          */
  48         int8_t   max_reg;   /* highest GPR # used by shader */
  49         int8_t   max_half_reg;
  50         int8_t   max_const;
  51 };
  52
  53 struct ir3_register {
  54         enum {
  55                 IR3_REG_CONST  = 0x001,
  56                 IR3_REG_IMMED  = 0x002,
  57                 IR3_REG_HALF   = 0x004,
  58                 IR3_REG_RELATIV= 0x008,
  59                 IR3_REG_R      = 0x010,
  60                 IR3_REG_NEGATE = 0x020,
  61                 IR3_REG_ABS    = 0x040,
  62                 IR3_REG_EVEN   = 0x080,
  63                 IR3_REG_POS_INF= 0x100,
  64                 /* (ei) flag, end-input?  Set on last bary, presumably to signal
  65                  * that the shader needs no more input:
  66                  */
  67                 IR3_REG_EI     = 0x200,
  68                 /* meta-flags, for intermediate stages of IR, ie.
  69                  * before register assignment is done:
  70                  */
  71                 IR3_REG_SSA    = 0x1000,   /* 'instr' is ptr to assigning instr */
  72                 IR3_REG_IA     = 0x2000,   /* meta-input dst is "assigned" */
  73                 IR3_REG_ADDR   = 0x4000,   /* register is a0.x */
  74         } flags;
  75         union {
  76                 /* normal registers:
  77                  * the component is in the low two bits of the reg #, so
  78                  * rN.x becomes: (N << 2) | x
  79                  */
  80                 int num;
  81                 /* immediate: */
  82                 int     iim_val;
  83                 float   fim_val;
  84                 /* relative: */
  85                 int offset;
  86                 /* for IR3_REG_SSA, src registers contain ptr back to
  87                  * assigning instruction.
  88                  */
  89                 struct ir3_instruction *instr;
  90         };
  91
  92         /* used for cat5 instructions, but also for internal/IR level
  93          * tracking of what registers are read/written by an instruction.
  94          * wrmask may be a bad name since it is used to represent both
  95          * src and dst that touch multiple adjacent registers.
  96          */
  97         int wrmask;
  98 };
  99
 100 struct ir3_instruction {
 101         struct ir3_block *block;
 102         int category;
 103         opc_t opc;
 104         enum {
 105                 /* (sy) flag is set on first instruction, and after sample
 106                  * instructions (probably just on RAW hazard).
 107                  */
 108                 IR3_INSTR_SY    = 0x001,
 109                 /* (ss) flag is set on first instruction, and first instruction
 110                  * to depend on the result of "long" instructions (RAW hazard):
 111                  *
 112                  *   rcp, rsq, log2, exp2, sin, cos, sqrt
 113                  *
 114                  * It seems to synchronize until all in-flight instructions are
 115                  * completed, for example:
 116                  *
 117                  *   rsq hr1.w, hr1.w
 118                  *   add.f hr2.z, (neg)hr2.z, hc0.y
 119                  *   mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
 120                  *   rsq hr2.x, hr2.x
 121                  *   (rpt1)nop
 122                  *   mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
 123                  *   nop
 124                  *   mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
 125                  *   (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
 126                  *   (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
 127                  *
 128                  * The last mul.f does not have (ss) set, presumably because the
 129                  * (ss) on the previous instruction does the job.
 130                  *
 131                  * The blob driver also seems to set it on WAR hazards, although
 132                  * not really clear if this is needed or just blob compiler being
 133                  * sloppy.  So far I haven't found a case where removing the (ss)
 134                  * causes problems for WAR hazard, but I could just be getting
 135                  * lucky:
 136                  *
 137                  *   rcp r1.y, r3.y
 138                  *   (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
 139                  *
 140                  */
 141                 IR3_INSTR_SS    = 0x002,
 142                 /* (jp) flag is set on jump targets:
 143                  */
 144                 IR3_INSTR_JP    = 0x004,
 145                 IR3_INSTR_UL    = 0x008,
 146                 IR3_INSTR_3D    = 0x010,
 147                 IR3_INSTR_A     = 0x020,
 148                 IR3_INSTR_O     = 0x040,
 149                 IR3_INSTR_P     = 0x080,
 150                 IR3_INSTR_S     = 0x100,
 151                 IR3_INSTR_S2EN  = 0x200,
 152                 /* meta-flags, for intermediate stages of IR, ie.
 153                  * before register assignment is done:
 154                  */
 155                 IR3_INSTR_MARK  = 0x1000,
 156         } flags;
 157         int repeat;
 158         unsigned regs_count;
 159         struct ir3_register *regs[5];
 160         union {
 161                 struct {
 162                         char inv;
 163                         char comp;
 164                         int  immed;
 165                 } cat0;
 166                 struct {
 167                         type_t src_type, dst_type;
 168                 } cat1;
 169                 struct {
 170                         enum {
 171                                 IR3_COND_LT = 0,
 172                                 IR3_COND_LE = 1,
 173                                 IR3_COND_GT = 2,
 174                                 IR3_COND_GE = 3,
 175                                 IR3_COND_EQ = 4,
 176                                 IR3_COND_NE = 5,
 177                         } condition;
 178                 } cat2;
 179                 struct {
 180                         unsigned samp, tex;
 181                         type_t type;
 182                 } cat5;
 183                 struct {
 184                         type_t type;
 185                         int offset;
 186                         int iim_val;
 187                 } cat6;
 188                 /* for meta-instructions, just used to hold extra data
 189                  * before instruction scheduling, etc
 190                  */
 191                 struct {
 192                         int off;              /* component/offset */
 193                 } fo;
 194                 struct {
 195                         struct ir3_block *if_block, *else_block;
 196                 } flow;
 197                 struct {
 198                         struct ir3_block *block;
 199                 } inout;
 200         };
 201
 202         /* transient values used during various algorithms: */
 203         union {
 204                 /* The instruction depth is the max dependency distance to output.
 205                  *
 206                  * You can also think of it as the "cost", if we did any sort of
 207                  * optimization for register footprint.  Ie. a value that is  just
 208                  * result of moving a const to a reg would have a low cost,  so to
 209                  * it could make sense to duplicate the instruction at various
 210                  * points where the result is needed to reduce register footprint.
 211                  */
 212                 unsigned depth;
 213         };
 214         struct ir3_instruction *next;
 215 #ifdef DEBUG
 216         uint32_t serialno;
 217 #endif
 218 };
 219
 220 struct ir3_heap_chunk;
 221
 222 struct ir3 {
 223         unsigned instrs_count, instrs_sz;
 224         struct ir3_instruction **instrs;
 225         unsigned heap_idx;
 226         struct ir3_heap_chunk *chunk;
 227 };
 228
 229 struct ir3_block {
 230         struct ir3 *shader;
 231         unsigned ntemporaries, ninputs, noutputs;
 232         /* maps TGSI_FILE_TEMPORARY index back to the assigning instruction: */
 233         struct ir3_instruction **temporaries;
 234         struct ir3_instruction **inputs;
 235         struct ir3_instruction **outputs;
 236         /* only a single address register: */
 237         struct ir3_instruction *address;
 238         struct ir3_block *parent;
 239         struct ir3_instruction *head;
 240 };
 241
 242 struct ir3 * ir3_create(void);
 243 void ir3_destroy(struct ir3 *shader);
 244 void * ir3_assemble(struct ir3 *shader,
 245                 struct ir3_info *info);
 246 void * ir3_alloc(struct ir3 *shader, int sz);
 247
 248 struct ir3_block * ir3_block_create(struct ir3 *shader,
 249                 unsigned ntmp, unsigned nin, unsigned nout);
 250
 251 struct ir3_instruction * ir3_instr_create(struct ir3_block *block,
 252                 int category, opc_t opc);
 253 struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr);
 254 const char *ir3_instr_name(struct ir3_instruction *instr);
 255
 256 struct ir3_register * ir3_reg_create(struct ir3_instruction *instr,
 257                 int num, int flags);
 258
 259
 260 static inline bool ir3_instr_check_mark(struct ir3_instruction *instr)
 261 {
 262         if (instr->flags & IR3_INSTR_MARK)
 263                 return true;  /* already visited */
 264         instr->flags ^= IR3_INSTR_MARK;
 265         return false;
 266 }
 267
 268 static inline void ir3_clear_mark(struct ir3 *shader)
 269 {
 270         /* TODO would be nice to drop the instruction array.. for
 271          * new compiler, _clear_mark() is all we use it for, and
 272          * we could probably manage a linked list instead..
 273          */
 274         unsigned i;
 275         for (i = 0; i < shader->instrs_count; i++) {
 276                 struct ir3_instruction *instr = shader->instrs[i];
 277                 instr->flags &= ~IR3_INSTR_MARK;
 278         }
 279 }
 280
 281 static inline int ir3_instr_regno(struct ir3_instruction *instr,
 282                 struct ir3_register *reg)
 283 {
 284         unsigned i;
 285         for (i = 0; i < instr->regs_count; i++)
 286                 if (reg == instr->regs[i])
 287                         return i;
 288         return -1;
 289 }
 290
 291
 292 /* comp:
 293  *   0 - x
 294  *   1 - y
 295  *   2 - z
 296  *   3 - w
 297  */
 298 static inline uint32_t regid(int num, int comp)
 299 {
 300         return (num << 2) | (comp & 0x3);
 301 }
 302
 303 static inline uint32_t reg_num(struct ir3_register *reg)
 304 {
 305         return reg->num >> 2;
 306 }
 307
 308 static inline uint32_t reg_comp(struct ir3_register *reg)
 309 {
 310         return reg->num & 0x3;
 311 }
 312
 313 static inline bool is_flow(struct ir3_instruction *instr)
 314 {
 315         return (instr->category == 0);
 316 }
 317
 318 static inline bool is_kill(struct ir3_instruction *instr)
 319 {
 320         return is_flow(instr) && (instr->opc == OPC_KILL);
 321 }
 322
 323 static inline bool is_nop(struct ir3_instruction *instr)
 324 {
 325         return is_flow(instr) && (instr->opc == OPC_NOP);
 326 }
 327
 328 static inline bool is_alu(struct ir3_instruction *instr)
 329 {
 330         return (1 <= instr->category) && (instr->category <= 3);
 331 }
 332
 333 static inline bool is_sfu(struct ir3_instruction *instr)
 334 {
 335         return (instr->category == 4);
 336 }
 337
 338 static inline bool is_tex(struct ir3_instruction *instr)
 339 {
 340         return (instr->category == 5);
 341 }
 342
 343 static inline bool is_input(struct ir3_instruction *instr)
 344 {
 345         return (instr->category == 2) && (instr->opc == OPC_BARY_F);
 346 }
 347
 348 static inline bool is_meta(struct ir3_instruction *instr)
 349 {
 350         /* TODO how should we count PHI (and maybe fan-in/out) which
 351          * might actually contribute some instructions to the final
 352          * result?
 353          */
 354         return (instr->category == -1);
 355 }
 356
 357 static inline bool is_addr(struct ir3_instruction *instr)
 358 {
 359         return is_meta(instr) && (instr->opc == OPC_META_DEREF);
 360 }
 361
 362 static inline bool writes_addr(struct ir3_instruction *instr)
 363 {
 364         if (instr->regs_count > 0) {
 365                 struct ir3_register *dst = instr->regs[0];
 366                 return !!(dst->flags & IR3_REG_ADDR);
 367         }
 368         return false;
 369 }
 370
 371 static inline bool writes_pred(struct ir3_instruction *instr)
 372 {
 373         if (instr->regs_count > 0) {
 374                 struct ir3_register *dst = instr->regs[0];
 375                 return reg_num(dst) == REG_P0;
 376         }
 377         return false;
 378 }
 379
 380 static inline bool reg_gpr(struct ir3_register *r)
 381 {
 382         if (r->flags & (IR3_REG_CONST | IR3_REG_IMMED | IR3_REG_RELATIV | IR3_REG_SSA | IR3_REG_ADDR))
 383                 return false;
 384         if ((reg_num(r) == REG_A0) || (reg_num(r) == REG_P0))
 385                 return false;
 386         return true;
 387 }
 388
 389 /* dump: */
 390 #include <stdio.h>
 391 void ir3_dump(struct ir3 *shader, const char *name,
 392                 struct ir3_block *block /* XXX maybe 'block' ptr should move to ir3? */,
 393                 FILE *f);
 394 void ir3_dump_instr_single(struct ir3_instruction *instr);
 395 void ir3_dump_instr_list(struct ir3_instruction *instr);
 396
 397 /* flatten if/else: */
 398 int ir3_block_flatten(struct ir3_block *block);
 399
 400 /* depth calculation: */
 401 int ir3_delayslots(struct ir3_instruction *assigner,
 402                 struct ir3_instruction *consumer, unsigned n);
 403 void ir3_block_depth(struct ir3_block *block);
 404
 405 /* copy-propagate: */
 406 void ir3_block_cp(struct ir3_block *block);
 407
 408 /* scheduling: */
 409 void ir3_block_sched(struct ir3_block *block);
 410
 411 /* register assignment: */
 412 int ir3_block_ra(struct ir3_block *block, enum shader_t type,
 413                 bool half_precision, bool frag_coord, bool frag_face,
 414                 bool *has_samp);
 415
 416 #ifndef ARRAY_SIZE
 417 #  define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
 418 #endif
 419
 420 /* ************************************************************************* */
 421 /* split this out or find some helper to use.. like main/bitset.h.. */
 422
 423 #include <string.h>
 424
 425 #define MAX_REG 256
 426
 427 typedef uint8_t regmask_t[2 * MAX_REG / 8];
 428
 429 static inline unsigned regmask_idx(struct ir3_register *reg)
 430 {
 431         unsigned num = reg->num;
 432         assert(num < MAX_REG);
 433         if (reg->flags & IR3_REG_HALF)
 434                 num += MAX_REG;
 435         return num;
 436 }
 437
 438 static inline void regmask_init(regmask_t *regmask)
 439 {
 440         memset(regmask, 0, sizeof(*regmask));
 441 }
 442
 443 static inline void regmask_set(regmask_t *regmask, struct ir3_register *reg)
 444 {
 445         unsigned idx = regmask_idx(reg);
 446         unsigned i;
 447         for (i = 0; i < 4; i++, idx++)
 448                 if (reg->wrmask & (1 << i))
 449                         (*regmask)[idx / 8] |= 1 << (idx % 8);
 450 }
 451
 452 /* set bits in a if not set in b, conceptually:
 453  *   a |= (reg & ~b)
 454  */
 455 static inline void regmask_set_if_not(regmask_t *a,
 456                 struct ir3_register *reg, regmask_t *b)
 457 {
 458         unsigned idx = regmask_idx(reg);
 459         unsigned i;
 460         for (i = 0; i < 4; i++, idx++)
 461                 if (reg->wrmask & (1 << i))
 462                         if (!((*b)[idx / 8] & (1 << (idx % 8))))
 463                                 (*a)[idx / 8] |= 1 << (idx % 8);
 464 }
 465
 466 static inline unsigned regmask_get(regmask_t *regmask,
 467                 struct ir3_register *reg)
 468 {
 469         unsigned idx = regmask_idx(reg);
 470         unsigned i;
 471         for (i = 0; i < 4; i++, idx++)
 472                 if (reg->wrmask & (1 << i))
 473                         if ((*regmask)[idx / 8] & (1 << (idx % 8)))
 474                                 return true;
 475         return false;
 476 }
 477
 478 /* ************************************************************************* */
 479
 480 #endif /* IR3_H_ */