1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
36 #include "freedreno_util.h"
38 #include "ir3_compiler.h"
39 #include "ir3_shader.h"
42 #include "instr-a3xx.h"
47 struct ir3_compiler
*compiler
;
52 struct ir3_shader_variant
*so
;
54 struct ir3_block
*block
; /* the current block */
55 struct ir3_block
*in_block
; /* block created for shader inputs */
57 nir_function_impl
*impl
;
59 /* For fragment shaders, from the hw perspective the only
60 * actual input is r0.xy position register passed to bary.f.
61 * But TGSI doesn't know that, it still declares things as
62 * IN[] registers. So we do all the input tracking normally
63 * and fix things up after compile_instructions()
65 * NOTE that frag_pos is the hardware position (possibly it
66 * is actually an index or tag or some such.. it is *not*
67 * values that can be directly used for gl_FragCoord..)
69 struct ir3_instruction
*frag_pos
, *frag_face
, *frag_coord
[4];
71 /* For vertex shaders, keep track of the system values sources */
72 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
74 /* Compute shader inputs: */
75 struct ir3_instruction
*local_invocation_id
, *work_group_id
;
77 /* mapping from nir_register to defining instruction: */
78 struct hash_table
*def_ht
;
82 /* a common pattern for indirect addressing is to request the
83 * same address register multiple times. To avoid generating
84 * duplicate instruction sequences (which our backend does not
85 * try to clean up, since that should be done as the NIR stage)
86 * we cache the address value generated for a given src value:
88 * Note that we have to cache these per alignment, since same
89 * src used for an array of vec1 cannot be also used for an
92 struct hash_table
*addr_ht
[4];
94 /* last dst array, for indirect we need to insert a var-store.
96 struct ir3_instruction
**last_dst
;
99 /* maps nir_block to ir3_block, mostly for the purposes of
100 * figuring out the blocks successors
102 struct hash_table
*block_ht
;
104 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
105 * so we need to use ldlv.u32 to load the varying directly:
109 /* on a3xx, we need to add one to # of array levels:
113 /* on a3xx, we need to scale up integer coords for isaml based
116 bool unminify_coords
;
118 /* on a4xx, for array textures we need to add 0.5 to the array
121 bool array_index_add_half
;
123 /* on a4xx, bitmask of samplers which need astc+srgb workaround: */
126 unsigned max_texture_index
;
128 /* set if we encounter something we can't handle yet, so we
129 * can bail cleanly and fallback to TGSI compiler f/e
134 /* gpu pointer size in units of 32bit registers/slots */
135 static unsigned pointer_size(struct ir3_context
*ctx
)
137 return (ctx
->compiler
->gpu_id
>= 500) ? 2 : 1;
140 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
141 static struct ir3_block
* get_block(struct ir3_context
*ctx
, nir_block
*nblock
);
144 static struct ir3_context
*
145 compile_init(struct ir3_compiler
*compiler
,
146 struct ir3_shader_variant
*so
)
148 struct ir3_context
*ctx
= rzalloc(NULL
, struct ir3_context
);
150 if (compiler
->gpu_id
>= 400) {
151 /* need special handling for "flat" */
152 ctx
->flat_bypass
= true;
153 ctx
->levels_add_one
= false;
154 ctx
->unminify_coords
= false;
155 ctx
->array_index_add_half
= true;
157 if (so
->type
== SHADER_VERTEX
)
158 ctx
->astc_srgb
= so
->key
.vastc_srgb
;
159 else if (so
->type
== SHADER_FRAGMENT
)
160 ctx
->astc_srgb
= so
->key
.fastc_srgb
;
163 /* no special handling for "flat" */
164 ctx
->flat_bypass
= false;
165 ctx
->levels_add_one
= true;
166 ctx
->unminify_coords
= true;
167 ctx
->array_index_add_half
= false;
170 ctx
->compiler
= compiler
;
173 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
174 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
175 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
176 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
178 /* TODO: maybe generate some sort of bitmask of what key
179 * lowers vs what shader has (ie. no need to lower
180 * texture clamp lowering if no texture sample instrs)..
181 * although should be done further up the stack to avoid
182 * creating duplicate variants..
185 if (ir3_key_lowers_nir(&so
->key
)) {
186 nir_shader
*s
= nir_shader_clone(ctx
, so
->shader
->nir
);
187 ctx
->s
= ir3_optimize_nir(so
->shader
, s
, &so
->key
);
189 /* fast-path for shader key that lowers nothing in NIR: */
190 ctx
->s
= so
->shader
->nir
;
193 /* this needs to be the last pass run, so do this here instead of
194 * in ir3_optimize_nir():
196 NIR_PASS_V(ctx
->s
, nir_lower_locals_to_regs
);
198 if (fd_mesa_debug
& FD_DBG_DISASM
) {
199 DBG("dump nir%dv%d: type=%d, k={bp=%u,cts=%u,hp=%u}",
200 so
->shader
->id
, so
->id
, so
->type
,
201 so
->key
.binning_pass
, so
->key
.color_two_side
,
202 so
->key
.half_precision
);
203 nir_print_shader(ctx
->s
, stdout
);
206 ir3_nir_scan_driver_consts(ctx
->s
, &so
->const_layout
);
208 so
->num_uniforms
= ctx
->s
->num_uniforms
;
209 so
->num_ubos
= ctx
->s
->info
.num_ubos
;
211 /* Layout of constant registers, each section aligned to vec4. Note
212 * that pointer size (ubo, etc) changes depending on generation.
217 * if (vertex shader) {
218 * driver params (IR3_DP_*)
219 * if (stream_output.num_outputs > 0)
220 * stream-out addresses
224 * Immediates go last mostly because they are inserted in the CP pass
225 * after the nir -> ir3 frontend.
227 unsigned constoff
= align(ctx
->s
->num_uniforms
, 4);
228 unsigned ptrsz
= pointer_size(ctx
);
230 memset(&so
->constbase
, ~0, sizeof(so
->constbase
));
232 if (so
->num_ubos
> 0) {
233 so
->constbase
.ubo
= constoff
;
234 constoff
+= align(ctx
->s
->info
.num_ubos
* ptrsz
, 4) / 4;
237 if (so
->const_layout
.ssbo_size
.count
> 0) {
238 unsigned cnt
= so
->const_layout
.ssbo_size
.count
;
239 so
->constbase
.ssbo_sizes
= constoff
;
240 constoff
+= align(cnt
, 4) / 4;
243 if (so
->const_layout
.image_dims
.count
> 0) {
244 unsigned cnt
= so
->const_layout
.image_dims
.count
;
245 so
->constbase
.image_dims
= constoff
;
246 constoff
+= align(cnt
, 4) / 4;
249 unsigned num_driver_params
= 0;
250 if (so
->type
== SHADER_VERTEX
) {
251 num_driver_params
= IR3_DP_VS_COUNT
;
252 } else if (so
->type
== SHADER_COMPUTE
) {
253 num_driver_params
= IR3_DP_CS_COUNT
;
256 so
->constbase
.driver_param
= constoff
;
257 constoff
+= align(num_driver_params
, 4) / 4;
259 if ((so
->type
== SHADER_VERTEX
) &&
260 (compiler
->gpu_id
< 500) &&
261 so
->shader
->stream_output
.num_outputs
> 0) {
262 so
->constbase
.tfbo
= constoff
;
263 constoff
+= align(PIPE_MAX_SO_BUFFERS
* ptrsz
, 4) / 4;
266 so
->constbase
.immediate
= constoff
;
272 compile_error(struct ir3_context
*ctx
, const char *format
, ...)
275 va_start(ap
, format
);
276 _debug_vprintf(format
, ap
);
278 nir_print_shader(ctx
->s
, stdout
);
283 #define compile_assert(ctx, cond) do { \
284 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
288 compile_free(struct ir3_context
*ctx
)
294 declare_array(struct ir3_context
*ctx
, nir_register
*reg
)
296 struct ir3_array
*arr
= rzalloc(ctx
, struct ir3_array
);
297 arr
->id
= ++ctx
->num_arrays
;
298 /* NOTE: sometimes we get non array regs, for example for arrays of
299 * length 1. See fs-const-array-of-struct-of-array.shader_test. So
300 * treat a non-array as if it was an array of length 1.
302 * It would be nice if there was a nir pass to convert arrays of
305 arr
->length
= reg
->num_components
* MAX2(1, reg
->num_array_elems
);
306 compile_assert(ctx
, arr
->length
> 0);
308 list_addtail(&arr
->node
, &ctx
->ir
->array_list
);
311 static struct ir3_array
*
312 get_array(struct ir3_context
*ctx
, nir_register
*reg
)
314 list_for_each_entry (struct ir3_array
, arr
, &ctx
->ir
->array_list
, node
) {
318 compile_error(ctx
, "bogus reg: %s\n", reg
->name
);
322 /* relative (indirect) if address!=NULL */
323 static struct ir3_instruction
*
324 create_array_load(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
325 struct ir3_instruction
*address
)
327 struct ir3_block
*block
= ctx
->block
;
328 struct ir3_instruction
*mov
;
329 struct ir3_register
*src
;
331 mov
= ir3_instr_create(block
, OPC_MOV
);
332 mov
->cat1
.src_type
= TYPE_U32
;
333 mov
->cat1
.dst_type
= TYPE_U32
;
334 mov
->barrier_class
= IR3_BARRIER_ARRAY_R
;
335 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_W
;
336 ir3_reg_create(mov
, 0, 0);
337 src
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
338 COND(address
, IR3_REG_RELATIV
));
339 src
->instr
= arr
->last_write
;
340 src
->size
= arr
->length
;
341 src
->array
.id
= arr
->id
;
342 src
->array
.offset
= n
;
345 ir3_instr_set_address(mov
, address
);
350 /* relative (indirect) if address!=NULL */
352 create_array_store(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
353 struct ir3_instruction
*src
, struct ir3_instruction
*address
)
355 struct ir3_block
*block
= ctx
->block
;
356 struct ir3_instruction
*mov
;
357 struct ir3_register
*dst
;
359 /* if not relative store, don't create an extra mov, since that
360 * ends up being difficult for cp to remove.
365 src
->barrier_class
|= IR3_BARRIER_ARRAY_W
;
366 src
->barrier_conflict
|= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
368 dst
->flags
|= IR3_REG_ARRAY
;
369 dst
->instr
= arr
->last_write
;
370 dst
->size
= arr
->length
;
371 dst
->array
.id
= arr
->id
;
372 dst
->array
.offset
= n
;
374 arr
->last_write
= src
;
376 array_insert(block
, block
->keeps
, src
);
381 mov
= ir3_instr_create(block
, OPC_MOV
);
382 mov
->cat1
.src_type
= TYPE_U32
;
383 mov
->cat1
.dst_type
= TYPE_U32
;
384 mov
->barrier_class
= IR3_BARRIER_ARRAY_W
;
385 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
386 dst
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
387 COND(address
, IR3_REG_RELATIV
));
388 dst
->instr
= arr
->last_write
;
389 dst
->size
= arr
->length
;
390 dst
->array
.id
= arr
->id
;
391 dst
->array
.offset
= n
;
392 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
395 ir3_instr_set_address(mov
, address
);
397 arr
->last_write
= mov
;
399 /* the array store may only matter to something in an earlier
400 * block (ie. loops), but since arrays are not in SSA, depth
401 * pass won't know this.. so keep all array stores:
403 array_insert(block
, block
->keeps
, mov
);
406 /* allocate a n element value array (to be populated by caller) and
409 static struct ir3_instruction
**
410 get_dst_ssa(struct ir3_context
*ctx
, nir_ssa_def
*dst
, unsigned n
)
412 struct ir3_instruction
**value
=
413 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
414 _mesa_hash_table_insert(ctx
->def_ht
, dst
, value
);
418 static struct ir3_instruction
**
419 get_dst(struct ir3_context
*ctx
, nir_dest
*dst
, unsigned n
)
421 struct ir3_instruction
**value
;
424 value
= get_dst_ssa(ctx
, &dst
->ssa
, n
);
426 value
= ralloc_array(ctx
, struct ir3_instruction
*, n
);
429 /* NOTE: in non-ssa case, we don't really need to store last_dst
430 * but this helps us catch cases where put_dst() call is forgotten
432 compile_assert(ctx
, !ctx
->last_dst
);
433 ctx
->last_dst
= value
;
439 static struct ir3_instruction
* get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
);
441 static struct ir3_instruction
* const *
442 get_src(struct ir3_context
*ctx
, nir_src
*src
)
445 struct hash_entry
*entry
;
446 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
447 compile_assert(ctx
, entry
);
450 nir_register
*reg
= src
->reg
.reg
;
451 struct ir3_array
*arr
= get_array(ctx
, reg
);
452 unsigned num_components
= arr
->r
->num_components
;
453 struct ir3_instruction
*addr
= NULL
;
454 struct ir3_instruction
**value
=
455 ralloc_array(ctx
, struct ir3_instruction
*, num_components
);
457 if (src
->reg
.indirect
)
458 addr
= get_addr(ctx
, get_src(ctx
, src
->reg
.indirect
)[0],
459 reg
->num_components
);
461 for (unsigned i
= 0; i
< num_components
; i
++) {
462 unsigned n
= src
->reg
.base_offset
* reg
->num_components
+ i
;
463 compile_assert(ctx
, n
< arr
->length
);
464 value
[i
] = create_array_load(ctx
, arr
, n
, addr
);
472 put_dst(struct ir3_context
*ctx
, nir_dest
*dst
)
475 nir_register
*reg
= dst
->reg
.reg
;
476 struct ir3_array
*arr
= get_array(ctx
, reg
);
477 unsigned num_components
= ctx
->last_dst_n
;
478 struct ir3_instruction
*addr
= NULL
;
480 if (dst
->reg
.indirect
)
481 addr
= get_addr(ctx
, get_src(ctx
, dst
->reg
.indirect
)[0],
482 reg
->num_components
);
484 for (unsigned i
= 0; i
< num_components
; i
++) {
485 unsigned n
= dst
->reg
.base_offset
* reg
->num_components
+ i
;
486 compile_assert(ctx
, n
< arr
->length
);
487 if (!ctx
->last_dst
[i
])
489 create_array_store(ctx
, arr
, n
, ctx
->last_dst
[i
], addr
);
492 ralloc_free(ctx
->last_dst
);
494 ctx
->last_dst
= NULL
;
498 static struct ir3_instruction
*
499 create_immed(struct ir3_block
*block
, uint32_t val
)
501 struct ir3_instruction
*mov
;
503 mov
= ir3_instr_create(block
, OPC_MOV
);
504 mov
->cat1
.src_type
= TYPE_U32
;
505 mov
->cat1
.dst_type
= TYPE_U32
;
506 ir3_reg_create(mov
, 0, 0);
507 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
512 static struct ir3_instruction
*
513 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
, int align
)
515 struct ir3_instruction
*instr
, *immed
;
517 /* TODO in at least some cases, the backend could probably be
518 * made clever enough to propagate IR3_REG_HALF..
520 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
521 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
528 /* src *= 2 => src <<= 1: */
529 immed
= create_immed(block
, 1);
530 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
532 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
533 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
534 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
538 immed
= create_immed(block
, 3);
539 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
541 instr
= ir3_MULL_U(block
, instr
, 0, immed
, 0);
542 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
543 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
546 /* src *= 4 => src <<= 2: */
547 immed
= create_immed(block
, 2);
548 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
550 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
551 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
552 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
555 unreachable("bad align");
559 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
560 instr
->regs
[0]->num
= regid(REG_A0
, 0);
561 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
562 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
567 /* caches addr values to avoid generating multiple cov/shl/mova
568 * sequences for each use of a given NIR level src as address
570 static struct ir3_instruction
*
571 get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
)
573 struct ir3_instruction
*addr
;
574 unsigned idx
= align
- 1;
576 compile_assert(ctx
, idx
< ARRAY_SIZE(ctx
->addr_ht
));
578 if (!ctx
->addr_ht
[idx
]) {
579 ctx
->addr_ht
[idx
] = _mesa_hash_table_create(ctx
,
580 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
582 struct hash_entry
*entry
;
583 entry
= _mesa_hash_table_search(ctx
->addr_ht
[idx
], src
);
588 addr
= create_addr(ctx
->block
, src
, align
);
589 _mesa_hash_table_insert(ctx
->addr_ht
[idx
], src
, addr
);
594 static struct ir3_instruction
*
595 get_predicate(struct ir3_context
*ctx
, struct ir3_instruction
*src
)
597 struct ir3_block
*b
= ctx
->block
;
598 struct ir3_instruction
*cond
;
600 /* NOTE: only cmps.*.* can write p0.x: */
601 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
602 cond
->cat2
.condition
= IR3_COND_NE
;
604 /* condition always goes in predicate register: */
605 cond
->regs
[0]->num
= regid(REG_P0
, 0);
610 static struct ir3_instruction
*
611 create_uniform(struct ir3_context
*ctx
, unsigned n
)
613 struct ir3_instruction
*mov
;
615 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
616 /* TODO get types right? */
617 mov
->cat1
.src_type
= TYPE_F32
;
618 mov
->cat1
.dst_type
= TYPE_F32
;
619 ir3_reg_create(mov
, 0, 0);
620 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
625 static struct ir3_instruction
*
626 create_uniform_indirect(struct ir3_context
*ctx
, int n
,
627 struct ir3_instruction
*address
)
629 struct ir3_instruction
*mov
;
631 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
632 mov
->cat1
.src_type
= TYPE_U32
;
633 mov
->cat1
.dst_type
= TYPE_U32
;
634 ir3_reg_create(mov
, 0, 0);
635 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
637 ir3_instr_set_address(mov
, address
);
642 static struct ir3_instruction
*
643 create_collect(struct ir3_block
*block
, struct ir3_instruction
*const *arr
,
646 struct ir3_instruction
*collect
;
651 collect
= ir3_instr_create2(block
, OPC_META_FI
, 1 + arrsz
);
652 ir3_reg_create(collect
, 0, 0); /* dst */
653 for (unsigned i
= 0; i
< arrsz
; i
++)
654 ir3_reg_create(collect
, 0, IR3_REG_SSA
)->instr
= arr
[i
];
659 static struct ir3_instruction
*
660 create_indirect_load(struct ir3_context
*ctx
, unsigned arrsz
, int n
,
661 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
663 struct ir3_block
*block
= ctx
->block
;
664 struct ir3_instruction
*mov
;
665 struct ir3_register
*src
;
667 mov
= ir3_instr_create(block
, OPC_MOV
);
668 mov
->cat1
.src_type
= TYPE_U32
;
669 mov
->cat1
.dst_type
= TYPE_U32
;
670 ir3_reg_create(mov
, 0, 0);
671 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
672 src
->instr
= collect
;
674 src
->array
.offset
= n
;
676 ir3_instr_set_address(mov
, address
);
681 static struct ir3_instruction
*
682 create_input_compmask(struct ir3_block
*block
, unsigned n
, unsigned compmask
)
684 struct ir3_instruction
*in
;
686 in
= ir3_instr_create(block
, OPC_META_INPUT
);
687 in
->inout
.block
= block
;
688 ir3_reg_create(in
, n
, 0);
690 in
->regs
[0]->wrmask
= compmask
;
695 static struct ir3_instruction
*
696 create_input(struct ir3_block
*block
, unsigned n
)
698 return create_input_compmask(block
, n
, 0x1);
701 static struct ir3_instruction
*
702 create_frag_input(struct ir3_context
*ctx
, bool use_ldlv
)
704 struct ir3_block
*block
= ctx
->block
;
705 struct ir3_instruction
*instr
;
706 /* actual inloc is assigned and fixed up later: */
707 struct ir3_instruction
*inloc
= create_immed(block
, 0);
710 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
711 instr
->cat6
.type
= TYPE_U32
;
712 instr
->cat6
.iim_val
= 1;
714 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_pos
, 0);
715 instr
->regs
[2]->wrmask
= 0x3;
721 static struct ir3_instruction
*
722 create_frag_coord(struct ir3_context
*ctx
, unsigned comp
)
724 struct ir3_block
*block
= ctx
->block
;
725 struct ir3_instruction
*instr
;
727 compile_assert(ctx
, !ctx
->frag_coord
[comp
]);
729 ctx
->frag_coord
[comp
] = create_input(ctx
->block
, 0);
734 /* for frag_coord, we get unsigned values.. we need
735 * to subtract (integer) 8 and divide by 16 (right-
736 * shift by 4) then convert to float:
740 * mov.u32f32 dst, tmp
743 instr
= ir3_SUB_S(block
, ctx
->frag_coord
[comp
], 0,
744 create_immed(block
, 8), 0);
745 instr
= ir3_SHR_B(block
, instr
, 0,
746 create_immed(block
, 4), 0);
747 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
753 /* seems that we can use these as-is: */
754 return ctx
->frag_coord
[comp
];
758 static struct ir3_instruction
*
759 create_driver_param(struct ir3_context
*ctx
, enum ir3_driver_param dp
)
761 /* first four vec4 sysval's reserved for UBOs: */
762 /* NOTE: dp is in scalar, but there can be >4 dp components: */
763 unsigned n
= ctx
->so
->constbase
.driver_param
;
764 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
765 return create_uniform(ctx
, r
);
768 /* helper for instructions that produce multiple consecutive scalar
769 * outputs which need to have a split/fanout meta instruction inserted
772 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
773 struct ir3_instruction
*src
, unsigned base
, unsigned n
)
775 struct ir3_instruction
*prev
= NULL
;
777 if ((n
== 1) && (src
->regs
[0]->wrmask
== 0x1)) {
782 for (int i
= 0, j
= 0; i
< n
; i
++) {
783 struct ir3_instruction
*split
= ir3_instr_create(block
, OPC_META_FO
);
784 ir3_reg_create(split
, 0, IR3_REG_SSA
);
785 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
786 split
->fo
.off
= i
+ base
;
789 split
->cp
.left
= prev
;
790 split
->cp
.left_cnt
++;
791 prev
->cp
.right
= split
;
792 prev
->cp
.right_cnt
++;
796 if (src
->regs
[0]->wrmask
& (1 << (i
+ base
)))
802 * Adreno uses uint rather than having dedicated bool type,
803 * which (potentially) requires some conversion, in particular
804 * when using output of an bool instr to int input, or visa
808 * -------+---------+-------+-
812 * To convert from an adreno bool (uint) to nir, use:
814 * absneg.s dst, (neg)src
816 * To convert back in the other direction:
818 * absneg.s dst, (abs)arc
820 * The CP step can clean up the absneg.s that cancel each other
821 * out, and with a slight bit of extra cleverness (to recognize
822 * the instructions which produce either a 0 or 1) can eliminate
823 * the absneg.s's completely when an instruction that wants
824 * 0/1 consumes the result. For example, when a nir 'bcsel'
825 * consumes the result of 'feq'. So we should be able to get by
826 * without a boolean resolve step, and without incuring any
827 * extra penalty in instruction count.
830 /* NIR bool -> native (adreno): */
831 static struct ir3_instruction
*
832 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
834 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
837 /* native (adreno) -> NIR bool: */
838 static struct ir3_instruction
*
839 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
841 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
845 * alu/sfu instructions:
849 emit_alu(struct ir3_context
*ctx
, nir_alu_instr
*alu
)
851 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
852 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
853 struct ir3_block
*b
= ctx
->block
;
854 unsigned dst_sz
, wrmask
;
856 if (alu
->dest
.dest
.is_ssa
) {
857 dst_sz
= alu
->dest
.dest
.ssa
.num_components
;
858 wrmask
= (1 << dst_sz
) - 1;
860 dst_sz
= alu
->dest
.dest
.reg
.reg
->num_components
;
861 wrmask
= alu
->dest
.write_mask
;
864 dst
= get_dst(ctx
, &alu
->dest
.dest
, dst_sz
);
866 /* Vectors are special in that they have non-scalarized writemasks,
867 * and just take the first swizzle channel for each argument in
868 * order into each writemask channel.
870 if ((alu
->op
== nir_op_vec2
) ||
871 (alu
->op
== nir_op_vec3
) ||
872 (alu
->op
== nir_op_vec4
)) {
874 for (int i
= 0; i
< info
->num_inputs
; i
++) {
875 nir_alu_src
*asrc
= &alu
->src
[i
];
877 compile_assert(ctx
, !asrc
->abs
);
878 compile_assert(ctx
, !asrc
->negate
);
880 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
882 src
[i
] = create_immed(ctx
->block
, 0);
883 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
886 put_dst(ctx
, &alu
->dest
.dest
);
890 /* We also get mov's with more than one component for mov's so
891 * handle those specially:
893 if ((alu
->op
== nir_op_imov
) || (alu
->op
== nir_op_fmov
)) {
894 type_t type
= (alu
->op
== nir_op_imov
) ? TYPE_U32
: TYPE_F32
;
895 nir_alu_src
*asrc
= &alu
->src
[0];
896 struct ir3_instruction
*const *src0
= get_src(ctx
, &asrc
->src
);
898 for (unsigned i
= 0; i
< dst_sz
; i
++) {
899 if (wrmask
& (1 << i
)) {
900 dst
[i
] = ir3_MOV(b
, src0
[asrc
->swizzle
[i
]], type
);
906 put_dst(ctx
, &alu
->dest
.dest
);
910 compile_assert(ctx
, alu
->dest
.dest
.is_ssa
);
912 /* General case: We can just grab the one used channel per src. */
913 for (int i
= 0; i
< info
->num_inputs
; i
++) {
914 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
915 nir_alu_src
*asrc
= &alu
->src
[i
];
917 compile_assert(ctx
, !asrc
->abs
);
918 compile_assert(ctx
, !asrc
->negate
);
920 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
922 compile_assert(ctx
, src
[i
]);
927 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_S32
);
930 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_U32
);
933 dst
[0] = ir3_COV(b
, src
[0], TYPE_S32
, TYPE_F32
);
936 dst
[0] = ir3_COV(b
, src
[0], TYPE_U32
, TYPE_F32
);
939 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
940 dst
[0]->cat2
.condition
= IR3_COND_NE
;
941 dst
[0] = ir3_n2b(b
, dst
[0]);
944 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
947 dst
[0] = ir3_b2n(b
, src
[0]);
950 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
951 dst
[0]->cat2
.condition
= IR3_COND_NE
;
952 dst
[0] = ir3_n2b(b
, dst
[0]);
956 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
959 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
962 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
965 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
968 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
971 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
974 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
977 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
980 dst
[0] = ir3_DSX(b
, src
[0], 0);
981 dst
[0]->cat5
.type
= TYPE_F32
;
984 dst
[0] = ir3_DSY(b
, src
[0], 0);
985 dst
[0]->cat5
.type
= TYPE_F32
;
989 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
990 dst
[0]->cat2
.condition
= IR3_COND_LT
;
991 dst
[0] = ir3_n2b(b
, dst
[0]);
994 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
995 dst
[0]->cat2
.condition
= IR3_COND_GE
;
996 dst
[0] = ir3_n2b(b
, dst
[0]);
999 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1000 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1001 dst
[0] = ir3_n2b(b
, dst
[0]);
1004 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1005 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1006 dst
[0] = ir3_n2b(b
, dst
[0]);
1009 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
1012 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
1015 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
1017 case nir_op_fround_even
:
1018 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
1021 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
1025 dst
[0] = ir3_SIN(b
, src
[0], 0);
1028 dst
[0] = ir3_COS(b
, src
[0], 0);
1031 dst
[0] = ir3_RSQ(b
, src
[0], 0);
1034 dst
[0] = ir3_RCP(b
, src
[0], 0);
1037 dst
[0] = ir3_LOG2(b
, src
[0], 0);
1040 dst
[0] = ir3_EXP2(b
, src
[0], 0);
1043 dst
[0] = ir3_SQRT(b
, src
[0], 0);
1047 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
1050 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
1053 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
1056 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
1059 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
1062 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
1065 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
1069 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
1070 * mull.u tmp0, a, b ; mul low, i.e. al * bl
1071 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
1072 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
1074 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
1075 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
1076 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
1079 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
1082 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
1085 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
1088 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
1091 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
1093 case nir_op_isign
: {
1094 /* maybe this would be sane to lower in nir.. */
1095 struct ir3_instruction
*neg
, *pos
;
1097 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1098 neg
->cat2
.condition
= IR3_COND_LT
;
1100 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1101 pos
->cat2
.condition
= IR3_COND_GT
;
1103 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
1108 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
1111 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
1114 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
1117 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1118 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1119 dst
[0] = ir3_n2b(b
, dst
[0]);
1122 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1123 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1124 dst
[0] = ir3_n2b(b
, dst
[0]);
1127 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1128 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1129 dst
[0] = ir3_n2b(b
, dst
[0]);
1132 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1133 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1134 dst
[0] = ir3_n2b(b
, dst
[0]);
1137 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1138 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1139 dst
[0] = ir3_n2b(b
, dst
[0]);
1142 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1143 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1144 dst
[0] = ir3_n2b(b
, dst
[0]);
1148 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, ir3_b2n(b
, src
[0]), 0, src
[2], 0);
1151 case nir_op_bit_count
:
1152 dst
[0] = ir3_CBITS_B(b
, src
[0], 0);
1154 case nir_op_ifind_msb
: {
1155 struct ir3_instruction
*cmp
;
1156 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
1157 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
1158 cmp
->cat2
.condition
= IR3_COND_GE
;
1159 dst
[0] = ir3_SEL_B32(b
,
1160 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1164 case nir_op_ufind_msb
:
1165 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
1166 dst
[0] = ir3_SEL_B32(b
,
1167 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1168 src
[0], 0, dst
[0], 0);
1170 case nir_op_find_lsb
:
1171 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1172 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
1174 case nir_op_bitfield_reverse
:
1175 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1179 compile_error(ctx
, "Unhandled ALU op: %s\n",
1180 nir_op_infos
[alu
->op
].name
);
1184 put_dst(ctx
, &alu
->dest
.dest
);
1187 /* handles direct/indirect UBO reads: */
1189 emit_intrinsic_load_ubo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1190 struct ir3_instruction
**dst
)
1192 struct ir3_block
*b
= ctx
->block
;
1193 struct ir3_instruction
*base_lo
, *base_hi
, *addr
, *src0
, *src1
;
1194 nir_const_value
*const_offset
;
1195 /* UBO addresses are the first driver params: */
1196 unsigned ubo
= regid(ctx
->so
->constbase
.ubo
, 0);
1197 const unsigned ptrsz
= pointer_size(ctx
);
1201 /* First src is ubo index, which could either be an immed or not: */
1202 src0
= get_src(ctx
, &intr
->src
[0])[0];
1203 if (is_same_type_mov(src0
) &&
1204 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1205 base_lo
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
));
1206 base_hi
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
) + 1);
1208 base_lo
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
, 4));
1209 base_hi
= create_uniform_indirect(ctx
, ubo
+ 1, get_addr(ctx
, src0
, 4));
1212 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
1215 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1217 off
+= const_offset
->u32
[0];
1219 /* For load_ubo_indirect, second src is indirect offset: */
1220 src1
= get_src(ctx
, &intr
->src
[1])[0];
1222 /* and add offset to addr: */
1223 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1226 /* if offset is to large to encode in the ldg, split it out: */
1227 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1228 /* split out the minimal amount to improve the odds that
1229 * cp can fit the immediate in the add.s instruction:
1231 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1232 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1237 struct ir3_instruction
*carry
;
1239 /* handle 32b rollover, ie:
1240 * if (addr < base_lo)
1243 carry
= ir3_CMPS_U(b
, addr
, 0, base_lo
, 0);
1244 carry
->cat2
.condition
= IR3_COND_LT
;
1245 base_hi
= ir3_ADD_S(b
, base_hi
, 0, carry
, 0);
1247 addr
= create_collect(b
, (struct ir3_instruction
*[]){ addr
, base_hi
}, 2);
1250 for (int i
= 0; i
< intr
->num_components
; i
++) {
1251 struct ir3_instruction
*load
=
1252 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1253 load
->cat6
.type
= TYPE_U32
;
1254 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
1259 /* src[] = { buffer_index, offset }. No const_index */
1261 emit_intrinsic_load_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1262 struct ir3_instruction
**dst
)
1264 struct ir3_block
*b
= ctx
->block
;
1265 struct ir3_instruction
*ldgb
, *src0
, *src1
, *offset
;
1266 nir_const_value
*const_offset
;
1268 /* can this be non-const buffer_index? how do we handle that? */
1269 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1270 compile_assert(ctx
, const_offset
);
1272 offset
= get_src(ctx
, &intr
->src
[1])[0];
1274 /* src0 is uvec2(offset*4, 0), src1 is offset.. nir already *= 4: */
1275 src0
= create_collect(b
, (struct ir3_instruction
*[]){
1279 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1281 ldgb
= ir3_LDGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1283 ldgb
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1284 ldgb
->cat6
.iim_val
= intr
->num_components
;
1286 ldgb
->cat6
.type
= TYPE_U32
;
1287 ldgb
->barrier_class
= IR3_BARRIER_BUFFER_R
;
1288 ldgb
->barrier_conflict
= IR3_BARRIER_BUFFER_W
;
1290 split_dest(b
, dst
, ldgb
, 0, intr
->num_components
);
1293 /* src[] = { value, block_index, offset }. const_index[] = { write_mask } */
1295 emit_intrinsic_store_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1297 struct ir3_block
*b
= ctx
->block
;
1298 struct ir3_instruction
*stgb
, *src0
, *src1
, *src2
, *offset
;
1299 nir_const_value
*const_offset
;
1300 /* TODO handle wrmask properly, see _store_shared().. but I think
1301 * it is more a PITA than that, since blob ends up loading the
1302 * masked components and writing them back out.
1304 unsigned wrmask
= intr
->const_index
[0];
1305 unsigned ncomp
= ffs(~wrmask
) - 1;
1307 /* can this be non-const buffer_index? how do we handle that? */
1308 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1309 compile_assert(ctx
, const_offset
);
1311 offset
= get_src(ctx
, &intr
->src
[2])[0];
1313 /* src0 is value, src1 is offset, src2 is uvec2(offset*4, 0)..
1316 src0
= create_collect(b
, get_src(ctx
, &intr
->src
[0]), ncomp
);
1317 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1318 src2
= create_collect(b
, (struct ir3_instruction
*[]){
1323 stgb
= ir3_STGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1324 src0
, 0, src1
, 0, src2
, 0);
1325 stgb
->cat6
.iim_val
= ncomp
;
1327 stgb
->cat6
.type
= TYPE_U32
;
1328 stgb
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1329 stgb
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1331 array_insert(b
, b
->keeps
, stgb
);
1334 /* src[] = { block_index } */
1336 emit_intrinsic_ssbo_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1337 struct ir3_instruction
**dst
)
1339 /* SSBO size stored as a const starting at ssbo_sizes: */
1340 unsigned blk_idx
= nir_src_as_const_value(intr
->src
[0])->u32
[0];
1341 unsigned idx
= regid(ctx
->so
->constbase
.ssbo_sizes
, 0) +
1342 ctx
->so
->const_layout
.ssbo_size
.off
[blk_idx
];
1344 debug_assert(ctx
->so
->const_layout
.ssbo_size
.mask
& (1 << blk_idx
));
1346 dst
[0] = create_uniform(ctx
, idx
);
1350 * SSBO atomic intrinsics
1352 * All of the SSBO atomic memory operations read a value from memory,
1353 * compute a new value using one of the operations below, write the new
1354 * value to memory, and return the original value read.
1356 * All operations take 3 sources except CompSwap that takes 4. These
1357 * sources represent:
1359 * 0: The SSBO buffer index.
1360 * 1: The offset into the SSBO buffer of the variable that the atomic
1361 * operation will operate on.
1362 * 2: The data parameter to the atomic function (i.e. the value to add
1363 * in ssbo_atomic_add, etc).
1364 * 3: For CompSwap only: the second data parameter.
1366 static struct ir3_instruction
*
1367 emit_intrinsic_atomic_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1369 struct ir3_block
*b
= ctx
->block
;
1370 struct ir3_instruction
*atomic
, *ssbo
, *src0
, *src1
, *src2
, *offset
;
1371 nir_const_value
*const_offset
;
1372 type_t type
= TYPE_U32
;
1374 /* can this be non-const buffer_index? how do we handle that? */
1375 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1376 compile_assert(ctx
, const_offset
);
1377 ssbo
= create_immed(b
, const_offset
->u32
[0]);
1379 offset
= get_src(ctx
, &intr
->src
[1])[0];
1381 /* src0 is data (or uvec2(data, compare))
1383 * src2 is uvec2(offset*4, 0) (appears to be 64b byte offset)
1385 * Note that nir already multiplies the offset by four
1387 src0
= get_src(ctx
, &intr
->src
[2])[0];
1388 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1389 src2
= create_collect(b
, (struct ir3_instruction
*[]){
1394 switch (intr
->intrinsic
) {
1395 case nir_intrinsic_ssbo_atomic_add
:
1396 atomic
= ir3_ATOMIC_ADD_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1398 case nir_intrinsic_ssbo_atomic_imin
:
1399 atomic
= ir3_ATOMIC_MIN_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1402 case nir_intrinsic_ssbo_atomic_umin
:
1403 atomic
= ir3_ATOMIC_MIN_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1405 case nir_intrinsic_ssbo_atomic_imax
:
1406 atomic
= ir3_ATOMIC_MAX_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1409 case nir_intrinsic_ssbo_atomic_umax
:
1410 atomic
= ir3_ATOMIC_MAX_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1412 case nir_intrinsic_ssbo_atomic_and
:
1413 atomic
= ir3_ATOMIC_AND_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1415 case nir_intrinsic_ssbo_atomic_or
:
1416 atomic
= ir3_ATOMIC_OR_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1418 case nir_intrinsic_ssbo_atomic_xor
:
1419 atomic
= ir3_ATOMIC_XOR_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1421 case nir_intrinsic_ssbo_atomic_exchange
:
1422 atomic
= ir3_ATOMIC_XCHG_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1424 case nir_intrinsic_ssbo_atomic_comp_swap
:
1425 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
1426 src0
= create_collect(b
, (struct ir3_instruction
*[]){
1428 get_src(ctx
, &intr
->src
[3])[0],
1430 atomic
= ir3_ATOMIC_CMPXCHG_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1436 atomic
->cat6
.iim_val
= 1;
1438 atomic
->cat6
.type
= type
;
1439 atomic
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1440 atomic
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1442 /* even if nothing consume the result, we can't DCE the instruction: */
1443 array_insert(b
, b
->keeps
, atomic
);
1448 /* src[] = { offset }. const_index[] = { base } */
1450 emit_intrinsic_load_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1451 struct ir3_instruction
**dst
)
1453 struct ir3_block
*b
= ctx
->block
;
1454 struct ir3_instruction
*ldl
, *offset
;
1457 offset
= get_src(ctx
, &intr
->src
[0])[0];
1458 base
= intr
->const_index
[0];
1460 ldl
= ir3_LDL(b
, offset
, 0, create_immed(b
, intr
->num_components
), 0);
1461 ldl
->cat6
.src_offset
= base
;
1462 ldl
->cat6
.type
= TYPE_U32
;
1463 ldl
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1465 ldl
->barrier_class
= IR3_BARRIER_SHARED_R
;
1466 ldl
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
1468 split_dest(b
, dst
, ldl
, 0, intr
->num_components
);
1471 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
1473 emit_intrinsic_store_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1475 struct ir3_block
*b
= ctx
->block
;
1476 struct ir3_instruction
*stl
, *offset
;
1477 struct ir3_instruction
* const *value
;
1478 unsigned base
, wrmask
;
1480 value
= get_src(ctx
, &intr
->src
[0]);
1481 offset
= get_src(ctx
, &intr
->src
[1])[0];
1483 base
= intr
->const_index
[0];
1484 wrmask
= intr
->const_index
[1];
1486 /* Combine groups of consecutive enabled channels in one write
1487 * message. We use ffs to find the first enabled channel and then ffs on
1488 * the bit-inverse, down-shifted writemask to determine the length of
1489 * the block of enabled bits.
1491 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
1494 unsigned first_component
= ffs(wrmask
) - 1;
1495 unsigned length
= ffs(~(wrmask
>> first_component
)) - 1;
1497 stl
= ir3_STL(b
, offset
, 0,
1498 create_collect(b
, &value
[first_component
], length
), 0,
1499 create_immed(b
, length
), 0);
1500 stl
->cat6
.dst_offset
= first_component
+ base
;
1501 stl
->cat6
.type
= TYPE_U32
;
1502 stl
->barrier_class
= IR3_BARRIER_SHARED_W
;
1503 stl
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1505 array_insert(b
, b
->keeps
, stl
);
1507 /* Clear the bits in the writemask that we just wrote, then try
1508 * again to see if more channels are left.
1510 wrmask
&= (15 << (first_component
+ length
));
1515 * CS shared variable atomic intrinsics
1517 * All of the shared variable atomic memory operations read a value from
1518 * memory, compute a new value using one of the operations below, write the
1519 * new value to memory, and return the original value read.
1521 * All operations take 2 sources except CompSwap that takes 3. These
1522 * sources represent:
1524 * 0: The offset into the shared variable storage region that the atomic
1525 * operation will operate on.
1526 * 1: The data parameter to the atomic function (i.e. the value to add
1527 * in shared_atomic_add, etc).
1528 * 2: For CompSwap only: the second data parameter.
1530 static struct ir3_instruction
*
1531 emit_intrinsic_atomic_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1533 struct ir3_block
*b
= ctx
->block
;
1534 struct ir3_instruction
*atomic
, *src0
, *src1
;
1535 type_t type
= TYPE_U32
;
1537 src0
= get_src(ctx
, &intr
->src
[0])[0]; /* offset */
1538 src1
= get_src(ctx
, &intr
->src
[1])[0]; /* value */
1540 switch (intr
->intrinsic
) {
1541 case nir_intrinsic_shared_atomic_add
:
1542 atomic
= ir3_ATOMIC_ADD(b
, src0
, 0, src1
, 0);
1544 case nir_intrinsic_shared_atomic_imin
:
1545 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1548 case nir_intrinsic_shared_atomic_umin
:
1549 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1551 case nir_intrinsic_shared_atomic_imax
:
1552 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1555 case nir_intrinsic_shared_atomic_umax
:
1556 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1558 case nir_intrinsic_shared_atomic_and
:
1559 atomic
= ir3_ATOMIC_AND(b
, src0
, 0, src1
, 0);
1561 case nir_intrinsic_shared_atomic_or
:
1562 atomic
= ir3_ATOMIC_OR(b
, src0
, 0, src1
, 0);
1564 case nir_intrinsic_shared_atomic_xor
:
1565 atomic
= ir3_ATOMIC_XOR(b
, src0
, 0, src1
, 0);
1567 case nir_intrinsic_shared_atomic_exchange
:
1568 atomic
= ir3_ATOMIC_XCHG(b
, src0
, 0, src1
, 0);
1570 case nir_intrinsic_shared_atomic_comp_swap
:
1571 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1572 src1
= create_collect(b
, (struct ir3_instruction
*[]){
1573 get_src(ctx
, &intr
->src
[2])[0],
1576 atomic
= ir3_ATOMIC_CMPXCHG(b
, src0
, 0, src1
, 0);
1582 atomic
->cat6
.iim_val
= 1;
1584 atomic
->cat6
.type
= type
;
1585 atomic
->barrier_class
= IR3_BARRIER_SHARED_W
;
1586 atomic
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1588 /* even if nothing consume the result, we can't DCE the instruction: */
1589 array_insert(b
, b
->keeps
, atomic
);
1594 /* Images get mapped into SSBO/image state (for store/atomic) and texture
1595 * state block (for load). To simplify things, invert the image id and
1596 * map it from end of state block, ie. image 0 becomes num-1, image 1
1597 * becomes num-2, etc. This potentially avoids needing to re-emit texture
1598 * state when switching shaders.
1600 * TODO is max # of samplers and SSBOs the same. This shouldn't be hard-
1601 * coded. Also, since all the gl shader stages (ie. everything but CS)
1602 * share the same SSBO/image state block, this might require some more
1603 * logic if we supported images in anything other than FS..
1606 get_image_slot(struct ir3_context
*ctx
, const nir_variable
*var
)
1608 /* TODO figure out real limit per generation, and don't hardcode: */
1609 const unsigned max_samplers
= 16;
1610 return max_samplers
- var
->data
.driver_location
- 1;
1614 get_image_coords(const nir_variable
*var
)
1616 switch (glsl_get_sampler_dim(glsl_without_array(var
->type
))) {
1617 case GLSL_SAMPLER_DIM_1D
:
1618 case GLSL_SAMPLER_DIM_BUF
:
1621 case GLSL_SAMPLER_DIM_2D
:
1622 case GLSL_SAMPLER_DIM_RECT
:
1623 case GLSL_SAMPLER_DIM_EXTERNAL
:
1624 case GLSL_SAMPLER_DIM_MS
:
1626 case GLSL_SAMPLER_DIM_3D
:
1627 case GLSL_SAMPLER_DIM_CUBE
:
1630 unreachable("bad sampler dim");
1636 get_image_type(const nir_variable
*var
)
1638 switch (glsl_get_sampler_result_type(glsl_without_array(var
->type
))) {
1639 case GLSL_TYPE_UINT
:
1643 case GLSL_TYPE_FLOAT
:
1646 unreachable("bad sampler type.");
1651 static struct ir3_instruction
*
1652 get_image_offset(struct ir3_context
*ctx
, const nir_variable
*var
,
1653 struct ir3_instruction
* const *coords
, bool byteoff
)
1655 struct ir3_block
*b
= ctx
->block
;
1656 struct ir3_instruction
*offset
;
1657 unsigned ncoords
= get_image_coords(var
);
1659 /* to calculate the byte offset (yes, uggg) we need (up to) three
1660 * const values to know the bytes per pixel, and y and z stride:
1662 unsigned cb
= regid(ctx
->so
->constbase
.image_dims
, 0) +
1663 ctx
->so
->const_layout
.image_dims
.off
[var
->data
.driver_location
];
1665 debug_assert(ctx
->so
->const_layout
.image_dims
.mask
&
1666 (1 << var
->data
.driver_location
));
1668 /* offset = coords.x * bytes_per_pixel: */
1669 offset
= ir3_MUL_S(b
, coords
[0], 0, create_uniform(ctx
, cb
+ 0), 0);
1671 /* offset += coords.y * y_pitch: */
1672 offset
= ir3_MAD_S24(b
, create_uniform(ctx
, cb
+ 1), 0,
1673 coords
[1], 0, offset
, 0);
1676 /* offset += coords.z * z_pitch: */
1677 offset
= ir3_MAD_S24(b
, create_uniform(ctx
, cb
+ 2), 0,
1678 coords
[2], 0, offset
, 0);
1682 /* Some cases, like atomics, seem to use dword offset instead
1683 * of byte offsets.. blob just puts an extra shr.b in there
1686 offset
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1689 return create_collect(b
, (struct ir3_instruction
*[]){
1695 /* src[] = { coord, sample_index }. const_index[] = {} */
1697 emit_intrinsic_load_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1698 struct ir3_instruction
**dst
)
1700 struct ir3_block
*b
= ctx
->block
;
1701 const nir_variable
*var
= intr
->variables
[0]->var
;
1702 struct ir3_instruction
*sam
;
1703 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[0]);
1704 unsigned ncoords
= get_image_coords(var
);
1705 unsigned tex_idx
= get_image_slot(ctx
, var
);
1706 type_t type
= get_image_type(var
);
1710 flags
|= IR3_INSTR_3D
;
1712 sam
= ir3_SAM(b
, OPC_ISAM
, type
, TGSI_WRITEMASK_XYZW
, flags
,
1713 tex_idx
, tex_idx
, create_collect(b
, coords
, ncoords
), NULL
);
1715 sam
->barrier_class
= IR3_BARRIER_IMAGE_R
;
1716 sam
->barrier_conflict
= IR3_BARRIER_IMAGE_W
;
1718 split_dest(b
, dst
, sam
, 0, 4);
1721 /* src[] = { coord, sample_index, value }. const_index[] = {} */
1723 emit_intrinsic_store_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1725 struct ir3_block
*b
= ctx
->block
;
1726 const nir_variable
*var
= intr
->variables
[0]->var
;
1727 struct ir3_instruction
*stib
, *offset
;
1728 struct ir3_instruction
* const *value
= get_src(ctx
, &intr
->src
[2]);
1729 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[0]);
1730 unsigned ncoords
= get_image_coords(var
);
1731 unsigned tex_idx
= get_image_slot(ctx
, var
);
1735 * src2 is 64b byte offset
1738 offset
= get_image_offset(ctx
, var
, coords
, true);
1740 /* NOTE: stib seems to take byte offset, but stgb.typed can be used
1741 * too and takes a dword offset.. not quite sure yet why blob uses
1742 * one over the other in various cases.
1745 stib
= ir3_STIB(b
, create_immed(b
, tex_idx
), 0,
1746 create_collect(b
, value
, 4), 0,
1747 create_collect(b
, coords
, ncoords
), 0,
1749 stib
->cat6
.iim_val
= 4;
1750 stib
->cat6
.d
= ncoords
;
1751 stib
->cat6
.type
= get_image_type(var
);
1752 stib
->cat6
.typed
= true;
1753 stib
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1754 stib
->barrier_conflict
= IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
;
1756 array_insert(b
, b
->keeps
, stib
);
1760 emit_intrinsic_image_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1761 struct ir3_instruction
**dst
)
1763 struct ir3_block
*b
= ctx
->block
;
1764 const nir_variable
*var
= intr
->variables
[0]->var
;
1765 unsigned ncoords
= get_image_coords(var
);
1766 unsigned tex_idx
= get_image_slot(ctx
, var
);
1767 struct ir3_instruction
*sam
, *lod
;
1771 flags
= IR3_INSTR_3D
;
1773 lod
= create_immed(b
, 0);
1774 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
1775 tex_idx
, tex_idx
, lod
, NULL
);
1777 split_dest(b
, dst
, sam
, 0, ncoords
);
1780 /* src[] = { coord, sample_index, value, compare }. const_index[] = {} */
1781 static struct ir3_instruction
*
1782 emit_intrinsic_atomic_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1784 struct ir3_block
*b
= ctx
->block
;
1785 const nir_variable
*var
= intr
->variables
[0]->var
;
1786 struct ir3_instruction
*atomic
, *image
, *src0
, *src1
, *src2
;
1787 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[0]);
1788 unsigned ncoords
= get_image_coords(var
);
1790 image
= create_immed(b
, get_image_slot(ctx
, var
));
1792 /* src0 is value (or uvec2(value, compare))
1794 * src2 is 64b byte offset
1796 src0
= get_src(ctx
, &intr
->src
[2])[0];
1797 src1
= create_collect(b
, coords
, ncoords
);
1798 src2
= get_image_offset(ctx
, var
, coords
, false);
1800 switch (intr
->intrinsic
) {
1801 case nir_intrinsic_image_atomic_add
:
1802 atomic
= ir3_ATOMIC_ADD_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1804 case nir_intrinsic_image_atomic_min
:
1805 atomic
= ir3_ATOMIC_MIN_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1807 case nir_intrinsic_image_atomic_max
:
1808 atomic
= ir3_ATOMIC_MAX_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1810 case nir_intrinsic_image_atomic_and
:
1811 atomic
= ir3_ATOMIC_AND_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1813 case nir_intrinsic_image_atomic_or
:
1814 atomic
= ir3_ATOMIC_OR_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1816 case nir_intrinsic_image_atomic_xor
:
1817 atomic
= ir3_ATOMIC_XOR_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1819 case nir_intrinsic_image_atomic_exchange
:
1820 atomic
= ir3_ATOMIC_XCHG_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1822 case nir_intrinsic_image_atomic_comp_swap
:
1823 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
1824 src0
= create_collect(b
, (struct ir3_instruction
*[]){
1826 get_src(ctx
, &intr
->src
[3])[0],
1828 atomic
= ir3_ATOMIC_CMPXCHG_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1834 atomic
->cat6
.iim_val
= 1;
1835 atomic
->cat6
.d
= ncoords
;
1836 atomic
->cat6
.type
= get_image_type(var
);
1837 atomic
->cat6
.typed
= true;
1838 atomic
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1839 atomic
->barrier_conflict
= IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
;
1841 /* even if nothing consume the result, we can't DCE the instruction: */
1842 array_insert(b
, b
->keeps
, atomic
);
1848 emit_intrinsic_barrier(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1850 struct ir3_block
*b
= ctx
->block
;
1851 struct ir3_instruction
*barrier
;
1853 switch (intr
->intrinsic
) {
1854 case nir_intrinsic_barrier
:
1855 barrier
= ir3_BAR(b
);
1856 barrier
->cat7
.g
= true;
1857 barrier
->cat7
.l
= true;
1858 barrier
->flags
= IR3_INSTR_SS
| IR3_INSTR_SY
;
1859 barrier
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1861 case nir_intrinsic_memory_barrier
:
1862 barrier
= ir3_FENCE(b
);
1863 barrier
->cat7
.g
= true;
1864 barrier
->cat7
.r
= true;
1865 barrier
->cat7
.w
= true;
1866 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
|
1867 IR3_BARRIER_BUFFER_W
;
1868 barrier
->barrier_conflict
=
1869 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1870 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1872 case nir_intrinsic_memory_barrier_atomic_counter
:
1873 case nir_intrinsic_memory_barrier_buffer
:
1874 barrier
= ir3_FENCE(b
);
1875 barrier
->cat7
.g
= true;
1876 barrier
->cat7
.r
= true;
1877 barrier
->cat7
.w
= true;
1878 barrier
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1879 barrier
->barrier_conflict
= IR3_BARRIER_BUFFER_R
|
1880 IR3_BARRIER_BUFFER_W
;
1882 case nir_intrinsic_memory_barrier_image
:
1883 // TODO double check if this should have .g set
1884 barrier
= ir3_FENCE(b
);
1885 barrier
->cat7
.g
= true;
1886 barrier
->cat7
.r
= true;
1887 barrier
->cat7
.w
= true;
1888 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1889 barrier
->barrier_conflict
= IR3_BARRIER_IMAGE_R
|
1890 IR3_BARRIER_IMAGE_W
;
1892 case nir_intrinsic_memory_barrier_shared
:
1893 barrier
= ir3_FENCE(b
);
1894 barrier
->cat7
.g
= true;
1895 barrier
->cat7
.l
= true;
1896 barrier
->cat7
.r
= true;
1897 barrier
->cat7
.w
= true;
1898 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
;
1899 barrier
->barrier_conflict
= IR3_BARRIER_SHARED_R
|
1900 IR3_BARRIER_SHARED_W
;
1902 case nir_intrinsic_group_memory_barrier
:
1903 barrier
= ir3_FENCE(b
);
1904 barrier
->cat7
.g
= true;
1905 barrier
->cat7
.l
= true;
1906 barrier
->cat7
.r
= true;
1907 barrier
->cat7
.w
= true;
1908 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
|
1909 IR3_BARRIER_IMAGE_W
|
1910 IR3_BARRIER_BUFFER_W
;
1911 barrier
->barrier_conflict
=
1912 IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
|
1913 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1914 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1920 /* make sure barrier doesn't get DCE'd */
1921 array_insert(b
, b
->keeps
, barrier
);
1924 static void add_sysval_input_compmask(struct ir3_context
*ctx
,
1925 gl_system_value slot
, unsigned compmask
,
1926 struct ir3_instruction
*instr
)
1928 struct ir3_shader_variant
*so
= ctx
->so
;
1929 unsigned r
= regid(so
->inputs_count
, 0);
1930 unsigned n
= so
->inputs_count
++;
1932 so
->inputs
[n
].sysval
= true;
1933 so
->inputs
[n
].slot
= slot
;
1934 so
->inputs
[n
].compmask
= compmask
;
1935 so
->inputs
[n
].regid
= r
;
1936 so
->inputs
[n
].interpolate
= INTERP_MODE_FLAT
;
1939 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
1940 ctx
->ir
->inputs
[r
] = instr
;
1943 static void add_sysval_input(struct ir3_context
*ctx
, gl_system_value slot
,
1944 struct ir3_instruction
*instr
)
1946 add_sysval_input_compmask(ctx
, slot
, 0x1, instr
);
1950 emit_intrinsic(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1952 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1953 struct ir3_instruction
**dst
;
1954 struct ir3_instruction
* const *src
;
1955 struct ir3_block
*b
= ctx
->block
;
1956 nir_const_value
*const_offset
;
1959 if (info
->has_dest
) {
1961 if (info
->dest_components
)
1962 n
= info
->dest_components
;
1964 n
= intr
->num_components
;
1965 dst
= get_dst(ctx
, &intr
->dest
, n
);
1970 switch (intr
->intrinsic
) {
1971 case nir_intrinsic_load_uniform
:
1972 idx
= nir_intrinsic_base(intr
);
1973 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1975 idx
+= const_offset
->u32
[0];
1976 for (int i
= 0; i
< intr
->num_components
; i
++) {
1977 unsigned n
= idx
* 4 + i
;
1978 dst
[i
] = create_uniform(ctx
, n
);
1981 src
= get_src(ctx
, &intr
->src
[0]);
1982 for (int i
= 0; i
< intr
->num_components
; i
++) {
1983 int n
= idx
* 4 + i
;
1984 dst
[i
] = create_uniform_indirect(ctx
, n
,
1985 get_addr(ctx
, src
[0], 4));
1987 /* NOTE: if relative addressing is used, we set
1988 * constlen in the compiler (to worst-case value)
1989 * since we don't know in the assembler what the max
1990 * addr reg value can be:
1992 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
1995 case nir_intrinsic_load_ubo
:
1996 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1998 case nir_intrinsic_load_input
:
1999 idx
= nir_intrinsic_base(intr
);
2000 comp
= nir_intrinsic_component(intr
);
2001 const_offset
= nir_src_as_const_value(intr
->src
[0]);
2003 idx
+= const_offset
->u32
[0];
2004 for (int i
= 0; i
< intr
->num_components
; i
++) {
2005 unsigned n
= idx
* 4 + i
+ comp
;
2006 dst
[i
] = ctx
->ir
->inputs
[n
];
2009 src
= get_src(ctx
, &intr
->src
[0]);
2010 struct ir3_instruction
*collect
=
2011 create_collect(b
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
2012 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0], 4);
2013 for (int i
= 0; i
< intr
->num_components
; i
++) {
2014 unsigned n
= idx
* 4 + i
+ comp
;
2015 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
2020 case nir_intrinsic_load_ssbo
:
2021 emit_intrinsic_load_ssbo(ctx
, intr
, dst
);
2023 case nir_intrinsic_store_ssbo
:
2024 emit_intrinsic_store_ssbo(ctx
, intr
);
2026 case nir_intrinsic_get_buffer_size
:
2027 emit_intrinsic_ssbo_size(ctx
, intr
, dst
);
2029 case nir_intrinsic_ssbo_atomic_add
:
2030 case nir_intrinsic_ssbo_atomic_imin
:
2031 case nir_intrinsic_ssbo_atomic_umin
:
2032 case nir_intrinsic_ssbo_atomic_imax
:
2033 case nir_intrinsic_ssbo_atomic_umax
:
2034 case nir_intrinsic_ssbo_atomic_and
:
2035 case nir_intrinsic_ssbo_atomic_or
:
2036 case nir_intrinsic_ssbo_atomic_xor
:
2037 case nir_intrinsic_ssbo_atomic_exchange
:
2038 case nir_intrinsic_ssbo_atomic_comp_swap
:
2039 dst
[0] = emit_intrinsic_atomic_ssbo(ctx
, intr
);
2041 case nir_intrinsic_load_shared
:
2042 emit_intrinsic_load_shared(ctx
, intr
, dst
);
2044 case nir_intrinsic_store_shared
:
2045 emit_intrinsic_store_shared(ctx
, intr
);
2047 case nir_intrinsic_shared_atomic_add
:
2048 case nir_intrinsic_shared_atomic_imin
:
2049 case nir_intrinsic_shared_atomic_umin
:
2050 case nir_intrinsic_shared_atomic_imax
:
2051 case nir_intrinsic_shared_atomic_umax
:
2052 case nir_intrinsic_shared_atomic_and
:
2053 case nir_intrinsic_shared_atomic_or
:
2054 case nir_intrinsic_shared_atomic_xor
:
2055 case nir_intrinsic_shared_atomic_exchange
:
2056 case nir_intrinsic_shared_atomic_comp_swap
:
2057 dst
[0] = emit_intrinsic_atomic_shared(ctx
, intr
);
2059 case nir_intrinsic_image_load
:
2060 emit_intrinsic_load_image(ctx
, intr
, dst
);
2062 case nir_intrinsic_image_store
:
2063 emit_intrinsic_store_image(ctx
, intr
);
2065 case nir_intrinsic_image_size
:
2066 emit_intrinsic_image_size(ctx
, intr
, dst
);
2068 case nir_intrinsic_image_atomic_add
:
2069 case nir_intrinsic_image_atomic_min
:
2070 case nir_intrinsic_image_atomic_max
:
2071 case nir_intrinsic_image_atomic_and
:
2072 case nir_intrinsic_image_atomic_or
:
2073 case nir_intrinsic_image_atomic_xor
:
2074 case nir_intrinsic_image_atomic_exchange
:
2075 case nir_intrinsic_image_atomic_comp_swap
:
2076 dst
[0] = emit_intrinsic_atomic_image(ctx
, intr
);
2078 case nir_intrinsic_barrier
:
2079 case nir_intrinsic_memory_barrier
:
2080 case nir_intrinsic_group_memory_barrier
:
2081 case nir_intrinsic_memory_barrier_atomic_counter
:
2082 case nir_intrinsic_memory_barrier_buffer
:
2083 case nir_intrinsic_memory_barrier_image
:
2084 case nir_intrinsic_memory_barrier_shared
:
2085 emit_intrinsic_barrier(ctx
, intr
);
2086 /* note that blk ptr no longer valid, make that obvious: */
2089 case nir_intrinsic_store_output
:
2090 idx
= nir_intrinsic_base(intr
);
2091 comp
= nir_intrinsic_component(intr
);
2092 const_offset
= nir_src_as_const_value(intr
->src
[1]);
2093 compile_assert(ctx
, const_offset
!= NULL
);
2094 idx
+= const_offset
->u32
[0];
2096 src
= get_src(ctx
, &intr
->src
[0]);
2097 for (int i
= 0; i
< intr
->num_components
; i
++) {
2098 unsigned n
= idx
* 4 + i
+ comp
;
2099 ctx
->ir
->outputs
[n
] = src
[i
];
2102 case nir_intrinsic_load_base_vertex
:
2103 if (!ctx
->basevertex
) {
2104 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
2105 add_sysval_input(ctx
, SYSTEM_VALUE_BASE_VERTEX
,
2108 dst
[0] = ctx
->basevertex
;
2110 case nir_intrinsic_load_vertex_id_zero_base
:
2111 case nir_intrinsic_load_vertex_id
:
2112 if (!ctx
->vertex_id
) {
2113 gl_system_value sv
= (intr
->intrinsic
== nir_intrinsic_load_vertex_id
) ?
2114 SYSTEM_VALUE_VERTEX_ID
: SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
;
2115 ctx
->vertex_id
= create_input(b
, 0);
2116 add_sysval_input(ctx
, sv
, ctx
->vertex_id
);
2118 dst
[0] = ctx
->vertex_id
;
2120 case nir_intrinsic_load_instance_id
:
2121 if (!ctx
->instance_id
) {
2122 ctx
->instance_id
= create_input(b
, 0);
2123 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
2126 dst
[0] = ctx
->instance_id
;
2128 case nir_intrinsic_load_user_clip_plane
:
2129 idx
= nir_intrinsic_ucp_id(intr
);
2130 for (int i
= 0; i
< intr
->num_components
; i
++) {
2131 unsigned n
= idx
* 4 + i
;
2132 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
2135 case nir_intrinsic_load_front_face
:
2136 if (!ctx
->frag_face
) {
2137 ctx
->so
->frag_face
= true;
2138 ctx
->frag_face
= create_input(b
, 0);
2139 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
2141 /* for fragface, we get -1 for back and 0 for front. However this is
2142 * the inverse of what nir expects (where ~0 is true).
2144 dst
[0] = ir3_COV(b
, ctx
->frag_face
, TYPE_S16
, TYPE_S32
);
2145 dst
[0] = ir3_NOT_B(b
, dst
[0], 0);
2147 case nir_intrinsic_load_local_invocation_id
:
2148 if (!ctx
->local_invocation_id
) {
2149 ctx
->local_invocation_id
= create_input_compmask(b
, 0, 0x7);
2150 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
,
2151 0x7, ctx
->local_invocation_id
);
2153 split_dest(b
, dst
, ctx
->local_invocation_id
, 0, 3);
2155 case nir_intrinsic_load_work_group_id
:
2156 if (!ctx
->work_group_id
) {
2157 ctx
->work_group_id
= create_input_compmask(b
, 0, 0x7);
2158 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_WORK_GROUP_ID
,
2159 0x7, ctx
->work_group_id
);
2160 ctx
->work_group_id
->regs
[0]->flags
|= IR3_REG_HIGH
;
2162 split_dest(b
, dst
, ctx
->work_group_id
, 0, 3);
2164 case nir_intrinsic_load_num_work_groups
:
2165 for (int i
= 0; i
< intr
->num_components
; i
++) {
2166 dst
[i
] = create_driver_param(ctx
, IR3_DP_NUM_WORK_GROUPS_X
+ i
);
2169 case nir_intrinsic_discard_if
:
2170 case nir_intrinsic_discard
: {
2171 struct ir3_instruction
*cond
, *kill
;
2173 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
2174 /* conditional discard: */
2175 src
= get_src(ctx
, &intr
->src
[0]);
2176 cond
= ir3_b2n(b
, src
[0]);
2178 /* unconditional discard: */
2179 cond
= create_immed(b
, 1);
2182 /* NOTE: only cmps.*.* can write p0.x: */
2183 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
2184 cond
->cat2
.condition
= IR3_COND_NE
;
2186 /* condition always goes in predicate register: */
2187 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2189 kill
= ir3_KILL(b
, cond
, 0);
2190 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
2192 array_insert(b
, b
->keeps
, kill
);
2193 ctx
->so
->has_kill
= true;
2198 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
2199 nir_intrinsic_infos
[intr
->intrinsic
].name
);
2204 put_dst(ctx
, &intr
->dest
);
2208 emit_load_const(struct ir3_context
*ctx
, nir_load_const_instr
*instr
)
2210 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
2211 instr
->def
.num_components
);
2212 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
2213 dst
[i
] = create_immed(ctx
->block
, instr
->value
.u32
[i
]);
2217 emit_undef(struct ir3_context
*ctx
, nir_ssa_undef_instr
*undef
)
2219 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
2220 undef
->def
.num_components
);
2221 /* backend doesn't want undefined instructions, so just plug
2224 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
2225 dst
[i
] = create_immed(ctx
->block
, fui(0.0));
2229 * texture fetch/sample instructions:
2233 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
2235 unsigned coords
, flags
= 0;
2237 /* note: would use tex->coord_components.. except txs.. also,
2238 * since array index goes after shadow ref, we don't want to
2241 switch (tex
->sampler_dim
) {
2242 case GLSL_SAMPLER_DIM_1D
:
2243 case GLSL_SAMPLER_DIM_BUF
:
2246 case GLSL_SAMPLER_DIM_2D
:
2247 case GLSL_SAMPLER_DIM_RECT
:
2248 case GLSL_SAMPLER_DIM_EXTERNAL
:
2249 case GLSL_SAMPLER_DIM_MS
:
2252 case GLSL_SAMPLER_DIM_3D
:
2253 case GLSL_SAMPLER_DIM_CUBE
:
2255 flags
|= IR3_INSTR_3D
;
2258 unreachable("bad sampler_dim");
2261 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2262 flags
|= IR3_INSTR_S
;
2264 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
2265 flags
|= IR3_INSTR_A
;
2272 emit_tex(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2274 struct ir3_block
*b
= ctx
->block
;
2275 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
2276 struct ir3_instruction
* const *coord
, * const *off
, * const *ddx
, * const *ddy
;
2277 struct ir3_instruction
*lod
, *compare
, *proj
;
2278 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
2279 unsigned i
, coords
, flags
;
2280 unsigned nsrc0
= 0, nsrc1
= 0;
2284 coord
= off
= ddx
= ddy
= NULL
;
2285 lod
= proj
= compare
= NULL
;
2287 /* TODO: might just be one component for gathers? */
2288 dst
= get_dst(ctx
, &tex
->dest
, 4);
2290 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
2291 switch (tex
->src
[i
].src_type
) {
2292 case nir_tex_src_coord
:
2293 coord
= get_src(ctx
, &tex
->src
[i
].src
);
2295 case nir_tex_src_bias
:
2296 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2299 case nir_tex_src_lod
:
2300 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2303 case nir_tex_src_comparator
: /* shadow comparator */
2304 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2306 case nir_tex_src_projector
:
2307 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2310 case nir_tex_src_offset
:
2311 off
= get_src(ctx
, &tex
->src
[i
].src
);
2314 case nir_tex_src_ddx
:
2315 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
2317 case nir_tex_src_ddy
:
2318 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
2321 compile_error(ctx
, "Unhandled NIR tex src type: %d\n",
2322 tex
->src
[i
].src_type
);
2328 case nir_texop_tex
: opc
= OPC_SAM
; break;
2329 case nir_texop_txb
: opc
= OPC_SAMB
; break;
2330 case nir_texop_txl
: opc
= OPC_SAML
; break;
2331 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
2332 case nir_texop_txf
: opc
= OPC_ISAML
; break;
2333 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
2335 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2336 * what blob does, seems gather is broken?), and a3xx did
2337 * not support it (but probably could also emulate).
2339 switch (tex
->component
) {
2340 case 0: opc
= OPC_GATHER4R
; break;
2341 case 1: opc
= OPC_GATHER4G
; break;
2342 case 2: opc
= OPC_GATHER4B
; break;
2343 case 3: opc
= OPC_GATHER4A
; break;
2346 case nir_texop_txf_ms
:
2348 case nir_texop_query_levels
:
2349 case nir_texop_texture_samples
:
2350 case nir_texop_samples_identical
:
2351 case nir_texop_txf_ms_mcs
:
2352 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
2356 tex_info(tex
, &flags
, &coords
);
2359 * lay out the first argument in the proper order:
2360 * - actual coordinates first
2361 * - shadow reference
2364 * - starting at offset 4, dpdx.xy, dpdy.xy
2366 * bias/lod go into the second arg
2369 /* insert tex coords: */
2370 for (i
= 0; i
< coords
; i
++)
2375 /* scale up integer coords for TXF based on the LOD */
2376 if (ctx
->unminify_coords
&& (opc
== OPC_ISAML
)) {
2378 for (i
= 0; i
< coords
; i
++)
2379 src0
[i
] = ir3_SHL_B(b
, src0
[i
], 0, lod
, 0);
2383 /* hw doesn't do 1d, so we treat it as 2d with
2384 * height of 1, and patch up the y coord.
2385 * TODO: y coord should be (int)0 in some cases..
2387 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
2390 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2391 src0
[nsrc0
++] = compare
;
2393 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
) {
2394 struct ir3_instruction
*idx
= coord
[coords
];
2396 /* the array coord for cube arrays needs 0.5 added to it */
2397 if (ctx
->array_index_add_half
&& (opc
!= OPC_ISAML
))
2398 idx
= ir3_ADD_F(b
, idx
, 0, create_immed(b
, fui(0.5)), 0);
2400 src0
[nsrc0
++] = idx
;
2404 src0
[nsrc0
++] = proj
;
2405 flags
|= IR3_INSTR_P
;
2408 /* pad to 4, then ddx/ddy: */
2409 if (tex
->op
== nir_texop_txd
) {
2411 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2412 for (i
= 0; i
< coords
; i
++)
2413 src0
[nsrc0
++] = ddx
[i
];
2415 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2416 for (i
= 0; i
< coords
; i
++)
2417 src0
[nsrc0
++] = ddy
[i
];
2419 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2423 * second argument (if applicable):
2428 if (has_off
| has_lod
| has_bias
) {
2430 unsigned off_coords
= coords
;
2431 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2433 for (i
= 0; i
< off_coords
; i
++)
2434 src1
[nsrc1
++] = off
[i
];
2436 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
2437 flags
|= IR3_INSTR_O
;
2440 if (has_lod
| has_bias
)
2441 src1
[nsrc1
++] = lod
;
2444 switch (tex
->dest_type
) {
2445 case nir_type_invalid
:
2446 case nir_type_float
:
2457 unreachable("bad dest_type");
2460 if (opc
== OPC_GETLOD
)
2463 unsigned tex_idx
= tex
->texture_index
;
2465 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex_idx
);
2467 struct ir3_instruction
*col0
= create_collect(b
, src0
, nsrc0
);
2468 struct ir3_instruction
*col1
= create_collect(b
, src1
, nsrc1
);
2470 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
, flags
,
2471 tex_idx
, tex_idx
, col0
, col1
);
2473 if ((ctx
->astc_srgb
& (1 << tex_idx
)) && !nir_tex_instr_is_query(tex
)) {
2474 /* only need first 3 components: */
2475 sam
->regs
[0]->wrmask
= 0x7;
2476 split_dest(b
, dst
, sam
, 0, 3);
2478 /* we need to sample the alpha separately with a non-ASTC
2481 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_W
, flags
,
2482 tex_idx
, tex_idx
, col0
, col1
);
2484 array_insert(ctx
->ir
, ctx
->ir
->astc_srgb
, sam
);
2486 /* fixup .w component: */
2487 split_dest(b
, &dst
[3], sam
, 3, 1);
2489 /* normal (non-workaround) case: */
2490 split_dest(b
, dst
, sam
, 0, 4);
2493 /* GETLOD returns results in 4.8 fixed point */
2494 if (opc
== OPC_GETLOD
) {
2495 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
2497 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
2498 for (i
= 0; i
< 2; i
++) {
2499 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_U32
, TYPE_F32
), 0,
2504 put_dst(ctx
, &tex
->dest
);
2508 emit_tex_query_levels(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2510 struct ir3_block
*b
= ctx
->block
;
2511 struct ir3_instruction
**dst
, *sam
;
2513 dst
= get_dst(ctx
, &tex
->dest
, 1);
2515 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
2516 tex
->texture_index
, tex
->texture_index
, NULL
, NULL
);
2518 /* even though there is only one component, since it ends
2519 * up in .z rather than .x, we need a split_dest()
2521 split_dest(b
, dst
, sam
, 0, 3);
2523 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2524 * the value in TEX_CONST_0 is zero-based.
2526 if (ctx
->levels_add_one
)
2527 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
2529 put_dst(ctx
, &tex
->dest
);
2533 emit_tex_txs(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2535 struct ir3_block
*b
= ctx
->block
;
2536 struct ir3_instruction
**dst
, *sam
;
2537 struct ir3_instruction
*lod
;
2538 unsigned flags
, coords
;
2540 tex_info(tex
, &flags
, &coords
);
2542 /* Actually we want the number of dimensions, not coordinates. This
2543 * distinction only matters for cubes.
2545 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2548 dst
= get_dst(ctx
, &tex
->dest
, 4);
2550 compile_assert(ctx
, tex
->num_srcs
== 1);
2551 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
2553 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
2555 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
2556 tex
->texture_index
, tex
->texture_index
, lod
, NULL
);
2558 split_dest(b
, dst
, sam
, 0, 4);
2560 /* Array size actually ends up in .w rather than .z. This doesn't
2561 * matter for miplevel 0, but for higher mips the value in z is
2562 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2563 * returned, which means that we have to add 1 to it for arrays.
2565 if (tex
->is_array
) {
2566 if (ctx
->levels_add_one
) {
2567 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
2569 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
2573 put_dst(ctx
, &tex
->dest
);
2577 emit_phi(struct ir3_context
*ctx
, nir_phi_instr
*nphi
)
2579 struct ir3_instruction
*phi
, **dst
;
2581 /* NOTE: phi's should be lowered to scalar at this point */
2582 compile_assert(ctx
, nphi
->dest
.ssa
.num_components
== 1);
2584 dst
= get_dst(ctx
, &nphi
->dest
, 1);
2586 phi
= ir3_instr_create2(ctx
->block
, OPC_META_PHI
,
2587 1 + exec_list_length(&nphi
->srcs
));
2588 ir3_reg_create(phi
, 0, 0); /* dst */
2589 phi
->phi
.nphi
= nphi
;
2593 put_dst(ctx
, &nphi
->dest
);
2596 /* phi instructions are left partially constructed. We don't resolve
2597 * their srcs until the end of the block, since (eg. loops) one of
2598 * the phi's srcs might be defined after the phi due to back edges in
2602 resolve_phis(struct ir3_context
*ctx
, struct ir3_block
*block
)
2604 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
2605 nir_phi_instr
*nphi
;
2607 /* phi's only come at start of block: */
2608 if (instr
->opc
!= OPC_META_PHI
)
2611 if (!instr
->phi
.nphi
)
2614 nphi
= instr
->phi
.nphi
;
2615 instr
->phi
.nphi
= NULL
;
2617 foreach_list_typed(nir_phi_src
, nsrc
, node
, &nphi
->srcs
) {
2618 struct ir3_instruction
*src
= get_src(ctx
, &nsrc
->src
)[0];
2620 /* NOTE: src might not be in the same block as it comes from
2621 * according to the phi.. but in the end the backend assumes
2622 * it will be able to assign the same register to each (which
2623 * only works if it is assigned in the src block), so insert
2624 * an extra mov to make sure the phi src is assigned in the
2625 * block it comes from:
2627 src
= ir3_MOV(get_block(ctx
, nsrc
->pred
), src
, TYPE_U32
);
2629 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
2635 emit_jump(struct ir3_context
*ctx
, nir_jump_instr
*jump
)
2637 switch (jump
->type
) {
2638 case nir_jump_break
:
2639 case nir_jump_continue
:
2640 /* I *think* we can simply just ignore this, and use the
2641 * successor block link to figure out where we need to
2642 * jump to for break/continue
2646 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
2652 emit_instr(struct ir3_context
*ctx
, nir_instr
*instr
)
2654 switch (instr
->type
) {
2655 case nir_instr_type_alu
:
2656 emit_alu(ctx
, nir_instr_as_alu(instr
));
2658 case nir_instr_type_intrinsic
:
2659 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2661 case nir_instr_type_load_const
:
2662 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2664 case nir_instr_type_ssa_undef
:
2665 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
2667 case nir_instr_type_tex
: {
2668 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
2669 /* couple tex instructions get special-cased:
2673 emit_tex_txs(ctx
, tex
);
2675 case nir_texop_query_levels
:
2676 emit_tex_query_levels(ctx
, tex
);
2684 case nir_instr_type_phi
:
2685 emit_phi(ctx
, nir_instr_as_phi(instr
));
2687 case nir_instr_type_jump
:
2688 emit_jump(ctx
, nir_instr_as_jump(instr
));
2690 case nir_instr_type_call
:
2691 case nir_instr_type_parallel_copy
:
2692 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
2697 static struct ir3_block
*
2698 get_block(struct ir3_context
*ctx
, nir_block
*nblock
)
2700 struct ir3_block
*block
;
2701 struct hash_entry
*entry
;
2702 entry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
2706 block
= ir3_block_create(ctx
->ir
);
2707 block
->nblock
= nblock
;
2708 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
2714 emit_block(struct ir3_context
*ctx
, nir_block
*nblock
)
2716 struct ir3_block
*block
= get_block(ctx
, nblock
);
2718 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
2719 if (nblock
->successors
[i
]) {
2720 block
->successors
[i
] =
2721 get_block(ctx
, nblock
->successors
[i
]);
2726 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
2728 /* re-emit addr register in each block if needed: */
2729 for (int i
= 0; i
< ARRAY_SIZE(ctx
->addr_ht
); i
++) {
2730 _mesa_hash_table_destroy(ctx
->addr_ht
[i
], NULL
);
2731 ctx
->addr_ht
[i
] = NULL
;
2734 nir_foreach_instr(instr
, nblock
) {
2735 emit_instr(ctx
, instr
);
2741 static void emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
);
2744 emit_if(struct ir3_context
*ctx
, nir_if
*nif
)
2746 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
2748 ctx
->block
->condition
=
2749 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
2751 emit_cf_list(ctx
, &nif
->then_list
);
2752 emit_cf_list(ctx
, &nif
->else_list
);
2756 emit_loop(struct ir3_context
*ctx
, nir_loop
*nloop
)
2758 emit_cf_list(ctx
, &nloop
->body
);
2762 emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
)
2764 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2765 switch (node
->type
) {
2766 case nir_cf_node_block
:
2767 emit_block(ctx
, nir_cf_node_as_block(node
));
2769 case nir_cf_node_if
:
2770 emit_if(ctx
, nir_cf_node_as_if(node
));
2772 case nir_cf_node_loop
:
2773 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2775 case nir_cf_node_function
:
2776 compile_error(ctx
, "TODO\n");
2782 /* emit stream-out code. At this point, the current block is the original
2783 * (nir) end block, and nir ensures that all flow control paths terminate
2784 * into the end block. We re-purpose the original end block to generate
2785 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2786 * block holding stream-out write instructions, followed by the new end
2790 * p0.x = (vtxcnt < maxvtxcnt)
2791 * // succs: blockStreamOut, blockNewEnd
2794 * ... stream-out instructions ...
2795 * // succs: blockNewEnd
2801 emit_stream_out(struct ir3_context
*ctx
)
2803 struct ir3_shader_variant
*v
= ctx
->so
;
2804 struct ir3
*ir
= ctx
->ir
;
2805 struct pipe_stream_output_info
*strmout
=
2806 &ctx
->so
->shader
->stream_output
;
2807 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
2808 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
2809 struct ir3_instruction
*bases
[PIPE_MAX_SO_BUFFERS
];
2811 /* create vtxcnt input in input block at top of shader,
2812 * so that it is seen as live over the entire duration
2815 vtxcnt
= create_input(ctx
->in_block
, 0);
2816 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
2818 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
2820 /* at this point, we are at the original 'end' block,
2821 * re-purpose this block to stream-out condition, then
2822 * append stream-out block and new-end block
2824 orig_end_block
= ctx
->block
;
2826 stream_out_block
= ir3_block_create(ir
);
2827 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
2829 new_end_block
= ir3_block_create(ir
);
2830 list_addtail(&new_end_block
->node
, &ir
->block_list
);
2832 orig_end_block
->successors
[0] = stream_out_block
;
2833 orig_end_block
->successors
[1] = new_end_block
;
2834 stream_out_block
->successors
[0] = new_end_block
;
2836 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2837 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
2838 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2839 cond
->cat2
.condition
= IR3_COND_LT
;
2841 /* condition goes on previous block to the conditional,
2842 * since it is used to pick which of the two successor
2845 orig_end_block
->condition
= cond
;
2847 /* switch to stream_out_block to generate the stream-out
2850 ctx
->block
= stream_out_block
;
2852 /* Calculate base addresses based on vtxcnt. Instructions
2853 * generated for bases not used in following loop will be
2854 * stripped out in the backend.
2856 for (unsigned i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
2857 unsigned stride
= strmout
->stride
[i
];
2858 struct ir3_instruction
*base
, *off
;
2860 base
= create_uniform(ctx
, regid(v
->constbase
.tfbo
, i
));
2862 /* 24-bit should be enough: */
2863 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
2864 create_immed(ctx
->block
, stride
* 4), 0);
2866 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
2869 /* Generate the per-output store instructions: */
2870 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
2871 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
2872 unsigned c
= j
+ strmout
->output
[i
].start_component
;
2873 struct ir3_instruction
*base
, *out
, *stg
;
2875 base
= bases
[strmout
->output
[i
].output_buffer
];
2876 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
2878 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
2879 create_immed(ctx
->block
, 1), 0);
2880 stg
->cat6
.type
= TYPE_U32
;
2881 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
2883 array_insert(ctx
->block
, ctx
->block
->keeps
, stg
);
2887 /* and finally switch to the new_end_block: */
2888 ctx
->block
= new_end_block
;
2892 emit_function(struct ir3_context
*ctx
, nir_function_impl
*impl
)
2894 nir_metadata_require(impl
, nir_metadata_block_index
);
2896 emit_cf_list(ctx
, &impl
->body
);
2897 emit_block(ctx
, impl
->end_block
);
2899 /* at this point, we should have a single empty block,
2900 * into which we emit the 'end' instruction.
2902 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
2904 /* If stream-out (aka transform-feedback) enabled, emit the
2905 * stream-out instructions, followed by a new empty block (into
2906 * which the 'end' instruction lands).
2908 * NOTE: it is done in this order, rather than inserting before
2909 * we emit end_block, because NIR guarantees that all blocks
2910 * flow into end_block, and that end_block has no successors.
2911 * So by re-purposing end_block as the first block of stream-
2912 * out, we guarantee that all exit paths flow into the stream-
2915 if ((ctx
->compiler
->gpu_id
< 500) &&
2916 (ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
2917 !ctx
->so
->key
.binning_pass
) {
2918 debug_assert(ctx
->so
->type
== SHADER_VERTEX
);
2919 emit_stream_out(ctx
);
2922 ir3_END(ctx
->block
);
2926 setup_input(struct ir3_context
*ctx
, nir_variable
*in
)
2928 struct ir3_shader_variant
*so
= ctx
->so
;
2929 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
2930 unsigned ncomp
= glsl_get_components(in
->type
);
2931 unsigned n
= in
->data
.driver_location
;
2932 unsigned slot
= in
->data
.location
;
2934 DBG("; in: slot=%u, len=%ux%u, drvloc=%u",
2935 slot
, array_len
, ncomp
, n
);
2937 /* let's pretend things other than vec4 don't exist: */
2938 ncomp
= MAX2(ncomp
, 4);
2939 compile_assert(ctx
, ncomp
== 4);
2941 so
->inputs
[n
].slot
= slot
;
2942 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
2943 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2944 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
2946 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2947 for (int i
= 0; i
< ncomp
; i
++) {
2948 struct ir3_instruction
*instr
= NULL
;
2949 unsigned idx
= (n
* 4) + i
;
2951 if (slot
== VARYING_SLOT_POS
) {
2952 so
->inputs
[n
].bary
= false;
2953 so
->frag_coord
= true;
2954 instr
= create_frag_coord(ctx
, i
);
2955 } else if (slot
== VARYING_SLOT_PNTC
) {
2956 /* see for example st_get_generic_varying_index().. this is
2957 * maybe a bit mesa/st specific. But we need things to line
2958 * up for this in fdN_program:
2959 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2960 * if (emit->sprite_coord_enable & texmask) {
2964 so
->inputs
[n
].slot
= VARYING_SLOT_VAR8
;
2965 so
->inputs
[n
].bary
= true;
2966 instr
= create_frag_input(ctx
, false);
2968 bool use_ldlv
= false;
2970 /* detect the special case for front/back colors where
2971 * we need to do flat vs smooth shading depending on
2974 if (in
->data
.interpolation
== INTERP_MODE_NONE
) {
2976 case VARYING_SLOT_COL0
:
2977 case VARYING_SLOT_COL1
:
2978 case VARYING_SLOT_BFC0
:
2979 case VARYING_SLOT_BFC1
:
2980 so
->inputs
[n
].rasterflat
= true;
2987 if (ctx
->flat_bypass
) {
2988 if ((so
->inputs
[n
].interpolate
== INTERP_MODE_FLAT
) ||
2989 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
2993 so
->inputs
[n
].bary
= true;
2995 instr
= create_frag_input(ctx
, use_ldlv
);
2998 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
3000 ctx
->ir
->inputs
[idx
] = instr
;
3002 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
3003 for (int i
= 0; i
< ncomp
; i
++) {
3004 unsigned idx
= (n
* 4) + i
;
3005 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
3006 ctx
->ir
->inputs
[idx
] = create_input(ctx
->block
, idx
);
3009 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3012 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
3013 so
->total_in
+= ncomp
;
3018 setup_output(struct ir3_context
*ctx
, nir_variable
*out
)
3020 struct ir3_shader_variant
*so
= ctx
->so
;
3021 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
3022 unsigned ncomp
= glsl_get_components(out
->type
);
3023 unsigned n
= out
->data
.driver_location
;
3024 unsigned slot
= out
->data
.location
;
3027 DBG("; out: slot=%u, len=%ux%u, drvloc=%u",
3028 slot
, array_len
, ncomp
, n
);
3030 /* let's pretend things other than vec4 don't exist: */
3031 ncomp
= MAX2(ncomp
, 4);
3032 compile_assert(ctx
, ncomp
== 4);
3034 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3036 case FRAG_RESULT_DEPTH
:
3037 comp
= 2; /* tgsi will write to .z component */
3038 so
->writes_pos
= true;
3040 case FRAG_RESULT_COLOR
:
3044 if (slot
>= FRAG_RESULT_DATA0
)
3046 compile_error(ctx
, "unknown FS output name: %s\n",
3047 gl_frag_result_name(slot
));
3049 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
3051 case VARYING_SLOT_POS
:
3052 so
->writes_pos
= true;
3054 case VARYING_SLOT_PSIZ
:
3055 so
->writes_psize
= true;
3057 case VARYING_SLOT_COL0
:
3058 case VARYING_SLOT_COL1
:
3059 case VARYING_SLOT_BFC0
:
3060 case VARYING_SLOT_BFC1
:
3061 case VARYING_SLOT_FOGC
:
3062 case VARYING_SLOT_CLIP_DIST0
:
3063 case VARYING_SLOT_CLIP_DIST1
:
3064 case VARYING_SLOT_CLIP_VERTEX
:
3067 if (slot
>= VARYING_SLOT_VAR0
)
3069 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
3071 compile_error(ctx
, "unknown VS output name: %s\n",
3072 gl_varying_slot_name(slot
));
3075 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3078 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
3080 so
->outputs
[n
].slot
= slot
;
3081 so
->outputs
[n
].regid
= regid(n
, comp
);
3082 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
3084 for (int i
= 0; i
< ncomp
; i
++) {
3085 unsigned idx
= (n
* 4) + i
;
3086 compile_assert(ctx
, idx
< ctx
->ir
->noutputs
);
3087 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
3092 max_drvloc(struct exec_list
*vars
)
3095 nir_foreach_variable(var
, vars
) {
3096 drvloc
= MAX2(drvloc
, (int)var
->data
.driver_location
);
3101 static const unsigned max_sysvals
[SHADER_MAX
] = {
3102 [SHADER_VERTEX
] = 16,
3103 [SHADER_COMPUTE
] = 16, // TODO how many do we actually need?
3107 emit_instructions(struct ir3_context
*ctx
)
3109 unsigned ninputs
, noutputs
;
3110 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
3112 ninputs
= (max_drvloc(&ctx
->s
->inputs
) + 1) * 4;
3113 noutputs
= (max_drvloc(&ctx
->s
->outputs
) + 1) * 4;
3115 /* we need to leave room for sysvals:
3117 ninputs
+= max_sysvals
[ctx
->so
->type
];
3119 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
3121 /* Create inputs in first block: */
3122 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
3123 ctx
->in_block
= ctx
->block
;
3124 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
3126 ninputs
-= max_sysvals
[ctx
->so
->type
];
3128 /* for fragment shader, we have a single input register (usually
3129 * r0.xy) which is used as the base for bary.f varying fetch instrs:
3131 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3132 // TODO maybe a helper for fi since we need it a few places..
3133 struct ir3_instruction
*instr
;
3134 instr
= ir3_instr_create(ctx
->block
, OPC_META_FI
);
3135 ir3_reg_create(instr
, 0, 0);
3136 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.x */
3137 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.y */
3138 ctx
->frag_pos
= instr
;
3142 nir_foreach_variable(var
, &ctx
->s
->inputs
) {
3143 setup_input(ctx
, var
);
3146 /* Setup outputs: */
3147 nir_foreach_variable(var
, &ctx
->s
->outputs
) {
3148 setup_output(ctx
, var
);
3151 /* Setup registers (which should only be arrays): */
3152 nir_foreach_register(reg
, &ctx
->s
->registers
) {
3153 declare_array(ctx
, reg
);
3156 /* NOTE: need to do something more clever when we support >1 fxn */
3157 nir_foreach_register(reg
, &fxn
->registers
) {
3158 declare_array(ctx
, reg
);
3160 /* And emit the body: */
3162 emit_function(ctx
, fxn
);
3164 list_for_each_entry (struct ir3_block
, block
, &ctx
->ir
->block_list
, node
) {
3165 resolve_phis(ctx
, block
);
3169 /* from NIR perspective, we actually have inputs. But most of the "inputs"
3170 * for a fragment shader are just bary.f instructions. The *actual* inputs
3171 * from the hw perspective are the frag_pos and optionally frag_coord and
3175 fixup_frag_inputs(struct ir3_context
*ctx
)
3177 struct ir3_shader_variant
*so
= ctx
->so
;
3178 struct ir3
*ir
= ctx
->ir
;
3179 struct ir3_instruction
**inputs
;
3180 struct ir3_instruction
*instr
;
3185 n
= 4; /* always have frag_pos */
3186 n
+= COND(so
->frag_face
, 4);
3187 n
+= COND(so
->frag_coord
, 4);
3189 inputs
= ir3_alloc(ctx
->ir
, n
* (sizeof(struct ir3_instruction
*)));
3191 if (so
->frag_face
) {
3192 /* this ultimately gets assigned to hr0.x so doesn't conflict
3193 * with frag_coord/frag_pos..
3195 inputs
[ir
->ninputs
++] = ctx
->frag_face
;
3196 ctx
->frag_face
->regs
[0]->num
= 0;
3198 /* remaining channels not used, but let's avoid confusing
3199 * other parts that expect inputs to come in groups of vec4
3201 inputs
[ir
->ninputs
++] = NULL
;
3202 inputs
[ir
->ninputs
++] = NULL
;
3203 inputs
[ir
->ninputs
++] = NULL
;
3206 /* since we don't know where to set the regid for frag_coord,
3207 * we have to use r0.x for it. But we don't want to *always*
3208 * use r1.x for frag_pos as that could increase the register
3209 * footprint on simple shaders:
3211 if (so
->frag_coord
) {
3212 ctx
->frag_coord
[0]->regs
[0]->num
= regid
++;
3213 ctx
->frag_coord
[1]->regs
[0]->num
= regid
++;
3214 ctx
->frag_coord
[2]->regs
[0]->num
= regid
++;
3215 ctx
->frag_coord
[3]->regs
[0]->num
= regid
++;
3217 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[0];
3218 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[1];
3219 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[2];
3220 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[3];
3223 /* we always have frag_pos: */
3224 so
->pos_regid
= regid
;
3227 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
3228 instr
->regs
[0]->num
= regid
++;
3229 inputs
[ir
->ninputs
++] = instr
;
3230 ctx
->frag_pos
->regs
[1]->instr
= instr
;
3233 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
3234 instr
->regs
[0]->num
= regid
++;
3235 inputs
[ir
->ninputs
++] = instr
;
3236 ctx
->frag_pos
->regs
[2]->instr
= instr
;
3238 ir
->inputs
= inputs
;
3241 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3242 * need to assign the tex state indexes for these after we know the
3246 fixup_astc_srgb(struct ir3_context
*ctx
)
3248 struct ir3_shader_variant
*so
= ctx
->so
;
3249 /* indexed by original tex idx, value is newly assigned alpha sampler
3250 * state tex idx. Zero is invalid since there is at least one sampler
3253 unsigned alt_tex_state
[16] = {0};
3254 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
3257 so
->astc_srgb
.base
= tex_idx
;
3259 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
3260 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
3262 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
3264 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
3265 /* assign new alternate/alpha tex state slot: */
3266 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
3267 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
3268 so
->astc_srgb
.count
++;
3271 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
3276 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
3277 struct ir3_shader_variant
*so
)
3279 struct ir3_context
*ctx
;
3281 struct ir3_instruction
**inputs
;
3282 unsigned i
, j
, actual_in
, inloc
;
3283 int ret
= 0, max_bary
;
3287 ctx
= compile_init(compiler
, so
);
3289 DBG("INIT failed!");
3294 emit_instructions(ctx
);
3297 DBG("EMIT failed!");
3302 ir
= so
->ir
= ctx
->ir
;
3304 /* keep track of the inputs from TGSI perspective.. */
3305 inputs
= ir
->inputs
;
3307 /* but fixup actual inputs for frag shader: */
3308 if (so
->type
== SHADER_FRAGMENT
)
3309 fixup_frag_inputs(ctx
);
3311 /* at this point, for binning pass, throw away unneeded outputs: */
3312 if (so
->key
.binning_pass
) {
3313 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
3314 unsigned slot
= so
->outputs
[i
].slot
;
3316 /* throw away everything but first position/psize */
3317 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
3319 so
->outputs
[j
] = so
->outputs
[i
];
3320 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
3321 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
3322 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
3323 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
3328 so
->outputs_count
= j
;
3329 ir
->noutputs
= j
* 4;
3332 /* if we want half-precision outputs, mark the output registers
3335 if (so
->key
.half_precision
) {
3336 for (i
= 0; i
< ir
->noutputs
; i
++) {
3337 struct ir3_instruction
*out
= ir
->outputs
[i
];
3342 /* if frag shader writes z, that needs to be full precision: */
3343 if (so
->outputs
[i
/4].slot
== FRAG_RESULT_DEPTH
)
3346 out
->regs
[0]->flags
|= IR3_REG_HALF
;
3347 /* output could be a fanout (ie. texture fetch output)
3348 * in which case we need to propagate the half-reg flag
3349 * up to the definer so that RA sees it:
3351 if (out
->opc
== OPC_META_FO
) {
3352 out
= out
->regs
[1]->instr
;
3353 out
->regs
[0]->flags
|= IR3_REG_HALF
;
3356 if (out
->opc
== OPC_MOV
) {
3357 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
3362 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3363 printf("BEFORE CP:\n");
3369 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3370 printf("BEFORE GROUPING:\n");
3374 ir3_sched_add_deps(ir
);
3376 /* Group left/right neighbors, inserting mov's where needed to
3381 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3382 printf("AFTER GROUPING:\n");
3388 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3389 printf("AFTER DEPTH:\n");
3393 ret
= ir3_sched(ir
);
3395 DBG("SCHED failed!");
3399 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3400 printf("AFTER SCHED:\n");
3404 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
3410 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3411 printf("AFTER RA:\n");
3415 /* fixup input/outputs: */
3416 for (i
= 0; i
< so
->outputs_count
; i
++) {
3417 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
3420 /* Note that some or all channels of an input may be unused: */
3423 for (i
= 0; i
< so
->inputs_count
; i
++) {
3424 unsigned j
, regid
= ~0, compmask
= 0, maxcomp
= 0;
3425 so
->inputs
[i
].ncomp
= 0;
3426 so
->inputs
[i
].inloc
= inloc
;
3427 for (j
= 0; j
< 4; j
++) {
3428 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
3429 if (in
&& !(in
->flags
& IR3_INSTR_UNUSED
)) {
3430 compmask
|= (1 << j
);
3431 regid
= in
->regs
[0]->num
- j
;
3433 so
->inputs
[i
].ncomp
++;
3434 if ((so
->type
== SHADER_FRAGMENT
) && so
->inputs
[i
].bary
) {
3436 assert(in
->regs
[1]->flags
& IR3_REG_IMMED
);
3437 in
->regs
[1]->iim_val
= inloc
+ j
;
3442 if ((so
->type
== SHADER_FRAGMENT
) && compmask
&& so
->inputs
[i
].bary
) {
3444 so
->inputs
[i
].compmask
= (1 << maxcomp
) - 1;
3447 so
->inputs
[i
].compmask
= compmask
;
3449 so
->inputs
[i
].regid
= regid
;
3453 fixup_astc_srgb(ctx
);
3455 /* We need to do legalize after (for frag shader's) the "bary.f"
3456 * offsets (inloc) have been assigned.
3458 ir3_legalize(ir
, &so
->has_samp
, &so
->has_ssbo
, &max_bary
);
3460 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3461 printf("AFTER LEGALIZE:\n");
3465 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3466 if (so
->type
== SHADER_VERTEX
)
3467 so
->total_in
= actual_in
;
3469 so
->total_in
= max_bary
+ 1;
3474 ir3_destroy(so
->ir
);