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[mesa.git] / src / gallium / drivers / freedreno / ir3 / ir3_compiler_nir.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include <stdarg.h>
30
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
35 #include "tgsi/tgsi_lowering.h"
36 #include "tgsi/tgsi_strings.h"
37
38 #include "nir/tgsi_to_nir.h"
39 #include "glsl/shader_enums.h"
40
41 #include "freedreno_util.h"
42
43 #include "ir3_compiler.h"
44 #include "ir3_shader.h"
45
46 #include "instr-a3xx.h"
47 #include "ir3.h"
48
49
50 static struct ir3_instruction * create_immed(struct ir3_block *block, uint32_t val);
51
52 struct ir3_compile {
53 const struct tgsi_token *tokens;
54 struct nir_shader *s;
55
56 struct ir3 *ir;
57 struct ir3_shader_variant *so;
58
59 /* bitmask of which samplers are integer: */
60 uint16_t integer_s;
61
62 struct ir3_block *block;
63
64 /* For fragment shaders, from the hw perspective the only
65 * actual input is r0.xy position register passed to bary.f.
66 * But TGSI doesn't know that, it still declares things as
67 * IN[] registers. So we do all the input tracking normally
68 * and fix things up after compile_instructions()
69 *
70 * NOTE that frag_pos is the hardware position (possibly it
71 * is actually an index or tag or some such.. it is *not*
72 * values that can be directly used for gl_FragCoord..)
73 */
74 struct ir3_instruction *frag_pos, *frag_face, *frag_coord[4];
75
76 /* For vertex shaders, keep track of the system values sources */
77 struct ir3_instruction *vertex_id, *basevertex, *instance_id;
78
79 /* mapping from nir_register to defining instruction: */
80 struct hash_table *def_ht;
81
82 /* mapping from nir_variable to ir3_array: */
83 struct hash_table *var_ht;
84 unsigned num_arrays;
85
86 /* a common pattern for indirect addressing is to request the
87 * same address register multiple times. To avoid generating
88 * duplicate instruction sequences (which our backend does not
89 * try to clean up, since that should be done as the NIR stage)
90 * we cache the address value generated for a given src value:
91 */
92 struct hash_table *addr_ht;
93
94 /* for calculating input/output positions/linkages: */
95 unsigned next_inloc;
96
97 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
98 * so we need to use ldlv.u32 to load the varying directly:
99 */
100 bool flat_bypass;
101
102 /* for looking up which system value is which */
103 unsigned sysval_semantics[8];
104
105 /* list of kill instructions: */
106 struct ir3_instruction *kill[16];
107 unsigned int kill_count;
108
109 /* set if we encounter something we can't handle yet, so we
110 * can bail cleanly and fallback to TGSI compiler f/e
111 */
112 bool error;
113 };
114
115
116 static struct nir_shader *to_nir(const struct tgsi_token *tokens)
117 {
118 struct nir_shader_compiler_options options = {
119 .lower_fpow = true,
120 .lower_fsat = true,
121 .lower_scmp = true,
122 .lower_flrp = true,
123 .native_integers = true,
124 };
125 bool progress;
126
127 struct nir_shader *s = tgsi_to_nir(tokens, &options);
128
129 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
130 debug_printf("----------------------\n");
131 nir_print_shader(s, stdout);
132 debug_printf("----------------------\n");
133 }
134
135 nir_opt_global_to_local(s);
136 nir_convert_to_ssa(s);
137 nir_lower_idiv(s);
138
139 do {
140 progress = false;
141
142 nir_lower_vars_to_ssa(s);
143 nir_lower_alu_to_scalar(s);
144
145 progress |= nir_copy_prop(s);
146 progress |= nir_opt_dce(s);
147 progress |= nir_opt_cse(s);
148 progress |= nir_opt_peephole_select(s);
149 progress |= nir_opt_algebraic(s);
150 progress |= nir_opt_constant_folding(s);
151
152 } while (progress);
153
154 nir_remove_dead_variables(s);
155 nir_validate_shader(s);
156
157 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
158 debug_printf("----------------------\n");
159 nir_print_shader(s, stdout);
160 debug_printf("----------------------\n");
161 }
162
163 return s;
164 }
165
166 /* TODO nir doesn't lower everything for us yet, but ideally it would: */
167 static const struct tgsi_token *
168 lower_tgsi(const struct tgsi_token *tokens, struct ir3_shader_variant *so)
169 {
170 struct tgsi_shader_info info;
171 struct tgsi_lowering_config lconfig = {
172 .color_two_side = so->key.color_two_side,
173 .lower_FRC = true,
174 };
175
176 switch (so->type) {
177 case SHADER_FRAGMENT:
178 case SHADER_COMPUTE:
179 lconfig.saturate_s = so->key.fsaturate_s;
180 lconfig.saturate_t = so->key.fsaturate_t;
181 lconfig.saturate_r = so->key.fsaturate_r;
182 break;
183 case SHADER_VERTEX:
184 lconfig.saturate_s = so->key.vsaturate_s;
185 lconfig.saturate_t = so->key.vsaturate_t;
186 lconfig.saturate_r = so->key.vsaturate_r;
187 break;
188 }
189
190 if (!so->shader) {
191 /* hack for standalone compiler which does not have
192 * screen/context:
193 */
194 } else if (ir3_shader_gpuid(so->shader) >= 400) {
195 /* a4xx seems to have *no* sam.p */
196 lconfig.lower_TXP = ~0; /* lower all txp */
197 } else {
198 /* a3xx just needs to avoid sam.p for 3d tex */
199 lconfig.lower_TXP = (1 << TGSI_TEXTURE_3D);
200 }
201
202 return tgsi_transform_lowering(&lconfig, tokens, &info);
203 }
204
205 static struct ir3_compile *
206 compile_init(struct ir3_shader_variant *so,
207 const struct tgsi_token *tokens)
208 {
209 struct ir3_compile *ctx = rzalloc(NULL, struct ir3_compile);
210 const struct tgsi_token *lowered_tokens;
211
212 if (!so->shader) {
213 /* hack for standalone compiler which does not have
214 * screen/context:
215 */
216 } else if (ir3_shader_gpuid(so->shader) >= 400) {
217 /* need special handling for "flat" */
218 ctx->flat_bypass = true;
219 } else {
220 /* no special handling for "flat" */
221 ctx->flat_bypass = false;
222 }
223
224 switch (so->type) {
225 case SHADER_FRAGMENT:
226 case SHADER_COMPUTE:
227 ctx->integer_s = so->key.finteger_s;
228 break;
229 case SHADER_VERTEX:
230 ctx->integer_s = so->key.vinteger_s;
231 break;
232 }
233
234 ctx->ir = so->ir;
235 ctx->so = so;
236 ctx->next_inloc = 8;
237 ctx->def_ht = _mesa_hash_table_create(ctx,
238 _mesa_hash_pointer, _mesa_key_pointer_equal);
239 ctx->var_ht = _mesa_hash_table_create(ctx,
240 _mesa_hash_pointer, _mesa_key_pointer_equal);
241 ctx->addr_ht = _mesa_hash_table_create(ctx,
242 _mesa_hash_pointer, _mesa_key_pointer_equal);
243
244 lowered_tokens = lower_tgsi(tokens, so);
245 if (!lowered_tokens)
246 lowered_tokens = tokens;
247 ctx->s = to_nir(lowered_tokens);
248
249 if (lowered_tokens != tokens)
250 free((void *)lowered_tokens);
251
252 so->first_immediate = ctx->s->num_uniforms;
253 /* for now, now driver params: */
254 so->first_driver_param = so->first_immediate;
255
256 return ctx;
257 }
258
259 static void
260 compile_error(struct ir3_compile *ctx, const char *format, ...)
261 {
262 va_list ap;
263 va_start(ap, format);
264 _debug_vprintf(format, ap);
265 va_end(ap);
266 nir_print_shader(ctx->s, stdout);
267 ctx->error = true;
268 debug_assert(0);
269 }
270
271 #define compile_assert(ctx, cond) do { \
272 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
273 } while (0)
274
275 static void
276 compile_free(struct ir3_compile *ctx)
277 {
278 ralloc_free(ctx);
279 }
280
281
282 struct ir3_array {
283 unsigned length, aid;
284 struct ir3_instruction *arr[];
285 };
286
287 static void
288 declare_var(struct ir3_compile *ctx, nir_variable *var)
289 {
290 unsigned length = glsl_get_length(var->type) * 4; /* always vec4, at least with ttn */
291 struct ir3_array *arr = ralloc_size(ctx, sizeof(*arr) +
292 (length * sizeof(arr->arr[0])));
293 arr->length = length;
294 arr->aid = ++ctx->num_arrays;
295 _mesa_hash_table_insert(ctx->var_ht, var, arr);
296 }
297
298 static struct ir3_array *
299 get_var(struct ir3_compile *ctx, nir_variable *var)
300 {
301 struct hash_entry *entry = _mesa_hash_table_search(ctx->var_ht, var);
302 return entry->data;
303 }
304
305 /* allocate a n element value array (to be populated by caller) and
306 * insert in def_ht
307 */
308 static struct ir3_instruction **
309 __get_dst(struct ir3_compile *ctx, void *key, unsigned n)
310 {
311 struct ir3_instruction **value =
312 ralloc_array(ctx->def_ht, struct ir3_instruction *, n);
313 _mesa_hash_table_insert(ctx->def_ht, key, value);
314 return value;
315 }
316
317 static struct ir3_instruction **
318 get_dst(struct ir3_compile *ctx, nir_dest *dst, unsigned n)
319 {
320 if (dst->is_ssa) {
321 return __get_dst(ctx, &dst->ssa, n);
322 } else {
323 return __get_dst(ctx, dst->reg.reg, n);
324 }
325 }
326
327 static struct ir3_instruction **
328 get_dst_ssa(struct ir3_compile *ctx, nir_ssa_def *dst, unsigned n)
329 {
330 return __get_dst(ctx, dst, n);
331 }
332
333 static struct ir3_instruction **
334 get_src(struct ir3_compile *ctx, nir_src *src)
335 {
336 struct hash_entry *entry;
337 if (src->is_ssa) {
338 entry = _mesa_hash_table_search(ctx->def_ht, src->ssa);
339 } else {
340 entry = _mesa_hash_table_search(ctx->def_ht, src->reg.reg);
341 }
342 compile_assert(ctx, entry);
343 return entry->data;
344 }
345
346 static struct ir3_instruction *
347 create_immed(struct ir3_block *block, uint32_t val)
348 {
349 struct ir3_instruction *mov;
350
351 mov = ir3_instr_create(block, 1, 0);
352 mov->cat1.src_type = TYPE_U32;
353 mov->cat1.dst_type = TYPE_U32;
354 ir3_reg_create(mov, 0, 0);
355 ir3_reg_create(mov, 0, IR3_REG_IMMED)->uim_val = val;
356
357 return mov;
358 }
359
360 static struct ir3_instruction *
361 create_addr(struct ir3_block *block, struct ir3_instruction *src)
362 {
363 struct ir3_instruction *instr, *immed;
364
365 /* TODO in at least some cases, the backend could probably be
366 * made clever enough to propagate IR3_REG_HALF..
367 */
368 instr = ir3_COV(block, src, TYPE_U32, TYPE_S16);
369 instr->regs[0]->flags |= IR3_REG_HALF;
370
371 immed = create_immed(block, 2);
372 immed->regs[0]->flags |= IR3_REG_HALF;
373
374 instr = ir3_SHL_B(block, instr, 0, immed, 0);
375 instr->regs[0]->flags |= IR3_REG_HALF;
376 instr->regs[1]->flags |= IR3_REG_HALF;
377
378 instr = ir3_MOV(block, instr, TYPE_S16);
379 instr->regs[0]->flags |= IR3_REG_ADDR | IR3_REG_HALF;
380 instr->regs[1]->flags |= IR3_REG_HALF;
381
382 return instr;
383 }
384
385 /* caches addr values to avoid generating multiple cov/shl/mova
386 * sequences for each use of a given NIR level src as address
387 */
388 static struct ir3_instruction *
389 get_addr(struct ir3_compile *ctx, struct ir3_instruction *src)
390 {
391 struct ir3_instruction *addr;
392 struct hash_entry *entry;
393 entry = _mesa_hash_table_search(ctx->addr_ht, src);
394 if (entry)
395 return entry->data;
396
397 /* TODO do we need to cache per block? */
398 addr = create_addr(ctx->block, src);
399 _mesa_hash_table_insert(ctx->addr_ht, src, addr);
400
401 return addr;
402 }
403
404 static struct ir3_instruction *
405 create_uniform(struct ir3_compile *ctx, unsigned n)
406 {
407 struct ir3_instruction *mov;
408
409 mov = ir3_instr_create(ctx->block, 1, 0);
410 /* TODO get types right? */
411 mov->cat1.src_type = TYPE_F32;
412 mov->cat1.dst_type = TYPE_F32;
413 ir3_reg_create(mov, 0, 0);
414 ir3_reg_create(mov, n, IR3_REG_CONST);
415
416 return mov;
417 }
418
419 static struct ir3_instruction *
420 create_uniform_indirect(struct ir3_compile *ctx, unsigned n,
421 struct ir3_instruction *address)
422 {
423 struct ir3_instruction *mov;
424
425 mov = ir3_instr_create(ctx->block, 1, 0);
426 mov->cat1.src_type = TYPE_U32;
427 mov->cat1.dst_type = TYPE_U32;
428 ir3_reg_create(mov, 0, 0);
429 ir3_reg_create(mov, n, IR3_REG_CONST | IR3_REG_RELATIV);
430 mov->address = address;
431
432 array_insert(ctx->ir->indirects, mov);
433
434 return mov;
435 }
436
437 static struct ir3_instruction *
438 create_collect(struct ir3_block *block, struct ir3_instruction **arr,
439 unsigned arrsz)
440 {
441 struct ir3_instruction *collect;
442
443 if (arrsz == 0)
444 return NULL;
445
446 collect = ir3_instr_create2(block, -1, OPC_META_FI, 1 + arrsz);
447 ir3_reg_create(collect, 0, 0);
448 for (unsigned i = 0; i < arrsz; i++)
449 ir3_reg_create(collect, 0, IR3_REG_SSA)->instr = arr[i];
450
451 return collect;
452 }
453
454 static struct ir3_instruction *
455 create_indirect_load(struct ir3_compile *ctx, unsigned arrsz, unsigned n,
456 struct ir3_instruction *address, struct ir3_instruction *collect)
457 {
458 struct ir3_block *block = ctx->block;
459 struct ir3_instruction *mov;
460 struct ir3_register *src;
461
462 mov = ir3_instr_create(block, 1, 0);
463 mov->cat1.src_type = TYPE_U32;
464 mov->cat1.dst_type = TYPE_U32;
465 ir3_reg_create(mov, 0, 0);
466 src = ir3_reg_create(mov, 0, IR3_REG_SSA | IR3_REG_RELATIV);
467 src->instr = collect;
468 src->size = arrsz;
469 src->offset = n;
470 mov->address = address;
471
472 array_insert(ctx->ir->indirects, mov);
473
474 return mov;
475 }
476
477 static struct ir3_instruction *
478 create_indirect_store(struct ir3_compile *ctx, unsigned arrsz, unsigned n,
479 struct ir3_instruction *src, struct ir3_instruction *address,
480 struct ir3_instruction *collect)
481 {
482 struct ir3_block *block = ctx->block;
483 struct ir3_instruction *mov;
484 struct ir3_register *dst;
485
486 mov = ir3_instr_create(block, 1, 0);
487 mov->cat1.src_type = TYPE_U32;
488 mov->cat1.dst_type = TYPE_U32;
489 dst = ir3_reg_create(mov, 0, IR3_REG_RELATIV);
490 dst->size = arrsz;
491 dst->offset = n;
492 ir3_reg_create(mov, 0, IR3_REG_SSA)->instr = src;
493 mov->address = address;
494 mov->fanin = collect;
495
496 array_insert(ctx->ir->indirects, mov);
497
498 return mov;
499 }
500
501 static struct ir3_instruction *
502 create_input(struct ir3_block *block, struct ir3_instruction *instr,
503 unsigned n)
504 {
505 struct ir3_instruction *in;
506
507 in = ir3_instr_create(block, -1, OPC_META_INPUT);
508 in->inout.block = block;
509 ir3_reg_create(in, n, 0);
510 if (instr)
511 ir3_reg_create(in, 0, IR3_REG_SSA)->instr = instr;
512
513 return in;
514 }
515
516 static struct ir3_instruction *
517 create_frag_input(struct ir3_compile *ctx, unsigned n, bool use_ldlv)
518 {
519 struct ir3_block *block = ctx->block;
520 struct ir3_instruction *instr;
521 struct ir3_instruction *inloc = create_immed(block, n);
522
523 if (use_ldlv) {
524 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
525 instr->cat6.type = TYPE_U32;
526 instr->cat6.iim_val = 1;
527 } else {
528 instr = ir3_BARY_F(block, inloc, 0, ctx->frag_pos, 0);
529 instr->regs[2]->wrmask = 0x3;
530 }
531
532 return instr;
533 }
534
535 static struct ir3_instruction *
536 create_frag_coord(struct ir3_compile *ctx, unsigned comp)
537 {
538 struct ir3_block *block = ctx->block;
539 struct ir3_instruction *instr;
540
541 compile_assert(ctx, !ctx->frag_coord[comp]);
542
543 ctx->frag_coord[comp] = create_input(ctx->block, NULL, 0);
544
545 switch (comp) {
546 case 0: /* .x */
547 case 1: /* .y */
548 /* for frag_coord, we get unsigned values.. we need
549 * to subtract (integer) 8 and divide by 16 (right-
550 * shift by 4) then convert to float:
551 *
552 * add.s tmp, src, -8
553 * shr.b tmp, tmp, 4
554 * mov.u32f32 dst, tmp
555 *
556 */
557 instr = ir3_ADD_S(block, ctx->frag_coord[comp], 0,
558 create_immed(block, -8), 0);
559 instr = ir3_SHR_B(block, instr, 0,
560 create_immed(block, 4), 0);
561 instr = ir3_COV(block, instr, TYPE_U32, TYPE_F32);
562
563 return instr;
564 case 2: /* .z */
565 case 3: /* .w */
566 default:
567 /* seems that we can use these as-is: */
568 return ctx->frag_coord[comp];
569 }
570 }
571
572 static struct ir3_instruction *
573 create_frag_face(struct ir3_compile *ctx, unsigned comp)
574 {
575 struct ir3_block *block = ctx->block;
576 struct ir3_instruction *instr;
577
578 switch (comp) {
579 case 0: /* .x */
580 compile_assert(ctx, !ctx->frag_face);
581
582 ctx->frag_face = create_input(block, NULL, 0);
583
584 /* for faceness, we always get -1 or 0 (int).. but TGSI expects
585 * positive vs negative float.. and piglit further seems to
586 * expect -1.0 or 1.0:
587 *
588 * mul.s tmp, hr0.x, 2
589 * add.s tmp, tmp, 1
590 * mov.s32f32, dst, tmp
591 *
592 */
593 instr = ir3_MUL_S(block, ctx->frag_face, 0,
594 create_immed(block, 2), 0);
595 instr = ir3_ADD_S(block, instr, 0,
596 create_immed(block, 1), 0);
597 instr = ir3_COV(block, instr, TYPE_S32, TYPE_F32);
598
599 return instr;
600 case 1: /* .y */
601 case 2: /* .z */
602 return create_immed(block, fui(0.0));
603 default:
604 case 3: /* .w */
605 return create_immed(block, fui(1.0));
606 }
607 }
608
609 /*
610 * Adreno uses uint rather than having dedicated bool type,
611 * which (potentially) requires some conversion, in particular
612 * when using output of an bool instr to int input, or visa
613 * versa.
614 *
615 * | Adreno | NIR |
616 * -------+---------+-------+-
617 * true | 1 | ~0 |
618 * false | 0 | 0 |
619 *
620 * To convert from an adreno bool (uint) to nir, use:
621 *
622 * absneg.s dst, (neg)src
623 *
624 * To convert back in the other direction:
625 *
626 * absneg.s dst, (abs)arc
627 *
628 * The CP step can clean up the absneg.s that cancel each other
629 * out, and with a slight bit of extra cleverness (to recognize
630 * the instructions which produce either a 0 or 1) can eliminate
631 * the absneg.s's completely when an instruction that wants
632 * 0/1 consumes the result. For example, when a nir 'bcsel'
633 * consumes the result of 'feq'. So we should be able to get by
634 * without a boolean resolve step, and without incuring any
635 * extra penalty in instruction count.
636 */
637
638 /* NIR bool -> native (adreno): */
639 static struct ir3_instruction *
640 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
641 {
642 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
643 }
644
645 /* native (adreno) -> NIR bool: */
646 static struct ir3_instruction *
647 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
648 {
649 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
650 }
651
652 /*
653 * alu/sfu instructions:
654 */
655
656 static void
657 emit_alu(struct ir3_compile *ctx, nir_alu_instr *alu)
658 {
659 const nir_op_info *info = &nir_op_infos[alu->op];
660 struct ir3_instruction **dst, *src[info->num_inputs];
661 struct ir3_block *b = ctx->block;
662
663 dst = get_dst(ctx, &alu->dest.dest, MAX2(info->output_size, 1));
664
665 /* Vectors are special in that they have non-scalarized writemasks,
666 * and just take the first swizzle channel for each argument in
667 * order into each writemask channel.
668 */
669 if ((alu->op == nir_op_vec2) ||
670 (alu->op == nir_op_vec3) ||
671 (alu->op == nir_op_vec4)) {
672
673 for (int i = 0; i < info->num_inputs; i++) {
674 nir_alu_src *asrc = &alu->src[i];
675
676 compile_assert(ctx, !asrc->abs);
677 compile_assert(ctx, !asrc->negate);
678
679 src[i] = get_src(ctx, &asrc->src)[asrc->swizzle[0]];
680 if (!src[i])
681 src[i] = create_immed(ctx->block, 0);
682 dst[i] = ir3_MOV(b, src[i], TYPE_U32);
683 }
684
685 return;
686 }
687
688 /* General case: We can just grab the one used channel per src. */
689 for (int i = 0; i < info->num_inputs; i++) {
690 unsigned chan = ffs(alu->dest.write_mask) - 1;
691 nir_alu_src *asrc = &alu->src[i];
692
693 compile_assert(ctx, !asrc->abs);
694 compile_assert(ctx, !asrc->negate);
695
696 src[i] = get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
697 }
698
699 switch (alu->op) {
700 case nir_op_f2i:
701 dst[0] = ir3_COV(b, src[0], TYPE_F32, TYPE_S32);
702 break;
703 case nir_op_f2u:
704 dst[0] = ir3_COV(b, src[0], TYPE_F32, TYPE_U32);
705 break;
706 case nir_op_i2f:
707 dst[0] = ir3_COV(b, src[0], TYPE_S32, TYPE_F32);
708 break;
709 case nir_op_u2f:
710 dst[0] = ir3_COV(b, src[0], TYPE_U32, TYPE_F32);
711 break;
712 case nir_op_imov:
713 dst[0] = ir3_MOV(b, src[0], TYPE_S32);
714 break;
715 case nir_op_fmov:
716 dst[0] = ir3_MOV(b, src[0], TYPE_F32);
717 break;
718 case nir_op_f2b:
719 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
720 dst[0]->cat2.condition = IR3_COND_NE;
721 dst[0] = ir3_n2b(b, dst[0]);
722 break;
723 case nir_op_b2f:
724 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
725 break;
726 case nir_op_b2i:
727 dst[0] = ir3_b2n(b, src[0]);
728 break;
729 case nir_op_i2b:
730 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
731 dst[0]->cat2.condition = IR3_COND_NE;
732 dst[0] = ir3_n2b(b, dst[0]);
733 break;
734
735 case nir_op_fneg:
736 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
737 break;
738 case nir_op_fabs:
739 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
740 break;
741 case nir_op_fmax:
742 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
743 break;
744 case nir_op_fmin:
745 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
746 break;
747 case nir_op_fmul:
748 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
749 break;
750 case nir_op_fadd:
751 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
752 break;
753 case nir_op_fsub:
754 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
755 break;
756 case nir_op_ffma:
757 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
758 break;
759 case nir_op_fddx:
760 dst[0] = ir3_DSX(b, src[0], 0);
761 dst[0]->cat5.type = TYPE_F32;
762 break;
763 case nir_op_fddy:
764 dst[0] = ir3_DSY(b, src[0], 0);
765 dst[0]->cat5.type = TYPE_F32;
766 break;
767 break;
768 case nir_op_flt:
769 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
770 dst[0]->cat2.condition = IR3_COND_LT;
771 dst[0] = ir3_n2b(b, dst[0]);
772 break;
773 case nir_op_fge:
774 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
775 dst[0]->cat2.condition = IR3_COND_GE;
776 dst[0] = ir3_n2b(b, dst[0]);
777 break;
778 case nir_op_feq:
779 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
780 dst[0]->cat2.condition = IR3_COND_EQ;
781 dst[0] = ir3_n2b(b, dst[0]);
782 break;
783 case nir_op_fne:
784 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
785 dst[0]->cat2.condition = IR3_COND_NE;
786 dst[0] = ir3_n2b(b, dst[0]);
787 break;
788 case nir_op_fceil:
789 dst[0] = ir3_CEIL_F(b, src[0], 0);
790 break;
791 case nir_op_ffloor:
792 dst[0] = ir3_FLOOR_F(b, src[0], 0);
793 break;
794 case nir_op_ftrunc:
795 dst[0] = ir3_TRUNC_F(b, src[0], 0);
796 break;
797 case nir_op_fround_even:
798 dst[0] = ir3_RNDNE_F(b, src[0], 0);
799 break;
800 case nir_op_fsign:
801 dst[0] = ir3_SIGN_F(b, src[0], 0);
802 break;
803
804 case nir_op_fsin:
805 dst[0] = ir3_SIN(b, src[0], 0);
806 break;
807 case nir_op_fcos:
808 dst[0] = ir3_COS(b, src[0], 0);
809 break;
810 case nir_op_frsq:
811 dst[0] = ir3_RSQ(b, src[0], 0);
812 break;
813 case nir_op_frcp:
814 dst[0] = ir3_RCP(b, src[0], 0);
815 break;
816 case nir_op_flog2:
817 dst[0] = ir3_LOG2(b, src[0], 0);
818 break;
819 case nir_op_fexp2:
820 dst[0] = ir3_EXP2(b, src[0], 0);
821 break;
822 case nir_op_fsqrt:
823 dst[0] = ir3_SQRT(b, src[0], 0);
824 break;
825
826 case nir_op_iabs:
827 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
828 break;
829 case nir_op_iadd:
830 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
831 break;
832 case nir_op_iand:
833 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
834 break;
835 case nir_op_imax:
836 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
837 break;
838 case nir_op_imin:
839 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
840 break;
841 case nir_op_imul:
842 /*
843 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
844 * mull.u tmp0, a, b ; mul low, i.e. al * bl
845 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
846 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
847 */
848 dst[0] = ir3_MADSH_M16(b, src[1], 0, src[0], 0,
849 ir3_MADSH_M16(b, src[0], 0, src[1], 0,
850 ir3_MULL_U(b, src[0], 0, src[1], 0), 0), 0);
851 break;
852 case nir_op_ineg:
853 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
854 break;
855 case nir_op_inot:
856 dst[0] = ir3_NOT_B(b, src[0], 0);
857 break;
858 case nir_op_ior:
859 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
860 break;
861 case nir_op_ishl:
862 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
863 break;
864 case nir_op_ishr:
865 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
866 break;
867 case nir_op_isign: {
868 /* maybe this would be sane to lower in nir.. */
869 struct ir3_instruction *neg, *pos;
870
871 neg = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
872 neg->cat2.condition = IR3_COND_LT;
873
874 pos = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
875 pos->cat2.condition = IR3_COND_GT;
876
877 dst[0] = ir3_SUB_U(b, pos, 0, neg, 0);
878
879 break;
880 }
881 case nir_op_isub:
882 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
883 break;
884 case nir_op_ixor:
885 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
886 break;
887 case nir_op_ushr:
888 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
889 break;
890 case nir_op_ilt:
891 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
892 dst[0]->cat2.condition = IR3_COND_LT;
893 dst[0] = ir3_n2b(b, dst[0]);
894 break;
895 case nir_op_ige:
896 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
897 dst[0]->cat2.condition = IR3_COND_GE;
898 dst[0] = ir3_n2b(b, dst[0]);
899 break;
900 case nir_op_ieq:
901 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
902 dst[0]->cat2.condition = IR3_COND_EQ;
903 dst[0] = ir3_n2b(b, dst[0]);
904 break;
905 case nir_op_ine:
906 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
907 dst[0]->cat2.condition = IR3_COND_NE;
908 dst[0] = ir3_n2b(b, dst[0]);
909 break;
910 case nir_op_ult:
911 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
912 dst[0]->cat2.condition = IR3_COND_LT;
913 dst[0] = ir3_n2b(b, dst[0]);
914 break;
915 case nir_op_uge:
916 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
917 dst[0]->cat2.condition = IR3_COND_GE;
918 dst[0] = ir3_n2b(b, dst[0]);
919 break;
920
921 case nir_op_bcsel:
922 dst[0] = ir3_SEL_B32(b, src[1], 0, ir3_b2n(b, src[0]), 0, src[2], 0);
923 break;
924
925 default:
926 compile_error(ctx, "Unhandled ALU op: %s\n",
927 nir_op_infos[alu->op].name);
928 break;
929 }
930 }
931
932 /* handles array reads: */
933 static void
934 emit_intrinisic_load_var(struct ir3_compile *ctx, nir_intrinsic_instr *intr,
935 struct ir3_instruction **dst)
936 {
937 nir_deref_var *dvar = intr->variables[0];
938 nir_deref_array *darr = nir_deref_as_array(dvar->deref.child);
939 struct ir3_array *arr = get_var(ctx, dvar->var);
940
941 compile_assert(ctx, dvar->deref.child &&
942 (dvar->deref.child->deref_type == nir_deref_type_array));
943
944 switch (darr->deref_array_type) {
945 case nir_deref_array_type_direct:
946 /* direct access does not require anything special: */
947 for (int i = 0; i < intr->num_components; i++) {
948 unsigned n = darr->base_offset * 4 + i;
949 compile_assert(ctx, n < arr->length);
950 dst[i] = arr->arr[n];
951 }
952 break;
953 case nir_deref_array_type_indirect: {
954 /* for indirect, we need to collect all the array elements: */
955 struct ir3_instruction *collect =
956 create_collect(ctx->block, arr->arr, arr->length);
957 struct ir3_instruction *addr =
958 get_addr(ctx, get_src(ctx, &darr->indirect)[0]);
959 for (int i = 0; i < intr->num_components; i++) {
960 unsigned n = darr->base_offset * 4 + i;
961 compile_assert(ctx, n < arr->length);
962 dst[i] = create_indirect_load(ctx, arr->length, n, addr, collect);
963 }
964 break;
965 }
966 default:
967 compile_error(ctx, "Unhandled load deref type: %u\n",
968 darr->deref_array_type);
969 break;
970 }
971 }
972
973 /* handles array writes: */
974 static void
975 emit_intrinisic_store_var(struct ir3_compile *ctx, nir_intrinsic_instr *intr)
976 {
977 nir_deref_var *dvar = intr->variables[0];
978 nir_deref_array *darr = nir_deref_as_array(dvar->deref.child);
979 struct ir3_array *arr = get_var(ctx, dvar->var);
980 struct ir3_instruction **src;
981
982 compile_assert(ctx, dvar->deref.child &&
983 (dvar->deref.child->deref_type == nir_deref_type_array));
984
985 src = get_src(ctx, &intr->src[0]);
986
987 switch (darr->deref_array_type) {
988 case nir_deref_array_type_direct:
989 /* direct access does not require anything special: */
990 for (int i = 0; i < intr->num_components; i++) {
991 unsigned n = darr->base_offset * 4 + i;
992 compile_assert(ctx, n < arr->length);
993 arr->arr[n] = src[i];
994 }
995 break;
996 case nir_deref_array_type_indirect: {
997 /* for indirect, create indirect-store and fan that out: */
998 struct ir3_instruction *collect =
999 create_collect(ctx->block, arr->arr, arr->length);
1000 struct ir3_instruction *addr =
1001 get_addr(ctx, get_src(ctx, &darr->indirect)[0]);
1002 for (int i = 0; i < intr->num_components; i++) {
1003 struct ir3_instruction *store;
1004 unsigned n = darr->base_offset * 4 + i;
1005 compile_assert(ctx, n < arr->length);
1006
1007 store = create_indirect_store(ctx, arr->length,
1008 n, src[i], addr, collect);
1009
1010 store->fanin->fi.aid = arr->aid;
1011
1012 /* TODO: probably split this out to be used for
1013 * store_output_indirect? or move this into
1014 * create_indirect_store()?
1015 */
1016 for (int j = i; j < arr->length; j += 4) {
1017 struct ir3_instruction *split;
1018
1019 split = ir3_instr_create(ctx->block, -1, OPC_META_FO);
1020 split->fo.off = j;
1021 ir3_reg_create(split, 0, 0);
1022 ir3_reg_create(split, 0, IR3_REG_SSA)->instr = store;
1023
1024 arr->arr[j] = split;
1025 }
1026 }
1027 break;
1028 }
1029 default:
1030 compile_error(ctx, "Unhandled store deref type: %u\n",
1031 darr->deref_array_type);
1032 break;
1033 }
1034 }
1035
1036 static void
1037 emit_intrinisic(struct ir3_compile *ctx, nir_intrinsic_instr *intr)
1038 {
1039 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1040 struct ir3_instruction **dst, **src;
1041 struct ir3_block *b = ctx->block;
1042 unsigned idx = intr->const_index[0];
1043
1044 if (info->has_dest) {
1045 dst = get_dst(ctx, &intr->dest, intr->num_components);
1046 }
1047
1048 switch (intr->intrinsic) {
1049 case nir_intrinsic_load_uniform:
1050 compile_assert(ctx, intr->const_index[1] == 1);
1051 for (int i = 0; i < intr->num_components; i++) {
1052 unsigned n = idx * 4 + i;
1053 dst[i] = create_uniform(ctx, n);
1054 }
1055 break;
1056 case nir_intrinsic_load_uniform_indirect:
1057 compile_assert(ctx, intr->const_index[1] == 1);
1058 src = get_src(ctx, &intr->src[0]);
1059 for (int i = 0; i < intr->num_components; i++) {
1060 unsigned n = idx * 4 + i;
1061 dst[i] = create_uniform_indirect(ctx, n,
1062 get_addr(ctx, src[0]));
1063 }
1064 break;
1065 case nir_intrinsic_load_input:
1066 compile_assert(ctx, intr->const_index[1] == 1);
1067 for (int i = 0; i < intr->num_components; i++) {
1068 unsigned n = idx * 4 + i;
1069 dst[i] = b->inputs[n];
1070 }
1071 break;
1072 case nir_intrinsic_load_input_indirect:
1073 compile_assert(ctx, intr->const_index[1] == 1);
1074 src = get_src(ctx, &intr->src[0]);
1075 struct ir3_instruction *collect =
1076 create_collect(b, b->inputs, b->ninputs);
1077 struct ir3_instruction *addr = get_addr(ctx, src[0]);
1078 for (int i = 0; i < intr->num_components; i++) {
1079 unsigned n = idx * 4 + i;
1080 dst[i] = create_indirect_load(ctx, b->ninputs, n, addr, collect);
1081 }
1082 break;
1083 case nir_intrinsic_load_var:
1084 emit_intrinisic_load_var(ctx, intr, dst);
1085 break;
1086 case nir_intrinsic_store_var:
1087 emit_intrinisic_store_var(ctx, intr);
1088 break;
1089 case nir_intrinsic_store_output:
1090 compile_assert(ctx, intr->const_index[1] == 1);
1091 src = get_src(ctx, &intr->src[0]);
1092 for (int i = 0; i < intr->num_components; i++) {
1093 unsigned n = idx * 4 + i;
1094 b->outputs[n] = src[i];
1095 }
1096 break;
1097 case nir_intrinsic_discard_if:
1098 case nir_intrinsic_discard: {
1099 struct ir3_instruction *cond, *kill;
1100
1101 if (intr->intrinsic == nir_intrinsic_discard_if) {
1102 /* conditional discard: */
1103 src = get_src(ctx, &intr->src[0]);
1104 cond = ir3_b2n(b, src[0]);
1105 } else {
1106 /* unconditional discard: */
1107 cond = create_immed(b, 1);
1108 }
1109
1110 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1111 cond->cat2.condition = IR3_COND_NE;
1112
1113 /* condition always goes in predicate register: */
1114 cond->regs[0]->num = regid(REG_P0, 0);
1115
1116 kill = ir3_KILL(b, cond, 0);
1117
1118 ctx->kill[ctx->kill_count++] = kill;
1119 ctx->so->has_kill = true;
1120
1121 break;
1122 }
1123 default:
1124 compile_error(ctx, "Unhandled intrinsic type: %s\n",
1125 nir_intrinsic_infos[intr->intrinsic].name);
1126 break;
1127 }
1128 }
1129
1130 static void
1131 emit_load_const(struct ir3_compile *ctx, nir_load_const_instr *instr)
1132 {
1133 struct ir3_instruction **dst = get_dst_ssa(ctx, &instr->def,
1134 instr->def.num_components);
1135 for (int i = 0; i < instr->def.num_components; i++)
1136 dst[i] = create_immed(ctx->block, instr->value.u[i]);
1137 }
1138
1139 static void
1140 emit_undef(struct ir3_compile *ctx, nir_ssa_undef_instr *undef)
1141 {
1142 struct ir3_instruction **dst = get_dst_ssa(ctx, &undef->def,
1143 undef->def.num_components);
1144 /* backend doesn't want undefined instructions, so just plug
1145 * in 0.0..
1146 */
1147 for (int i = 0; i < undef->def.num_components; i++)
1148 dst[i] = create_immed(ctx->block, fui(0.0));
1149 }
1150
1151 /*
1152 * texture fetch/sample instructions:
1153 */
1154
1155 static void
1156 emit_tex(struct ir3_compile *ctx, nir_tex_instr *tex)
1157 {
1158 struct ir3_block *b = ctx->block;
1159 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1160 struct ir3_instruction **coord, *lod, *compare, *proj, **off, **ddx, **ddy;
1161 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1162 unsigned i, coords, flags = 0;
1163 unsigned nsrc0 = 0, nsrc1 = 0;
1164 type_t type;
1165 opc_t opc;
1166
1167 /* TODO: might just be one component for gathers? */
1168 dst = get_dst(ctx, &tex->dest, 4);
1169
1170 for (unsigned i = 0; i < tex->num_srcs; i++) {
1171 switch (tex->src[i].src_type) {
1172 case nir_tex_src_coord:
1173 coord = get_src(ctx, &tex->src[i].src);
1174 break;
1175 case nir_tex_src_bias:
1176 lod = get_src(ctx, &tex->src[i].src)[0];
1177 has_bias = true;
1178 break;
1179 case nir_tex_src_lod:
1180 lod = get_src(ctx, &tex->src[i].src)[0];
1181 has_lod = true;
1182 break;
1183 case nir_tex_src_comparitor: /* shadow comparator */
1184 compare = get_src(ctx, &tex->src[i].src)[0];
1185 break;
1186 case nir_tex_src_projector:
1187 proj = get_src(ctx, &tex->src[i].src)[0];
1188 has_proj = true;
1189 break;
1190 case nir_tex_src_offset:
1191 off = get_src(ctx, &tex->src[i].src);
1192 has_off = true;
1193 break;
1194 case nir_tex_src_ddx:
1195 ddx = get_src(ctx, &tex->src[i].src);
1196 break;
1197 case nir_tex_src_ddy:
1198 ddy = get_src(ctx, &tex->src[i].src);
1199 break;
1200 default:
1201 compile_error(ctx, "Unhandled NIR tex serc type: %d\n",
1202 tex->src[i].src_type);
1203 return;
1204 }
1205 }
1206
1207 /*
1208 * lay out the first argument in the proper order:
1209 * - actual coordinates first
1210 * - shadow reference
1211 * - array index
1212 * - projection w
1213 * - starting at offset 4, dpdx.xy, dpdy.xy
1214 *
1215 * bias/lod go into the second arg
1216 */
1217
1218 coords = tex->coord_components;
1219 if (tex->is_array) /* array idx goes after shadow ref */
1220 coords--;
1221
1222 /* insert tex coords: */
1223 for (i = 0; i < coords; i++)
1224 src0[nsrc0++] = coord[i];
1225
1226 if (coords == 1) {
1227 /* hw doesn't do 1d, so we treat it as 2d with
1228 * height of 1, and patch up the y coord.
1229 * TODO: y coord should be (int)0 in some cases..
1230 */
1231 src0[nsrc0++] = create_immed(b, fui(0.5));
1232 } else if (coords == 3) {
1233 flags |= IR3_INSTR_3D;
1234 }
1235
1236 if (tex->is_shadow) {
1237 src0[nsrc0++] = compare;
1238 flags |= IR3_INSTR_S;
1239 }
1240
1241 if (tex->is_array) {
1242 src0[nsrc0++] = coord[coords];
1243 flags |= IR3_INSTR_A;
1244 }
1245
1246 if (has_proj) {
1247 src0[nsrc0++] = proj;
1248 flags |= IR3_INSTR_P;
1249 }
1250
1251 /* pad to 4, then ddx/ddy: */
1252 if (tex->op == nir_texop_txd) {
1253 while (nsrc0 < 4)
1254 src0[nsrc0++] = create_immed(b, fui(0.0));
1255 for (i = 0; i < coords; i++)
1256 src0[nsrc0++] = ddx[i];
1257 if (coords < 2)
1258 src0[nsrc0++] = create_immed(b, fui(0.0));
1259 for (i = 0; i < coords; i++)
1260 src0[nsrc0++] = ddy[i];
1261 if (coords < 2)
1262 src0[nsrc0++] = create_immed(b, fui(0.0));
1263 }
1264
1265 /*
1266 * second argument (if applicable):
1267 * - offsets
1268 * - lod
1269 * - bias
1270 */
1271 if (has_off | has_lod | has_bias) {
1272 if (has_off) {
1273 for (i = 0; i < coords; i++)
1274 src1[nsrc1++] = off[i];
1275 if (coords < 2)
1276 src1[nsrc1++] = create_immed(b, fui(0.0));
1277 flags |= IR3_INSTR_O;
1278 }
1279
1280 if (has_lod | has_bias)
1281 src1[nsrc1++] = lod;
1282 }
1283
1284 switch (tex->op) {
1285 case nir_texop_tex: opc = OPC_SAM; break;
1286 case nir_texop_txb: opc = OPC_SAMB; break;
1287 case nir_texop_txl: opc = OPC_SAML; break;
1288 case nir_texop_txd: opc = OPC_SAMGQ; break;
1289 case nir_texop_txf: opc = OPC_ISAML; break;
1290 case nir_texop_txf_ms:
1291 case nir_texop_txs:
1292 case nir_texop_lod:
1293 case nir_texop_tg4:
1294 case nir_texop_query_levels:
1295 compile_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
1296 return;
1297 }
1298
1299 switch (tex->dest_type) {
1300 case nir_type_invalid:
1301 case nir_type_float:
1302 type = TYPE_F32;
1303 break;
1304 case nir_type_int:
1305 type = TYPE_S32;
1306 break;
1307 case nir_type_unsigned:
1308 case nir_type_bool:
1309 type = TYPE_U32;
1310 break;
1311 }
1312
1313 sam = ir3_SAM(b, opc, type, 0xf, flags,
1314 tex->sampler_index, tex->sampler_index,
1315 create_collect(b, src0, nsrc0),
1316 create_collect(b, src1, nsrc1));
1317
1318 // TODO maybe split this out into a helper, for other cases that
1319 // write multiple?
1320 struct ir3_instruction *prev = NULL;
1321 for (int i = 0; i < 4; i++) {
1322 struct ir3_instruction *split =
1323 ir3_instr_create(b, -1, OPC_META_FO);
1324 ir3_reg_create(split, 0, IR3_REG_SSA);
1325 ir3_reg_create(split, 0, IR3_REG_SSA)->instr = sam;
1326 split->fo.off = i;
1327
1328 if (prev) {
1329 split->cp.left = prev;
1330 split->cp.left_cnt++;
1331 prev->cp.right = split;
1332 prev->cp.right_cnt++;
1333 }
1334 prev = split;
1335
1336 dst[i] = split;
1337 }
1338 }
1339
1340
1341 static void
1342 emit_instr(struct ir3_compile *ctx, nir_instr *instr)
1343 {
1344 switch (instr->type) {
1345 case nir_instr_type_alu:
1346 emit_alu(ctx, nir_instr_as_alu(instr));
1347 break;
1348 case nir_instr_type_intrinsic:
1349 emit_intrinisic(ctx, nir_instr_as_intrinsic(instr));
1350 break;
1351 case nir_instr_type_load_const:
1352 emit_load_const(ctx, nir_instr_as_load_const(instr));
1353 break;
1354 case nir_instr_type_ssa_undef:
1355 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
1356 break;
1357 case nir_instr_type_tex:
1358 emit_tex(ctx, nir_instr_as_tex(instr));
1359 break;
1360
1361 case nir_instr_type_call:
1362 case nir_instr_type_jump:
1363 case nir_instr_type_phi:
1364 case nir_instr_type_parallel_copy:
1365 compile_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
1366 break;
1367 }
1368 }
1369
1370 static void
1371 emit_block(struct ir3_compile *ctx, nir_block *block)
1372 {
1373 nir_foreach_instr(block, instr) {
1374 emit_instr(ctx, instr);
1375 if (ctx->error)
1376 return;
1377 }
1378 }
1379
1380 static void
1381 emit_function(struct ir3_compile *ctx, nir_function_impl *impl)
1382 {
1383 foreach_list_typed(nir_cf_node, node, node, &impl->body) {
1384 switch (node->type) {
1385 case nir_cf_node_block:
1386 emit_block(ctx, nir_cf_node_as_block(node));
1387 break;
1388 case nir_cf_node_if:
1389 case nir_cf_node_loop:
1390 case nir_cf_node_function:
1391 compile_error(ctx, "TODO\n");
1392 break;
1393 }
1394 if (ctx->error)
1395 return;
1396 }
1397 }
1398
1399 static void
1400 setup_input(struct ir3_compile *ctx, nir_variable *in)
1401 {
1402 struct ir3_shader_variant *so = ctx->so;
1403 unsigned array_len = MAX2(glsl_get_length(in->type), 1);
1404 unsigned ncomp = glsl_get_components(in->type);
1405 /* XXX: map loc slots to semantics */
1406 unsigned semantic_name = in->data.location;
1407 unsigned semantic_index = in->data.index;
1408 unsigned n = in->data.driver_location;
1409
1410 DBG("; in: %u:%u, len=%ux%u, loc=%u\n",
1411 semantic_name, semantic_index, array_len,
1412 ncomp, n);
1413
1414 so->inputs[n].semantic =
1415 ir3_semantic_name(semantic_name, semantic_index);
1416 so->inputs[n].compmask = (1 << ncomp) - 1;
1417 so->inputs[n].inloc = ctx->next_inloc;
1418 so->inputs[n].interpolate = 0;
1419 so->inputs_count = MAX2(so->inputs_count, n + 1);
1420
1421 /* the fdN_program_emit() code expects tgsi consts here, so map
1422 * things back to tgsi for now:
1423 */
1424 switch (in->data.interpolation) {
1425 case INTERP_QUALIFIER_FLAT:
1426 so->inputs[n].interpolate = TGSI_INTERPOLATE_CONSTANT;
1427 break;
1428 case INTERP_QUALIFIER_NOPERSPECTIVE:
1429 so->inputs[n].interpolate = TGSI_INTERPOLATE_LINEAR;
1430 break;
1431 case INTERP_QUALIFIER_SMOOTH:
1432 so->inputs[n].interpolate = TGSI_INTERPOLATE_PERSPECTIVE;
1433 break;
1434 }
1435
1436 for (int i = 0; i < ncomp; i++) {
1437 struct ir3_instruction *instr = NULL;
1438 unsigned idx = (n * 4) + i;
1439
1440 if (ctx->so->type == SHADER_FRAGMENT) {
1441 if (semantic_name == TGSI_SEMANTIC_POSITION) {
1442 so->inputs[n].bary = false;
1443 so->frag_coord = true;
1444 instr = create_frag_coord(ctx, i);
1445 } else if (semantic_name == TGSI_SEMANTIC_FACE) {
1446 so->inputs[n].bary = false;
1447 so->frag_face = true;
1448 instr = create_frag_face(ctx, i);
1449 } else {
1450 bool use_ldlv = false;
1451
1452 /* with NIR, we need to infer TGSI_INTERPOLATE_COLOR
1453 * from the semantic name:
1454 */
1455 if (semantic_name == TGSI_SEMANTIC_COLOR)
1456 so->inputs[n].interpolate = TGSI_INTERPOLATE_COLOR;
1457
1458 if (ctx->flat_bypass) {
1459 /* with NIR, we need to infer TGSI_INTERPOLATE_COLOR
1460 * from the semantic name:
1461 */
1462 switch (so->inputs[n].interpolate) {
1463 case TGSI_INTERPOLATE_COLOR:
1464 if (!ctx->so->key.rasterflat)
1465 break;
1466 /* fallthrough */
1467 case TGSI_INTERPOLATE_CONSTANT:
1468 use_ldlv = true;
1469 break;
1470 }
1471 }
1472
1473 so->inputs[n].bary = true;
1474
1475 instr = create_frag_input(ctx, idx, use_ldlv);
1476 }
1477 } else {
1478 instr = create_input(ctx->block, NULL, idx);
1479 }
1480
1481 ctx->block->inputs[idx] = instr;
1482 }
1483
1484 if (so->inputs[n].bary || (ctx->so->type == SHADER_VERTEX)) {
1485 ctx->next_inloc += ncomp;
1486 so->total_in += ncomp;
1487 }
1488 }
1489
1490 static void
1491 setup_output(struct ir3_compile *ctx, nir_variable *out)
1492 {
1493 struct ir3_shader_variant *so = ctx->so;
1494 unsigned array_len = MAX2(glsl_get_length(out->type), 1);
1495 unsigned ncomp = glsl_get_components(out->type);
1496 /* XXX: map loc slots to semantics */
1497 unsigned semantic_name = out->data.location;
1498 unsigned semantic_index = out->data.index;
1499 unsigned n = out->data.driver_location;
1500 unsigned comp = 0;
1501
1502 DBG("; out: %u:%u, len=%ux%u, loc=%u\n",
1503 semantic_name, semantic_index, array_len,
1504 ncomp, n);
1505
1506 if (ctx->so->type == SHADER_VERTEX) {
1507 switch (semantic_name) {
1508 case TGSI_SEMANTIC_POSITION:
1509 so->writes_pos = true;
1510 break;
1511 case TGSI_SEMANTIC_PSIZE:
1512 so->writes_psize = true;
1513 break;
1514 case TGSI_SEMANTIC_COLOR:
1515 case TGSI_SEMANTIC_BCOLOR:
1516 case TGSI_SEMANTIC_GENERIC:
1517 case TGSI_SEMANTIC_FOG:
1518 case TGSI_SEMANTIC_TEXCOORD:
1519 break;
1520 default:
1521 compile_error(ctx, "unknown VS semantic name: %s\n",
1522 tgsi_semantic_names[semantic_name]);
1523 }
1524 } else {
1525 switch (semantic_name) {
1526 case TGSI_SEMANTIC_POSITION:
1527 comp = 2; /* tgsi will write to .z component */
1528 so->writes_pos = true;
1529 break;
1530 case TGSI_SEMANTIC_COLOR:
1531 break;
1532 default:
1533 compile_error(ctx, "unknown FS semantic name: %s\n",
1534 tgsi_semantic_names[semantic_name]);
1535 }
1536 }
1537
1538 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
1539
1540 so->outputs[n].semantic =
1541 ir3_semantic_name(semantic_name, semantic_index);
1542 so->outputs[n].regid = regid(n, comp);
1543 so->outputs_count = MAX2(so->outputs_count, n + 1);
1544
1545 for (int i = 0; i < ncomp; i++) {
1546 unsigned idx = (n * 4) + i;
1547
1548 ctx->block->outputs[idx] = create_immed(ctx->block, fui(0.0));
1549 }
1550 }
1551
1552 static void
1553 emit_instructions(struct ir3_compile *ctx)
1554 {
1555 unsigned ninputs = exec_list_length(&ctx->s->inputs) * 4;
1556 unsigned noutputs = exec_list_length(&ctx->s->outputs) * 4;
1557
1558 /* we need to allocate big enough outputs array so that
1559 * we can stuff the kill's at the end:
1560 */
1561 if (ctx->so->type == SHADER_FRAGMENT)
1562 noutputs += ARRAY_SIZE(ctx->kill);
1563
1564 ctx->block = ir3_block_create(ctx->ir, 0, ninputs, noutputs);
1565
1566 if (ctx->so->type == SHADER_FRAGMENT)
1567 ctx->block->noutputs -= ARRAY_SIZE(ctx->kill);
1568
1569
1570 /* for fragment shader, we have a single input register (usually
1571 * r0.xy) which is used as the base for bary.f varying fetch instrs:
1572 */
1573 if (ctx->so->type == SHADER_FRAGMENT) {
1574 // TODO maybe a helper for fi since we need it a few places..
1575 struct ir3_instruction *instr;
1576 instr = ir3_instr_create(ctx->block, -1, OPC_META_FI);
1577 ir3_reg_create(instr, 0, 0);
1578 ir3_reg_create(instr, 0, IR3_REG_SSA); /* r0.x */
1579 ir3_reg_create(instr, 0, IR3_REG_SSA); /* r0.y */
1580 ctx->frag_pos = instr;
1581 }
1582
1583 /* Setup inputs: */
1584 foreach_list_typed(nir_variable, var, node, &ctx->s->inputs) {
1585 setup_input(ctx, var);
1586 }
1587
1588 /* Setup outputs: */
1589 foreach_list_typed(nir_variable, var, node, &ctx->s->outputs) {
1590 setup_output(ctx, var);
1591 }
1592
1593 /* Setup variables (which should only be arrays): */
1594 foreach_list_typed(nir_variable, var, node, &ctx->s->globals) {
1595 declare_var(ctx, var);
1596 }
1597
1598 /* Find the main function and emit the body: */
1599 nir_foreach_overload(ctx->s, overload) {
1600 compile_assert(ctx, strcmp(overload->function->name, "main") == 0);
1601 compile_assert(ctx, overload->impl);
1602 emit_function(ctx, overload->impl);
1603 if (ctx->error)
1604 return;
1605 }
1606 }
1607
1608 /* from NIR perspective, we actually have inputs. But most of the "inputs"
1609 * for a fragment shader are just bary.f instructions. The *actual* inputs
1610 * from the hw perspective are the frag_pos and optionally frag_coord and
1611 * frag_face.
1612 */
1613 static void
1614 fixup_frag_inputs(struct ir3_compile *ctx)
1615 {
1616 struct ir3_shader_variant *so = ctx->so;
1617 struct ir3_block *block = ctx->block;
1618 struct ir3_instruction **inputs;
1619 struct ir3_instruction *instr;
1620 int n, regid = 0;
1621
1622 block->ninputs = 0;
1623
1624 n = 4; /* always have frag_pos */
1625 n += COND(so->frag_face, 4);
1626 n += COND(so->frag_coord, 4);
1627
1628 inputs = ir3_alloc(ctx->ir, n * (sizeof(struct ir3_instruction *)));
1629
1630 if (so->frag_face) {
1631 /* this ultimately gets assigned to hr0.x so doesn't conflict
1632 * with frag_coord/frag_pos..
1633 */
1634 inputs[block->ninputs++] = ctx->frag_face;
1635 ctx->frag_face->regs[0]->num = 0;
1636
1637 /* remaining channels not used, but let's avoid confusing
1638 * other parts that expect inputs to come in groups of vec4
1639 */
1640 inputs[block->ninputs++] = NULL;
1641 inputs[block->ninputs++] = NULL;
1642 inputs[block->ninputs++] = NULL;
1643 }
1644
1645 /* since we don't know where to set the regid for frag_coord,
1646 * we have to use r0.x for it. But we don't want to *always*
1647 * use r1.x for frag_pos as that could increase the register
1648 * footprint on simple shaders:
1649 */
1650 if (so->frag_coord) {
1651 ctx->frag_coord[0]->regs[0]->num = regid++;
1652 ctx->frag_coord[1]->regs[0]->num = regid++;
1653 ctx->frag_coord[2]->regs[0]->num = regid++;
1654 ctx->frag_coord[3]->regs[0]->num = regid++;
1655
1656 inputs[block->ninputs++] = ctx->frag_coord[0];
1657 inputs[block->ninputs++] = ctx->frag_coord[1];
1658 inputs[block->ninputs++] = ctx->frag_coord[2];
1659 inputs[block->ninputs++] = ctx->frag_coord[3];
1660 }
1661
1662 /* we always have frag_pos: */
1663 so->pos_regid = regid;
1664
1665 /* r0.x */
1666 instr = create_input(block, NULL, block->ninputs);
1667 instr->regs[0]->num = regid++;
1668 inputs[block->ninputs++] = instr;
1669 ctx->frag_pos->regs[1]->instr = instr;
1670
1671 /* r0.y */
1672 instr = create_input(block, NULL, block->ninputs);
1673 instr->regs[0]->num = regid++;
1674 inputs[block->ninputs++] = instr;
1675 ctx->frag_pos->regs[2]->instr = instr;
1676
1677 block->inputs = inputs;
1678 }
1679
1680 static void
1681 compile_dump(struct ir3_compile *ctx)
1682 {
1683 const char *name = (ctx->so->type == SHADER_VERTEX) ? "vert" : "frag";
1684 static unsigned n = 0;
1685 char fname[16];
1686 FILE *f;
1687 snprintf(fname, sizeof(fname), "%s-%04u.dot", name, n++);
1688 f = fopen(fname, "w");
1689 if (!f)
1690 return;
1691 ir3_block_depth(ctx->block);
1692 ir3_dump(ctx->ir, name, ctx->block, f);
1693 fclose(f);
1694 }
1695
1696 int
1697 ir3_compile_shader_nir(struct ir3_shader_variant *so,
1698 const struct tgsi_token *tokens, struct ir3_shader_key key)
1699 {
1700 struct ir3_compile *ctx;
1701 struct ir3_block *block;
1702 struct ir3_instruction **inputs;
1703 unsigned i, j, actual_in;
1704 int ret = 0, max_bary;
1705
1706 assert(!so->ir);
1707
1708 so->ir = ir3_create();
1709
1710 assert(so->ir);
1711
1712 ctx = compile_init(so, tokens);
1713 if (!ctx) {
1714 DBG("INIT failed!");
1715 ret = -1;
1716 goto out;
1717 }
1718
1719 emit_instructions(ctx);
1720
1721 if (ctx->error) {
1722 DBG("EMIT failed!");
1723 ret = -1;
1724 goto out;
1725 }
1726
1727 block = ctx->block;
1728 so->ir->block = block;
1729
1730 /* keep track of the inputs from TGSI perspective.. */
1731 inputs = block->inputs;
1732
1733 /* but fixup actual inputs for frag shader: */
1734 if (so->type == SHADER_FRAGMENT)
1735 fixup_frag_inputs(ctx);
1736
1737 /* at this point, for binning pass, throw away unneeded outputs: */
1738 if (key.binning_pass) {
1739 for (i = 0, j = 0; i < so->outputs_count; i++) {
1740 unsigned name = sem2name(so->outputs[i].semantic);
1741 unsigned idx = sem2idx(so->outputs[i].semantic);
1742
1743 /* throw away everything but first position/psize */
1744 if ((idx == 0) && ((name == TGSI_SEMANTIC_POSITION) ||
1745 (name == TGSI_SEMANTIC_PSIZE))) {
1746 if (i != j) {
1747 so->outputs[j] = so->outputs[i];
1748 block->outputs[(j*4)+0] = block->outputs[(i*4)+0];
1749 block->outputs[(j*4)+1] = block->outputs[(i*4)+1];
1750 block->outputs[(j*4)+2] = block->outputs[(i*4)+2];
1751 block->outputs[(j*4)+3] = block->outputs[(i*4)+3];
1752 }
1753 j++;
1754 }
1755 }
1756 so->outputs_count = j;
1757 block->noutputs = j * 4;
1758 }
1759
1760 /* if we want half-precision outputs, mark the output registers
1761 * as half:
1762 */
1763 if (key.half_precision) {
1764 for (i = 0; i < block->noutputs; i++) {
1765 if (!block->outputs[i])
1766 continue;
1767 block->outputs[i]->regs[0]->flags |= IR3_REG_HALF;
1768 }
1769 }
1770
1771 /* at this point, we want the kill's in the outputs array too,
1772 * so that they get scheduled (since they have no dst).. we've
1773 * already ensured that the array is big enough in push_block():
1774 */
1775 if (so->type == SHADER_FRAGMENT) {
1776 for (i = 0; i < ctx->kill_count; i++)
1777 block->outputs[block->noutputs++] = ctx->kill[i];
1778 }
1779
1780 if (fd_mesa_debug & FD_DBG_OPTDUMP)
1781 compile_dump(ctx);
1782
1783 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
1784 printf("BEFORE CP:\n");
1785 ir3_dump_instr_list(block->head);
1786 }
1787
1788 ir3_block_depth(block);
1789
1790 ir3_block_cp(block);
1791
1792 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
1793 printf("BEFORE GROUPING:\n");
1794 ir3_dump_instr_list(block->head);
1795 }
1796
1797 /* Group left/right neighbors, inserting mov's where needed to
1798 * solve conflicts:
1799 */
1800 ir3_block_group(block);
1801
1802 if (fd_mesa_debug & FD_DBG_OPTDUMP)
1803 compile_dump(ctx);
1804
1805 ir3_block_depth(block);
1806
1807 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
1808 printf("AFTER DEPTH:\n");
1809 ir3_dump_instr_list(block->head);
1810 }
1811
1812 ret = ir3_block_sched(block);
1813 if (ret) {
1814 DBG("SCHED failed!");
1815 goto out;
1816 }
1817
1818 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
1819 printf("AFTER SCHED:\n");
1820 ir3_dump_instr_list(block->head);
1821 }
1822
1823 ret = ir3_block_ra(block, so->type, so->frag_coord, so->frag_face);
1824 if (ret) {
1825 DBG("RA failed!");
1826 goto out;
1827 }
1828
1829 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
1830 printf("AFTER RA:\n");
1831 ir3_dump_instr_list(block->head);
1832 }
1833
1834 ir3_block_legalize(block, &so->has_samp, &max_bary);
1835
1836 /* fixup input/outputs: */
1837 for (i = 0; i < so->outputs_count; i++) {
1838 so->outputs[i].regid = block->outputs[i*4]->regs[0]->num;
1839 /* preserve hack for depth output.. tgsi writes depth to .z,
1840 * but what we give the hw is the scalar register:
1841 */
1842 if ((so->type == SHADER_FRAGMENT) &&
1843 (sem2name(so->outputs[i].semantic) == TGSI_SEMANTIC_POSITION))
1844 so->outputs[i].regid += 2;
1845 }
1846
1847 /* Note that some or all channels of an input may be unused: */
1848 actual_in = 0;
1849 for (i = 0; i < so->inputs_count; i++) {
1850 unsigned j, regid = ~0, compmask = 0;
1851 so->inputs[i].ncomp = 0;
1852 for (j = 0; j < 4; j++) {
1853 struct ir3_instruction *in = inputs[(i*4) + j];
1854 if (in) {
1855 compmask |= (1 << j);
1856 regid = in->regs[0]->num - j;
1857 actual_in++;
1858 so->inputs[i].ncomp++;
1859 }
1860 }
1861 so->inputs[i].regid = regid;
1862 so->inputs[i].compmask = compmask;
1863 }
1864
1865 /* fragment shader always gets full vec4's even if it doesn't
1866 * fetch all components, but vertex shader we need to update
1867 * with the actual number of components fetch, otherwise thing
1868 * will hang due to mismaptch between VFD_DECODE's and
1869 * TOTALATTRTOVS
1870 */
1871 if (so->type == SHADER_VERTEX)
1872 so->total_in = actual_in;
1873 else
1874 so->total_in = align(max_bary + 1, 4);
1875
1876 out:
1877 if (ret) {
1878 ir3_destroy(so->ir);
1879 so->ir = NULL;
1880 }
1881 compile_free(ctx);
1882
1883 return ret;
1884 }