1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
36 #include "freedreno_util.h"
38 #include "ir3_compiler.h"
39 #include "ir3_shader.h"
42 #include "instr-a3xx.h"
47 struct ir3_compiler
*compiler
;
52 struct ir3_shader_variant
*so
;
54 struct ir3_block
*block
; /* the current block */
55 struct ir3_block
*in_block
; /* block created for shader inputs */
57 nir_function_impl
*impl
;
59 /* For fragment shaders, from the hw perspective the only
60 * actual input is r0.xy position register passed to bary.f.
61 * But TGSI doesn't know that, it still declares things as
62 * IN[] registers. So we do all the input tracking normally
63 * and fix things up after compile_instructions()
65 * NOTE that frag_pos is the hardware position (possibly it
66 * is actually an index or tag or some such.. it is *not*
67 * values that can be directly used for gl_FragCoord..)
69 struct ir3_instruction
*frag_pos
, *frag_face
, *frag_coord
[4];
71 /* For vertex shaders, keep track of the system values sources */
72 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
74 /* Compute shader inputs: */
75 struct ir3_instruction
*local_invocation_id
, *work_group_id
;
77 /* For SSBO's and atomics, we need to preserve order, such
78 * that reads don't overtake writes, and the order of writes
79 * is preserved. Atomics are considered as a write.
81 * To do this, we track last write and last access, in a
82 * similar way to ir3_array. But since we don't know whether
83 * the same SSBO is bound to multiple slots, so we simply
84 * track this globally rather than per-SSBO.
86 * TODO should we track this per block instead? I guess it
87 * shouldn't matter much?
89 struct ir3_instruction
*last_write
, *last_access
;
91 /* mapping from nir_register to defining instruction: */
92 struct hash_table
*def_ht
;
96 /* a common pattern for indirect addressing is to request the
97 * same address register multiple times. To avoid generating
98 * duplicate instruction sequences (which our backend does not
99 * try to clean up, since that should be done as the NIR stage)
100 * we cache the address value generated for a given src value:
102 * Note that we have to cache these per alignment, since same
103 * src used for an array of vec1 cannot be also used for an
106 struct hash_table
*addr_ht
[4];
108 /* last dst array, for indirect we need to insert a var-store.
110 struct ir3_instruction
**last_dst
;
113 /* maps nir_block to ir3_block, mostly for the purposes of
114 * figuring out the blocks successors
116 struct hash_table
*block_ht
;
118 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
119 * so we need to use ldlv.u32 to load the varying directly:
123 /* on a3xx, we need to add one to # of array levels:
127 /* on a3xx, we need to scale up integer coords for isaml based
130 bool unminify_coords
;
132 /* on a4xx, for array textures we need to add 0.5 to the array
135 bool array_index_add_half
;
137 /* on a4xx, bitmask of samplers which need astc+srgb workaround: */
140 unsigned max_texture_index
;
142 /* set if we encounter something we can't handle yet, so we
143 * can bail cleanly and fallback to TGSI compiler f/e
148 /* gpu pointer size in units of 32bit registers/slots */
149 static unsigned pointer_size(struct ir3_context
*ctx
)
151 return (ctx
->compiler
->gpu_id
>= 500) ? 2 : 1;
154 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
155 static struct ir3_block
* get_block(struct ir3_context
*ctx
, nir_block
*nblock
);
158 static struct ir3_context
*
159 compile_init(struct ir3_compiler
*compiler
,
160 struct ir3_shader_variant
*so
)
162 struct ir3_context
*ctx
= rzalloc(NULL
, struct ir3_context
);
164 if (compiler
->gpu_id
>= 400) {
165 /* need special handling for "flat" */
166 ctx
->flat_bypass
= true;
167 ctx
->levels_add_one
= false;
168 ctx
->unminify_coords
= false;
169 ctx
->array_index_add_half
= true;
171 if (so
->type
== SHADER_VERTEX
)
172 ctx
->astc_srgb
= so
->key
.vastc_srgb
;
173 else if (so
->type
== SHADER_FRAGMENT
)
174 ctx
->astc_srgb
= so
->key
.fastc_srgb
;
177 /* no special handling for "flat" */
178 ctx
->flat_bypass
= false;
179 ctx
->levels_add_one
= true;
180 ctx
->unminify_coords
= true;
181 ctx
->array_index_add_half
= false;
184 ctx
->compiler
= compiler
;
187 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
188 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
189 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
190 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
192 /* TODO: maybe generate some sort of bitmask of what key
193 * lowers vs what shader has (ie. no need to lower
194 * texture clamp lowering if no texture sample instrs)..
195 * although should be done further up the stack to avoid
196 * creating duplicate variants..
199 if (ir3_key_lowers_nir(&so
->key
)) {
200 nir_shader
*s
= nir_shader_clone(ctx
, so
->shader
->nir
);
201 ctx
->s
= ir3_optimize_nir(so
->shader
, s
, &so
->key
);
203 /* fast-path for shader key that lowers nothing in NIR: */
204 ctx
->s
= so
->shader
->nir
;
207 /* this needs to be the last pass run, so do this here instead of
208 * in ir3_optimize_nir():
210 NIR_PASS_V(ctx
->s
, nir_lower_locals_to_regs
);
212 if (fd_mesa_debug
& FD_DBG_DISASM
) {
213 DBG("dump nir%dv%d: type=%d, k={bp=%u,cts=%u,hp=%u}",
214 so
->shader
->id
, so
->id
, so
->type
,
215 so
->key
.binning_pass
, so
->key
.color_two_side
,
216 so
->key
.half_precision
);
217 nir_print_shader(ctx
->s
, stdout
);
220 ir3_nir_scan_driver_consts(ctx
->s
, &so
->const_layout
);
222 so
->num_uniforms
= ctx
->s
->num_uniforms
;
223 so
->num_ubos
= ctx
->s
->info
.num_ubos
;
225 /* Layout of constant registers, each section aligned to vec4. Note
226 * that pointer size (ubo, etc) changes depending on generation.
231 * if (vertex shader) {
232 * driver params (IR3_DP_*)
233 * if (stream_output.num_outputs > 0)
234 * stream-out addresses
238 * Immediates go last mostly because they are inserted in the CP pass
239 * after the nir -> ir3 frontend.
241 unsigned constoff
= align(ctx
->s
->num_uniforms
, 4);
242 unsigned ptrsz
= pointer_size(ctx
);
244 memset(&so
->constbase
, ~0, sizeof(so
->constbase
));
246 if (so
->num_ubos
> 0) {
247 so
->constbase
.ubo
= constoff
;
248 constoff
+= align(ctx
->s
->info
.num_ubos
* ptrsz
, 4) / 4;
251 if (so
->const_layout
.ssbo_size
.count
> 0) {
252 unsigned cnt
= so
->const_layout
.ssbo_size
.count
;
253 so
->constbase
.ssbo_sizes
= constoff
;
254 constoff
+= align(cnt
, 4) / 4;
257 unsigned num_driver_params
= 0;
258 if (so
->type
== SHADER_VERTEX
) {
259 num_driver_params
= IR3_DP_VS_COUNT
;
260 } else if (so
->type
== SHADER_COMPUTE
) {
261 num_driver_params
= IR3_DP_CS_COUNT
;
264 so
->constbase
.driver_param
= constoff
;
265 constoff
+= align(num_driver_params
, 4) / 4;
267 if ((so
->type
== SHADER_VERTEX
) &&
268 (compiler
->gpu_id
< 500) &&
269 so
->shader
->stream_output
.num_outputs
> 0) {
270 so
->constbase
.tfbo
= constoff
;
271 constoff
+= align(PIPE_MAX_SO_BUFFERS
* ptrsz
, 4) / 4;
274 so
->constbase
.immediate
= constoff
;
280 compile_error(struct ir3_context
*ctx
, const char *format
, ...)
283 va_start(ap
, format
);
284 _debug_vprintf(format
, ap
);
286 nir_print_shader(ctx
->s
, stdout
);
291 #define compile_assert(ctx, cond) do { \
292 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
296 compile_free(struct ir3_context
*ctx
)
302 declare_array(struct ir3_context
*ctx
, nir_register
*reg
)
304 struct ir3_array
*arr
= rzalloc(ctx
, struct ir3_array
);
305 arr
->id
= ++ctx
->num_arrays
;
306 /* NOTE: sometimes we get non array regs, for example for arrays of
307 * length 1. See fs-const-array-of-struct-of-array.shader_test. So
308 * treat a non-array as if it was an array of length 1.
310 * It would be nice if there was a nir pass to convert arrays of
313 arr
->length
= reg
->num_components
* MAX2(1, reg
->num_array_elems
);
314 compile_assert(ctx
, arr
->length
> 0);
316 list_addtail(&arr
->node
, &ctx
->ir
->array_list
);
319 static struct ir3_array
*
320 get_array(struct ir3_context
*ctx
, nir_register
*reg
)
322 list_for_each_entry (struct ir3_array
, arr
, &ctx
->ir
->array_list
, node
) {
326 compile_error(ctx
, "bogus reg: %s\n", reg
->name
);
330 /* relative (indirect) if address!=NULL */
331 static struct ir3_instruction
*
332 create_array_load(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
333 struct ir3_instruction
*address
)
335 struct ir3_block
*block
= ctx
->block
;
336 struct ir3_instruction
*mov
;
337 struct ir3_register
*src
;
339 mov
= ir3_instr_create(block
, OPC_MOV
);
340 mov
->cat1
.src_type
= TYPE_U32
;
341 mov
->cat1
.dst_type
= TYPE_U32
;
342 ir3_reg_create(mov
, 0, 0);
343 src
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
344 COND(address
, IR3_REG_RELATIV
));
345 src
->instr
= arr
->last_write
;
346 src
->size
= arr
->length
;
347 src
->array
.id
= arr
->id
;
348 src
->array
.offset
= n
;
351 ir3_instr_set_address(mov
, address
);
353 arr
->last_access
= mov
;
358 /* relative (indirect) if address!=NULL */
359 static struct ir3_instruction
*
360 create_array_store(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
361 struct ir3_instruction
*src
, struct ir3_instruction
*address
)
363 struct ir3_block
*block
= ctx
->block
;
364 struct ir3_instruction
*mov
;
365 struct ir3_register
*dst
;
367 mov
= ir3_instr_create(block
, OPC_MOV
);
368 mov
->cat1
.src_type
= TYPE_U32
;
369 mov
->cat1
.dst_type
= TYPE_U32
;
370 dst
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
371 COND(address
, IR3_REG_RELATIV
));
372 dst
->instr
= arr
->last_access
;
373 dst
->size
= arr
->length
;
374 dst
->array
.id
= arr
->id
;
375 dst
->array
.offset
= n
;
376 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
379 ir3_instr_set_address(mov
, address
);
381 arr
->last_write
= arr
->last_access
= mov
;
386 /* allocate a n element value array (to be populated by caller) and
389 static struct ir3_instruction
**
390 get_dst_ssa(struct ir3_context
*ctx
, nir_ssa_def
*dst
, unsigned n
)
392 struct ir3_instruction
**value
=
393 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
394 _mesa_hash_table_insert(ctx
->def_ht
, dst
, value
);
398 static struct ir3_instruction
**
399 get_dst(struct ir3_context
*ctx
, nir_dest
*dst
, unsigned n
)
401 struct ir3_instruction
**value
;
404 value
= get_dst_ssa(ctx
, &dst
->ssa
, n
);
406 value
= ralloc_array(ctx
, struct ir3_instruction
*, n
);
409 /* NOTE: in non-ssa case, we don't really need to store last_dst
410 * but this helps us catch cases where put_dst() call is forgotten
412 compile_assert(ctx
, !ctx
->last_dst
);
413 ctx
->last_dst
= value
;
419 static struct ir3_instruction
* get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
);
421 static struct ir3_instruction
* const *
422 get_src(struct ir3_context
*ctx
, nir_src
*src
)
425 struct hash_entry
*entry
;
426 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
427 compile_assert(ctx
, entry
);
430 nir_register
*reg
= src
->reg
.reg
;
431 struct ir3_array
*arr
= get_array(ctx
, reg
);
432 unsigned num_components
= arr
->r
->num_components
;
433 struct ir3_instruction
*addr
= NULL
;
434 struct ir3_instruction
**value
=
435 ralloc_array(ctx
, struct ir3_instruction
*, num_components
);
437 if (src
->reg
.indirect
)
438 addr
= get_addr(ctx
, get_src(ctx
, src
->reg
.indirect
)[0],
439 reg
->num_components
);
441 for (unsigned i
= 0; i
< num_components
; i
++) {
442 unsigned n
= src
->reg
.base_offset
* reg
->num_components
+ i
;
443 compile_assert(ctx
, n
< arr
->length
);
444 value
[i
] = create_array_load(ctx
, arr
, n
, addr
);
452 put_dst(struct ir3_context
*ctx
, nir_dest
*dst
)
455 nir_register
*reg
= dst
->reg
.reg
;
456 struct ir3_array
*arr
= get_array(ctx
, reg
);
457 unsigned num_components
= ctx
->last_dst_n
;
458 struct ir3_instruction
*addr
= NULL
;
460 if (dst
->reg
.indirect
)
461 addr
= get_addr(ctx
, get_src(ctx
, dst
->reg
.indirect
)[0],
462 reg
->num_components
);
464 for (unsigned i
= 0; i
< num_components
; i
++) {
465 unsigned n
= dst
->reg
.base_offset
* reg
->num_components
+ i
;
466 compile_assert(ctx
, n
< arr
->length
);
467 if (!ctx
->last_dst
[i
])
469 create_array_store(ctx
, arr
, n
, ctx
->last_dst
[i
], addr
);
472 ralloc_free(ctx
->last_dst
);
474 ctx
->last_dst
= NULL
;
478 static struct ir3_instruction
*
479 create_immed(struct ir3_block
*block
, uint32_t val
)
481 struct ir3_instruction
*mov
;
483 mov
= ir3_instr_create(block
, OPC_MOV
);
484 mov
->cat1
.src_type
= TYPE_U32
;
485 mov
->cat1
.dst_type
= TYPE_U32
;
486 ir3_reg_create(mov
, 0, 0);
487 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
492 static struct ir3_instruction
*
493 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
, int align
)
495 struct ir3_instruction
*instr
, *immed
;
497 /* TODO in at least some cases, the backend could probably be
498 * made clever enough to propagate IR3_REG_HALF..
500 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
501 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
508 /* src *= 2 => src <<= 1: */
509 immed
= create_immed(block
, 1);
510 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
512 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
513 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
514 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
518 immed
= create_immed(block
, 3);
519 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
521 instr
= ir3_MULL_U(block
, instr
, 0, immed
, 0);
522 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
523 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
526 /* src *= 4 => src <<= 2: */
527 immed
= create_immed(block
, 2);
528 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
530 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
531 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
532 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
535 unreachable("bad align");
539 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
540 instr
->regs
[0]->num
= regid(REG_A0
, 0);
541 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
542 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
547 /* caches addr values to avoid generating multiple cov/shl/mova
548 * sequences for each use of a given NIR level src as address
550 static struct ir3_instruction
*
551 get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
)
553 struct ir3_instruction
*addr
;
554 unsigned idx
= align
- 1;
556 compile_assert(ctx
, idx
< ARRAY_SIZE(ctx
->addr_ht
));
558 if (!ctx
->addr_ht
[idx
]) {
559 ctx
->addr_ht
[idx
] = _mesa_hash_table_create(ctx
,
560 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
562 struct hash_entry
*entry
;
563 entry
= _mesa_hash_table_search(ctx
->addr_ht
[idx
], src
);
568 addr
= create_addr(ctx
->block
, src
, align
);
569 _mesa_hash_table_insert(ctx
->addr_ht
[idx
], src
, addr
);
574 static struct ir3_instruction
*
575 get_predicate(struct ir3_context
*ctx
, struct ir3_instruction
*src
)
577 struct ir3_block
*b
= ctx
->block
;
578 struct ir3_instruction
*cond
;
580 /* NOTE: only cmps.*.* can write p0.x: */
581 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
582 cond
->cat2
.condition
= IR3_COND_NE
;
584 /* condition always goes in predicate register: */
585 cond
->regs
[0]->num
= regid(REG_P0
, 0);
590 static struct ir3_instruction
*
591 create_uniform(struct ir3_context
*ctx
, unsigned n
)
593 struct ir3_instruction
*mov
;
595 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
596 /* TODO get types right? */
597 mov
->cat1
.src_type
= TYPE_F32
;
598 mov
->cat1
.dst_type
= TYPE_F32
;
599 ir3_reg_create(mov
, 0, 0);
600 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
605 static struct ir3_instruction
*
606 create_uniform_indirect(struct ir3_context
*ctx
, int n
,
607 struct ir3_instruction
*address
)
609 struct ir3_instruction
*mov
;
611 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
612 mov
->cat1
.src_type
= TYPE_U32
;
613 mov
->cat1
.dst_type
= TYPE_U32
;
614 ir3_reg_create(mov
, 0, 0);
615 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
617 ir3_instr_set_address(mov
, address
);
622 static struct ir3_instruction
*
623 create_collect(struct ir3_block
*block
, struct ir3_instruction
*const *arr
,
626 struct ir3_instruction
*collect
;
631 collect
= ir3_instr_create2(block
, OPC_META_FI
, 1 + arrsz
);
632 ir3_reg_create(collect
, 0, 0); /* dst */
633 for (unsigned i
= 0; i
< arrsz
; i
++)
634 ir3_reg_create(collect
, 0, IR3_REG_SSA
)->instr
= arr
[i
];
639 static struct ir3_instruction
*
640 create_indirect_load(struct ir3_context
*ctx
, unsigned arrsz
, int n
,
641 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
643 struct ir3_block
*block
= ctx
->block
;
644 struct ir3_instruction
*mov
;
645 struct ir3_register
*src
;
647 mov
= ir3_instr_create(block
, OPC_MOV
);
648 mov
->cat1
.src_type
= TYPE_U32
;
649 mov
->cat1
.dst_type
= TYPE_U32
;
650 ir3_reg_create(mov
, 0, 0);
651 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
652 src
->instr
= collect
;
654 src
->array
.offset
= n
;
656 ir3_instr_set_address(mov
, address
);
661 static struct ir3_instruction
*
662 create_input_compmask(struct ir3_block
*block
, unsigned n
, unsigned compmask
)
664 struct ir3_instruction
*in
;
666 in
= ir3_instr_create(block
, OPC_META_INPUT
);
667 in
->inout
.block
= block
;
668 ir3_reg_create(in
, n
, 0);
670 in
->regs
[0]->wrmask
= compmask
;
675 static struct ir3_instruction
*
676 create_input(struct ir3_block
*block
, unsigned n
)
678 return create_input_compmask(block
, n
, 0x1);
681 static struct ir3_instruction
*
682 create_frag_input(struct ir3_context
*ctx
, bool use_ldlv
)
684 struct ir3_block
*block
= ctx
->block
;
685 struct ir3_instruction
*instr
;
686 /* actual inloc is assigned and fixed up later: */
687 struct ir3_instruction
*inloc
= create_immed(block
, 0);
690 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
691 instr
->cat6
.type
= TYPE_U32
;
692 instr
->cat6
.iim_val
= 1;
694 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_pos
, 0);
695 instr
->regs
[2]->wrmask
= 0x3;
701 static struct ir3_instruction
*
702 create_frag_coord(struct ir3_context
*ctx
, unsigned comp
)
704 struct ir3_block
*block
= ctx
->block
;
705 struct ir3_instruction
*instr
;
707 compile_assert(ctx
, !ctx
->frag_coord
[comp
]);
709 ctx
->frag_coord
[comp
] = create_input(ctx
->block
, 0);
714 /* for frag_coord, we get unsigned values.. we need
715 * to subtract (integer) 8 and divide by 16 (right-
716 * shift by 4) then convert to float:
720 * mov.u32f32 dst, tmp
723 instr
= ir3_SUB_S(block
, ctx
->frag_coord
[comp
], 0,
724 create_immed(block
, 8), 0);
725 instr
= ir3_SHR_B(block
, instr
, 0,
726 create_immed(block
, 4), 0);
727 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
733 /* seems that we can use these as-is: */
734 return ctx
->frag_coord
[comp
];
738 static struct ir3_instruction
*
739 create_driver_param(struct ir3_context
*ctx
, enum ir3_driver_param dp
)
741 /* first four vec4 sysval's reserved for UBOs: */
742 /* NOTE: dp is in scalar, but there can be >4 dp components: */
743 unsigned n
= ctx
->so
->constbase
.driver_param
;
744 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
745 return create_uniform(ctx
, r
);
748 /* helper for instructions that produce multiple consecutive scalar
749 * outputs which need to have a split/fanout meta instruction inserted
752 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
753 struct ir3_instruction
*src
, unsigned base
, unsigned n
)
755 struct ir3_instruction
*prev
= NULL
;
756 for (int i
= 0, j
= 0; i
< n
; i
++) {
757 struct ir3_instruction
*split
= ir3_instr_create(block
, OPC_META_FO
);
758 ir3_reg_create(split
, 0, IR3_REG_SSA
);
759 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
760 split
->fo
.off
= i
+ base
;
763 split
->cp
.left
= prev
;
764 split
->cp
.left_cnt
++;
765 prev
->cp
.right
= split
;
766 prev
->cp
.right_cnt
++;
770 if (src
->regs
[0]->wrmask
& (1 << (i
+ base
)))
776 * Adreno uses uint rather than having dedicated bool type,
777 * which (potentially) requires some conversion, in particular
778 * when using output of an bool instr to int input, or visa
782 * -------+---------+-------+-
786 * To convert from an adreno bool (uint) to nir, use:
788 * absneg.s dst, (neg)src
790 * To convert back in the other direction:
792 * absneg.s dst, (abs)arc
794 * The CP step can clean up the absneg.s that cancel each other
795 * out, and with a slight bit of extra cleverness (to recognize
796 * the instructions which produce either a 0 or 1) can eliminate
797 * the absneg.s's completely when an instruction that wants
798 * 0/1 consumes the result. For example, when a nir 'bcsel'
799 * consumes the result of 'feq'. So we should be able to get by
800 * without a boolean resolve step, and without incuring any
801 * extra penalty in instruction count.
804 /* NIR bool -> native (adreno): */
805 static struct ir3_instruction
*
806 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
808 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
811 /* native (adreno) -> NIR bool: */
812 static struct ir3_instruction
*
813 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
815 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
819 * alu/sfu instructions:
823 emit_alu(struct ir3_context
*ctx
, nir_alu_instr
*alu
)
825 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
826 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
827 struct ir3_block
*b
= ctx
->block
;
828 unsigned dst_sz
, wrmask
;
830 if (alu
->dest
.dest
.is_ssa
) {
831 dst_sz
= alu
->dest
.dest
.ssa
.num_components
;
832 wrmask
= (1 << dst_sz
) - 1;
834 dst_sz
= alu
->dest
.dest
.reg
.reg
->num_components
;
835 wrmask
= alu
->dest
.write_mask
;
838 dst
= get_dst(ctx
, &alu
->dest
.dest
, dst_sz
);
840 /* Vectors are special in that they have non-scalarized writemasks,
841 * and just take the first swizzle channel for each argument in
842 * order into each writemask channel.
844 if ((alu
->op
== nir_op_vec2
) ||
845 (alu
->op
== nir_op_vec3
) ||
846 (alu
->op
== nir_op_vec4
)) {
848 for (int i
= 0; i
< info
->num_inputs
; i
++) {
849 nir_alu_src
*asrc
= &alu
->src
[i
];
851 compile_assert(ctx
, !asrc
->abs
);
852 compile_assert(ctx
, !asrc
->negate
);
854 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
856 src
[i
] = create_immed(ctx
->block
, 0);
857 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
860 put_dst(ctx
, &alu
->dest
.dest
);
864 /* We also get mov's with more than one component for mov's so
865 * handle those specially:
867 if ((alu
->op
== nir_op_imov
) || (alu
->op
== nir_op_fmov
)) {
868 type_t type
= (alu
->op
== nir_op_imov
) ? TYPE_U32
: TYPE_F32
;
869 nir_alu_src
*asrc
= &alu
->src
[0];
870 struct ir3_instruction
*const *src0
= get_src(ctx
, &asrc
->src
);
872 for (unsigned i
= 0; i
< dst_sz
; i
++) {
873 if (wrmask
& (1 << i
)) {
874 dst
[i
] = ir3_MOV(b
, src0
[asrc
->swizzle
[i
]], type
);
880 put_dst(ctx
, &alu
->dest
.dest
);
884 compile_assert(ctx
, alu
->dest
.dest
.is_ssa
);
886 /* General case: We can just grab the one used channel per src. */
887 for (int i
= 0; i
< info
->num_inputs
; i
++) {
888 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
889 nir_alu_src
*asrc
= &alu
->src
[i
];
891 compile_assert(ctx
, !asrc
->abs
);
892 compile_assert(ctx
, !asrc
->negate
);
894 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
896 compile_assert(ctx
, src
[i
]);
901 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_S32
);
904 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_U32
);
907 dst
[0] = ir3_COV(b
, src
[0], TYPE_S32
, TYPE_F32
);
910 dst
[0] = ir3_COV(b
, src
[0], TYPE_U32
, TYPE_F32
);
913 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
914 dst
[0]->cat2
.condition
= IR3_COND_NE
;
915 dst
[0] = ir3_n2b(b
, dst
[0]);
918 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
921 dst
[0] = ir3_b2n(b
, src
[0]);
924 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
925 dst
[0]->cat2
.condition
= IR3_COND_NE
;
926 dst
[0] = ir3_n2b(b
, dst
[0]);
930 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
933 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
936 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
939 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
942 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
945 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
948 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
951 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
954 dst
[0] = ir3_DSX(b
, src
[0], 0);
955 dst
[0]->cat5
.type
= TYPE_F32
;
958 dst
[0] = ir3_DSY(b
, src
[0], 0);
959 dst
[0]->cat5
.type
= TYPE_F32
;
963 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
964 dst
[0]->cat2
.condition
= IR3_COND_LT
;
965 dst
[0] = ir3_n2b(b
, dst
[0]);
968 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
969 dst
[0]->cat2
.condition
= IR3_COND_GE
;
970 dst
[0] = ir3_n2b(b
, dst
[0]);
973 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
974 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
975 dst
[0] = ir3_n2b(b
, dst
[0]);
978 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
979 dst
[0]->cat2
.condition
= IR3_COND_NE
;
980 dst
[0] = ir3_n2b(b
, dst
[0]);
983 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
986 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
989 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
991 case nir_op_fround_even
:
992 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
995 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
999 dst
[0] = ir3_SIN(b
, src
[0], 0);
1002 dst
[0] = ir3_COS(b
, src
[0], 0);
1005 dst
[0] = ir3_RSQ(b
, src
[0], 0);
1008 dst
[0] = ir3_RCP(b
, src
[0], 0);
1011 dst
[0] = ir3_LOG2(b
, src
[0], 0);
1014 dst
[0] = ir3_EXP2(b
, src
[0], 0);
1017 dst
[0] = ir3_SQRT(b
, src
[0], 0);
1021 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
1024 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
1027 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
1030 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
1033 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
1036 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
1039 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
1043 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
1044 * mull.u tmp0, a, b ; mul low, i.e. al * bl
1045 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
1046 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
1048 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
1049 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
1050 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
1053 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
1056 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
1059 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
1062 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
1065 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
1067 case nir_op_isign
: {
1068 /* maybe this would be sane to lower in nir.. */
1069 struct ir3_instruction
*neg
, *pos
;
1071 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1072 neg
->cat2
.condition
= IR3_COND_LT
;
1074 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1075 pos
->cat2
.condition
= IR3_COND_GT
;
1077 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
1082 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
1085 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
1088 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
1091 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1092 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1093 dst
[0] = ir3_n2b(b
, dst
[0]);
1096 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1097 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1098 dst
[0] = ir3_n2b(b
, dst
[0]);
1101 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1102 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1103 dst
[0] = ir3_n2b(b
, dst
[0]);
1106 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1107 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1108 dst
[0] = ir3_n2b(b
, dst
[0]);
1111 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1112 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1113 dst
[0] = ir3_n2b(b
, dst
[0]);
1116 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1117 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1118 dst
[0] = ir3_n2b(b
, dst
[0]);
1122 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, ir3_b2n(b
, src
[0]), 0, src
[2], 0);
1125 case nir_op_bit_count
:
1126 dst
[0] = ir3_CBITS_B(b
, src
[0], 0);
1128 case nir_op_ifind_msb
: {
1129 struct ir3_instruction
*cmp
;
1130 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
1131 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
1132 cmp
->cat2
.condition
= IR3_COND_GE
;
1133 dst
[0] = ir3_SEL_B32(b
,
1134 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1138 case nir_op_ufind_msb
:
1139 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
1140 dst
[0] = ir3_SEL_B32(b
,
1141 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1142 src
[0], 0, dst
[0], 0);
1144 case nir_op_find_lsb
:
1145 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1146 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
1148 case nir_op_bitfield_reverse
:
1149 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1153 compile_error(ctx
, "Unhandled ALU op: %s\n",
1154 nir_op_infos
[alu
->op
].name
);
1158 put_dst(ctx
, &alu
->dest
.dest
);
1161 /* handles direct/indirect UBO reads: */
1163 emit_intrinsic_load_ubo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1164 struct ir3_instruction
**dst
)
1166 struct ir3_block
*b
= ctx
->block
;
1167 struct ir3_instruction
*base_lo
, *base_hi
, *addr
, *src0
, *src1
;
1168 nir_const_value
*const_offset
;
1169 /* UBO addresses are the first driver params: */
1170 unsigned ubo
= regid(ctx
->so
->constbase
.ubo
, 0);
1171 const unsigned ptrsz
= pointer_size(ctx
);
1175 /* First src is ubo index, which could either be an immed or not: */
1176 src0
= get_src(ctx
, &intr
->src
[0])[0];
1177 if (is_same_type_mov(src0
) &&
1178 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1179 base_lo
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
));
1180 base_hi
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
) + 1);
1182 base_lo
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
, 4));
1183 base_hi
= create_uniform_indirect(ctx
, ubo
+ 1, get_addr(ctx
, src0
, 4));
1186 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
1189 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1191 off
+= const_offset
->u32
[0];
1193 /* For load_ubo_indirect, second src is indirect offset: */
1194 src1
= get_src(ctx
, &intr
->src
[1])[0];
1196 /* and add offset to addr: */
1197 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1200 /* if offset is to large to encode in the ldg, split it out: */
1201 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1202 /* split out the minimal amount to improve the odds that
1203 * cp can fit the immediate in the add.s instruction:
1205 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1206 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1211 struct ir3_instruction
*carry
;
1213 /* handle 32b rollover, ie:
1214 * if (addr < base_lo)
1217 carry
= ir3_CMPS_U(b
, addr
, 0, base_lo
, 0);
1218 carry
->cat2
.condition
= IR3_COND_LT
;
1219 base_hi
= ir3_ADD_S(b
, base_hi
, 0, carry
, 0);
1221 addr
= create_collect(b
, (struct ir3_instruction
*[]){ addr
, base_hi
}, 2);
1224 for (int i
= 0; i
< intr
->num_components
; i
++) {
1225 struct ir3_instruction
*load
=
1226 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1227 load
->cat6
.type
= TYPE_U32
;
1228 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
1234 mark_read(struct ir3_context
*ctx
, struct ir3_instruction
*instr
)
1236 instr
->regs
[0]->instr
= ctx
->last_write
;
1237 instr
->regs
[0]->flags
|= IR3_REG_SSA
;
1238 ctx
->last_access
= instr
;
1242 mark_write(struct ir3_context
*ctx
, struct ir3_instruction
*instr
)
1244 instr
->regs
[0]->instr
= ctx
->last_access
;
1245 instr
->regs
[0]->flags
|= IR3_REG_SSA
;
1246 ctx
->last_write
= ctx
->last_access
= instr
;
1249 /* src[] = { buffer_index, offset }. No const_index */
1251 emit_intrinsic_load_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1252 struct ir3_instruction
**dst
)
1254 struct ir3_block
*b
= ctx
->block
;
1255 struct ir3_instruction
*ldgb
, *src0
, *src1
, *offset
;
1256 nir_const_value
*const_offset
;
1258 /* can this be non-const buffer_index? how do we handle that? */
1259 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1260 compile_assert(ctx
, const_offset
);
1262 offset
= get_src(ctx
, &intr
->src
[1])[0];
1264 /* src0 is uvec2(offset*4, 0), src1 is offset.. nir already *= 4: */
1265 src0
= create_collect(b
, (struct ir3_instruction
*[]){
1269 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1271 ldgb
= ir3_LDGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1273 ldgb
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1274 ldgb
->cat6
.iim_val
= intr
->num_components
;
1276 ldgb
->cat6
.type
= TYPE_U32
;
1277 mark_read(ctx
, ldgb
);
1279 split_dest(b
, dst
, ldgb
, 0, intr
->num_components
);
1282 /* src[] = { value, block_index, offset }. const_index[] = { write_mask } */
1284 emit_intrinsic_store_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1286 struct ir3_block
*b
= ctx
->block
;
1287 struct ir3_instruction
*stgb
, *src0
, *src1
, *src2
, *offset
;
1288 nir_const_value
*const_offset
;
1289 /* TODO handle wrmask properly, see _store_shared().. but I think
1290 * it is more a PITA than that, since blob ends up loading the
1291 * masked components and writing them back out.
1293 unsigned wrmask
= intr
->const_index
[0];
1294 unsigned ncomp
= ffs(~wrmask
) - 1;
1296 /* can this be non-const buffer_index? how do we handle that? */
1297 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1298 compile_assert(ctx
, const_offset
);
1300 offset
= get_src(ctx
, &intr
->src
[2])[0];
1302 /* src0 is value, src1 is offset, src2 is uvec2(offset*4, 0)..
1305 src0
= create_collect(b
, get_src(ctx
, &intr
->src
[0]), ncomp
);
1306 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1307 src2
= create_collect(b
, (struct ir3_instruction
*[]){
1312 stgb
= ir3_STGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1313 src0
, 0, src1
, 0, src2
, 0);
1314 stgb
->cat6
.iim_val
= ncomp
;
1316 stgb
->cat6
.type
= TYPE_U32
;
1317 mark_write(ctx
, stgb
);
1319 array_insert(b
, b
->keeps
, stgb
);
1322 /* src[] = { block_index } */
1324 emit_intrinsic_ssbo_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1325 struct ir3_instruction
**dst
)
1327 /* SSBO size stored as a const starting at ssbo_sizes: */
1328 unsigned blk_idx
= nir_src_as_const_value(intr
->src
[0])->u32
[0];
1329 unsigned idx
= regid(ctx
->so
->constbase
.ssbo_sizes
, 0) +
1330 ctx
->so
->const_layout
.ssbo_size
.off
[blk_idx
];
1332 debug_assert(ctx
->so
->const_layout
.ssbo_size
.mask
& (1 << blk_idx
));
1334 dst
[0] = create_uniform(ctx
, idx
);
1338 * SSBO atomic intrinsics
1340 * All of the SSBO atomic memory operations read a value from memory,
1341 * compute a new value using one of the operations below, write the new
1342 * value to memory, and return the original value read.
1344 * All operations take 3 sources except CompSwap that takes 4. These
1345 * sources represent:
1347 * 0: The SSBO buffer index.
1348 * 1: The offset into the SSBO buffer of the variable that the atomic
1349 * operation will operate on.
1350 * 2: The data parameter to the atomic function (i.e. the value to add
1351 * in ssbo_atomic_add, etc).
1352 * 3: For CompSwap only: the second data parameter.
1354 static struct ir3_instruction
*
1355 emit_intrinsic_atomic_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1357 struct ir3_block
*b
= ctx
->block
;
1358 struct ir3_instruction
*atomic
, *ssbo
, *src0
, *src1
, *src2
, *offset
;
1359 nir_const_value
*const_offset
;
1360 type_t type
= TYPE_U32
;
1362 /* can this be non-const buffer_index? how do we handle that? */
1363 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1364 compile_assert(ctx
, const_offset
);
1365 ssbo
= create_immed(b
, const_offset
->u32
[0]);
1367 offset
= get_src(ctx
, &intr
->src
[1])[0];
1369 /* src0 is data (or uvec2(data, compare))
1371 * src2 is uvec2(offset*4, 0) (appears to be 64b byte offset)
1373 * Note that nir already multiplies the offset by four
1375 src0
= get_src(ctx
, &intr
->src
[2])[0];
1376 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1377 src2
= create_collect(b
, (struct ir3_instruction
*[]){
1382 switch (intr
->intrinsic
) {
1383 case nir_intrinsic_ssbo_atomic_add
:
1384 atomic
= ir3_ATOMIC_ADD_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1386 case nir_intrinsic_ssbo_atomic_imin
:
1387 atomic
= ir3_ATOMIC_MIN_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1390 case nir_intrinsic_ssbo_atomic_umin
:
1391 atomic
= ir3_ATOMIC_MIN_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1393 case nir_intrinsic_ssbo_atomic_imax
:
1394 atomic
= ir3_ATOMIC_MAX_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1397 case nir_intrinsic_ssbo_atomic_umax
:
1398 atomic
= ir3_ATOMIC_MAX_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1400 case nir_intrinsic_ssbo_atomic_and
:
1401 atomic
= ir3_ATOMIC_AND_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1403 case nir_intrinsic_ssbo_atomic_or
:
1404 atomic
= ir3_ATOMIC_OR_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1406 case nir_intrinsic_ssbo_atomic_xor
:
1407 atomic
= ir3_ATOMIC_XOR_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1409 case nir_intrinsic_ssbo_atomic_exchange
:
1410 atomic
= ir3_ATOMIC_XCHG_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1412 case nir_intrinsic_ssbo_atomic_comp_swap
:
1413 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
1414 src0
= create_collect(b
, (struct ir3_instruction
*[]){
1416 get_src(ctx
, &intr
->src
[3])[0],
1418 atomic
= ir3_ATOMIC_CMPXCHG_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1424 atomic
->cat6
.iim_val
= 1;
1426 atomic
->cat6
.type
= type
;
1427 mark_write(ctx
, atomic
);
1429 /* even if nothing consume the result, we can't DCE the instruction: */
1430 array_insert(b
, b
->keeps
, atomic
);
1436 emit_intrinsic_barrier(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1438 struct ir3_block
*b
= ctx
->block
;
1439 struct ir3_instruction
*barrier
;
1441 switch (intr
->intrinsic
) {
1442 case nir_intrinsic_barrier
:
1443 barrier
= ir3_BAR(b
);
1444 barrier
->cat7
.g
= true;
1445 barrier
->cat7
.l
= true;
1446 barrier
->flags
= IR3_INSTR_SS
| IR3_INSTR_SY
;
1448 case nir_intrinsic_memory_barrier
:
1449 case nir_intrinsic_memory_barrier_atomic_counter
:
1450 case nir_intrinsic_memory_barrier_buffer
:
1451 barrier
= ir3_FENCE(b
);
1452 barrier
->cat7
.g
= true;
1453 barrier
->cat7
.r
= true;
1454 barrier
->cat7
.w
= true;
1456 case nir_intrinsic_group_memory_barrier
:
1457 case nir_intrinsic_memory_barrier_image
:
1458 case nir_intrinsic_memory_barrier_shared
:
1459 barrier
= ir3_FENCE(b
);
1460 barrier
->cat7
.g
= true;
1461 barrier
->cat7
.l
= true;
1462 barrier
->cat7
.r
= true;
1463 barrier
->cat7
.w
= true;
1469 /* make sure barrier doesn't get DCE'd */
1470 array_insert(b
, b
->keeps
, barrier
);
1473 static void add_sysval_input_compmask(struct ir3_context
*ctx
,
1474 gl_system_value slot
, unsigned compmask
,
1475 struct ir3_instruction
*instr
)
1477 struct ir3_shader_variant
*so
= ctx
->so
;
1478 unsigned r
= regid(so
->inputs_count
, 0);
1479 unsigned n
= so
->inputs_count
++;
1481 so
->inputs
[n
].sysval
= true;
1482 so
->inputs
[n
].slot
= slot
;
1483 so
->inputs
[n
].compmask
= compmask
;
1484 so
->inputs
[n
].regid
= r
;
1485 so
->inputs
[n
].interpolate
= INTERP_MODE_FLAT
;
1488 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
1489 ctx
->ir
->inputs
[r
] = instr
;
1492 static void add_sysval_input(struct ir3_context
*ctx
, gl_system_value slot
,
1493 struct ir3_instruction
*instr
)
1495 add_sysval_input_compmask(ctx
, slot
, 0x1, instr
);
1499 emit_intrinsic(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1501 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1502 struct ir3_instruction
**dst
;
1503 struct ir3_instruction
* const *src
;
1504 struct ir3_block
*b
= ctx
->block
;
1505 nir_const_value
*const_offset
;
1508 if (info
->has_dest
) {
1510 if (info
->dest_components
)
1511 n
= info
->dest_components
;
1513 n
= intr
->num_components
;
1514 dst
= get_dst(ctx
, &intr
->dest
, n
);
1519 switch (intr
->intrinsic
) {
1520 case nir_intrinsic_load_uniform
:
1521 idx
= nir_intrinsic_base(intr
);
1522 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1524 idx
+= const_offset
->u32
[0];
1525 for (int i
= 0; i
< intr
->num_components
; i
++) {
1526 unsigned n
= idx
* 4 + i
;
1527 dst
[i
] = create_uniform(ctx
, n
);
1530 src
= get_src(ctx
, &intr
->src
[0]);
1531 for (int i
= 0; i
< intr
->num_components
; i
++) {
1532 int n
= idx
* 4 + i
;
1533 dst
[i
] = create_uniform_indirect(ctx
, n
,
1534 get_addr(ctx
, src
[0], 4));
1536 /* NOTE: if relative addressing is used, we set
1537 * constlen in the compiler (to worst-case value)
1538 * since we don't know in the assembler what the max
1539 * addr reg value can be:
1541 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
1544 case nir_intrinsic_load_ubo
:
1545 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1547 case nir_intrinsic_load_input
:
1548 idx
= nir_intrinsic_base(intr
);
1549 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1551 idx
+= const_offset
->u32
[0];
1552 for (int i
= 0; i
< intr
->num_components
; i
++) {
1553 unsigned n
= idx
* 4 + i
;
1554 dst
[i
] = ctx
->ir
->inputs
[n
];
1557 src
= get_src(ctx
, &intr
->src
[0]);
1558 struct ir3_instruction
*collect
=
1559 create_collect(b
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
1560 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0], 4);
1561 for (int i
= 0; i
< intr
->num_components
; i
++) {
1562 unsigned n
= idx
* 4 + i
;
1563 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
1568 case nir_intrinsic_load_ssbo
:
1569 emit_intrinsic_load_ssbo(ctx
, intr
, dst
);
1571 case nir_intrinsic_store_ssbo
:
1572 emit_intrinsic_store_ssbo(ctx
, intr
);
1574 case nir_intrinsic_get_buffer_size
:
1575 emit_intrinsic_ssbo_size(ctx
, intr
, dst
);
1577 case nir_intrinsic_ssbo_atomic_add
:
1578 case nir_intrinsic_ssbo_atomic_imin
:
1579 case nir_intrinsic_ssbo_atomic_umin
:
1580 case nir_intrinsic_ssbo_atomic_imax
:
1581 case nir_intrinsic_ssbo_atomic_umax
:
1582 case nir_intrinsic_ssbo_atomic_and
:
1583 case nir_intrinsic_ssbo_atomic_or
:
1584 case nir_intrinsic_ssbo_atomic_xor
:
1585 case nir_intrinsic_ssbo_atomic_exchange
:
1586 case nir_intrinsic_ssbo_atomic_comp_swap
:
1587 dst
[0] = emit_intrinsic_atomic_ssbo(ctx
, intr
);
1589 case nir_intrinsic_barrier
:
1590 case nir_intrinsic_memory_barrier
:
1591 case nir_intrinsic_group_memory_barrier
:
1592 case nir_intrinsic_memory_barrier_atomic_counter
:
1593 case nir_intrinsic_memory_barrier_buffer
:
1594 case nir_intrinsic_memory_barrier_image
:
1595 case nir_intrinsic_memory_barrier_shared
:
1596 emit_intrinsic_barrier(ctx
, intr
);
1597 /* note that blk ptr no longer valid, make that obvious: */
1600 case nir_intrinsic_store_output
:
1601 idx
= nir_intrinsic_base(intr
);
1602 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1603 compile_assert(ctx
, const_offset
!= NULL
);
1604 idx
+= const_offset
->u32
[0];
1606 src
= get_src(ctx
, &intr
->src
[0]);
1607 for (int i
= 0; i
< intr
->num_components
; i
++) {
1608 unsigned n
= idx
* 4 + i
;
1609 ctx
->ir
->outputs
[n
] = src
[i
];
1612 case nir_intrinsic_load_base_vertex
:
1613 if (!ctx
->basevertex
) {
1614 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
1615 add_sysval_input(ctx
, SYSTEM_VALUE_BASE_VERTEX
,
1618 dst
[0] = ctx
->basevertex
;
1620 case nir_intrinsic_load_vertex_id_zero_base
:
1621 case nir_intrinsic_load_vertex_id
:
1622 if (!ctx
->vertex_id
) {
1623 gl_system_value sv
= (intr
->intrinsic
== nir_intrinsic_load_vertex_id
) ?
1624 SYSTEM_VALUE_VERTEX_ID
: SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
;
1625 ctx
->vertex_id
= create_input(b
, 0);
1626 add_sysval_input(ctx
, sv
, ctx
->vertex_id
);
1628 dst
[0] = ctx
->vertex_id
;
1630 case nir_intrinsic_load_instance_id
:
1631 if (!ctx
->instance_id
) {
1632 ctx
->instance_id
= create_input(b
, 0);
1633 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
1636 dst
[0] = ctx
->instance_id
;
1638 case nir_intrinsic_load_user_clip_plane
:
1639 idx
= nir_intrinsic_ucp_id(intr
);
1640 for (int i
= 0; i
< intr
->num_components
; i
++) {
1641 unsigned n
= idx
* 4 + i
;
1642 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
1645 case nir_intrinsic_load_front_face
:
1646 if (!ctx
->frag_face
) {
1647 ctx
->so
->frag_face
= true;
1648 ctx
->frag_face
= create_input(b
, 0);
1649 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
1651 /* for fragface, we get -1 for back and 0 for front. However this is
1652 * the inverse of what nir expects (where ~0 is true).
1654 dst
[0] = ir3_COV(b
, ctx
->frag_face
, TYPE_S16
, TYPE_S32
);
1655 dst
[0] = ir3_NOT_B(b
, dst
[0], 0);
1657 case nir_intrinsic_load_local_invocation_id
:
1658 if (!ctx
->local_invocation_id
) {
1659 ctx
->local_invocation_id
= create_input_compmask(b
, 0, 0x7);
1660 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
,
1661 0x7, ctx
->local_invocation_id
);
1663 split_dest(b
, dst
, ctx
->local_invocation_id
, 0, 3);
1665 case nir_intrinsic_load_work_group_id
:
1666 if (!ctx
->work_group_id
) {
1667 ctx
->work_group_id
= create_input_compmask(b
, 0, 0x7);
1668 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_WORK_GROUP_ID
,
1669 0x7, ctx
->work_group_id
);
1670 ctx
->work_group_id
->regs
[0]->flags
|= IR3_REG_HIGH
;
1672 split_dest(b
, dst
, ctx
->work_group_id
, 0, 3);
1674 case nir_intrinsic_load_num_work_groups
:
1675 for (int i
= 0; i
< intr
->num_components
; i
++) {
1676 dst
[i
] = create_driver_param(ctx
, IR3_DP_NUM_WORK_GROUPS_X
+ i
);
1679 case nir_intrinsic_discard_if
:
1680 case nir_intrinsic_discard
: {
1681 struct ir3_instruction
*cond
, *kill
;
1683 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
1684 /* conditional discard: */
1685 src
= get_src(ctx
, &intr
->src
[0]);
1686 cond
= ir3_b2n(b
, src
[0]);
1688 /* unconditional discard: */
1689 cond
= create_immed(b
, 1);
1692 /* NOTE: only cmps.*.* can write p0.x: */
1693 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1694 cond
->cat2
.condition
= IR3_COND_NE
;
1696 /* condition always goes in predicate register: */
1697 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1699 kill
= ir3_KILL(b
, cond
, 0);
1700 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
1702 array_insert(b
, b
->keeps
, kill
);
1703 ctx
->so
->has_kill
= true;
1708 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
1709 nir_intrinsic_infos
[intr
->intrinsic
].name
);
1714 put_dst(ctx
, &intr
->dest
);
1718 emit_load_const(struct ir3_context
*ctx
, nir_load_const_instr
*instr
)
1720 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
1721 instr
->def
.num_components
);
1722 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1723 dst
[i
] = create_immed(ctx
->block
, instr
->value
.u32
[i
]);
1727 emit_undef(struct ir3_context
*ctx
, nir_ssa_undef_instr
*undef
)
1729 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
1730 undef
->def
.num_components
);
1731 /* backend doesn't want undefined instructions, so just plug
1734 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
1735 dst
[i
] = create_immed(ctx
->block
, fui(0.0));
1739 * texture fetch/sample instructions:
1743 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
1745 unsigned coords
, flags
= 0;
1747 /* note: would use tex->coord_components.. except txs.. also,
1748 * since array index goes after shadow ref, we don't want to
1751 switch (tex
->sampler_dim
) {
1752 case GLSL_SAMPLER_DIM_1D
:
1753 case GLSL_SAMPLER_DIM_BUF
:
1756 case GLSL_SAMPLER_DIM_2D
:
1757 case GLSL_SAMPLER_DIM_RECT
:
1758 case GLSL_SAMPLER_DIM_EXTERNAL
:
1759 case GLSL_SAMPLER_DIM_MS
:
1762 case GLSL_SAMPLER_DIM_3D
:
1763 case GLSL_SAMPLER_DIM_CUBE
:
1765 flags
|= IR3_INSTR_3D
;
1768 unreachable("bad sampler_dim");
1771 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1772 flags
|= IR3_INSTR_S
;
1774 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
1775 flags
|= IR3_INSTR_A
;
1782 emit_tex(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
1784 struct ir3_block
*b
= ctx
->block
;
1785 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
1786 struct ir3_instruction
* const *coord
, * const *off
, * const *ddx
, * const *ddy
;
1787 struct ir3_instruction
*lod
, *compare
, *proj
;
1788 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
1789 unsigned i
, coords
, flags
;
1790 unsigned nsrc0
= 0, nsrc1
= 0;
1794 coord
= off
= ddx
= ddy
= NULL
;
1795 lod
= proj
= compare
= NULL
;
1797 /* TODO: might just be one component for gathers? */
1798 dst
= get_dst(ctx
, &tex
->dest
, 4);
1800 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
1801 switch (tex
->src
[i
].src_type
) {
1802 case nir_tex_src_coord
:
1803 coord
= get_src(ctx
, &tex
->src
[i
].src
);
1805 case nir_tex_src_bias
:
1806 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1809 case nir_tex_src_lod
:
1810 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1813 case nir_tex_src_comparator
: /* shadow comparator */
1814 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1816 case nir_tex_src_projector
:
1817 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1820 case nir_tex_src_offset
:
1821 off
= get_src(ctx
, &tex
->src
[i
].src
);
1824 case nir_tex_src_ddx
:
1825 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
1827 case nir_tex_src_ddy
:
1828 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
1831 compile_error(ctx
, "Unhandled NIR tex src type: %d\n",
1832 tex
->src
[i
].src_type
);
1838 case nir_texop_tex
: opc
= OPC_SAM
; break;
1839 case nir_texop_txb
: opc
= OPC_SAMB
; break;
1840 case nir_texop_txl
: opc
= OPC_SAML
; break;
1841 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
1842 case nir_texop_txf
: opc
= OPC_ISAML
; break;
1843 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
1844 case nir_texop_txf_ms
:
1847 case nir_texop_query_levels
:
1848 case nir_texop_texture_samples
:
1849 case nir_texop_samples_identical
:
1850 case nir_texop_txf_ms_mcs
:
1851 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
1855 tex_info(tex
, &flags
, &coords
);
1858 * lay out the first argument in the proper order:
1859 * - actual coordinates first
1860 * - shadow reference
1863 * - starting at offset 4, dpdx.xy, dpdy.xy
1865 * bias/lod go into the second arg
1868 /* insert tex coords: */
1869 for (i
= 0; i
< coords
; i
++)
1874 /* scale up integer coords for TXF based on the LOD */
1875 if (ctx
->unminify_coords
&& (opc
== OPC_ISAML
)) {
1877 for (i
= 0; i
< coords
; i
++)
1878 src0
[i
] = ir3_SHL_B(b
, src0
[i
], 0, lod
, 0);
1882 /* hw doesn't do 1d, so we treat it as 2d with
1883 * height of 1, and patch up the y coord.
1884 * TODO: y coord should be (int)0 in some cases..
1886 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
1889 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1890 src0
[nsrc0
++] = compare
;
1892 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
) {
1893 struct ir3_instruction
*idx
= coord
[coords
];
1895 /* the array coord for cube arrays needs 0.5 added to it */
1896 if (ctx
->array_index_add_half
&& (opc
!= OPC_ISAML
))
1897 idx
= ir3_ADD_F(b
, idx
, 0, create_immed(b
, fui(0.5)), 0);
1899 src0
[nsrc0
++] = idx
;
1903 src0
[nsrc0
++] = proj
;
1904 flags
|= IR3_INSTR_P
;
1907 /* pad to 4, then ddx/ddy: */
1908 if (tex
->op
== nir_texop_txd
) {
1910 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1911 for (i
= 0; i
< coords
; i
++)
1912 src0
[nsrc0
++] = ddx
[i
];
1914 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1915 for (i
= 0; i
< coords
; i
++)
1916 src0
[nsrc0
++] = ddy
[i
];
1918 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1922 * second argument (if applicable):
1927 if (has_off
| has_lod
| has_bias
) {
1929 for (i
= 0; i
< coords
; i
++)
1930 src1
[nsrc1
++] = off
[i
];
1932 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
1933 flags
|= IR3_INSTR_O
;
1936 if (has_lod
| has_bias
)
1937 src1
[nsrc1
++] = lod
;
1940 switch (tex
->dest_type
) {
1941 case nir_type_invalid
:
1942 case nir_type_float
:
1953 unreachable("bad dest_type");
1956 if (opc
== OPC_GETLOD
)
1959 unsigned tex_idx
= tex
->texture_index
;
1961 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex_idx
);
1963 struct ir3_instruction
*col0
= create_collect(b
, src0
, nsrc0
);
1964 struct ir3_instruction
*col1
= create_collect(b
, src1
, nsrc1
);
1966 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
, flags
,
1967 tex_idx
, tex_idx
, col0
, col1
);
1969 if ((ctx
->astc_srgb
& (1 << tex_idx
)) && !nir_tex_instr_is_query(tex
)) {
1970 /* only need first 3 components: */
1971 sam
->regs
[0]->wrmask
= 0x7;
1972 split_dest(b
, dst
, sam
, 0, 3);
1974 /* we need to sample the alpha separately with a non-ASTC
1977 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_W
, flags
,
1978 tex_idx
, tex_idx
, col0
, col1
);
1980 array_insert(ctx
->ir
, ctx
->ir
->astc_srgb
, sam
);
1982 /* fixup .w component: */
1983 split_dest(b
, &dst
[3], sam
, 3, 1);
1985 /* normal (non-workaround) case: */
1986 split_dest(b
, dst
, sam
, 0, 4);
1989 /* GETLOD returns results in 4.8 fixed point */
1990 if (opc
== OPC_GETLOD
) {
1991 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
1993 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
1994 for (i
= 0; i
< 2; i
++) {
1995 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_U32
, TYPE_F32
), 0,
2000 put_dst(ctx
, &tex
->dest
);
2004 emit_tex_query_levels(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2006 struct ir3_block
*b
= ctx
->block
;
2007 struct ir3_instruction
**dst
, *sam
;
2009 dst
= get_dst(ctx
, &tex
->dest
, 1);
2011 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
2012 tex
->texture_index
, tex
->texture_index
, NULL
, NULL
);
2014 /* even though there is only one component, since it ends
2015 * up in .z rather than .x, we need a split_dest()
2017 split_dest(b
, dst
, sam
, 0, 3);
2019 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2020 * the value in TEX_CONST_0 is zero-based.
2022 if (ctx
->levels_add_one
)
2023 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
2025 put_dst(ctx
, &tex
->dest
);
2029 emit_tex_txs(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2031 struct ir3_block
*b
= ctx
->block
;
2032 struct ir3_instruction
**dst
, *sam
;
2033 struct ir3_instruction
*lod
;
2034 unsigned flags
, coords
;
2036 tex_info(tex
, &flags
, &coords
);
2038 /* Actually we want the number of dimensions, not coordinates. This
2039 * distinction only matters for cubes.
2041 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2044 dst
= get_dst(ctx
, &tex
->dest
, 4);
2046 compile_assert(ctx
, tex
->num_srcs
== 1);
2047 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
2049 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
2051 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
2052 tex
->texture_index
, tex
->texture_index
, lod
, NULL
);
2054 split_dest(b
, dst
, sam
, 0, 4);
2056 /* Array size actually ends up in .w rather than .z. This doesn't
2057 * matter for miplevel 0, but for higher mips the value in z is
2058 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2059 * returned, which means that we have to add 1 to it for arrays.
2061 if (tex
->is_array
) {
2062 if (ctx
->levels_add_one
) {
2063 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
2065 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
2069 put_dst(ctx
, &tex
->dest
);
2073 emit_phi(struct ir3_context
*ctx
, nir_phi_instr
*nphi
)
2075 struct ir3_instruction
*phi
, **dst
;
2077 /* NOTE: phi's should be lowered to scalar at this point */
2078 compile_assert(ctx
, nphi
->dest
.ssa
.num_components
== 1);
2080 dst
= get_dst(ctx
, &nphi
->dest
, 1);
2082 phi
= ir3_instr_create2(ctx
->block
, OPC_META_PHI
,
2083 1 + exec_list_length(&nphi
->srcs
));
2084 ir3_reg_create(phi
, 0, 0); /* dst */
2085 phi
->phi
.nphi
= nphi
;
2089 put_dst(ctx
, &nphi
->dest
);
2092 /* phi instructions are left partially constructed. We don't resolve
2093 * their srcs until the end of the block, since (eg. loops) one of
2094 * the phi's srcs might be defined after the phi due to back edges in
2098 resolve_phis(struct ir3_context
*ctx
, struct ir3_block
*block
)
2100 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
2101 nir_phi_instr
*nphi
;
2103 /* phi's only come at start of block: */
2104 if (instr
->opc
!= OPC_META_PHI
)
2107 if (!instr
->phi
.nphi
)
2110 nphi
= instr
->phi
.nphi
;
2111 instr
->phi
.nphi
= NULL
;
2113 foreach_list_typed(nir_phi_src
, nsrc
, node
, &nphi
->srcs
) {
2114 struct ir3_instruction
*src
= get_src(ctx
, &nsrc
->src
)[0];
2116 /* NOTE: src might not be in the same block as it comes from
2117 * according to the phi.. but in the end the backend assumes
2118 * it will be able to assign the same register to each (which
2119 * only works if it is assigned in the src block), so insert
2120 * an extra mov to make sure the phi src is assigned in the
2121 * block it comes from:
2123 src
= ir3_MOV(get_block(ctx
, nsrc
->pred
), src
, TYPE_U32
);
2125 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
2131 emit_jump(struct ir3_context
*ctx
, nir_jump_instr
*jump
)
2133 switch (jump
->type
) {
2134 case nir_jump_break
:
2135 case nir_jump_continue
:
2136 /* I *think* we can simply just ignore this, and use the
2137 * successor block link to figure out where we need to
2138 * jump to for break/continue
2142 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
2148 emit_instr(struct ir3_context
*ctx
, nir_instr
*instr
)
2150 switch (instr
->type
) {
2151 case nir_instr_type_alu
:
2152 emit_alu(ctx
, nir_instr_as_alu(instr
));
2154 case nir_instr_type_intrinsic
:
2155 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2157 case nir_instr_type_load_const
:
2158 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2160 case nir_instr_type_ssa_undef
:
2161 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
2163 case nir_instr_type_tex
: {
2164 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
2165 /* couple tex instructions get special-cased:
2169 emit_tex_txs(ctx
, tex
);
2171 case nir_texop_query_levels
:
2172 emit_tex_query_levels(ctx
, tex
);
2180 case nir_instr_type_phi
:
2181 emit_phi(ctx
, nir_instr_as_phi(instr
));
2183 case nir_instr_type_jump
:
2184 emit_jump(ctx
, nir_instr_as_jump(instr
));
2186 case nir_instr_type_call
:
2187 case nir_instr_type_parallel_copy
:
2188 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
2193 static struct ir3_block
*
2194 get_block(struct ir3_context
*ctx
, nir_block
*nblock
)
2196 struct ir3_block
*block
;
2197 struct hash_entry
*entry
;
2198 entry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
2202 block
= ir3_block_create(ctx
->ir
);
2203 block
->nblock
= nblock
;
2204 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
2210 emit_block(struct ir3_context
*ctx
, nir_block
*nblock
)
2212 struct ir3_block
*block
= get_block(ctx
, nblock
);
2214 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
2215 if (nblock
->successors
[i
]) {
2216 block
->successors
[i
] =
2217 get_block(ctx
, nblock
->successors
[i
]);
2222 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
2224 /* re-emit addr register in each block if needed: */
2225 for (int i
= 0; i
< ARRAY_SIZE(ctx
->addr_ht
); i
++) {
2226 _mesa_hash_table_destroy(ctx
->addr_ht
[i
], NULL
);
2227 ctx
->addr_ht
[i
] = NULL
;
2230 nir_foreach_instr(instr
, nblock
) {
2231 emit_instr(ctx
, instr
);
2237 static void emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
);
2240 emit_if(struct ir3_context
*ctx
, nir_if
*nif
)
2242 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
2244 ctx
->block
->condition
=
2245 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
2247 emit_cf_list(ctx
, &nif
->then_list
);
2248 emit_cf_list(ctx
, &nif
->else_list
);
2252 emit_loop(struct ir3_context
*ctx
, nir_loop
*nloop
)
2254 emit_cf_list(ctx
, &nloop
->body
);
2258 emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
)
2260 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2261 switch (node
->type
) {
2262 case nir_cf_node_block
:
2263 emit_block(ctx
, nir_cf_node_as_block(node
));
2265 case nir_cf_node_if
:
2266 emit_if(ctx
, nir_cf_node_as_if(node
));
2268 case nir_cf_node_loop
:
2269 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2271 case nir_cf_node_function
:
2272 compile_error(ctx
, "TODO\n");
2278 /* emit stream-out code. At this point, the current block is the original
2279 * (nir) end block, and nir ensures that all flow control paths terminate
2280 * into the end block. We re-purpose the original end block to generate
2281 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2282 * block holding stream-out write instructions, followed by the new end
2286 * p0.x = (vtxcnt < maxvtxcnt)
2287 * // succs: blockStreamOut, blockNewEnd
2290 * ... stream-out instructions ...
2291 * // succs: blockNewEnd
2297 emit_stream_out(struct ir3_context
*ctx
)
2299 struct ir3_shader_variant
*v
= ctx
->so
;
2300 struct ir3
*ir
= ctx
->ir
;
2301 struct pipe_stream_output_info
*strmout
=
2302 &ctx
->so
->shader
->stream_output
;
2303 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
2304 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
2305 struct ir3_instruction
*bases
[PIPE_MAX_SO_BUFFERS
];
2307 /* create vtxcnt input in input block at top of shader,
2308 * so that it is seen as live over the entire duration
2311 vtxcnt
= create_input(ctx
->in_block
, 0);
2312 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
2314 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
2316 /* at this point, we are at the original 'end' block,
2317 * re-purpose this block to stream-out condition, then
2318 * append stream-out block and new-end block
2320 orig_end_block
= ctx
->block
;
2322 stream_out_block
= ir3_block_create(ir
);
2323 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
2325 new_end_block
= ir3_block_create(ir
);
2326 list_addtail(&new_end_block
->node
, &ir
->block_list
);
2328 orig_end_block
->successors
[0] = stream_out_block
;
2329 orig_end_block
->successors
[1] = new_end_block
;
2330 stream_out_block
->successors
[0] = new_end_block
;
2332 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2333 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
2334 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2335 cond
->cat2
.condition
= IR3_COND_LT
;
2337 /* condition goes on previous block to the conditional,
2338 * since it is used to pick which of the two successor
2341 orig_end_block
->condition
= cond
;
2343 /* switch to stream_out_block to generate the stream-out
2346 ctx
->block
= stream_out_block
;
2348 /* Calculate base addresses based on vtxcnt. Instructions
2349 * generated for bases not used in following loop will be
2350 * stripped out in the backend.
2352 for (unsigned i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
2353 unsigned stride
= strmout
->stride
[i
];
2354 struct ir3_instruction
*base
, *off
;
2356 base
= create_uniform(ctx
, regid(v
->constbase
.tfbo
, i
));
2358 /* 24-bit should be enough: */
2359 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
2360 create_immed(ctx
->block
, stride
* 4), 0);
2362 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
2365 /* Generate the per-output store instructions: */
2366 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
2367 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
2368 unsigned c
= j
+ strmout
->output
[i
].start_component
;
2369 struct ir3_instruction
*base
, *out
, *stg
;
2371 base
= bases
[strmout
->output
[i
].output_buffer
];
2372 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
2374 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
2375 create_immed(ctx
->block
, 1), 0);
2376 stg
->cat6
.type
= TYPE_U32
;
2377 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
2379 array_insert(ctx
->block
, ctx
->block
->keeps
, stg
);
2383 /* and finally switch to the new_end_block: */
2384 ctx
->block
= new_end_block
;
2388 emit_function(struct ir3_context
*ctx
, nir_function_impl
*impl
)
2390 nir_metadata_require(impl
, nir_metadata_block_index
);
2392 emit_cf_list(ctx
, &impl
->body
);
2393 emit_block(ctx
, impl
->end_block
);
2395 /* at this point, we should have a single empty block,
2396 * into which we emit the 'end' instruction.
2398 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
2400 /* If stream-out (aka transform-feedback) enabled, emit the
2401 * stream-out instructions, followed by a new empty block (into
2402 * which the 'end' instruction lands).
2404 * NOTE: it is done in this order, rather than inserting before
2405 * we emit end_block, because NIR guarantees that all blocks
2406 * flow into end_block, and that end_block has no successors.
2407 * So by re-purposing end_block as the first block of stream-
2408 * out, we guarantee that all exit paths flow into the stream-
2411 if ((ctx
->compiler
->gpu_id
< 500) &&
2412 (ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
2413 !ctx
->so
->key
.binning_pass
) {
2414 debug_assert(ctx
->so
->type
== SHADER_VERTEX
);
2415 emit_stream_out(ctx
);
2418 ir3_END(ctx
->block
);
2422 setup_input(struct ir3_context
*ctx
, nir_variable
*in
)
2424 struct ir3_shader_variant
*so
= ctx
->so
;
2425 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
2426 unsigned ncomp
= glsl_get_components(in
->type
);
2427 unsigned n
= in
->data
.driver_location
;
2428 unsigned slot
= in
->data
.location
;
2430 DBG("; in: slot=%u, len=%ux%u, drvloc=%u",
2431 slot
, array_len
, ncomp
, n
);
2433 /* let's pretend things other than vec4 don't exist: */
2434 ncomp
= MAX2(ncomp
, 4);
2435 compile_assert(ctx
, ncomp
== 4);
2437 so
->inputs
[n
].slot
= slot
;
2438 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
2439 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2440 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
2442 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2443 for (int i
= 0; i
< ncomp
; i
++) {
2444 struct ir3_instruction
*instr
= NULL
;
2445 unsigned idx
= (n
* 4) + i
;
2447 if (slot
== VARYING_SLOT_POS
) {
2448 so
->inputs
[n
].bary
= false;
2449 so
->frag_coord
= true;
2450 instr
= create_frag_coord(ctx
, i
);
2451 } else if (slot
== VARYING_SLOT_PNTC
) {
2452 /* see for example st_get_generic_varying_index().. this is
2453 * maybe a bit mesa/st specific. But we need things to line
2454 * up for this in fdN_program:
2455 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2456 * if (emit->sprite_coord_enable & texmask) {
2460 so
->inputs
[n
].slot
= VARYING_SLOT_VAR8
;
2461 so
->inputs
[n
].bary
= true;
2462 instr
= create_frag_input(ctx
, false);
2464 bool use_ldlv
= false;
2466 /* detect the special case for front/back colors where
2467 * we need to do flat vs smooth shading depending on
2470 if (in
->data
.interpolation
== INTERP_MODE_NONE
) {
2472 case VARYING_SLOT_COL0
:
2473 case VARYING_SLOT_COL1
:
2474 case VARYING_SLOT_BFC0
:
2475 case VARYING_SLOT_BFC1
:
2476 so
->inputs
[n
].rasterflat
= true;
2483 if (ctx
->flat_bypass
) {
2484 if ((so
->inputs
[n
].interpolate
== INTERP_MODE_FLAT
) ||
2485 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
2489 so
->inputs
[n
].bary
= true;
2491 instr
= create_frag_input(ctx
, use_ldlv
);
2494 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
2496 ctx
->ir
->inputs
[idx
] = instr
;
2498 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2499 for (int i
= 0; i
< ncomp
; i
++) {
2500 unsigned idx
= (n
* 4) + i
;
2501 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
2502 ctx
->ir
->inputs
[idx
] = create_input(ctx
->block
, idx
);
2505 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2508 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
2509 so
->total_in
+= ncomp
;
2514 setup_output(struct ir3_context
*ctx
, nir_variable
*out
)
2516 struct ir3_shader_variant
*so
= ctx
->so
;
2517 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
2518 unsigned ncomp
= glsl_get_components(out
->type
);
2519 unsigned n
= out
->data
.driver_location
;
2520 unsigned slot
= out
->data
.location
;
2523 DBG("; out: slot=%u, len=%ux%u, drvloc=%u",
2524 slot
, array_len
, ncomp
, n
);
2526 /* let's pretend things other than vec4 don't exist: */
2527 ncomp
= MAX2(ncomp
, 4);
2528 compile_assert(ctx
, ncomp
== 4);
2530 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2532 case FRAG_RESULT_DEPTH
:
2533 comp
= 2; /* tgsi will write to .z component */
2534 so
->writes_pos
= true;
2536 case FRAG_RESULT_COLOR
:
2540 if (slot
>= FRAG_RESULT_DATA0
)
2542 compile_error(ctx
, "unknown FS output name: %s\n",
2543 gl_frag_result_name(slot
));
2545 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2547 case VARYING_SLOT_POS
:
2548 so
->writes_pos
= true;
2550 case VARYING_SLOT_PSIZ
:
2551 so
->writes_psize
= true;
2553 case VARYING_SLOT_COL0
:
2554 case VARYING_SLOT_COL1
:
2555 case VARYING_SLOT_BFC0
:
2556 case VARYING_SLOT_BFC1
:
2557 case VARYING_SLOT_FOGC
:
2558 case VARYING_SLOT_CLIP_DIST0
:
2559 case VARYING_SLOT_CLIP_DIST1
:
2560 case VARYING_SLOT_CLIP_VERTEX
:
2563 if (slot
>= VARYING_SLOT_VAR0
)
2565 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
2567 compile_error(ctx
, "unknown VS output name: %s\n",
2568 gl_varying_slot_name(slot
));
2571 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2574 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
2576 so
->outputs
[n
].slot
= slot
;
2577 so
->outputs
[n
].regid
= regid(n
, comp
);
2578 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
2580 for (int i
= 0; i
< ncomp
; i
++) {
2581 unsigned idx
= (n
* 4) + i
;
2582 compile_assert(ctx
, idx
< ctx
->ir
->noutputs
);
2583 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
2588 max_drvloc(struct exec_list
*vars
)
2591 nir_foreach_variable(var
, vars
) {
2592 drvloc
= MAX2(drvloc
, (int)var
->data
.driver_location
);
2597 static const unsigned max_sysvals
[SHADER_MAX
] = {
2598 [SHADER_VERTEX
] = 16,
2599 [SHADER_COMPUTE
] = 16, // TODO how many do we actually need?
2603 emit_instructions(struct ir3_context
*ctx
)
2605 unsigned ninputs
, noutputs
;
2606 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
2608 ninputs
= (max_drvloc(&ctx
->s
->inputs
) + 1) * 4;
2609 noutputs
= (max_drvloc(&ctx
->s
->outputs
) + 1) * 4;
2611 /* we need to leave room for sysvals:
2613 ninputs
+= max_sysvals
[ctx
->so
->type
];
2615 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
2617 /* Create inputs in first block: */
2618 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
2619 ctx
->in_block
= ctx
->block
;
2620 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
2622 ninputs
-= max_sysvals
[ctx
->so
->type
];
2624 /* for fragment shader, we have a single input register (usually
2625 * r0.xy) which is used as the base for bary.f varying fetch instrs:
2627 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2628 // TODO maybe a helper for fi since we need it a few places..
2629 struct ir3_instruction
*instr
;
2630 instr
= ir3_instr_create(ctx
->block
, OPC_META_FI
);
2631 ir3_reg_create(instr
, 0, 0);
2632 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.x */
2633 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.y */
2634 ctx
->frag_pos
= instr
;
2638 nir_foreach_variable(var
, &ctx
->s
->inputs
) {
2639 setup_input(ctx
, var
);
2642 /* Setup outputs: */
2643 nir_foreach_variable(var
, &ctx
->s
->outputs
) {
2644 setup_output(ctx
, var
);
2647 /* Setup registers (which should only be arrays): */
2648 nir_foreach_register(reg
, &ctx
->s
->registers
) {
2649 declare_array(ctx
, reg
);
2652 /* NOTE: need to do something more clever when we support >1 fxn */
2653 nir_foreach_register(reg
, &fxn
->registers
) {
2654 declare_array(ctx
, reg
);
2656 /* And emit the body: */
2658 emit_function(ctx
, fxn
);
2660 list_for_each_entry (struct ir3_block
, block
, &ctx
->ir
->block_list
, node
) {
2661 resolve_phis(ctx
, block
);
2665 /* from NIR perspective, we actually have inputs. But most of the "inputs"
2666 * for a fragment shader are just bary.f instructions. The *actual* inputs
2667 * from the hw perspective are the frag_pos and optionally frag_coord and
2671 fixup_frag_inputs(struct ir3_context
*ctx
)
2673 struct ir3_shader_variant
*so
= ctx
->so
;
2674 struct ir3
*ir
= ctx
->ir
;
2675 struct ir3_instruction
**inputs
;
2676 struct ir3_instruction
*instr
;
2681 n
= 4; /* always have frag_pos */
2682 n
+= COND(so
->frag_face
, 4);
2683 n
+= COND(so
->frag_coord
, 4);
2685 inputs
= ir3_alloc(ctx
->ir
, n
* (sizeof(struct ir3_instruction
*)));
2687 if (so
->frag_face
) {
2688 /* this ultimately gets assigned to hr0.x so doesn't conflict
2689 * with frag_coord/frag_pos..
2691 inputs
[ir
->ninputs
++] = ctx
->frag_face
;
2692 ctx
->frag_face
->regs
[0]->num
= 0;
2694 /* remaining channels not used, but let's avoid confusing
2695 * other parts that expect inputs to come in groups of vec4
2697 inputs
[ir
->ninputs
++] = NULL
;
2698 inputs
[ir
->ninputs
++] = NULL
;
2699 inputs
[ir
->ninputs
++] = NULL
;
2702 /* since we don't know where to set the regid for frag_coord,
2703 * we have to use r0.x for it. But we don't want to *always*
2704 * use r1.x for frag_pos as that could increase the register
2705 * footprint on simple shaders:
2707 if (so
->frag_coord
) {
2708 ctx
->frag_coord
[0]->regs
[0]->num
= regid
++;
2709 ctx
->frag_coord
[1]->regs
[0]->num
= regid
++;
2710 ctx
->frag_coord
[2]->regs
[0]->num
= regid
++;
2711 ctx
->frag_coord
[3]->regs
[0]->num
= regid
++;
2713 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[0];
2714 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[1];
2715 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[2];
2716 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[3];
2719 /* we always have frag_pos: */
2720 so
->pos_regid
= regid
;
2723 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2724 instr
->regs
[0]->num
= regid
++;
2725 inputs
[ir
->ninputs
++] = instr
;
2726 ctx
->frag_pos
->regs
[1]->instr
= instr
;
2729 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2730 instr
->regs
[0]->num
= regid
++;
2731 inputs
[ir
->ninputs
++] = instr
;
2732 ctx
->frag_pos
->regs
[2]->instr
= instr
;
2734 ir
->inputs
= inputs
;
2737 /* Fixup tex sampler state for astc/srgb workaround instructions. We
2738 * need to assign the tex state indexes for these after we know the
2742 fixup_astc_srgb(struct ir3_context
*ctx
)
2744 struct ir3_shader_variant
*so
= ctx
->so
;
2745 /* indexed by original tex idx, value is newly assigned alpha sampler
2746 * state tex idx. Zero is invalid since there is at least one sampler
2749 unsigned alt_tex_state
[16] = {0};
2750 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
2753 so
->astc_srgb
.base
= tex_idx
;
2755 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
2756 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
2758 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
2760 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
2761 /* assign new alternate/alpha tex state slot: */
2762 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
2763 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
2764 so
->astc_srgb
.count
++;
2767 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
2772 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
2773 struct ir3_shader_variant
*so
)
2775 struct ir3_context
*ctx
;
2777 struct ir3_instruction
**inputs
;
2778 unsigned i
, j
, actual_in
, inloc
;
2779 int ret
= 0, max_bary
;
2783 ctx
= compile_init(compiler
, so
);
2785 DBG("INIT failed!");
2790 emit_instructions(ctx
);
2793 DBG("EMIT failed!");
2798 ir
= so
->ir
= ctx
->ir
;
2800 /* keep track of the inputs from TGSI perspective.. */
2801 inputs
= ir
->inputs
;
2803 /* but fixup actual inputs for frag shader: */
2804 if (so
->type
== SHADER_FRAGMENT
)
2805 fixup_frag_inputs(ctx
);
2807 /* at this point, for binning pass, throw away unneeded outputs: */
2808 if (so
->key
.binning_pass
) {
2809 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
2810 unsigned slot
= so
->outputs
[i
].slot
;
2812 /* throw away everything but first position/psize */
2813 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
2815 so
->outputs
[j
] = so
->outputs
[i
];
2816 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
2817 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
2818 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
2819 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
2824 so
->outputs_count
= j
;
2825 ir
->noutputs
= j
* 4;
2828 /* if we want half-precision outputs, mark the output registers
2831 if (so
->key
.half_precision
) {
2832 for (i
= 0; i
< ir
->noutputs
; i
++) {
2833 struct ir3_instruction
*out
= ir
->outputs
[i
];
2838 /* if frag shader writes z, that needs to be full precision: */
2839 if (so
->outputs
[i
/4].slot
== FRAG_RESULT_DEPTH
)
2842 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2843 /* output could be a fanout (ie. texture fetch output)
2844 * in which case we need to propagate the half-reg flag
2845 * up to the definer so that RA sees it:
2847 if (out
->opc
== OPC_META_FO
) {
2848 out
= out
->regs
[1]->instr
;
2849 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2852 if (out
->opc
== OPC_MOV
) {
2853 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
2858 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2859 printf("BEFORE CP:\n");
2865 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2866 printf("BEFORE GROUPING:\n");
2870 /* Group left/right neighbors, inserting mov's where needed to
2877 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2878 printf("AFTER DEPTH:\n");
2882 ret
= ir3_sched(ir
);
2884 DBG("SCHED failed!");
2888 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2889 printf("AFTER SCHED:\n");
2893 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
2899 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2900 printf("AFTER RA:\n");
2904 /* fixup input/outputs: */
2905 for (i
= 0; i
< so
->outputs_count
; i
++) {
2906 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
2909 /* Note that some or all channels of an input may be unused: */
2912 for (i
= 0; i
< so
->inputs_count
; i
++) {
2913 unsigned j
, regid
= ~0, compmask
= 0, maxcomp
= 0;
2914 so
->inputs
[i
].ncomp
= 0;
2915 so
->inputs
[i
].inloc
= inloc
;
2916 for (j
= 0; j
< 4; j
++) {
2917 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
2918 if (in
&& !(in
->flags
& IR3_INSTR_UNUSED
)) {
2919 compmask
|= (1 << j
);
2920 regid
= in
->regs
[0]->num
- j
;
2922 so
->inputs
[i
].ncomp
++;
2923 if ((so
->type
== SHADER_FRAGMENT
) && so
->inputs
[i
].bary
) {
2925 assert(in
->regs
[1]->flags
& IR3_REG_IMMED
);
2926 in
->regs
[1]->iim_val
= inloc
+ j
;
2931 if ((so
->type
== SHADER_FRAGMENT
) && compmask
&& so
->inputs
[i
].bary
) {
2933 so
->inputs
[i
].compmask
= (1 << maxcomp
) - 1;
2936 so
->inputs
[i
].compmask
= compmask
;
2938 so
->inputs
[i
].regid
= regid
;
2942 fixup_astc_srgb(ctx
);
2944 /* We need to do legalize after (for frag shader's) the "bary.f"
2945 * offsets (inloc) have been assigned.
2947 ir3_legalize(ir
, &so
->has_samp
, &so
->has_ssbo
, &max_bary
);
2949 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2950 printf("AFTER LEGALIZE:\n");
2954 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
2955 if (so
->type
== SHADER_VERTEX
)
2956 so
->total_in
= actual_in
;
2958 so
->total_in
= max_bary
+ 1;
2963 ir3_destroy(so
->ir
);