1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
36 #include "freedreno_util.h"
38 #include "ir3_compiler.h"
39 #include "ir3_shader.h"
42 #include "instr-a3xx.h"
47 struct ir3_compiler
*compiler
;
51 struct nir_instr
*cur_instr
; /* current instruction, just for debug */
54 struct ir3_shader_variant
*so
;
56 struct ir3_block
*block
; /* the current block */
57 struct ir3_block
*in_block
; /* block created for shader inputs */
59 nir_function_impl
*impl
;
61 /* For fragment shaders, varyings are not actual shader inputs,
62 * instead the hw passes a varying-coord which is used with
65 * But NIR doesn't know that, it still declares varyings as
66 * inputs. So we do all the input tracking normally and fix
67 * things up after compile_instructions()
69 * NOTE that frag_vcoord is the hardware position (possibly it
70 * is actually an index or tag or some such.. it is *not*
71 * values that can be directly used for gl_FragCoord..)
73 struct ir3_instruction
*frag_vcoord
;
75 /* for fragment shaders, for gl_FrontFacing and gl_FragCoord: */
76 struct ir3_instruction
*frag_face
, *frag_coord
;
78 /* For vertex shaders, keep track of the system values sources */
79 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
81 /* For fragment shaders: */
82 struct ir3_instruction
*samp_id
, *samp_mask_in
;
84 /* Compute shader inputs: */
85 struct ir3_instruction
*local_invocation_id
, *work_group_id
;
87 /* mapping from nir_register to defining instruction: */
88 struct hash_table
*def_ht
;
92 /* a common pattern for indirect addressing is to request the
93 * same address register multiple times. To avoid generating
94 * duplicate instruction sequences (which our backend does not
95 * try to clean up, since that should be done as the NIR stage)
96 * we cache the address value generated for a given src value:
98 * Note that we have to cache these per alignment, since same
99 * src used for an array of vec1 cannot be also used for an
102 struct hash_table
*addr_ht
[4];
104 /* last dst array, for indirect we need to insert a var-store.
106 struct ir3_instruction
**last_dst
;
109 /* maps nir_block to ir3_block, mostly for the purposes of
110 * figuring out the blocks successors
112 struct hash_table
*block_ht
;
114 /* on a4xx, bitmask of samplers which need astc+srgb workaround: */
117 unsigned samples
; /* bitmask of x,y sample shifts */
119 unsigned max_texture_index
;
121 /* set if we encounter something we can't handle yet, so we
122 * can bail cleanly and fallback to TGSI compiler f/e
127 /* gpu pointer size in units of 32bit registers/slots */
128 static unsigned pointer_size(struct ir3_context
*ctx
)
130 return (ctx
->compiler
->gpu_id
>= 500) ? 2 : 1;
133 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
134 static struct ir3_block
* get_block(struct ir3_context
*ctx
, const nir_block
*nblock
);
137 static struct ir3_context
*
138 compile_init(struct ir3_compiler
*compiler
,
139 struct ir3_shader_variant
*so
)
141 struct ir3_context
*ctx
= rzalloc(NULL
, struct ir3_context
);
143 if (compiler
->gpu_id
>= 400) {
144 if (so
->type
== SHADER_VERTEX
) {
145 ctx
->astc_srgb
= so
->key
.vastc_srgb
;
146 } else if (so
->type
== SHADER_FRAGMENT
) {
147 ctx
->astc_srgb
= so
->key
.fastc_srgb
;
151 if (so
->type
== SHADER_VERTEX
) {
152 ctx
->samples
= so
->key
.vsamples
;
153 } else if (so
->type
== SHADER_FRAGMENT
) {
154 ctx
->samples
= so
->key
.fsamples
;
158 ctx
->compiler
= compiler
;
160 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
161 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
162 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
163 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
165 /* TODO: maybe generate some sort of bitmask of what key
166 * lowers vs what shader has (ie. no need to lower
167 * texture clamp lowering if no texture sample instrs)..
168 * although should be done further up the stack to avoid
169 * creating duplicate variants..
172 if (ir3_key_lowers_nir(&so
->key
)) {
173 nir_shader
*s
= nir_shader_clone(ctx
, so
->shader
->nir
);
174 ctx
->s
= ir3_optimize_nir(so
->shader
, s
, &so
->key
);
176 /* fast-path for shader key that lowers nothing in NIR: */
177 ctx
->s
= so
->shader
->nir
;
180 /* this needs to be the last pass run, so do this here instead of
181 * in ir3_optimize_nir():
183 NIR_PASS_V(ctx
->s
, nir_lower_locals_to_regs
);
184 NIR_PASS_V(ctx
->s
, nir_convert_from_ssa
, true);
186 if (fd_mesa_debug
& FD_DBG_DISASM
) {
187 DBG("dump nir%dv%d: type=%d, k={bp=%u,cts=%u,hp=%u}",
188 so
->shader
->id
, so
->id
, so
->type
,
189 so
->key
.binning_pass
, so
->key
.color_two_side
,
190 so
->key
.half_precision
);
191 nir_print_shader(ctx
->s
, stdout
);
194 if (shader_debug_enabled(so
->type
)) {
195 fprintf(stderr
, "NIR (final form) for %s shader:\n",
196 shader_stage_name(so
->type
));
197 nir_print_shader(ctx
->s
, stderr
);
200 ir3_nir_scan_driver_consts(ctx
->s
, &so
->const_layout
);
202 so
->num_uniforms
= ctx
->s
->num_uniforms
;
203 so
->num_ubos
= ctx
->s
->info
.num_ubos
;
205 /* Layout of constant registers, each section aligned to vec4. Note
206 * that pointer size (ubo, etc) changes depending on generation.
211 * if (vertex shader) {
212 * driver params (IR3_DP_*)
213 * if (stream_output.num_outputs > 0)
214 * stream-out addresses
218 * Immediates go last mostly because they are inserted in the CP pass
219 * after the nir -> ir3 frontend.
221 unsigned constoff
= align(ctx
->s
->num_uniforms
, 4);
222 unsigned ptrsz
= pointer_size(ctx
);
224 memset(&so
->constbase
, ~0, sizeof(so
->constbase
));
226 if (so
->num_ubos
> 0) {
227 so
->constbase
.ubo
= constoff
;
228 constoff
+= align(ctx
->s
->info
.num_ubos
* ptrsz
, 4) / 4;
231 if (so
->const_layout
.ssbo_size
.count
> 0) {
232 unsigned cnt
= so
->const_layout
.ssbo_size
.count
;
233 so
->constbase
.ssbo_sizes
= constoff
;
234 constoff
+= align(cnt
, 4) / 4;
237 if (so
->const_layout
.image_dims
.count
> 0) {
238 unsigned cnt
= so
->const_layout
.image_dims
.count
;
239 so
->constbase
.image_dims
= constoff
;
240 constoff
+= align(cnt
, 4) / 4;
243 unsigned num_driver_params
= 0;
244 if (so
->type
== SHADER_VERTEX
) {
245 num_driver_params
= IR3_DP_VS_COUNT
;
246 } else if (so
->type
== SHADER_COMPUTE
) {
247 num_driver_params
= IR3_DP_CS_COUNT
;
250 so
->constbase
.driver_param
= constoff
;
251 constoff
+= align(num_driver_params
, 4) / 4;
253 if ((so
->type
== SHADER_VERTEX
) &&
254 (compiler
->gpu_id
< 500) &&
255 so
->shader
->stream_output
.num_outputs
> 0) {
256 so
->constbase
.tfbo
= constoff
;
257 constoff
+= align(PIPE_MAX_SO_BUFFERS
* ptrsz
, 4) / 4;
260 so
->constbase
.immediate
= constoff
;
266 compile_error(struct ir3_context
*ctx
, const char *format
, ...)
268 struct hash_table
*errors
= NULL
;
270 va_start(ap
, format
);
271 if (ctx
->cur_instr
) {
272 errors
= _mesa_hash_table_create(NULL
,
274 _mesa_key_pointer_equal
);
275 char *msg
= ralloc_vasprintf(errors
, format
, ap
);
276 _mesa_hash_table_insert(errors
, ctx
->cur_instr
, msg
);
278 _debug_vprintf(format
, ap
);
281 nir_print_shader_annotated(ctx
->s
, stdout
, errors
);
287 #define compile_assert(ctx, cond) do { \
288 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
292 compile_free(struct ir3_context
*ctx
)
298 declare_array(struct ir3_context
*ctx
, nir_register
*reg
)
300 struct ir3_array
*arr
= rzalloc(ctx
, struct ir3_array
);
301 arr
->id
= ++ctx
->num_arrays
;
302 /* NOTE: sometimes we get non array regs, for example for arrays of
303 * length 1. See fs-const-array-of-struct-of-array.shader_test. So
304 * treat a non-array as if it was an array of length 1.
306 * It would be nice if there was a nir pass to convert arrays of
309 arr
->length
= reg
->num_components
* MAX2(1, reg
->num_array_elems
);
310 compile_assert(ctx
, arr
->length
> 0);
312 list_addtail(&arr
->node
, &ctx
->ir
->array_list
);
315 static struct ir3_array
*
316 get_array(struct ir3_context
*ctx
, nir_register
*reg
)
318 list_for_each_entry (struct ir3_array
, arr
, &ctx
->ir
->array_list
, node
) {
322 compile_error(ctx
, "bogus reg: %s\n", reg
->name
);
326 /* relative (indirect) if address!=NULL */
327 static struct ir3_instruction
*
328 create_array_load(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
329 struct ir3_instruction
*address
)
331 struct ir3_block
*block
= ctx
->block
;
332 struct ir3_instruction
*mov
;
333 struct ir3_register
*src
;
335 mov
= ir3_instr_create(block
, OPC_MOV
);
336 mov
->cat1
.src_type
= TYPE_U32
;
337 mov
->cat1
.dst_type
= TYPE_U32
;
338 mov
->barrier_class
= IR3_BARRIER_ARRAY_R
;
339 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_W
;
340 ir3_reg_create(mov
, 0, 0);
341 src
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
342 COND(address
, IR3_REG_RELATIV
));
343 src
->instr
= arr
->last_write
;
344 src
->size
= arr
->length
;
345 src
->array
.id
= arr
->id
;
346 src
->array
.offset
= n
;
349 ir3_instr_set_address(mov
, address
);
354 /* relative (indirect) if address!=NULL */
356 create_array_store(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
357 struct ir3_instruction
*src
, struct ir3_instruction
*address
)
359 struct ir3_block
*block
= ctx
->block
;
360 struct ir3_instruction
*mov
;
361 struct ir3_register
*dst
;
363 /* if not relative store, don't create an extra mov, since that
364 * ends up being difficult for cp to remove.
369 src
->barrier_class
|= IR3_BARRIER_ARRAY_W
;
370 src
->barrier_conflict
|= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
372 dst
->flags
|= IR3_REG_ARRAY
;
373 dst
->instr
= arr
->last_write
;
374 dst
->size
= arr
->length
;
375 dst
->array
.id
= arr
->id
;
376 dst
->array
.offset
= n
;
378 arr
->last_write
= src
;
380 array_insert(block
, block
->keeps
, src
);
385 mov
= ir3_instr_create(block
, OPC_MOV
);
386 mov
->cat1
.src_type
= TYPE_U32
;
387 mov
->cat1
.dst_type
= TYPE_U32
;
388 mov
->barrier_class
= IR3_BARRIER_ARRAY_W
;
389 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
390 dst
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
391 COND(address
, IR3_REG_RELATIV
));
392 dst
->instr
= arr
->last_write
;
393 dst
->size
= arr
->length
;
394 dst
->array
.id
= arr
->id
;
395 dst
->array
.offset
= n
;
396 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
399 ir3_instr_set_address(mov
, address
);
401 arr
->last_write
= mov
;
403 /* the array store may only matter to something in an earlier
404 * block (ie. loops), but since arrays are not in SSA, depth
405 * pass won't know this.. so keep all array stores:
407 array_insert(block
, block
->keeps
, mov
);
410 static inline type_t
utype_for_size(unsigned bit_size
)
413 case 32: return TYPE_U32
;
414 case 16: return TYPE_U16
;
415 case 8: return TYPE_U8
;
416 default: unreachable("bad bitsize"); return ~0;
420 static inline type_t
utype_src(nir_src src
)
421 { return utype_for_size(nir_src_bit_size(src
)); }
423 static inline type_t
utype_dst(nir_dest dst
)
424 { return utype_for_size(nir_dest_bit_size(dst
)); }
426 /* allocate a n element value array (to be populated by caller) and
429 static struct ir3_instruction
**
430 get_dst_ssa(struct ir3_context
*ctx
, nir_ssa_def
*dst
, unsigned n
)
432 struct ir3_instruction
**value
=
433 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
434 _mesa_hash_table_insert(ctx
->def_ht
, dst
, value
);
438 static struct ir3_instruction
**
439 get_dst(struct ir3_context
*ctx
, nir_dest
*dst
, unsigned n
)
441 struct ir3_instruction
**value
;
444 value
= get_dst_ssa(ctx
, &dst
->ssa
, n
);
446 value
= ralloc_array(ctx
, struct ir3_instruction
*, n
);
449 /* NOTE: in non-ssa case, we don't really need to store last_dst
450 * but this helps us catch cases where put_dst() call is forgotten
452 compile_assert(ctx
, !ctx
->last_dst
);
453 ctx
->last_dst
= value
;
459 static struct ir3_instruction
* get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
);
461 static struct ir3_instruction
* const *
462 get_src(struct ir3_context
*ctx
, nir_src
*src
)
465 struct hash_entry
*entry
;
466 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
467 compile_assert(ctx
, entry
);
470 nir_register
*reg
= src
->reg
.reg
;
471 struct ir3_array
*arr
= get_array(ctx
, reg
);
472 unsigned num_components
= arr
->r
->num_components
;
473 struct ir3_instruction
*addr
= NULL
;
474 struct ir3_instruction
**value
=
475 ralloc_array(ctx
, struct ir3_instruction
*, num_components
);
477 if (src
->reg
.indirect
)
478 addr
= get_addr(ctx
, get_src(ctx
, src
->reg
.indirect
)[0],
479 reg
->num_components
);
481 for (unsigned i
= 0; i
< num_components
; i
++) {
482 unsigned n
= src
->reg
.base_offset
* reg
->num_components
+ i
;
483 compile_assert(ctx
, n
< arr
->length
);
484 value
[i
] = create_array_load(ctx
, arr
, n
, addr
);
492 put_dst(struct ir3_context
*ctx
, nir_dest
*dst
)
494 unsigned bit_size
= nir_dest_bit_size(*dst
);
497 for (unsigned i
= 0; i
< ctx
->last_dst_n
; i
++) {
498 struct ir3_instruction
*dst
= ctx
->last_dst
[i
];
499 dst
->regs
[0]->flags
|= IR3_REG_HALF
;
500 if (ctx
->last_dst
[i
]->opc
== OPC_META_FO
)
501 dst
->regs
[1]->instr
->regs
[0]->flags
|= IR3_REG_HALF
;
506 nir_register
*reg
= dst
->reg
.reg
;
507 struct ir3_array
*arr
= get_array(ctx
, reg
);
508 unsigned num_components
= ctx
->last_dst_n
;
509 struct ir3_instruction
*addr
= NULL
;
511 if (dst
->reg
.indirect
)
512 addr
= get_addr(ctx
, get_src(ctx
, dst
->reg
.indirect
)[0],
513 reg
->num_components
);
515 for (unsigned i
= 0; i
< num_components
; i
++) {
516 unsigned n
= dst
->reg
.base_offset
* reg
->num_components
+ i
;
517 compile_assert(ctx
, n
< arr
->length
);
518 if (!ctx
->last_dst
[i
])
520 create_array_store(ctx
, arr
, n
, ctx
->last_dst
[i
], addr
);
523 ralloc_free(ctx
->last_dst
);
525 ctx
->last_dst
= NULL
;
529 static struct ir3_instruction
*
530 create_immed_typed(struct ir3_block
*block
, uint32_t val
, type_t type
)
532 struct ir3_instruction
*mov
;
533 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
535 mov
= ir3_instr_create(block
, OPC_MOV
);
536 mov
->cat1
.src_type
= type
;
537 mov
->cat1
.dst_type
= type
;
538 ir3_reg_create(mov
, 0, flags
);
539 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
544 static struct ir3_instruction
*
545 create_immed(struct ir3_block
*block
, uint32_t val
)
547 return create_immed_typed(block
, val
, TYPE_U32
);
550 static struct ir3_instruction
*
551 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
, int align
)
553 struct ir3_instruction
*instr
, *immed
;
555 /* TODO in at least some cases, the backend could probably be
556 * made clever enough to propagate IR3_REG_HALF..
558 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
559 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
566 /* src *= 2 => src <<= 1: */
567 immed
= create_immed(block
, 1);
568 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
570 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
571 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
572 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
576 immed
= create_immed(block
, 3);
577 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
579 instr
= ir3_MULL_U(block
, instr
, 0, immed
, 0);
580 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
581 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
584 /* src *= 4 => src <<= 2: */
585 immed
= create_immed(block
, 2);
586 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
588 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
589 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
590 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
593 unreachable("bad align");
597 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
598 instr
->regs
[0]->num
= regid(REG_A0
, 0);
599 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
600 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
605 /* caches addr values to avoid generating multiple cov/shl/mova
606 * sequences for each use of a given NIR level src as address
608 static struct ir3_instruction
*
609 get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
)
611 struct ir3_instruction
*addr
;
612 unsigned idx
= align
- 1;
614 compile_assert(ctx
, idx
< ARRAY_SIZE(ctx
->addr_ht
));
616 if (!ctx
->addr_ht
[idx
]) {
617 ctx
->addr_ht
[idx
] = _mesa_hash_table_create(ctx
,
618 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
620 struct hash_entry
*entry
;
621 entry
= _mesa_hash_table_search(ctx
->addr_ht
[idx
], src
);
626 addr
= create_addr(ctx
->block
, src
, align
);
627 _mesa_hash_table_insert(ctx
->addr_ht
[idx
], src
, addr
);
632 static struct ir3_instruction
*
633 get_predicate(struct ir3_context
*ctx
, struct ir3_instruction
*src
)
635 struct ir3_block
*b
= ctx
->block
;
636 struct ir3_instruction
*cond
;
638 /* NOTE: only cmps.*.* can write p0.x: */
639 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
640 cond
->cat2
.condition
= IR3_COND_NE
;
642 /* condition always goes in predicate register: */
643 cond
->regs
[0]->num
= regid(REG_P0
, 0);
648 static struct ir3_instruction
*
649 create_uniform(struct ir3_context
*ctx
, unsigned n
)
651 struct ir3_instruction
*mov
;
653 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
654 /* TODO get types right? */
655 mov
->cat1
.src_type
= TYPE_F32
;
656 mov
->cat1
.dst_type
= TYPE_F32
;
657 ir3_reg_create(mov
, 0, 0);
658 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
663 static struct ir3_instruction
*
664 create_uniform_indirect(struct ir3_context
*ctx
, int n
,
665 struct ir3_instruction
*address
)
667 struct ir3_instruction
*mov
;
669 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
670 mov
->cat1
.src_type
= TYPE_U32
;
671 mov
->cat1
.dst_type
= TYPE_U32
;
672 ir3_reg_create(mov
, 0, 0);
673 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
675 ir3_instr_set_address(mov
, address
);
680 static struct ir3_instruction
*
681 create_collect(struct ir3_context
*ctx
, struct ir3_instruction
*const *arr
,
684 struct ir3_block
*block
= ctx
->block
;
685 struct ir3_instruction
*collect
;
690 unsigned flags
= arr
[0]->regs
[0]->flags
& IR3_REG_HALF
;
692 collect
= ir3_instr_create2(block
, OPC_META_FI
, 1 + arrsz
);
693 ir3_reg_create(collect
, 0, flags
); /* dst */
694 for (unsigned i
= 0; i
< arrsz
; i
++) {
695 struct ir3_instruction
*elem
= arr
[i
];
697 /* Since arrays are pre-colored in RA, we can't assume that
698 * things will end up in the right place. (Ie. if a collect
699 * joins elements from two different arrays.) So insert an
702 * We could possibly skip this if all the collected elements
703 * are contiguous elements in a single array.. not sure how
704 * likely that is to happen.
706 * Fixes a problem with glamor shaders, that in effect do
713 * color = texture2D(tex, texcoord);
715 * In this case, texcoord will end up as nir registers (which
716 * translate to ir3 array's of length 1. And we can't assume
717 * the two (or more) arrays will get allocated in consecutive
721 if (elem
->regs
[0]->flags
& IR3_REG_ARRAY
) {
722 type_t type
= (flags
& IR3_REG_HALF
) ? TYPE_U16
: TYPE_U32
;
723 elem
= ir3_MOV(block
, elem
, type
);
726 compile_assert(ctx
, (elem
->regs
[0]->flags
& IR3_REG_HALF
) == flags
);
727 ir3_reg_create(collect
, 0, IR3_REG_SSA
| flags
)->instr
= elem
;
733 static struct ir3_instruction
*
734 create_indirect_load(struct ir3_context
*ctx
, unsigned arrsz
, int n
,
735 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
737 struct ir3_block
*block
= ctx
->block
;
738 struct ir3_instruction
*mov
;
739 struct ir3_register
*src
;
741 mov
= ir3_instr_create(block
, OPC_MOV
);
742 mov
->cat1
.src_type
= TYPE_U32
;
743 mov
->cat1
.dst_type
= TYPE_U32
;
744 ir3_reg_create(mov
, 0, 0);
745 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
746 src
->instr
= collect
;
748 src
->array
.offset
= n
;
750 ir3_instr_set_address(mov
, address
);
755 static struct ir3_instruction
*
756 create_input_compmask(struct ir3_context
*ctx
, unsigned n
, unsigned compmask
)
758 struct ir3_instruction
*in
;
760 in
= ir3_instr_create(ctx
->in_block
, OPC_META_INPUT
);
761 in
->inout
.block
= ctx
->in_block
;
762 ir3_reg_create(in
, n
, 0);
764 in
->regs
[0]->wrmask
= compmask
;
769 static struct ir3_instruction
*
770 create_input(struct ir3_context
*ctx
, unsigned n
)
772 return create_input_compmask(ctx
, n
, 0x1);
775 static struct ir3_instruction
*
776 create_frag_input(struct ir3_context
*ctx
, bool use_ldlv
)
778 struct ir3_block
*block
= ctx
->block
;
779 struct ir3_instruction
*instr
;
780 /* actual inloc is assigned and fixed up later: */
781 struct ir3_instruction
*inloc
= create_immed(block
, 0);
784 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
785 instr
->cat6
.type
= TYPE_U32
;
786 instr
->cat6
.iim_val
= 1;
788 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_vcoord
, 0);
789 instr
->regs
[2]->wrmask
= 0x3;
795 static struct ir3_instruction
*
796 create_driver_param(struct ir3_context
*ctx
, enum ir3_driver_param dp
)
798 /* first four vec4 sysval's reserved for UBOs: */
799 /* NOTE: dp is in scalar, but there can be >4 dp components: */
800 unsigned n
= ctx
->so
->constbase
.driver_param
;
801 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
802 return create_uniform(ctx
, r
);
805 /* helper for instructions that produce multiple consecutive scalar
806 * outputs which need to have a split/fanout meta instruction inserted
809 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
810 struct ir3_instruction
*src
, unsigned base
, unsigned n
)
812 struct ir3_instruction
*prev
= NULL
;
814 if ((n
== 1) && (src
->regs
[0]->wrmask
== 0x1)) {
819 for (int i
= 0, j
= 0; i
< n
; i
++) {
820 struct ir3_instruction
*split
= ir3_instr_create(block
, OPC_META_FO
);
821 ir3_reg_create(split
, 0, IR3_REG_SSA
);
822 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
823 split
->fo
.off
= i
+ base
;
826 split
->cp
.left
= prev
;
827 split
->cp
.left_cnt
++;
828 prev
->cp
.right
= split
;
829 prev
->cp
.right_cnt
++;
833 if (src
->regs
[0]->wrmask
& (1 << (i
+ base
)))
839 * Adreno uses uint rather than having dedicated bool type,
840 * which (potentially) requires some conversion, in particular
841 * when using output of an bool instr to int input, or visa
845 * -------+---------+-------+-
849 * To convert from an adreno bool (uint) to nir, use:
851 * absneg.s dst, (neg)src
853 * To convert back in the other direction:
855 * absneg.s dst, (abs)arc
857 * The CP step can clean up the absneg.s that cancel each other
858 * out, and with a slight bit of extra cleverness (to recognize
859 * the instructions which produce either a 0 or 1) can eliminate
860 * the absneg.s's completely when an instruction that wants
861 * 0/1 consumes the result. For example, when a nir 'bcsel'
862 * consumes the result of 'feq'. So we should be able to get by
863 * without a boolean resolve step, and without incuring any
864 * extra penalty in instruction count.
867 /* NIR bool -> native (adreno): */
868 static struct ir3_instruction
*
869 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
871 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
874 /* native (adreno) -> NIR bool: */
875 static struct ir3_instruction
*
876 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
878 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
882 * alu/sfu instructions:
885 static struct ir3_instruction
*
886 create_cov(struct ir3_context
*ctx
, struct ir3_instruction
*src
,
887 unsigned src_bitsize
, nir_op op
)
889 type_t src_type
, dst_type
;
893 case nir_op_f2f16_rtne
:
894 case nir_op_f2f16_rtz
:
902 switch (src_bitsize
) {
910 compile_error(ctx
, "invalid src bit size: %u", src_bitsize
);
919 switch (src_bitsize
) {
930 compile_error(ctx
, "invalid src bit size: %u", src_bitsize
);
939 switch (src_bitsize
) {
950 compile_error(ctx
, "invalid src bit size: %u", src_bitsize
);
955 compile_error(ctx
, "invalid conversion op: %u", op
);
965 case nir_op_f2f16_rtne
:
966 case nir_op_f2f16_rtz
:
968 /* TODO how to handle rounding mode? */
1005 compile_error(ctx
, "invalid conversion op: %u", op
);
1008 return ir3_COV(ctx
->block
, src
, src_type
, dst_type
);
1012 emit_alu(struct ir3_context
*ctx
, nir_alu_instr
*alu
)
1014 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
1015 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
1016 unsigned bs
[info
->num_inputs
]; /* bit size */
1017 struct ir3_block
*b
= ctx
->block
;
1018 unsigned dst_sz
, wrmask
;
1020 if (alu
->dest
.dest
.is_ssa
) {
1021 dst_sz
= alu
->dest
.dest
.ssa
.num_components
;
1022 wrmask
= (1 << dst_sz
) - 1;
1024 dst_sz
= alu
->dest
.dest
.reg
.reg
->num_components
;
1025 wrmask
= alu
->dest
.write_mask
;
1028 dst
= get_dst(ctx
, &alu
->dest
.dest
, dst_sz
);
1030 /* Vectors are special in that they have non-scalarized writemasks,
1031 * and just take the first swizzle channel for each argument in
1032 * order into each writemask channel.
1034 if ((alu
->op
== nir_op_vec2
) ||
1035 (alu
->op
== nir_op_vec3
) ||
1036 (alu
->op
== nir_op_vec4
)) {
1038 for (int i
= 0; i
< info
->num_inputs
; i
++) {
1039 nir_alu_src
*asrc
= &alu
->src
[i
];
1041 compile_assert(ctx
, !asrc
->abs
);
1042 compile_assert(ctx
, !asrc
->negate
);
1044 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
1046 src
[i
] = create_immed(ctx
->block
, 0);
1047 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
1050 put_dst(ctx
, &alu
->dest
.dest
);
1054 /* We also get mov's with more than one component for mov's so
1055 * handle those specially:
1057 if ((alu
->op
== nir_op_imov
) || (alu
->op
== nir_op_fmov
)) {
1058 type_t type
= (alu
->op
== nir_op_imov
) ? TYPE_U32
: TYPE_F32
;
1059 nir_alu_src
*asrc
= &alu
->src
[0];
1060 struct ir3_instruction
*const *src0
= get_src(ctx
, &asrc
->src
);
1062 for (unsigned i
= 0; i
< dst_sz
; i
++) {
1063 if (wrmask
& (1 << i
)) {
1064 dst
[i
] = ir3_MOV(b
, src0
[asrc
->swizzle
[i
]], type
);
1070 put_dst(ctx
, &alu
->dest
.dest
);
1074 /* General case: We can just grab the one used channel per src. */
1075 for (int i
= 0; i
< info
->num_inputs
; i
++) {
1076 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
1077 nir_alu_src
*asrc
= &alu
->src
[i
];
1079 compile_assert(ctx
, !asrc
->abs
);
1080 compile_assert(ctx
, !asrc
->negate
);
1082 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
1083 bs
[i
] = nir_src_bit_size(asrc
->src
);
1085 compile_assert(ctx
, src
[i
]);
1090 case nir_op_f2f16_rtne
:
1091 case nir_op_f2f16_rtz
:
1109 dst
[0] = create_cov(ctx
, src
[0], bs
[0], alu
->op
);
1112 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
1113 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1114 dst
[0] = ir3_n2b(b
, dst
[0]);
1117 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
1120 dst
[0] = ir3_b2n(b
, src
[0]);
1123 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1124 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1125 dst
[0] = ir3_n2b(b
, dst
[0]);
1129 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
1132 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
1135 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
1138 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
1141 /* if there is just a single use of the src, and it supports
1142 * (sat) bit, we can just fold the (sat) flag back to the
1143 * src instruction and create a mov. This is easier for cp
1146 * TODO probably opc_cat==4 is ok too
1148 if (alu
->src
[0].src
.is_ssa
&&
1149 (list_length(&alu
->src
[0].src
.ssa
->uses
) == 1) &&
1150 ((opc_cat(src
[0]->opc
) == 2) || (opc_cat(src
[0]->opc
) == 3))) {
1151 src
[0]->flags
|= IR3_INSTR_SAT
;
1152 dst
[0] = ir3_MOV(b
, src
[0], TYPE_U32
);
1154 /* otherwise generate a max.f that saturates.. blob does
1155 * similar (generating a cat2 mov using max.f)
1157 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[0], 0);
1158 dst
[0]->flags
|= IR3_INSTR_SAT
;
1162 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
1165 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
1168 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
1171 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
1174 dst
[0] = ir3_DSX(b
, src
[0], 0);
1175 dst
[0]->cat5
.type
= TYPE_F32
;
1178 dst
[0] = ir3_DSY(b
, src
[0], 0);
1179 dst
[0]->cat5
.type
= TYPE_F32
;
1183 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1184 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1185 dst
[0] = ir3_n2b(b
, dst
[0]);
1188 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1189 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1190 dst
[0] = ir3_n2b(b
, dst
[0]);
1193 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1194 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1195 dst
[0] = ir3_n2b(b
, dst
[0]);
1198 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1199 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1200 dst
[0] = ir3_n2b(b
, dst
[0]);
1203 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
1206 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
1209 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
1211 case nir_op_fround_even
:
1212 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
1215 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
1219 dst
[0] = ir3_SIN(b
, src
[0], 0);
1222 dst
[0] = ir3_COS(b
, src
[0], 0);
1225 dst
[0] = ir3_RSQ(b
, src
[0], 0);
1228 dst
[0] = ir3_RCP(b
, src
[0], 0);
1231 dst
[0] = ir3_LOG2(b
, src
[0], 0);
1234 dst
[0] = ir3_EXP2(b
, src
[0], 0);
1237 dst
[0] = ir3_SQRT(b
, src
[0], 0);
1241 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
1244 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
1247 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
1250 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
1253 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
1256 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
1259 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
1263 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
1264 * mull.u tmp0, a, b ; mul low, i.e. al * bl
1265 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
1266 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
1268 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
1269 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
1270 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
1273 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
1276 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
1279 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
1282 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
1285 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
1287 case nir_op_isign
: {
1288 /* maybe this would be sane to lower in nir.. */
1289 struct ir3_instruction
*neg
, *pos
;
1291 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1292 neg
->cat2
.condition
= IR3_COND_LT
;
1294 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1295 pos
->cat2
.condition
= IR3_COND_GT
;
1297 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
1302 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
1305 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
1308 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
1311 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1312 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1313 dst
[0] = ir3_n2b(b
, dst
[0]);
1316 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1317 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1318 dst
[0] = ir3_n2b(b
, dst
[0]);
1321 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1322 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1323 dst
[0] = ir3_n2b(b
, dst
[0]);
1326 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1327 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1328 dst
[0] = ir3_n2b(b
, dst
[0]);
1331 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1332 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1333 dst
[0] = ir3_n2b(b
, dst
[0]);
1336 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1337 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1338 dst
[0] = ir3_n2b(b
, dst
[0]);
1341 case nir_op_bcsel
: {
1342 struct ir3_instruction
*cond
= ir3_b2n(b
, src
[0]);
1343 compile_assert(ctx
, bs
[1] == bs
[2]);
1344 /* the boolean condition is 32b even if src[1] and src[2] are
1345 * half-precision, but sel.b16 wants all three src's to be the
1349 cond
= ir3_COV(b
, cond
, TYPE_U32
, TYPE_U16
);
1350 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, cond
, 0, src
[2], 0);
1353 case nir_op_bit_count
:
1354 dst
[0] = ir3_CBITS_B(b
, src
[0], 0);
1356 case nir_op_ifind_msb
: {
1357 struct ir3_instruction
*cmp
;
1358 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
1359 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
1360 cmp
->cat2
.condition
= IR3_COND_GE
;
1361 dst
[0] = ir3_SEL_B32(b
,
1362 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1366 case nir_op_ufind_msb
:
1367 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
1368 dst
[0] = ir3_SEL_B32(b
,
1369 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1370 src
[0], 0, dst
[0], 0);
1372 case nir_op_find_lsb
:
1373 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1374 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
1376 case nir_op_bitfield_reverse
:
1377 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1381 compile_error(ctx
, "Unhandled ALU op: %s\n",
1382 nir_op_infos
[alu
->op
].name
);
1386 put_dst(ctx
, &alu
->dest
.dest
);
1389 /* handles direct/indirect UBO reads: */
1391 emit_intrinsic_load_ubo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1392 struct ir3_instruction
**dst
)
1394 struct ir3_block
*b
= ctx
->block
;
1395 struct ir3_instruction
*base_lo
, *base_hi
, *addr
, *src0
, *src1
;
1396 nir_const_value
*const_offset
;
1397 /* UBO addresses are the first driver params: */
1398 unsigned ubo
= regid(ctx
->so
->constbase
.ubo
, 0);
1399 const unsigned ptrsz
= pointer_size(ctx
);
1403 /* First src is ubo index, which could either be an immed or not: */
1404 src0
= get_src(ctx
, &intr
->src
[0])[0];
1405 if (is_same_type_mov(src0
) &&
1406 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1407 base_lo
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
));
1408 base_hi
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
) + 1);
1410 base_lo
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
, 4));
1411 base_hi
= create_uniform_indirect(ctx
, ubo
+ 1, get_addr(ctx
, src0
, 4));
1414 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
1417 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1419 off
+= const_offset
->u32
[0];
1421 /* For load_ubo_indirect, second src is indirect offset: */
1422 src1
= get_src(ctx
, &intr
->src
[1])[0];
1424 /* and add offset to addr: */
1425 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1428 /* if offset is to large to encode in the ldg, split it out: */
1429 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1430 /* split out the minimal amount to improve the odds that
1431 * cp can fit the immediate in the add.s instruction:
1433 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1434 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1439 struct ir3_instruction
*carry
;
1441 /* handle 32b rollover, ie:
1442 * if (addr < base_lo)
1445 carry
= ir3_CMPS_U(b
, addr
, 0, base_lo
, 0);
1446 carry
->cat2
.condition
= IR3_COND_LT
;
1447 base_hi
= ir3_ADD_S(b
, base_hi
, 0, carry
, 0);
1449 addr
= create_collect(ctx
, (struct ir3_instruction
*[]){ addr
, base_hi
}, 2);
1452 for (int i
= 0; i
< intr
->num_components
; i
++) {
1453 struct ir3_instruction
*load
=
1454 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1455 load
->cat6
.type
= TYPE_U32
;
1456 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
1461 /* src[] = { buffer_index, offset }. No const_index */
1463 emit_intrinsic_load_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1464 struct ir3_instruction
**dst
)
1466 struct ir3_block
*b
= ctx
->block
;
1467 struct ir3_instruction
*ldgb
, *src0
, *src1
, *offset
;
1468 nir_const_value
*const_offset
;
1470 /* can this be non-const buffer_index? how do we handle that? */
1471 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1472 compile_assert(ctx
, const_offset
);
1474 offset
= get_src(ctx
, &intr
->src
[1])[0];
1476 /* src0 is uvec2(offset*4, 0), src1 is offset.. nir already *= 4: */
1477 src0
= create_collect(ctx
, (struct ir3_instruction
*[]){
1481 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1483 ldgb
= ir3_LDGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1485 ldgb
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1486 ldgb
->cat6
.iim_val
= intr
->num_components
;
1488 ldgb
->cat6
.type
= TYPE_U32
;
1489 ldgb
->barrier_class
= IR3_BARRIER_BUFFER_R
;
1490 ldgb
->barrier_conflict
= IR3_BARRIER_BUFFER_W
;
1492 split_dest(b
, dst
, ldgb
, 0, intr
->num_components
);
1495 /* src[] = { value, block_index, offset }. const_index[] = { write_mask } */
1497 emit_intrinsic_store_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1499 struct ir3_block
*b
= ctx
->block
;
1500 struct ir3_instruction
*stgb
, *src0
, *src1
, *src2
, *offset
;
1501 nir_const_value
*const_offset
;
1502 /* TODO handle wrmask properly, see _store_shared().. but I think
1503 * it is more a PITA than that, since blob ends up loading the
1504 * masked components and writing them back out.
1506 unsigned wrmask
= intr
->const_index
[0];
1507 unsigned ncomp
= ffs(~wrmask
) - 1;
1509 /* can this be non-const buffer_index? how do we handle that? */
1510 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1511 compile_assert(ctx
, const_offset
);
1513 offset
= get_src(ctx
, &intr
->src
[2])[0];
1515 /* src0 is value, src1 is offset, src2 is uvec2(offset*4, 0)..
1518 src0
= create_collect(ctx
, get_src(ctx
, &intr
->src
[0]), ncomp
);
1519 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1520 src2
= create_collect(ctx
, (struct ir3_instruction
*[]){
1525 stgb
= ir3_STGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1526 src0
, 0, src1
, 0, src2
, 0);
1527 stgb
->cat6
.iim_val
= ncomp
;
1529 stgb
->cat6
.type
= TYPE_U32
;
1530 stgb
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1531 stgb
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1533 array_insert(b
, b
->keeps
, stgb
);
1536 /* src[] = { block_index } */
1538 emit_intrinsic_ssbo_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1539 struct ir3_instruction
**dst
)
1541 /* SSBO size stored as a const starting at ssbo_sizes: */
1542 unsigned blk_idx
= nir_src_as_const_value(intr
->src
[0])->u32
[0];
1543 unsigned idx
= regid(ctx
->so
->constbase
.ssbo_sizes
, 0) +
1544 ctx
->so
->const_layout
.ssbo_size
.off
[blk_idx
];
1546 debug_assert(ctx
->so
->const_layout
.ssbo_size
.mask
& (1 << blk_idx
));
1548 dst
[0] = create_uniform(ctx
, idx
);
1552 * SSBO atomic intrinsics
1554 * All of the SSBO atomic memory operations read a value from memory,
1555 * compute a new value using one of the operations below, write the new
1556 * value to memory, and return the original value read.
1558 * All operations take 3 sources except CompSwap that takes 4. These
1559 * sources represent:
1561 * 0: The SSBO buffer index.
1562 * 1: The offset into the SSBO buffer of the variable that the atomic
1563 * operation will operate on.
1564 * 2: The data parameter to the atomic function (i.e. the value to add
1565 * in ssbo_atomic_add, etc).
1566 * 3: For CompSwap only: the second data parameter.
1568 static struct ir3_instruction
*
1569 emit_intrinsic_atomic_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1571 struct ir3_block
*b
= ctx
->block
;
1572 struct ir3_instruction
*atomic
, *ssbo
, *src0
, *src1
, *src2
, *offset
;
1573 nir_const_value
*const_offset
;
1574 type_t type
= TYPE_U32
;
1576 /* can this be non-const buffer_index? how do we handle that? */
1577 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1578 compile_assert(ctx
, const_offset
);
1579 ssbo
= create_immed(b
, const_offset
->u32
[0]);
1581 offset
= get_src(ctx
, &intr
->src
[1])[0];
1583 /* src0 is data (or uvec2(data, compare))
1585 * src2 is uvec2(offset*4, 0) (appears to be 64b byte offset)
1587 * Note that nir already multiplies the offset by four
1589 src0
= get_src(ctx
, &intr
->src
[2])[0];
1590 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1591 src2
= create_collect(ctx
, (struct ir3_instruction
*[]){
1596 switch (intr
->intrinsic
) {
1597 case nir_intrinsic_ssbo_atomic_add
:
1598 atomic
= ir3_ATOMIC_ADD_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1600 case nir_intrinsic_ssbo_atomic_imin
:
1601 atomic
= ir3_ATOMIC_MIN_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1604 case nir_intrinsic_ssbo_atomic_umin
:
1605 atomic
= ir3_ATOMIC_MIN_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1607 case nir_intrinsic_ssbo_atomic_imax
:
1608 atomic
= ir3_ATOMIC_MAX_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1611 case nir_intrinsic_ssbo_atomic_umax
:
1612 atomic
= ir3_ATOMIC_MAX_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1614 case nir_intrinsic_ssbo_atomic_and
:
1615 atomic
= ir3_ATOMIC_AND_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1617 case nir_intrinsic_ssbo_atomic_or
:
1618 atomic
= ir3_ATOMIC_OR_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1620 case nir_intrinsic_ssbo_atomic_xor
:
1621 atomic
= ir3_ATOMIC_XOR_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1623 case nir_intrinsic_ssbo_atomic_exchange
:
1624 atomic
= ir3_ATOMIC_XCHG_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1626 case nir_intrinsic_ssbo_atomic_comp_swap
:
1627 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
1628 src0
= create_collect(ctx
, (struct ir3_instruction
*[]){
1629 get_src(ctx
, &intr
->src
[3])[0],
1632 atomic
= ir3_ATOMIC_CMPXCHG_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1638 atomic
->cat6
.iim_val
= 1;
1640 atomic
->cat6
.type
= type
;
1641 atomic
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1642 atomic
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1644 /* even if nothing consume the result, we can't DCE the instruction: */
1645 array_insert(b
, b
->keeps
, atomic
);
1650 /* src[] = { offset }. const_index[] = { base } */
1652 emit_intrinsic_load_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1653 struct ir3_instruction
**dst
)
1655 struct ir3_block
*b
= ctx
->block
;
1656 struct ir3_instruction
*ldl
, *offset
;
1659 offset
= get_src(ctx
, &intr
->src
[0])[0];
1660 base
= nir_intrinsic_base(intr
);
1662 ldl
= ir3_LDL(b
, offset
, 0, create_immed(b
, intr
->num_components
), 0);
1663 ldl
->cat6
.src_offset
= base
;
1664 ldl
->cat6
.type
= utype_dst(intr
->dest
);
1665 ldl
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1667 ldl
->barrier_class
= IR3_BARRIER_SHARED_R
;
1668 ldl
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
1670 split_dest(b
, dst
, ldl
, 0, intr
->num_components
);
1673 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
1675 emit_intrinsic_store_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1677 struct ir3_block
*b
= ctx
->block
;
1678 struct ir3_instruction
*stl
, *offset
;
1679 struct ir3_instruction
* const *value
;
1680 unsigned base
, wrmask
;
1682 value
= get_src(ctx
, &intr
->src
[0]);
1683 offset
= get_src(ctx
, &intr
->src
[1])[0];
1685 base
= nir_intrinsic_base(intr
);
1686 wrmask
= nir_intrinsic_write_mask(intr
);
1688 /* Combine groups of consecutive enabled channels in one write
1689 * message. We use ffs to find the first enabled channel and then ffs on
1690 * the bit-inverse, down-shifted writemask to determine the length of
1691 * the block of enabled bits.
1693 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
1696 unsigned first_component
= ffs(wrmask
) - 1;
1697 unsigned length
= ffs(~(wrmask
>> first_component
)) - 1;
1699 stl
= ir3_STL(b
, offset
, 0,
1700 create_collect(ctx
, &value
[first_component
], length
), 0,
1701 create_immed(b
, length
), 0);
1702 stl
->cat6
.dst_offset
= first_component
+ base
;
1703 stl
->cat6
.type
= utype_src(intr
->src
[0]);
1704 stl
->barrier_class
= IR3_BARRIER_SHARED_W
;
1705 stl
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1707 array_insert(b
, b
->keeps
, stl
);
1709 /* Clear the bits in the writemask that we just wrote, then try
1710 * again to see if more channels are left.
1712 wrmask
&= (15 << (first_component
+ length
));
1717 * CS shared variable atomic intrinsics
1719 * All of the shared variable atomic memory operations read a value from
1720 * memory, compute a new value using one of the operations below, write the
1721 * new value to memory, and return the original value read.
1723 * All operations take 2 sources except CompSwap that takes 3. These
1724 * sources represent:
1726 * 0: The offset into the shared variable storage region that the atomic
1727 * operation will operate on.
1728 * 1: The data parameter to the atomic function (i.e. the value to add
1729 * in shared_atomic_add, etc).
1730 * 2: For CompSwap only: the second data parameter.
1732 static struct ir3_instruction
*
1733 emit_intrinsic_atomic_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1735 struct ir3_block
*b
= ctx
->block
;
1736 struct ir3_instruction
*atomic
, *src0
, *src1
;
1737 type_t type
= TYPE_U32
;
1739 src0
= get_src(ctx
, &intr
->src
[0])[0]; /* offset */
1740 src1
= get_src(ctx
, &intr
->src
[1])[0]; /* value */
1742 switch (intr
->intrinsic
) {
1743 case nir_intrinsic_shared_atomic_add
:
1744 atomic
= ir3_ATOMIC_ADD(b
, src0
, 0, src1
, 0);
1746 case nir_intrinsic_shared_atomic_imin
:
1747 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1750 case nir_intrinsic_shared_atomic_umin
:
1751 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1753 case nir_intrinsic_shared_atomic_imax
:
1754 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1757 case nir_intrinsic_shared_atomic_umax
:
1758 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1760 case nir_intrinsic_shared_atomic_and
:
1761 atomic
= ir3_ATOMIC_AND(b
, src0
, 0, src1
, 0);
1763 case nir_intrinsic_shared_atomic_or
:
1764 atomic
= ir3_ATOMIC_OR(b
, src0
, 0, src1
, 0);
1766 case nir_intrinsic_shared_atomic_xor
:
1767 atomic
= ir3_ATOMIC_XOR(b
, src0
, 0, src1
, 0);
1769 case nir_intrinsic_shared_atomic_exchange
:
1770 atomic
= ir3_ATOMIC_XCHG(b
, src0
, 0, src1
, 0);
1772 case nir_intrinsic_shared_atomic_comp_swap
:
1773 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1774 src1
= create_collect(ctx
, (struct ir3_instruction
*[]){
1775 get_src(ctx
, &intr
->src
[2])[0],
1778 atomic
= ir3_ATOMIC_CMPXCHG(b
, src0
, 0, src1
, 0);
1784 atomic
->cat6
.iim_val
= 1;
1786 atomic
->cat6
.type
= type
;
1787 atomic
->barrier_class
= IR3_BARRIER_SHARED_W
;
1788 atomic
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1790 /* even if nothing consume the result, we can't DCE the instruction: */
1791 array_insert(b
, b
->keeps
, atomic
);
1796 /* Images get mapped into SSBO/image state (for store/atomic) and texture
1797 * state block (for load). To simplify things, invert the image id and
1798 * map it from end of state block, ie. image 0 becomes num-1, image 1
1799 * becomes num-2, etc. This potentially avoids needing to re-emit texture
1800 * state when switching shaders.
1802 * TODO is max # of samplers and SSBOs the same. This shouldn't be hard-
1803 * coded. Also, since all the gl shader stages (ie. everything but CS)
1804 * share the same SSBO/image state block, this might require some more
1805 * logic if we supported images in anything other than FS..
1808 get_image_slot(struct ir3_context
*ctx
, nir_deref_instr
*deref
)
1810 unsigned int loc
= 0;
1811 unsigned inner_size
= 1;
1813 while (deref
->deref_type
!= nir_deref_type_var
) {
1814 assert(deref
->deref_type
== nir_deref_type_array
);
1815 nir_const_value
*const_index
= nir_src_as_const_value(deref
->arr
.index
);
1816 assert(const_index
);
1818 /* Go to the next instruction */
1819 deref
= nir_deref_instr_parent(deref
);
1821 assert(glsl_type_is_array(deref
->type
));
1822 const unsigned array_len
= glsl_get_length(deref
->type
);
1823 loc
+= MIN2(const_index
->u32
[0], array_len
- 1) * inner_size
;
1825 /* Update the inner size */
1826 inner_size
*= array_len
;
1829 loc
+= deref
->var
->data
.driver_location
;
1831 /* TODO figure out real limit per generation, and don't hardcode: */
1832 const unsigned max_samplers
= 16;
1833 return max_samplers
- loc
- 1;
1836 /* see tex_info() for equiv logic for texture instructions.. it would be
1837 * nice if this could be better unified..
1840 get_image_coords(const nir_variable
*var
, unsigned *flagsp
)
1842 const struct glsl_type
*type
= glsl_without_array(var
->type
);
1843 unsigned coords
, flags
= 0;
1845 switch (glsl_get_sampler_dim(type
)) {
1846 case GLSL_SAMPLER_DIM_1D
:
1847 case GLSL_SAMPLER_DIM_BUF
:
1850 case GLSL_SAMPLER_DIM_2D
:
1851 case GLSL_SAMPLER_DIM_RECT
:
1852 case GLSL_SAMPLER_DIM_EXTERNAL
:
1853 case GLSL_SAMPLER_DIM_MS
:
1856 case GLSL_SAMPLER_DIM_3D
:
1857 case GLSL_SAMPLER_DIM_CUBE
:
1858 flags
|= IR3_INSTR_3D
;
1862 unreachable("bad sampler dim");
1866 if (glsl_sampler_type_is_array(type
)) {
1867 /* note: unlike tex_info(), adjust # of coords to include array idx: */
1869 flags
|= IR3_INSTR_A
;
1879 get_image_type(const nir_variable
*var
)
1881 switch (glsl_get_sampler_result_type(glsl_without_array(var
->type
))) {
1882 case GLSL_TYPE_UINT
:
1886 case GLSL_TYPE_FLOAT
:
1889 unreachable("bad sampler type.");
1894 static struct ir3_instruction
*
1895 get_image_offset(struct ir3_context
*ctx
, const nir_variable
*var
,
1896 struct ir3_instruction
* const *coords
, bool byteoff
)
1898 struct ir3_block
*b
= ctx
->block
;
1899 struct ir3_instruction
*offset
;
1900 unsigned ncoords
= get_image_coords(var
, NULL
);
1902 /* to calculate the byte offset (yes, uggg) we need (up to) three
1903 * const values to know the bytes per pixel, and y and z stride:
1905 unsigned cb
= regid(ctx
->so
->constbase
.image_dims
, 0) +
1906 ctx
->so
->const_layout
.image_dims
.off
[var
->data
.driver_location
];
1908 debug_assert(ctx
->so
->const_layout
.image_dims
.mask
&
1909 (1 << var
->data
.driver_location
));
1911 /* offset = coords.x * bytes_per_pixel: */
1912 offset
= ir3_MUL_S(b
, coords
[0], 0, create_uniform(ctx
, cb
+ 0), 0);
1914 /* offset += coords.y * y_pitch: */
1915 offset
= ir3_MAD_S24(b
, create_uniform(ctx
, cb
+ 1), 0,
1916 coords
[1], 0, offset
, 0);
1919 /* offset += coords.z * z_pitch: */
1920 offset
= ir3_MAD_S24(b
, create_uniform(ctx
, cb
+ 2), 0,
1921 coords
[2], 0, offset
, 0);
1925 /* Some cases, like atomics, seem to use dword offset instead
1926 * of byte offsets.. blob just puts an extra shr.b in there
1929 offset
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1932 return create_collect(ctx
, (struct ir3_instruction
*[]){
1938 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1940 emit_intrinsic_load_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1941 struct ir3_instruction
**dst
)
1943 struct ir3_block
*b
= ctx
->block
;
1944 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
1945 struct ir3_instruction
*sam
;
1946 struct ir3_instruction
* const *src0
= get_src(ctx
, &intr
->src
[1]);
1947 struct ir3_instruction
*coords
[4];
1948 unsigned flags
, ncoords
= get_image_coords(var
, &flags
);
1949 unsigned tex_idx
= get_image_slot(ctx
, nir_src_as_deref(intr
->src
[0]));
1950 type_t type
= get_image_type(var
);
1952 /* hmm, this seems a bit odd, but it is what blob does and (at least
1953 * a5xx) just faults on bogus addresses otherwise:
1955 if (flags
& IR3_INSTR_3D
) {
1956 flags
&= ~IR3_INSTR_3D
;
1957 flags
|= IR3_INSTR_A
;
1960 for (unsigned i
= 0; i
< ncoords
; i
++)
1961 coords
[i
] = src0
[i
];
1964 coords
[ncoords
++] = create_immed(b
, 0);
1966 sam
= ir3_SAM(b
, OPC_ISAM
, type
, TGSI_WRITEMASK_XYZW
, flags
,
1967 tex_idx
, tex_idx
, create_collect(ctx
, coords
, ncoords
), NULL
);
1969 sam
->barrier_class
= IR3_BARRIER_IMAGE_R
;
1970 sam
->barrier_conflict
= IR3_BARRIER_IMAGE_W
;
1972 split_dest(b
, dst
, sam
, 0, 4);
1975 /* src[] = { deref, coord, sample_index, value }. const_index[] = {} */
1977 emit_intrinsic_store_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1979 struct ir3_block
*b
= ctx
->block
;
1980 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
1981 struct ir3_instruction
*stib
, *offset
;
1982 struct ir3_instruction
* const *value
= get_src(ctx
, &intr
->src
[3]);
1983 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[1]);
1984 unsigned ncoords
= get_image_coords(var
, NULL
);
1985 unsigned tex_idx
= get_image_slot(ctx
, nir_src_as_deref(intr
->src
[0]));
1989 * src2 is 64b byte offset
1992 offset
= get_image_offset(ctx
, var
, coords
, true);
1994 /* NOTE: stib seems to take byte offset, but stgb.typed can be used
1995 * too and takes a dword offset.. not quite sure yet why blob uses
1996 * one over the other in various cases.
1999 stib
= ir3_STIB(b
, create_immed(b
, tex_idx
), 0,
2000 create_collect(ctx
, value
, 4), 0,
2001 create_collect(ctx
, coords
, ncoords
), 0,
2003 stib
->cat6
.iim_val
= 4;
2004 stib
->cat6
.d
= ncoords
;
2005 stib
->cat6
.type
= get_image_type(var
);
2006 stib
->cat6
.typed
= true;
2007 stib
->barrier_class
= IR3_BARRIER_IMAGE_W
;
2008 stib
->barrier_conflict
= IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
;
2010 array_insert(b
, b
->keeps
, stib
);
2014 emit_intrinsic_image_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
2015 struct ir3_instruction
**dst
)
2017 struct ir3_block
*b
= ctx
->block
;
2018 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
2019 unsigned tex_idx
= get_image_slot(ctx
, nir_src_as_deref(intr
->src
[0]));
2020 struct ir3_instruction
*sam
, *lod
;
2021 unsigned flags
, ncoords
= get_image_coords(var
, &flags
);
2023 lod
= create_immed(b
, 0);
2024 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
2025 tex_idx
, tex_idx
, lod
, NULL
);
2027 /* Array size actually ends up in .w rather than .z. This doesn't
2028 * matter for miplevel 0, but for higher mips the value in z is
2029 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2030 * returned, which means that we have to add 1 to it for arrays for
2033 * Note use a temporary dst and then copy, since the size of the dst
2034 * array that is passed in is based on nir's understanding of the
2035 * result size, not the hardware's
2037 struct ir3_instruction
*tmp
[4];
2039 split_dest(b
, tmp
, sam
, 0, 4);
2041 for (unsigned i
= 0; i
< ncoords
; i
++)
2044 if (flags
& IR3_INSTR_A
) {
2045 if (ctx
->compiler
->levels_add_one
) {
2046 dst
[ncoords
-1] = ir3_ADD_U(b
, tmp
[3], 0, create_immed(b
, 1), 0);
2048 dst
[ncoords
-1] = ir3_MOV(b
, tmp
[3], TYPE_U32
);
2053 /* src[] = { deref, coord, sample_index, value, compare }. const_index[] = {} */
2054 static struct ir3_instruction
*
2055 emit_intrinsic_atomic_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
2057 struct ir3_block
*b
= ctx
->block
;
2058 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
2059 struct ir3_instruction
*atomic
, *image
, *src0
, *src1
, *src2
;
2060 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[1]);
2061 unsigned ncoords
= get_image_coords(var
, NULL
);
2063 image
= create_immed(b
, get_image_slot(ctx
, nir_src_as_deref(intr
->src
[0])));
2065 /* src0 is value (or uvec2(value, compare))
2067 * src2 is 64b byte offset
2069 src0
= get_src(ctx
, &intr
->src
[3])[0];
2070 src1
= create_collect(ctx
, coords
, ncoords
);
2071 src2
= get_image_offset(ctx
, var
, coords
, false);
2073 switch (intr
->intrinsic
) {
2074 case nir_intrinsic_image_deref_atomic_add
:
2075 atomic
= ir3_ATOMIC_ADD_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2077 case nir_intrinsic_image_deref_atomic_min
:
2078 atomic
= ir3_ATOMIC_MIN_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2080 case nir_intrinsic_image_deref_atomic_max
:
2081 atomic
= ir3_ATOMIC_MAX_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2083 case nir_intrinsic_image_deref_atomic_and
:
2084 atomic
= ir3_ATOMIC_AND_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2086 case nir_intrinsic_image_deref_atomic_or
:
2087 atomic
= ir3_ATOMIC_OR_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2089 case nir_intrinsic_image_deref_atomic_xor
:
2090 atomic
= ir3_ATOMIC_XOR_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2092 case nir_intrinsic_image_deref_atomic_exchange
:
2093 atomic
= ir3_ATOMIC_XCHG_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2095 case nir_intrinsic_image_deref_atomic_comp_swap
:
2096 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
2097 src0
= create_collect(ctx
, (struct ir3_instruction
*[]){
2098 get_src(ctx
, &intr
->src
[4])[0],
2101 atomic
= ir3_ATOMIC_CMPXCHG_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2107 atomic
->cat6
.iim_val
= 1;
2108 atomic
->cat6
.d
= ncoords
;
2109 atomic
->cat6
.type
= get_image_type(var
);
2110 atomic
->cat6
.typed
= true;
2111 atomic
->barrier_class
= IR3_BARRIER_IMAGE_W
;
2112 atomic
->barrier_conflict
= IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
;
2114 /* even if nothing consume the result, we can't DCE the instruction: */
2115 array_insert(b
, b
->keeps
, atomic
);
2121 emit_intrinsic_barrier(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
2123 struct ir3_block
*b
= ctx
->block
;
2124 struct ir3_instruction
*barrier
;
2126 switch (intr
->intrinsic
) {
2127 case nir_intrinsic_barrier
:
2128 barrier
= ir3_BAR(b
);
2129 barrier
->cat7
.g
= true;
2130 barrier
->cat7
.l
= true;
2131 barrier
->flags
= IR3_INSTR_SS
| IR3_INSTR_SY
;
2132 barrier
->barrier_class
= IR3_BARRIER_EVERYTHING
;
2134 case nir_intrinsic_memory_barrier
:
2135 barrier
= ir3_FENCE(b
);
2136 barrier
->cat7
.g
= true;
2137 barrier
->cat7
.r
= true;
2138 barrier
->cat7
.w
= true;
2139 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
|
2140 IR3_BARRIER_BUFFER_W
;
2141 barrier
->barrier_conflict
=
2142 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
2143 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
2145 case nir_intrinsic_memory_barrier_atomic_counter
:
2146 case nir_intrinsic_memory_barrier_buffer
:
2147 barrier
= ir3_FENCE(b
);
2148 barrier
->cat7
.g
= true;
2149 barrier
->cat7
.r
= true;
2150 barrier
->cat7
.w
= true;
2151 barrier
->barrier_class
= IR3_BARRIER_BUFFER_W
;
2152 barrier
->barrier_conflict
= IR3_BARRIER_BUFFER_R
|
2153 IR3_BARRIER_BUFFER_W
;
2155 case nir_intrinsic_memory_barrier_image
:
2156 // TODO double check if this should have .g set
2157 barrier
= ir3_FENCE(b
);
2158 barrier
->cat7
.g
= true;
2159 barrier
->cat7
.r
= true;
2160 barrier
->cat7
.w
= true;
2161 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
;
2162 barrier
->barrier_conflict
= IR3_BARRIER_IMAGE_R
|
2163 IR3_BARRIER_IMAGE_W
;
2165 case nir_intrinsic_memory_barrier_shared
:
2166 barrier
= ir3_FENCE(b
);
2167 barrier
->cat7
.g
= true;
2168 barrier
->cat7
.l
= true;
2169 barrier
->cat7
.r
= true;
2170 barrier
->cat7
.w
= true;
2171 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
;
2172 barrier
->barrier_conflict
= IR3_BARRIER_SHARED_R
|
2173 IR3_BARRIER_SHARED_W
;
2175 case nir_intrinsic_group_memory_barrier
:
2176 barrier
= ir3_FENCE(b
);
2177 barrier
->cat7
.g
= true;
2178 barrier
->cat7
.l
= true;
2179 barrier
->cat7
.r
= true;
2180 barrier
->cat7
.w
= true;
2181 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
|
2182 IR3_BARRIER_IMAGE_W
|
2183 IR3_BARRIER_BUFFER_W
;
2184 barrier
->barrier_conflict
=
2185 IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
|
2186 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
2187 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
2193 /* make sure barrier doesn't get DCE'd */
2194 array_insert(b
, b
->keeps
, barrier
);
2197 static void add_sysval_input_compmask(struct ir3_context
*ctx
,
2198 gl_system_value slot
, unsigned compmask
,
2199 struct ir3_instruction
*instr
)
2201 struct ir3_shader_variant
*so
= ctx
->so
;
2202 unsigned r
= regid(so
->inputs_count
, 0);
2203 unsigned n
= so
->inputs_count
++;
2205 so
->inputs
[n
].sysval
= true;
2206 so
->inputs
[n
].slot
= slot
;
2207 so
->inputs
[n
].compmask
= compmask
;
2208 so
->inputs
[n
].regid
= r
;
2209 so
->inputs
[n
].interpolate
= INTERP_MODE_FLAT
;
2212 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
2213 ctx
->ir
->inputs
[r
] = instr
;
2216 static void add_sysval_input(struct ir3_context
*ctx
, gl_system_value slot
,
2217 struct ir3_instruction
*instr
)
2219 add_sysval_input_compmask(ctx
, slot
, 0x1, instr
);
2223 emit_intrinsic(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
2225 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
2226 struct ir3_instruction
**dst
;
2227 struct ir3_instruction
* const *src
;
2228 struct ir3_block
*b
= ctx
->block
;
2229 nir_const_value
*const_offset
;
2232 if (info
->has_dest
) {
2233 unsigned n
= nir_intrinsic_dest_components(intr
);
2234 dst
= get_dst(ctx
, &intr
->dest
, n
);
2239 switch (intr
->intrinsic
) {
2240 case nir_intrinsic_load_uniform
:
2241 idx
= nir_intrinsic_base(intr
);
2242 const_offset
= nir_src_as_const_value(intr
->src
[0]);
2244 idx
+= const_offset
->u32
[0];
2245 for (int i
= 0; i
< intr
->num_components
; i
++) {
2246 unsigned n
= idx
* 4 + i
;
2247 dst
[i
] = create_uniform(ctx
, n
);
2250 src
= get_src(ctx
, &intr
->src
[0]);
2251 for (int i
= 0; i
< intr
->num_components
; i
++) {
2252 int n
= idx
* 4 + i
;
2253 dst
[i
] = create_uniform_indirect(ctx
, n
,
2254 get_addr(ctx
, src
[0], 4));
2256 /* NOTE: if relative addressing is used, we set
2257 * constlen in the compiler (to worst-case value)
2258 * since we don't know in the assembler what the max
2259 * addr reg value can be:
2261 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
2264 case nir_intrinsic_load_ubo
:
2265 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
2267 case nir_intrinsic_load_input
:
2268 idx
= nir_intrinsic_base(intr
);
2269 comp
= nir_intrinsic_component(intr
);
2270 const_offset
= nir_src_as_const_value(intr
->src
[0]);
2272 idx
+= const_offset
->u32
[0];
2273 for (int i
= 0; i
< intr
->num_components
; i
++) {
2274 unsigned n
= idx
* 4 + i
+ comp
;
2275 dst
[i
] = ctx
->ir
->inputs
[n
];
2278 src
= get_src(ctx
, &intr
->src
[0]);
2279 struct ir3_instruction
*collect
=
2280 create_collect(ctx
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
2281 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0], 4);
2282 for (int i
= 0; i
< intr
->num_components
; i
++) {
2283 unsigned n
= idx
* 4 + i
+ comp
;
2284 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
2289 case nir_intrinsic_load_ssbo
:
2290 emit_intrinsic_load_ssbo(ctx
, intr
, dst
);
2292 case nir_intrinsic_store_ssbo
:
2293 emit_intrinsic_store_ssbo(ctx
, intr
);
2295 case nir_intrinsic_get_buffer_size
:
2296 emit_intrinsic_ssbo_size(ctx
, intr
, dst
);
2298 case nir_intrinsic_ssbo_atomic_add
:
2299 case nir_intrinsic_ssbo_atomic_imin
:
2300 case nir_intrinsic_ssbo_atomic_umin
:
2301 case nir_intrinsic_ssbo_atomic_imax
:
2302 case nir_intrinsic_ssbo_atomic_umax
:
2303 case nir_intrinsic_ssbo_atomic_and
:
2304 case nir_intrinsic_ssbo_atomic_or
:
2305 case nir_intrinsic_ssbo_atomic_xor
:
2306 case nir_intrinsic_ssbo_atomic_exchange
:
2307 case nir_intrinsic_ssbo_atomic_comp_swap
:
2308 dst
[0] = emit_intrinsic_atomic_ssbo(ctx
, intr
);
2310 case nir_intrinsic_load_shared
:
2311 emit_intrinsic_load_shared(ctx
, intr
, dst
);
2313 case nir_intrinsic_store_shared
:
2314 emit_intrinsic_store_shared(ctx
, intr
);
2316 case nir_intrinsic_shared_atomic_add
:
2317 case nir_intrinsic_shared_atomic_imin
:
2318 case nir_intrinsic_shared_atomic_umin
:
2319 case nir_intrinsic_shared_atomic_imax
:
2320 case nir_intrinsic_shared_atomic_umax
:
2321 case nir_intrinsic_shared_atomic_and
:
2322 case nir_intrinsic_shared_atomic_or
:
2323 case nir_intrinsic_shared_atomic_xor
:
2324 case nir_intrinsic_shared_atomic_exchange
:
2325 case nir_intrinsic_shared_atomic_comp_swap
:
2326 dst
[0] = emit_intrinsic_atomic_shared(ctx
, intr
);
2328 case nir_intrinsic_image_deref_load
:
2329 emit_intrinsic_load_image(ctx
, intr
, dst
);
2331 case nir_intrinsic_image_deref_store
:
2332 emit_intrinsic_store_image(ctx
, intr
);
2334 case nir_intrinsic_image_deref_size
:
2335 emit_intrinsic_image_size(ctx
, intr
, dst
);
2337 case nir_intrinsic_image_deref_atomic_add
:
2338 case nir_intrinsic_image_deref_atomic_min
:
2339 case nir_intrinsic_image_deref_atomic_max
:
2340 case nir_intrinsic_image_deref_atomic_and
:
2341 case nir_intrinsic_image_deref_atomic_or
:
2342 case nir_intrinsic_image_deref_atomic_xor
:
2343 case nir_intrinsic_image_deref_atomic_exchange
:
2344 case nir_intrinsic_image_deref_atomic_comp_swap
:
2345 dst
[0] = emit_intrinsic_atomic_image(ctx
, intr
);
2347 case nir_intrinsic_barrier
:
2348 case nir_intrinsic_memory_barrier
:
2349 case nir_intrinsic_group_memory_barrier
:
2350 case nir_intrinsic_memory_barrier_atomic_counter
:
2351 case nir_intrinsic_memory_barrier_buffer
:
2352 case nir_intrinsic_memory_barrier_image
:
2353 case nir_intrinsic_memory_barrier_shared
:
2354 emit_intrinsic_barrier(ctx
, intr
);
2355 /* note that blk ptr no longer valid, make that obvious: */
2358 case nir_intrinsic_store_output
:
2359 idx
= nir_intrinsic_base(intr
);
2360 comp
= nir_intrinsic_component(intr
);
2361 const_offset
= nir_src_as_const_value(intr
->src
[1]);
2362 compile_assert(ctx
, const_offset
!= NULL
);
2363 idx
+= const_offset
->u32
[0];
2365 src
= get_src(ctx
, &intr
->src
[0]);
2366 for (int i
= 0; i
< intr
->num_components
; i
++) {
2367 unsigned n
= idx
* 4 + i
+ comp
;
2368 ctx
->ir
->outputs
[n
] = src
[i
];
2371 case nir_intrinsic_load_base_vertex
:
2372 case nir_intrinsic_load_first_vertex
:
2373 if (!ctx
->basevertex
) {
2374 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
2375 add_sysval_input(ctx
, SYSTEM_VALUE_FIRST_VERTEX
, ctx
->basevertex
);
2377 dst
[0] = ctx
->basevertex
;
2379 case nir_intrinsic_load_vertex_id_zero_base
:
2380 case nir_intrinsic_load_vertex_id
:
2381 if (!ctx
->vertex_id
) {
2382 gl_system_value sv
= (intr
->intrinsic
== nir_intrinsic_load_vertex_id
) ?
2383 SYSTEM_VALUE_VERTEX_ID
: SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
;
2384 ctx
->vertex_id
= create_input(ctx
, 0);
2385 add_sysval_input(ctx
, sv
, ctx
->vertex_id
);
2387 dst
[0] = ctx
->vertex_id
;
2389 case nir_intrinsic_load_instance_id
:
2390 if (!ctx
->instance_id
) {
2391 ctx
->instance_id
= create_input(ctx
, 0);
2392 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
2395 dst
[0] = ctx
->instance_id
;
2397 case nir_intrinsic_load_sample_id
:
2398 case nir_intrinsic_load_sample_id_no_per_sample
:
2399 if (!ctx
->samp_id
) {
2400 ctx
->samp_id
= create_input(ctx
, 0);
2401 ctx
->samp_id
->regs
[0]->flags
|= IR3_REG_HALF
;
2402 add_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_ID
,
2405 dst
[0] = ir3_COV(b
, ctx
->samp_id
, TYPE_U16
, TYPE_U32
);
2407 case nir_intrinsic_load_sample_mask_in
:
2408 if (!ctx
->samp_mask_in
) {
2409 ctx
->samp_mask_in
= create_input(ctx
, 0);
2410 add_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_MASK_IN
,
2413 dst
[0] = ctx
->samp_mask_in
;
2415 case nir_intrinsic_load_user_clip_plane
:
2416 idx
= nir_intrinsic_ucp_id(intr
);
2417 for (int i
= 0; i
< intr
->num_components
; i
++) {
2418 unsigned n
= idx
* 4 + i
;
2419 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
2422 case nir_intrinsic_load_front_face
:
2423 if (!ctx
->frag_face
) {
2424 ctx
->so
->frag_face
= true;
2425 ctx
->frag_face
= create_input(ctx
, 0);
2426 add_sysval_input(ctx
, SYSTEM_VALUE_FRONT_FACE
, ctx
->frag_face
);
2427 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
2429 /* for fragface, we get -1 for back and 0 for front. However this is
2430 * the inverse of what nir expects (where ~0 is true).
2432 dst
[0] = ir3_COV(b
, ctx
->frag_face
, TYPE_S16
, TYPE_S32
);
2433 dst
[0] = ir3_NOT_B(b
, dst
[0], 0);
2435 case nir_intrinsic_load_local_invocation_id
:
2436 if (!ctx
->local_invocation_id
) {
2437 ctx
->local_invocation_id
= create_input_compmask(ctx
, 0, 0x7);
2438 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
,
2439 0x7, ctx
->local_invocation_id
);
2441 split_dest(b
, dst
, ctx
->local_invocation_id
, 0, 3);
2443 case nir_intrinsic_load_work_group_id
:
2444 if (!ctx
->work_group_id
) {
2445 ctx
->work_group_id
= create_input_compmask(ctx
, 0, 0x7);
2446 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_WORK_GROUP_ID
,
2447 0x7, ctx
->work_group_id
);
2448 ctx
->work_group_id
->regs
[0]->flags
|= IR3_REG_HIGH
;
2450 split_dest(b
, dst
, ctx
->work_group_id
, 0, 3);
2452 case nir_intrinsic_load_num_work_groups
:
2453 for (int i
= 0; i
< intr
->num_components
; i
++) {
2454 dst
[i
] = create_driver_param(ctx
, IR3_DP_NUM_WORK_GROUPS_X
+ i
);
2457 case nir_intrinsic_load_local_group_size
:
2458 for (int i
= 0; i
< intr
->num_components
; i
++) {
2459 dst
[i
] = create_driver_param(ctx
, IR3_DP_LOCAL_GROUP_SIZE_X
+ i
);
2462 case nir_intrinsic_discard_if
:
2463 case nir_intrinsic_discard
: {
2464 struct ir3_instruction
*cond
, *kill
;
2466 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
2467 /* conditional discard: */
2468 src
= get_src(ctx
, &intr
->src
[0]);
2469 cond
= ir3_b2n(b
, src
[0]);
2471 /* unconditional discard: */
2472 cond
= create_immed(b
, 1);
2475 /* NOTE: only cmps.*.* can write p0.x: */
2476 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
2477 cond
->cat2
.condition
= IR3_COND_NE
;
2479 /* condition always goes in predicate register: */
2480 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2482 kill
= ir3_KILL(b
, cond
, 0);
2483 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
2485 array_insert(b
, b
->keeps
, kill
);
2486 ctx
->so
->has_kill
= true;
2491 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
2492 nir_intrinsic_infos
[intr
->intrinsic
].name
);
2497 put_dst(ctx
, &intr
->dest
);
2501 emit_load_const(struct ir3_context
*ctx
, nir_load_const_instr
*instr
)
2503 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
2504 instr
->def
.num_components
);
2505 type_t type
= (instr
->def
.bit_size
< 32) ? TYPE_U16
: TYPE_U32
;
2507 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
2508 dst
[i
] = create_immed_typed(ctx
->block
, instr
->value
.u32
[i
], type
);
2512 emit_undef(struct ir3_context
*ctx
, nir_ssa_undef_instr
*undef
)
2514 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
2515 undef
->def
.num_components
);
2516 type_t type
= (undef
->def
.bit_size
< 32) ? TYPE_U16
: TYPE_U32
;
2518 /* backend doesn't want undefined instructions, so just plug
2521 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
2522 dst
[i
] = create_immed_typed(ctx
->block
, fui(0.0), type
);
2526 * texture fetch/sample instructions:
2530 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
2532 unsigned coords
, flags
= 0;
2534 /* note: would use tex->coord_components.. except txs.. also,
2535 * since array index goes after shadow ref, we don't want to
2538 switch (tex
->sampler_dim
) {
2539 case GLSL_SAMPLER_DIM_1D
:
2540 case GLSL_SAMPLER_DIM_BUF
:
2543 case GLSL_SAMPLER_DIM_2D
:
2544 case GLSL_SAMPLER_DIM_RECT
:
2545 case GLSL_SAMPLER_DIM_EXTERNAL
:
2546 case GLSL_SAMPLER_DIM_MS
:
2549 case GLSL_SAMPLER_DIM_3D
:
2550 case GLSL_SAMPLER_DIM_CUBE
:
2552 flags
|= IR3_INSTR_3D
;
2555 unreachable("bad sampler_dim");
2558 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2559 flags
|= IR3_INSTR_S
;
2561 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
2562 flags
|= IR3_INSTR_A
;
2569 emit_tex(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2571 struct ir3_block
*b
= ctx
->block
;
2572 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
2573 struct ir3_instruction
* const *coord
, * const *off
, * const *ddx
, * const *ddy
;
2574 struct ir3_instruction
*lod
, *compare
, *proj
, *sample_index
;
2575 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
2576 unsigned i
, coords
, flags
;
2577 unsigned nsrc0
= 0, nsrc1
= 0;
2581 coord
= off
= ddx
= ddy
= NULL
;
2582 lod
= proj
= compare
= sample_index
= NULL
;
2584 /* TODO: might just be one component for gathers? */
2585 dst
= get_dst(ctx
, &tex
->dest
, 4);
2587 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
2588 switch (tex
->src
[i
].src_type
) {
2589 case nir_tex_src_coord
:
2590 coord
= get_src(ctx
, &tex
->src
[i
].src
);
2592 case nir_tex_src_bias
:
2593 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2596 case nir_tex_src_lod
:
2597 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2600 case nir_tex_src_comparator
: /* shadow comparator */
2601 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2603 case nir_tex_src_projector
:
2604 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2607 case nir_tex_src_offset
:
2608 off
= get_src(ctx
, &tex
->src
[i
].src
);
2611 case nir_tex_src_ddx
:
2612 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
2614 case nir_tex_src_ddy
:
2615 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
2617 case nir_tex_src_ms_index
:
2618 sample_index
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2621 compile_error(ctx
, "Unhandled NIR tex src type: %d\n",
2622 tex
->src
[i
].src_type
);
2628 case nir_texop_tex
: opc
= has_lod
? OPC_SAML
: OPC_SAM
; break;
2629 case nir_texop_txb
: opc
= OPC_SAMB
; break;
2630 case nir_texop_txl
: opc
= OPC_SAML
; break;
2631 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
2632 case nir_texop_txf
: opc
= OPC_ISAML
; break;
2633 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
2635 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2636 * what blob does, seems gather is broken?), and a3xx did
2637 * not support it (but probably could also emulate).
2639 switch (tex
->component
) {
2640 case 0: opc
= OPC_GATHER4R
; break;
2641 case 1: opc
= OPC_GATHER4G
; break;
2642 case 2: opc
= OPC_GATHER4B
; break;
2643 case 3: opc
= OPC_GATHER4A
; break;
2646 case nir_texop_txf_ms
: opc
= OPC_ISAMM
; break;
2648 case nir_texop_query_levels
:
2649 case nir_texop_texture_samples
:
2650 case nir_texop_samples_identical
:
2651 case nir_texop_txf_ms_mcs
:
2652 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
2656 tex_info(tex
, &flags
, &coords
);
2659 * lay out the first argument in the proper order:
2660 * - actual coordinates first
2661 * - shadow reference
2664 * - starting at offset 4, dpdx.xy, dpdy.xy
2666 * bias/lod go into the second arg
2669 /* insert tex coords: */
2670 for (i
= 0; i
< coords
; i
++)
2675 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2676 * with scaled x coord according to requested sample:
2678 if (tex
->op
== nir_texop_txf_ms
) {
2679 if (ctx
->compiler
->txf_ms_with_isaml
) {
2680 /* the samples are laid out in x dimension as
2682 * x_ms = (x << ms) + sample_index;
2684 struct ir3_instruction
*ms
;
2685 ms
= create_immed(b
, (ctx
->samples
>> (2 * tex
->texture_index
)) & 3);
2687 src0
[0] = ir3_SHL_B(b
, src0
[0], 0, ms
, 0);
2688 src0
[0] = ir3_ADD_U(b
, src0
[0], 0, sample_index
, 0);
2692 src0
[nsrc0
++] = sample_index
;
2696 /* scale up integer coords for TXF based on the LOD */
2697 if (ctx
->compiler
->unminify_coords
&& (opc
== OPC_ISAML
)) {
2699 for (i
= 0; i
< coords
; i
++)
2700 src0
[i
] = ir3_SHL_B(b
, src0
[i
], 0, lod
, 0);
2704 /* hw doesn't do 1d, so we treat it as 2d with
2705 * height of 1, and patch up the y coord.
2706 * TODO: y coord should be (int)0 in some cases..
2708 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
2711 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2712 src0
[nsrc0
++] = compare
;
2714 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
) {
2715 struct ir3_instruction
*idx
= coord
[coords
];
2717 /* the array coord for cube arrays needs 0.5 added to it */
2718 if (ctx
->compiler
->array_index_add_half
&& (opc
!= OPC_ISAML
))
2719 idx
= ir3_ADD_F(b
, idx
, 0, create_immed(b
, fui(0.5)), 0);
2721 src0
[nsrc0
++] = idx
;
2725 src0
[nsrc0
++] = proj
;
2726 flags
|= IR3_INSTR_P
;
2729 /* pad to 4, then ddx/ddy: */
2730 if (tex
->op
== nir_texop_txd
) {
2732 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2733 for (i
= 0; i
< coords
; i
++)
2734 src0
[nsrc0
++] = ddx
[i
];
2736 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2737 for (i
= 0; i
< coords
; i
++)
2738 src0
[nsrc0
++] = ddy
[i
];
2740 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2744 * second argument (if applicable):
2749 if (has_off
| has_lod
| has_bias
) {
2751 unsigned off_coords
= coords
;
2752 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2754 for (i
= 0; i
< off_coords
; i
++)
2755 src1
[nsrc1
++] = off
[i
];
2757 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
2758 flags
|= IR3_INSTR_O
;
2761 if (has_lod
| has_bias
)
2762 src1
[nsrc1
++] = lod
;
2765 switch (tex
->dest_type
) {
2766 case nir_type_invalid
:
2767 case nir_type_float
:
2778 unreachable("bad dest_type");
2781 if (opc
== OPC_GETLOD
)
2784 unsigned tex_idx
= tex
->texture_index
;
2786 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex_idx
);
2788 struct ir3_instruction
*col0
= create_collect(ctx
, src0
, nsrc0
);
2789 struct ir3_instruction
*col1
= create_collect(ctx
, src1
, nsrc1
);
2791 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
, flags
,
2792 tex_idx
, tex_idx
, col0
, col1
);
2794 if ((ctx
->astc_srgb
& (1 << tex_idx
)) && !nir_tex_instr_is_query(tex
)) {
2795 /* only need first 3 components: */
2796 sam
->regs
[0]->wrmask
= 0x7;
2797 split_dest(b
, dst
, sam
, 0, 3);
2799 /* we need to sample the alpha separately with a non-ASTC
2802 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_W
, flags
,
2803 tex_idx
, tex_idx
, col0
, col1
);
2805 array_insert(ctx
->ir
, ctx
->ir
->astc_srgb
, sam
);
2807 /* fixup .w component: */
2808 split_dest(b
, &dst
[3], sam
, 3, 1);
2810 /* normal (non-workaround) case: */
2811 split_dest(b
, dst
, sam
, 0, 4);
2814 /* GETLOD returns results in 4.8 fixed point */
2815 if (opc
== OPC_GETLOD
) {
2816 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
2818 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
2819 for (i
= 0; i
< 2; i
++) {
2820 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_U32
, TYPE_F32
), 0,
2825 put_dst(ctx
, &tex
->dest
);
2829 emit_tex_query_levels(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2831 struct ir3_block
*b
= ctx
->block
;
2832 struct ir3_instruction
**dst
, *sam
;
2834 dst
= get_dst(ctx
, &tex
->dest
, 1);
2836 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
2837 tex
->texture_index
, tex
->texture_index
, NULL
, NULL
);
2839 /* even though there is only one component, since it ends
2840 * up in .z rather than .x, we need a split_dest()
2842 split_dest(b
, dst
, sam
, 0, 3);
2844 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2845 * the value in TEX_CONST_0 is zero-based.
2847 if (ctx
->compiler
->levels_add_one
)
2848 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
2850 put_dst(ctx
, &tex
->dest
);
2854 emit_tex_txs(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2856 struct ir3_block
*b
= ctx
->block
;
2857 struct ir3_instruction
**dst
, *sam
;
2858 struct ir3_instruction
*lod
;
2859 unsigned flags
, coords
;
2861 tex_info(tex
, &flags
, &coords
);
2863 /* Actually we want the number of dimensions, not coordinates. This
2864 * distinction only matters for cubes.
2866 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2869 dst
= get_dst(ctx
, &tex
->dest
, 4);
2871 compile_assert(ctx
, tex
->num_srcs
== 1);
2872 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
2874 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
2876 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
2877 tex
->texture_index
, tex
->texture_index
, lod
, NULL
);
2879 split_dest(b
, dst
, sam
, 0, 4);
2881 /* Array size actually ends up in .w rather than .z. This doesn't
2882 * matter for miplevel 0, but for higher mips the value in z is
2883 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2884 * returned, which means that we have to add 1 to it for arrays.
2886 if (tex
->is_array
) {
2887 if (ctx
->compiler
->levels_add_one
) {
2888 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
2890 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
2894 put_dst(ctx
, &tex
->dest
);
2898 emit_jump(struct ir3_context
*ctx
, nir_jump_instr
*jump
)
2900 switch (jump
->type
) {
2901 case nir_jump_break
:
2902 case nir_jump_continue
:
2903 case nir_jump_return
:
2904 /* I *think* we can simply just ignore this, and use the
2905 * successor block link to figure out where we need to
2906 * jump to for break/continue
2910 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
2916 emit_instr(struct ir3_context
*ctx
, nir_instr
*instr
)
2918 switch (instr
->type
) {
2919 case nir_instr_type_alu
:
2920 emit_alu(ctx
, nir_instr_as_alu(instr
));
2922 case nir_instr_type_deref
:
2923 /* ignored, handled as part of the intrinsic they are src to */
2925 case nir_instr_type_intrinsic
:
2926 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2928 case nir_instr_type_load_const
:
2929 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2931 case nir_instr_type_ssa_undef
:
2932 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
2934 case nir_instr_type_tex
: {
2935 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
2936 /* couple tex instructions get special-cased:
2940 emit_tex_txs(ctx
, tex
);
2942 case nir_texop_query_levels
:
2943 emit_tex_query_levels(ctx
, tex
);
2951 case nir_instr_type_jump
:
2952 emit_jump(ctx
, nir_instr_as_jump(instr
));
2954 case nir_instr_type_phi
:
2955 /* we have converted phi webs to regs in NIR by now */
2956 compile_error(ctx
, "Unexpected NIR instruction type: %d\n", instr
->type
);
2958 case nir_instr_type_call
:
2959 case nir_instr_type_parallel_copy
:
2960 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
2965 static struct ir3_block
*
2966 get_block(struct ir3_context
*ctx
, const nir_block
*nblock
)
2968 struct ir3_block
*block
;
2969 struct hash_entry
*hentry
;
2970 struct set_entry
*sentry
;
2973 hentry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
2975 return hentry
->data
;
2977 block
= ir3_block_create(ctx
->ir
);
2978 block
->nblock
= nblock
;
2979 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
2981 block
->predecessors_count
= nblock
->predecessors
->entries
;
2982 block
->predecessors
= ralloc_array_size(block
,
2983 sizeof(block
->predecessors
[0]), block
->predecessors_count
);
2985 set_foreach(nblock
->predecessors
, sentry
) {
2986 block
->predecessors
[i
++] = get_block(ctx
, sentry
->key
);
2993 emit_block(struct ir3_context
*ctx
, nir_block
*nblock
)
2995 struct ir3_block
*block
= get_block(ctx
, nblock
);
2997 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
2998 if (nblock
->successors
[i
]) {
2999 block
->successors
[i
] =
3000 get_block(ctx
, nblock
->successors
[i
]);
3005 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
3007 /* re-emit addr register in each block if needed: */
3008 for (int i
= 0; i
< ARRAY_SIZE(ctx
->addr_ht
); i
++) {
3009 _mesa_hash_table_destroy(ctx
->addr_ht
[i
], NULL
);
3010 ctx
->addr_ht
[i
] = NULL
;
3013 nir_foreach_instr(instr
, nblock
) {
3014 ctx
->cur_instr
= instr
;
3015 emit_instr(ctx
, instr
);
3016 ctx
->cur_instr
= NULL
;
3022 static void emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
);
3025 emit_if(struct ir3_context
*ctx
, nir_if
*nif
)
3027 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
3029 ctx
->block
->condition
=
3030 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
3032 emit_cf_list(ctx
, &nif
->then_list
);
3033 emit_cf_list(ctx
, &nif
->else_list
);
3037 emit_loop(struct ir3_context
*ctx
, nir_loop
*nloop
)
3039 emit_cf_list(ctx
, &nloop
->body
);
3043 emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
)
3045 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
3046 switch (node
->type
) {
3047 case nir_cf_node_block
:
3048 emit_block(ctx
, nir_cf_node_as_block(node
));
3050 case nir_cf_node_if
:
3051 emit_if(ctx
, nir_cf_node_as_if(node
));
3053 case nir_cf_node_loop
:
3054 emit_loop(ctx
, nir_cf_node_as_loop(node
));
3056 case nir_cf_node_function
:
3057 compile_error(ctx
, "TODO\n");
3063 /* emit stream-out code. At this point, the current block is the original
3064 * (nir) end block, and nir ensures that all flow control paths terminate
3065 * into the end block. We re-purpose the original end block to generate
3066 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
3067 * block holding stream-out write instructions, followed by the new end
3071 * p0.x = (vtxcnt < maxvtxcnt)
3072 * // succs: blockStreamOut, blockNewEnd
3075 * ... stream-out instructions ...
3076 * // succs: blockNewEnd
3082 emit_stream_out(struct ir3_context
*ctx
)
3084 struct ir3_shader_variant
*v
= ctx
->so
;
3085 struct ir3
*ir
= ctx
->ir
;
3086 struct pipe_stream_output_info
*strmout
=
3087 &ctx
->so
->shader
->stream_output
;
3088 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
3089 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
3090 struct ir3_instruction
*bases
[PIPE_MAX_SO_BUFFERS
];
3092 /* create vtxcnt input in input block at top of shader,
3093 * so that it is seen as live over the entire duration
3096 vtxcnt
= create_input(ctx
, 0);
3097 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
3099 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
3101 /* at this point, we are at the original 'end' block,
3102 * re-purpose this block to stream-out condition, then
3103 * append stream-out block and new-end block
3105 orig_end_block
= ctx
->block
;
3107 // TODO these blocks need to update predecessors..
3108 // maybe w/ store_global intrinsic, we could do this
3109 // stuff in nir->nir pass
3111 stream_out_block
= ir3_block_create(ir
);
3112 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
3114 new_end_block
= ir3_block_create(ir
);
3115 list_addtail(&new_end_block
->node
, &ir
->block_list
);
3117 orig_end_block
->successors
[0] = stream_out_block
;
3118 orig_end_block
->successors
[1] = new_end_block
;
3119 stream_out_block
->successors
[0] = new_end_block
;
3121 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
3122 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
3123 cond
->regs
[0]->num
= regid(REG_P0
, 0);
3124 cond
->cat2
.condition
= IR3_COND_LT
;
3126 /* condition goes on previous block to the conditional,
3127 * since it is used to pick which of the two successor
3130 orig_end_block
->condition
= cond
;
3132 /* switch to stream_out_block to generate the stream-out
3135 ctx
->block
= stream_out_block
;
3137 /* Calculate base addresses based on vtxcnt. Instructions
3138 * generated for bases not used in following loop will be
3139 * stripped out in the backend.
3141 for (unsigned i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
3142 unsigned stride
= strmout
->stride
[i
];
3143 struct ir3_instruction
*base
, *off
;
3145 base
= create_uniform(ctx
, regid(v
->constbase
.tfbo
, i
));
3147 /* 24-bit should be enough: */
3148 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
3149 create_immed(ctx
->block
, stride
* 4), 0);
3151 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
3154 /* Generate the per-output store instructions: */
3155 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
3156 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
3157 unsigned c
= j
+ strmout
->output
[i
].start_component
;
3158 struct ir3_instruction
*base
, *out
, *stg
;
3160 base
= bases
[strmout
->output
[i
].output_buffer
];
3161 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
3163 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
3164 create_immed(ctx
->block
, 1), 0);
3165 stg
->cat6
.type
= TYPE_U32
;
3166 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
3168 array_insert(ctx
->block
, ctx
->block
->keeps
, stg
);
3172 /* and finally switch to the new_end_block: */
3173 ctx
->block
= new_end_block
;
3177 emit_function(struct ir3_context
*ctx
, nir_function_impl
*impl
)
3179 nir_metadata_require(impl
, nir_metadata_block_index
);
3181 emit_cf_list(ctx
, &impl
->body
);
3182 emit_block(ctx
, impl
->end_block
);
3184 /* at this point, we should have a single empty block,
3185 * into which we emit the 'end' instruction.
3187 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
3189 /* If stream-out (aka transform-feedback) enabled, emit the
3190 * stream-out instructions, followed by a new empty block (into
3191 * which the 'end' instruction lands).
3193 * NOTE: it is done in this order, rather than inserting before
3194 * we emit end_block, because NIR guarantees that all blocks
3195 * flow into end_block, and that end_block has no successors.
3196 * So by re-purposing end_block as the first block of stream-
3197 * out, we guarantee that all exit paths flow into the stream-
3200 if ((ctx
->compiler
->gpu_id
< 500) &&
3201 (ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
3202 !ctx
->so
->key
.binning_pass
) {
3203 debug_assert(ctx
->so
->type
== SHADER_VERTEX
);
3204 emit_stream_out(ctx
);
3207 ir3_END(ctx
->block
);
3210 static struct ir3_instruction
*
3211 create_frag_coord(struct ir3_context
*ctx
, unsigned comp
)
3213 struct ir3_block
*block
= ctx
->block
;
3214 struct ir3_instruction
*instr
;
3216 if (!ctx
->frag_coord
) {
3217 ctx
->frag_coord
= create_input_compmask(ctx
, 0, 0xf);
3218 /* defer add_sysval_input() until after all inputs created */
3221 split_dest(block
, &instr
, ctx
->frag_coord
, comp
, 1);
3226 /* for frag_coord, we get unsigned values.. we need
3227 * to subtract (integer) 8 and divide by 16 (right-
3228 * shift by 4) then convert to float:
3232 * mov.u32f32 dst, tmp
3235 instr
= ir3_SUB_S(block
, instr
, 0,
3236 create_immed(block
, 8), 0);
3237 instr
= ir3_SHR_B(block
, instr
, 0,
3238 create_immed(block
, 4), 0);
3239 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
3245 /* seems that we can use these as-is: */
3251 setup_input(struct ir3_context
*ctx
, nir_variable
*in
)
3253 struct ir3_shader_variant
*so
= ctx
->so
;
3254 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
3255 unsigned ncomp
= glsl_get_components(in
->type
);
3256 unsigned n
= in
->data
.driver_location
;
3257 unsigned slot
= in
->data
.location
;
3259 DBG("; in: slot=%u, len=%ux%u, drvloc=%u",
3260 slot
, array_len
, ncomp
, n
);
3262 /* let's pretend things other than vec4 don't exist: */
3263 ncomp
= MAX2(ncomp
, 4);
3265 /* skip unread inputs, we could end up with (for example), unsplit
3266 * matrix/etc inputs in the case they are not read, so just silently
3272 compile_assert(ctx
, ncomp
== 4);
3274 so
->inputs
[n
].slot
= slot
;
3275 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
3276 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
3277 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
3279 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3280 for (int i
= 0; i
< ncomp
; i
++) {
3281 struct ir3_instruction
*instr
= NULL
;
3282 unsigned idx
= (n
* 4) + i
;
3284 if (slot
== VARYING_SLOT_POS
) {
3285 so
->inputs
[n
].bary
= false;
3286 so
->frag_coord
= true;
3287 instr
= create_frag_coord(ctx
, i
);
3288 } else if (slot
== VARYING_SLOT_PNTC
) {
3289 /* see for example st_nir_fixup_varying_slots().. this is
3290 * maybe a bit mesa/st specific. But we need things to line
3291 * up for this in fdN_program:
3292 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
3293 * if (emit->sprite_coord_enable & texmask) {
3297 so
->inputs
[n
].slot
= VARYING_SLOT_VAR8
;
3298 so
->inputs
[n
].bary
= true;
3299 instr
= create_frag_input(ctx
, false);
3301 bool use_ldlv
= false;
3303 /* detect the special case for front/back colors where
3304 * we need to do flat vs smooth shading depending on
3307 if (in
->data
.interpolation
== INTERP_MODE_NONE
) {
3309 case VARYING_SLOT_COL0
:
3310 case VARYING_SLOT_COL1
:
3311 case VARYING_SLOT_BFC0
:
3312 case VARYING_SLOT_BFC1
:
3313 so
->inputs
[n
].rasterflat
= true;
3320 if (ctx
->compiler
->flat_bypass
) {
3321 if ((so
->inputs
[n
].interpolate
== INTERP_MODE_FLAT
) ||
3322 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
3326 so
->inputs
[n
].bary
= true;
3328 instr
= create_frag_input(ctx
, use_ldlv
);
3331 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
3333 ctx
->ir
->inputs
[idx
] = instr
;
3335 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
3336 for (int i
= 0; i
< ncomp
; i
++) {
3337 unsigned idx
= (n
* 4) + i
;
3338 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
3339 ctx
->ir
->inputs
[idx
] = create_input(ctx
, idx
);
3342 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3345 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
3346 so
->total_in
+= ncomp
;
3351 setup_output(struct ir3_context
*ctx
, nir_variable
*out
)
3353 struct ir3_shader_variant
*so
= ctx
->so
;
3354 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
3355 unsigned ncomp
= glsl_get_components(out
->type
);
3356 unsigned n
= out
->data
.driver_location
;
3357 unsigned slot
= out
->data
.location
;
3360 DBG("; out: slot=%u, len=%ux%u, drvloc=%u",
3361 slot
, array_len
, ncomp
, n
);
3363 /* let's pretend things other than vec4 don't exist: */
3364 ncomp
= MAX2(ncomp
, 4);
3365 compile_assert(ctx
, ncomp
== 4);
3367 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3369 case FRAG_RESULT_DEPTH
:
3370 comp
= 2; /* tgsi will write to .z component */
3371 so
->writes_pos
= true;
3373 case FRAG_RESULT_COLOR
:
3377 if (slot
>= FRAG_RESULT_DATA0
)
3379 compile_error(ctx
, "unknown FS output name: %s\n",
3380 gl_frag_result_name(slot
));
3382 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
3384 case VARYING_SLOT_POS
:
3385 so
->writes_pos
= true;
3387 case VARYING_SLOT_PSIZ
:
3388 so
->writes_psize
= true;
3390 case VARYING_SLOT_COL0
:
3391 case VARYING_SLOT_COL1
:
3392 case VARYING_SLOT_BFC0
:
3393 case VARYING_SLOT_BFC1
:
3394 case VARYING_SLOT_FOGC
:
3395 case VARYING_SLOT_CLIP_DIST0
:
3396 case VARYING_SLOT_CLIP_DIST1
:
3397 case VARYING_SLOT_CLIP_VERTEX
:
3400 if (slot
>= VARYING_SLOT_VAR0
)
3402 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
3404 compile_error(ctx
, "unknown VS output name: %s\n",
3405 gl_varying_slot_name(slot
));
3408 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3411 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
3413 so
->outputs
[n
].slot
= slot
;
3414 so
->outputs
[n
].regid
= regid(n
, comp
);
3415 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
3417 for (int i
= 0; i
< ncomp
; i
++) {
3418 unsigned idx
= (n
* 4) + i
;
3419 compile_assert(ctx
, idx
< ctx
->ir
->noutputs
);
3420 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
3425 max_drvloc(struct exec_list
*vars
)
3428 nir_foreach_variable(var
, vars
) {
3429 drvloc
= MAX2(drvloc
, (int)var
->data
.driver_location
);
3434 static const unsigned max_sysvals
[SHADER_MAX
] = {
3435 [SHADER_FRAGMENT
] = 24, // TODO
3436 [SHADER_VERTEX
] = 16,
3437 [SHADER_COMPUTE
] = 16, // TODO how many do we actually need?
3441 emit_instructions(struct ir3_context
*ctx
)
3443 unsigned ninputs
, noutputs
;
3444 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
3446 ninputs
= (max_drvloc(&ctx
->s
->inputs
) + 1) * 4;
3447 noutputs
= (max_drvloc(&ctx
->s
->outputs
) + 1) * 4;
3449 /* we need to leave room for sysvals:
3451 ninputs
+= max_sysvals
[ctx
->so
->type
];
3453 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
3455 /* Create inputs in first block: */
3456 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
3457 ctx
->in_block
= ctx
->block
;
3458 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
3460 ninputs
-= max_sysvals
[ctx
->so
->type
];
3462 /* for fragment shader, the vcoord input register is used as the
3463 * base for bary.f varying fetch instrs:
3465 struct ir3_instruction
*vcoord
= NULL
;
3466 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3467 struct ir3_instruction
*xy
[2];
3469 vcoord
= create_input_compmask(ctx
, 0, 0x3);
3470 split_dest(ctx
->block
, xy
, vcoord
, 0, 2);
3472 ctx
->frag_vcoord
= create_collect(ctx
, xy
, 2);
3476 nir_foreach_variable(var
, &ctx
->s
->inputs
) {
3477 setup_input(ctx
, var
);
3480 /* Defer add_sysval_input() stuff until after setup_inputs(),
3481 * because sysvals need to be appended after varyings:
3484 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_VARYING_COORD
,
3488 if (ctx
->frag_coord
) {
3489 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_FRAG_COORD
,
3490 0xf, ctx
->frag_coord
);
3493 /* Setup outputs: */
3494 nir_foreach_variable(var
, &ctx
->s
->outputs
) {
3495 setup_output(ctx
, var
);
3498 /* Setup registers (which should only be arrays): */
3499 nir_foreach_register(reg
, &ctx
->s
->registers
) {
3500 declare_array(ctx
, reg
);
3503 /* NOTE: need to do something more clever when we support >1 fxn */
3504 nir_foreach_register(reg
, &fxn
->registers
) {
3505 declare_array(ctx
, reg
);
3507 /* And emit the body: */
3509 emit_function(ctx
, fxn
);
3512 /* from NIR perspective, we actually have varying inputs. But the varying
3513 * inputs, from an IR standpoint, are just bary.f/ldlv instructions. The
3514 * only actual inputs are the sysvals.
3517 fixup_frag_inputs(struct ir3_context
*ctx
)
3519 struct ir3_shader_variant
*so
= ctx
->so
;
3520 struct ir3
*ir
= ctx
->ir
;
3523 /* sysvals should appear at the end of the inputs, drop everything else: */
3524 while ((i
< so
->inputs_count
) && !so
->inputs
[i
].sysval
)
3527 /* at IR level, inputs are always blocks of 4 scalars: */
3530 ir
->inputs
= &ir
->inputs
[i
];
3534 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3535 * need to assign the tex state indexes for these after we know the
3539 fixup_astc_srgb(struct ir3_context
*ctx
)
3541 struct ir3_shader_variant
*so
= ctx
->so
;
3542 /* indexed by original tex idx, value is newly assigned alpha sampler
3543 * state tex idx. Zero is invalid since there is at least one sampler
3546 unsigned alt_tex_state
[16] = {0};
3547 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
3550 so
->astc_srgb
.base
= tex_idx
;
3552 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
3553 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
3555 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
3557 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
3558 /* assign new alternate/alpha tex state slot: */
3559 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
3560 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
3561 so
->astc_srgb
.count
++;
3564 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
3569 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
3570 struct ir3_shader_variant
*so
)
3572 struct ir3_context
*ctx
;
3574 struct ir3_instruction
**inputs
;
3575 unsigned i
, j
, actual_in
, inloc
;
3576 int ret
= 0, max_bary
;
3580 ctx
= compile_init(compiler
, so
);
3582 DBG("INIT failed!");
3587 emit_instructions(ctx
);
3590 DBG("EMIT failed!");
3595 ir
= so
->ir
= ctx
->ir
;
3597 /* keep track of the inputs from TGSI perspective.. */
3598 inputs
= ir
->inputs
;
3600 /* but fixup actual inputs for frag shader: */
3601 if (so
->type
== SHADER_FRAGMENT
)
3602 fixup_frag_inputs(ctx
);
3604 /* at this point, for binning pass, throw away unneeded outputs: */
3605 if (so
->key
.binning_pass
) {
3606 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
3607 unsigned slot
= so
->outputs
[i
].slot
;
3609 /* throw away everything but first position/psize */
3610 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
3612 so
->outputs
[j
] = so
->outputs
[i
];
3613 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
3614 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
3615 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
3616 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
3621 so
->outputs_count
= j
;
3622 ir
->noutputs
= j
* 4;
3625 /* if we want half-precision outputs, mark the output registers
3628 if (so
->key
.half_precision
) {
3629 for (i
= 0; i
< ir
->noutputs
; i
++) {
3630 struct ir3_instruction
*out
= ir
->outputs
[i
];
3635 /* if frag shader writes z, that needs to be full precision: */
3636 if (so
->outputs
[i
/4].slot
== FRAG_RESULT_DEPTH
)
3639 out
->regs
[0]->flags
|= IR3_REG_HALF
;
3640 /* output could be a fanout (ie. texture fetch output)
3641 * in which case we need to propagate the half-reg flag
3642 * up to the definer so that RA sees it:
3644 if (out
->opc
== OPC_META_FO
) {
3645 out
= out
->regs
[1]->instr
;
3646 out
->regs
[0]->flags
|= IR3_REG_HALF
;
3649 if (out
->opc
== OPC_MOV
) {
3650 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
3655 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3656 printf("BEFORE CP:\n");
3662 /* Insert mov if there's same instruction for each output.
3663 * eg. dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_expression.vertex.sampler2dshadow
3665 for (int i
= ir
->noutputs
- 1; i
>= 0; i
--) {
3666 if (!ir
->outputs
[i
])
3668 for (unsigned j
= 0; j
< i
; j
++) {
3669 if (ir
->outputs
[i
] == ir
->outputs
[j
]) {
3671 ir3_MOV(ir
->outputs
[i
]->block
, ir
->outputs
[i
], TYPE_F32
);
3676 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3677 printf("BEFORE GROUPING:\n");
3681 ir3_sched_add_deps(ir
);
3683 /* Group left/right neighbors, inserting mov's where needed to
3688 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3689 printf("AFTER GROUPING:\n");
3695 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3696 printf("AFTER DEPTH:\n");
3700 ret
= ir3_sched(ir
);
3702 DBG("SCHED failed!");
3706 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3707 printf("AFTER SCHED:\n");
3711 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
3717 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3718 printf("AFTER RA:\n");
3722 /* fixup input/outputs: */
3723 for (i
= 0; i
< so
->outputs_count
; i
++) {
3724 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
3727 /* Note that some or all channels of an input may be unused: */
3730 for (i
= 0; i
< so
->inputs_count
; i
++) {
3731 unsigned j
, reg
= regid(63,0), compmask
= 0, maxcomp
= 0;
3732 so
->inputs
[i
].ncomp
= 0;
3733 so
->inputs
[i
].inloc
= inloc
;
3734 for (j
= 0; j
< 4; j
++) {
3735 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
3736 if (in
&& !(in
->flags
& IR3_INSTR_UNUSED
)) {
3737 compmask
|= (1 << j
);
3738 reg
= in
->regs
[0]->num
- j
;
3740 so
->inputs
[i
].ncomp
++;
3741 if ((so
->type
== SHADER_FRAGMENT
) && so
->inputs
[i
].bary
) {
3743 assert(in
->regs
[1]->flags
& IR3_REG_IMMED
);
3744 in
->regs
[1]->iim_val
= inloc
+ j
;
3749 if ((so
->type
== SHADER_FRAGMENT
) && compmask
&& so
->inputs
[i
].bary
) {
3751 so
->inputs
[i
].compmask
= (1 << maxcomp
) - 1;
3753 } else if (!so
->inputs
[i
].sysval
) {
3754 so
->inputs
[i
].compmask
= compmask
;
3756 so
->inputs
[i
].regid
= reg
;
3760 fixup_astc_srgb(ctx
);
3762 /* We need to do legalize after (for frag shader's) the "bary.f"
3763 * offsets (inloc) have been assigned.
3765 ir3_legalize(ir
, &so
->has_samp
, &so
->has_ssbo
, &max_bary
);
3767 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3768 printf("AFTER LEGALIZE:\n");
3772 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3773 if (so
->type
== SHADER_VERTEX
)
3774 so
->total_in
= actual_in
;
3776 so
->total_in
= max_bary
+ 1;
3781 ir3_destroy(so
->ir
);