1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
36 #include "freedreno_util.h"
38 #include "ir3_compiler.h"
39 #include "ir3_shader.h"
42 #include "instr-a3xx.h"
47 struct ir3_compiler
*compiler
;
52 struct ir3_shader_variant
*so
;
54 struct ir3_block
*block
; /* the current block */
55 struct ir3_block
*in_block
; /* block created for shader inputs */
57 nir_function_impl
*impl
;
59 /* For fragment shaders, from the hw perspective the only
60 * actual input is r0.xy position register passed to bary.f.
61 * But TGSI doesn't know that, it still declares things as
62 * IN[] registers. So we do all the input tracking normally
63 * and fix things up after compile_instructions()
65 * NOTE that frag_pos is the hardware position (possibly it
66 * is actually an index or tag or some such.. it is *not*
67 * values that can be directly used for gl_FragCoord..)
69 struct ir3_instruction
*frag_pos
, *frag_face
, *frag_coord
[4];
71 /* For vertex shaders, keep track of the system values sources */
72 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
74 /* Compute shader inputs: */
75 struct ir3_instruction
*local_invocation_id
, *work_group_id
;
77 /* mapping from nir_register to defining instruction: */
78 struct hash_table
*def_ht
;
82 /* a common pattern for indirect addressing is to request the
83 * same address register multiple times. To avoid generating
84 * duplicate instruction sequences (which our backend does not
85 * try to clean up, since that should be done as the NIR stage)
86 * we cache the address value generated for a given src value:
88 * Note that we have to cache these per alignment, since same
89 * src used for an array of vec1 cannot be also used for an
92 struct hash_table
*addr_ht
[4];
94 /* last dst array, for indirect we need to insert a var-store.
96 struct ir3_instruction
**last_dst
;
99 /* maps nir_block to ir3_block, mostly for the purposes of
100 * figuring out the blocks successors
102 struct hash_table
*block_ht
;
104 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
105 * so we need to use ldlv.u32 to load the varying directly:
109 /* on a3xx, we need to add one to # of array levels:
113 /* on a3xx, we need to scale up integer coords for isaml based
116 bool unminify_coords
;
118 /* on a4xx, for array textures we need to add 0.5 to the array
121 bool array_index_add_half
;
123 /* on a4xx, bitmask of samplers which need astc+srgb workaround: */
126 unsigned max_texture_index
;
128 /* set if we encounter something we can't handle yet, so we
129 * can bail cleanly and fallback to TGSI compiler f/e
134 /* gpu pointer size in units of 32bit registers/slots */
135 static unsigned pointer_size(struct ir3_context
*ctx
)
137 return (ctx
->compiler
->gpu_id
>= 500) ? 2 : 1;
140 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
141 static struct ir3_block
* get_block(struct ir3_context
*ctx
, const nir_block
*nblock
);
144 static struct ir3_context
*
145 compile_init(struct ir3_compiler
*compiler
,
146 struct ir3_shader_variant
*so
)
148 struct ir3_context
*ctx
= rzalloc(NULL
, struct ir3_context
);
150 if (compiler
->gpu_id
>= 400) {
151 /* need special handling for "flat" */
152 ctx
->flat_bypass
= true;
153 ctx
->levels_add_one
= false;
154 ctx
->unminify_coords
= false;
155 ctx
->array_index_add_half
= true;
157 if (so
->type
== SHADER_VERTEX
)
158 ctx
->astc_srgb
= so
->key
.vastc_srgb
;
159 else if (so
->type
== SHADER_FRAGMENT
)
160 ctx
->astc_srgb
= so
->key
.fastc_srgb
;
163 /* no special handling for "flat" */
164 ctx
->flat_bypass
= false;
165 ctx
->levels_add_one
= true;
166 ctx
->unminify_coords
= true;
167 ctx
->array_index_add_half
= false;
170 ctx
->compiler
= compiler
;
173 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
174 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
175 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
176 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
178 /* TODO: maybe generate some sort of bitmask of what key
179 * lowers vs what shader has (ie. no need to lower
180 * texture clamp lowering if no texture sample instrs)..
181 * although should be done further up the stack to avoid
182 * creating duplicate variants..
185 if (ir3_key_lowers_nir(&so
->key
)) {
186 nir_shader
*s
= nir_shader_clone(ctx
, so
->shader
->nir
);
187 ctx
->s
= ir3_optimize_nir(so
->shader
, s
, &so
->key
);
189 /* fast-path for shader key that lowers nothing in NIR: */
190 ctx
->s
= so
->shader
->nir
;
193 /* this needs to be the last pass run, so do this here instead of
194 * in ir3_optimize_nir():
196 NIR_PASS_V(ctx
->s
, nir_lower_locals_to_regs
);
197 NIR_PASS_V(ctx
->s
, nir_convert_from_ssa
, true);
199 if (fd_mesa_debug
& FD_DBG_DISASM
) {
200 DBG("dump nir%dv%d: type=%d, k={bp=%u,cts=%u,hp=%u}",
201 so
->shader
->id
, so
->id
, so
->type
,
202 so
->key
.binning_pass
, so
->key
.color_two_side
,
203 so
->key
.half_precision
);
204 nir_print_shader(ctx
->s
, stdout
);
207 ir3_nir_scan_driver_consts(ctx
->s
, &so
->const_layout
);
209 so
->num_uniforms
= ctx
->s
->num_uniforms
;
210 so
->num_ubos
= ctx
->s
->info
.num_ubos
;
212 /* Layout of constant registers, each section aligned to vec4. Note
213 * that pointer size (ubo, etc) changes depending on generation.
218 * if (vertex shader) {
219 * driver params (IR3_DP_*)
220 * if (stream_output.num_outputs > 0)
221 * stream-out addresses
225 * Immediates go last mostly because they are inserted in the CP pass
226 * after the nir -> ir3 frontend.
228 unsigned constoff
= align(ctx
->s
->num_uniforms
, 4);
229 unsigned ptrsz
= pointer_size(ctx
);
231 memset(&so
->constbase
, ~0, sizeof(so
->constbase
));
233 if (so
->num_ubos
> 0) {
234 so
->constbase
.ubo
= constoff
;
235 constoff
+= align(ctx
->s
->info
.num_ubos
* ptrsz
, 4) / 4;
238 if (so
->const_layout
.ssbo_size
.count
> 0) {
239 unsigned cnt
= so
->const_layout
.ssbo_size
.count
;
240 so
->constbase
.ssbo_sizes
= constoff
;
241 constoff
+= align(cnt
, 4) / 4;
244 if (so
->const_layout
.image_dims
.count
> 0) {
245 unsigned cnt
= so
->const_layout
.image_dims
.count
;
246 so
->constbase
.image_dims
= constoff
;
247 constoff
+= align(cnt
, 4) / 4;
250 unsigned num_driver_params
= 0;
251 if (so
->type
== SHADER_VERTEX
) {
252 num_driver_params
= IR3_DP_VS_COUNT
;
253 } else if (so
->type
== SHADER_COMPUTE
) {
254 num_driver_params
= IR3_DP_CS_COUNT
;
257 so
->constbase
.driver_param
= constoff
;
258 constoff
+= align(num_driver_params
, 4) / 4;
260 if ((so
->type
== SHADER_VERTEX
) &&
261 (compiler
->gpu_id
< 500) &&
262 so
->shader
->stream_output
.num_outputs
> 0) {
263 so
->constbase
.tfbo
= constoff
;
264 constoff
+= align(PIPE_MAX_SO_BUFFERS
* ptrsz
, 4) / 4;
267 so
->constbase
.immediate
= constoff
;
273 compile_error(struct ir3_context
*ctx
, const char *format
, ...)
276 va_start(ap
, format
);
277 _debug_vprintf(format
, ap
);
279 nir_print_shader(ctx
->s
, stdout
);
284 #define compile_assert(ctx, cond) do { \
285 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
289 compile_free(struct ir3_context
*ctx
)
295 declare_array(struct ir3_context
*ctx
, nir_register
*reg
)
297 struct ir3_array
*arr
= rzalloc(ctx
, struct ir3_array
);
298 arr
->id
= ++ctx
->num_arrays
;
299 /* NOTE: sometimes we get non array regs, for example for arrays of
300 * length 1. See fs-const-array-of-struct-of-array.shader_test. So
301 * treat a non-array as if it was an array of length 1.
303 * It would be nice if there was a nir pass to convert arrays of
306 arr
->length
= reg
->num_components
* MAX2(1, reg
->num_array_elems
);
307 compile_assert(ctx
, arr
->length
> 0);
309 list_addtail(&arr
->node
, &ctx
->ir
->array_list
);
312 static struct ir3_array
*
313 get_array(struct ir3_context
*ctx
, nir_register
*reg
)
315 list_for_each_entry (struct ir3_array
, arr
, &ctx
->ir
->array_list
, node
) {
319 compile_error(ctx
, "bogus reg: %s\n", reg
->name
);
323 /* relative (indirect) if address!=NULL */
324 static struct ir3_instruction
*
325 create_array_load(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
326 struct ir3_instruction
*address
)
328 struct ir3_block
*block
= ctx
->block
;
329 struct ir3_instruction
*mov
;
330 struct ir3_register
*src
;
332 mov
= ir3_instr_create(block
, OPC_MOV
);
333 mov
->cat1
.src_type
= TYPE_U32
;
334 mov
->cat1
.dst_type
= TYPE_U32
;
335 mov
->barrier_class
= IR3_BARRIER_ARRAY_R
;
336 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_W
;
337 ir3_reg_create(mov
, 0, 0);
338 src
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
339 COND(address
, IR3_REG_RELATIV
));
340 src
->instr
= arr
->last_write
;
341 src
->size
= arr
->length
;
342 src
->array
.id
= arr
->id
;
343 src
->array
.offset
= n
;
346 ir3_instr_set_address(mov
, address
);
351 /* relative (indirect) if address!=NULL */
353 create_array_store(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
354 struct ir3_instruction
*src
, struct ir3_instruction
*address
)
356 struct ir3_block
*block
= ctx
->block
;
357 struct ir3_instruction
*mov
;
358 struct ir3_register
*dst
;
360 /* if not relative store, don't create an extra mov, since that
361 * ends up being difficult for cp to remove.
366 src
->barrier_class
|= IR3_BARRIER_ARRAY_W
;
367 src
->barrier_conflict
|= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
369 dst
->flags
|= IR3_REG_ARRAY
;
370 dst
->instr
= arr
->last_write
;
371 dst
->size
= arr
->length
;
372 dst
->array
.id
= arr
->id
;
373 dst
->array
.offset
= n
;
375 arr
->last_write
= src
;
377 array_insert(block
, block
->keeps
, src
);
382 mov
= ir3_instr_create(block
, OPC_MOV
);
383 mov
->cat1
.src_type
= TYPE_U32
;
384 mov
->cat1
.dst_type
= TYPE_U32
;
385 mov
->barrier_class
= IR3_BARRIER_ARRAY_W
;
386 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
387 dst
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
388 COND(address
, IR3_REG_RELATIV
));
389 dst
->instr
= arr
->last_write
;
390 dst
->size
= arr
->length
;
391 dst
->array
.id
= arr
->id
;
392 dst
->array
.offset
= n
;
393 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
396 ir3_instr_set_address(mov
, address
);
398 arr
->last_write
= mov
;
400 /* the array store may only matter to something in an earlier
401 * block (ie. loops), but since arrays are not in SSA, depth
402 * pass won't know this.. so keep all array stores:
404 array_insert(block
, block
->keeps
, mov
);
407 /* allocate a n element value array (to be populated by caller) and
410 static struct ir3_instruction
**
411 get_dst_ssa(struct ir3_context
*ctx
, nir_ssa_def
*dst
, unsigned n
)
413 struct ir3_instruction
**value
=
414 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
415 _mesa_hash_table_insert(ctx
->def_ht
, dst
, value
);
419 static struct ir3_instruction
**
420 get_dst(struct ir3_context
*ctx
, nir_dest
*dst
, unsigned n
)
422 struct ir3_instruction
**value
;
425 value
= get_dst_ssa(ctx
, &dst
->ssa
, n
);
427 value
= ralloc_array(ctx
, struct ir3_instruction
*, n
);
430 /* NOTE: in non-ssa case, we don't really need to store last_dst
431 * but this helps us catch cases where put_dst() call is forgotten
433 compile_assert(ctx
, !ctx
->last_dst
);
434 ctx
->last_dst
= value
;
440 static struct ir3_instruction
* get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
);
442 static struct ir3_instruction
* const *
443 get_src(struct ir3_context
*ctx
, nir_src
*src
)
446 struct hash_entry
*entry
;
447 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
448 compile_assert(ctx
, entry
);
451 nir_register
*reg
= src
->reg
.reg
;
452 struct ir3_array
*arr
= get_array(ctx
, reg
);
453 unsigned num_components
= arr
->r
->num_components
;
454 struct ir3_instruction
*addr
= NULL
;
455 struct ir3_instruction
**value
=
456 ralloc_array(ctx
, struct ir3_instruction
*, num_components
);
458 if (src
->reg
.indirect
)
459 addr
= get_addr(ctx
, get_src(ctx
, src
->reg
.indirect
)[0],
460 reg
->num_components
);
462 for (unsigned i
= 0; i
< num_components
; i
++) {
463 unsigned n
= src
->reg
.base_offset
* reg
->num_components
+ i
;
464 compile_assert(ctx
, n
< arr
->length
);
465 value
[i
] = create_array_load(ctx
, arr
, n
, addr
);
473 put_dst(struct ir3_context
*ctx
, nir_dest
*dst
)
475 unsigned bit_size
= nir_dest_bit_size(*dst
);
478 for (unsigned i
= 0; i
< ctx
->last_dst_n
; i
++) {
479 ctx
->last_dst
[i
]->regs
[0]->flags
|= IR3_REG_HALF
;
484 nir_register
*reg
= dst
->reg
.reg
;
485 struct ir3_array
*arr
= get_array(ctx
, reg
);
486 unsigned num_components
= ctx
->last_dst_n
;
487 struct ir3_instruction
*addr
= NULL
;
489 if (dst
->reg
.indirect
)
490 addr
= get_addr(ctx
, get_src(ctx
, dst
->reg
.indirect
)[0],
491 reg
->num_components
);
493 for (unsigned i
= 0; i
< num_components
; i
++) {
494 unsigned n
= dst
->reg
.base_offset
* reg
->num_components
+ i
;
495 compile_assert(ctx
, n
< arr
->length
);
496 if (!ctx
->last_dst
[i
])
498 create_array_store(ctx
, arr
, n
, ctx
->last_dst
[i
], addr
);
501 ralloc_free(ctx
->last_dst
);
503 ctx
->last_dst
= NULL
;
507 static struct ir3_instruction
*
508 create_immed(struct ir3_block
*block
, uint32_t val
)
510 struct ir3_instruction
*mov
;
512 mov
= ir3_instr_create(block
, OPC_MOV
);
513 mov
->cat1
.src_type
= TYPE_U32
;
514 mov
->cat1
.dst_type
= TYPE_U32
;
515 ir3_reg_create(mov
, 0, 0);
516 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
521 static struct ir3_instruction
*
522 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
, int align
)
524 struct ir3_instruction
*instr
, *immed
;
526 /* TODO in at least some cases, the backend could probably be
527 * made clever enough to propagate IR3_REG_HALF..
529 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
530 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
537 /* src *= 2 => src <<= 1: */
538 immed
= create_immed(block
, 1);
539 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
541 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
542 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
543 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
547 immed
= create_immed(block
, 3);
548 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
550 instr
= ir3_MULL_U(block
, instr
, 0, immed
, 0);
551 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
552 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
555 /* src *= 4 => src <<= 2: */
556 immed
= create_immed(block
, 2);
557 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
559 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
560 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
561 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
564 unreachable("bad align");
568 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
569 instr
->regs
[0]->num
= regid(REG_A0
, 0);
570 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
571 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
576 /* caches addr values to avoid generating multiple cov/shl/mova
577 * sequences for each use of a given NIR level src as address
579 static struct ir3_instruction
*
580 get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
)
582 struct ir3_instruction
*addr
;
583 unsigned idx
= align
- 1;
585 compile_assert(ctx
, idx
< ARRAY_SIZE(ctx
->addr_ht
));
587 if (!ctx
->addr_ht
[idx
]) {
588 ctx
->addr_ht
[idx
] = _mesa_hash_table_create(ctx
,
589 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
591 struct hash_entry
*entry
;
592 entry
= _mesa_hash_table_search(ctx
->addr_ht
[idx
], src
);
597 addr
= create_addr(ctx
->block
, src
, align
);
598 _mesa_hash_table_insert(ctx
->addr_ht
[idx
], src
, addr
);
603 static struct ir3_instruction
*
604 get_predicate(struct ir3_context
*ctx
, struct ir3_instruction
*src
)
606 struct ir3_block
*b
= ctx
->block
;
607 struct ir3_instruction
*cond
;
609 /* NOTE: only cmps.*.* can write p0.x: */
610 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
611 cond
->cat2
.condition
= IR3_COND_NE
;
613 /* condition always goes in predicate register: */
614 cond
->regs
[0]->num
= regid(REG_P0
, 0);
619 static struct ir3_instruction
*
620 create_uniform(struct ir3_context
*ctx
, unsigned n
)
622 struct ir3_instruction
*mov
;
624 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
625 /* TODO get types right? */
626 mov
->cat1
.src_type
= TYPE_F32
;
627 mov
->cat1
.dst_type
= TYPE_F32
;
628 ir3_reg_create(mov
, 0, 0);
629 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
634 static struct ir3_instruction
*
635 create_uniform_indirect(struct ir3_context
*ctx
, int n
,
636 struct ir3_instruction
*address
)
638 struct ir3_instruction
*mov
;
640 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
641 mov
->cat1
.src_type
= TYPE_U32
;
642 mov
->cat1
.dst_type
= TYPE_U32
;
643 ir3_reg_create(mov
, 0, 0);
644 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
646 ir3_instr_set_address(mov
, address
);
651 static struct ir3_instruction
*
652 create_collect(struct ir3_context
*ctx
, struct ir3_instruction
*const *arr
,
655 struct ir3_block
*block
= ctx
->block
;
656 struct ir3_instruction
*collect
;
661 collect
= ir3_instr_create2(block
, OPC_META_FI
, 1 + arrsz
);
662 ir3_reg_create(collect
, 0, 0); /* dst */
663 for (unsigned i
= 0; i
< arrsz
; i
++)
664 ir3_reg_create(collect
, 0, IR3_REG_SSA
)->instr
= arr
[i
];
669 static struct ir3_instruction
*
670 create_indirect_load(struct ir3_context
*ctx
, unsigned arrsz
, int n
,
671 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
673 struct ir3_block
*block
= ctx
->block
;
674 struct ir3_instruction
*mov
;
675 struct ir3_register
*src
;
677 mov
= ir3_instr_create(block
, OPC_MOV
);
678 mov
->cat1
.src_type
= TYPE_U32
;
679 mov
->cat1
.dst_type
= TYPE_U32
;
680 ir3_reg_create(mov
, 0, 0);
681 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
682 src
->instr
= collect
;
684 src
->array
.offset
= n
;
686 ir3_instr_set_address(mov
, address
);
691 static struct ir3_instruction
*
692 create_input_compmask(struct ir3_block
*block
, unsigned n
, unsigned compmask
)
694 struct ir3_instruction
*in
;
696 in
= ir3_instr_create(block
, OPC_META_INPUT
);
697 in
->inout
.block
= block
;
698 ir3_reg_create(in
, n
, 0);
700 in
->regs
[0]->wrmask
= compmask
;
705 static struct ir3_instruction
*
706 create_input(struct ir3_block
*block
, unsigned n
)
708 return create_input_compmask(block
, n
, 0x1);
711 static struct ir3_instruction
*
712 create_frag_input(struct ir3_context
*ctx
, bool use_ldlv
)
714 struct ir3_block
*block
= ctx
->block
;
715 struct ir3_instruction
*instr
;
716 /* actual inloc is assigned and fixed up later: */
717 struct ir3_instruction
*inloc
= create_immed(block
, 0);
720 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
721 instr
->cat6
.type
= TYPE_U32
;
722 instr
->cat6
.iim_val
= 1;
724 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_pos
, 0);
725 instr
->regs
[2]->wrmask
= 0x3;
731 static struct ir3_instruction
*
732 create_frag_coord(struct ir3_context
*ctx
, unsigned comp
)
734 struct ir3_block
*block
= ctx
->block
;
735 struct ir3_instruction
*instr
;
737 compile_assert(ctx
, !ctx
->frag_coord
[comp
]);
739 ctx
->frag_coord
[comp
] = create_input(ctx
->block
, 0);
744 /* for frag_coord, we get unsigned values.. we need
745 * to subtract (integer) 8 and divide by 16 (right-
746 * shift by 4) then convert to float:
750 * mov.u32f32 dst, tmp
753 instr
= ir3_SUB_S(block
, ctx
->frag_coord
[comp
], 0,
754 create_immed(block
, 8), 0);
755 instr
= ir3_SHR_B(block
, instr
, 0,
756 create_immed(block
, 4), 0);
757 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
763 /* seems that we can use these as-is: */
764 return ctx
->frag_coord
[comp
];
768 static struct ir3_instruction
*
769 create_driver_param(struct ir3_context
*ctx
, enum ir3_driver_param dp
)
771 /* first four vec4 sysval's reserved for UBOs: */
772 /* NOTE: dp is in scalar, but there can be >4 dp components: */
773 unsigned n
= ctx
->so
->constbase
.driver_param
;
774 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
775 return create_uniform(ctx
, r
);
778 /* helper for instructions that produce multiple consecutive scalar
779 * outputs which need to have a split/fanout meta instruction inserted
782 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
783 struct ir3_instruction
*src
, unsigned base
, unsigned n
)
785 struct ir3_instruction
*prev
= NULL
;
787 if ((n
== 1) && (src
->regs
[0]->wrmask
== 0x1)) {
792 for (int i
= 0, j
= 0; i
< n
; i
++) {
793 struct ir3_instruction
*split
= ir3_instr_create(block
, OPC_META_FO
);
794 ir3_reg_create(split
, 0, IR3_REG_SSA
);
795 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
796 split
->fo
.off
= i
+ base
;
799 split
->cp
.left
= prev
;
800 split
->cp
.left_cnt
++;
801 prev
->cp
.right
= split
;
802 prev
->cp
.right_cnt
++;
806 if (src
->regs
[0]->wrmask
& (1 << (i
+ base
)))
812 * Adreno uses uint rather than having dedicated bool type,
813 * which (potentially) requires some conversion, in particular
814 * when using output of an bool instr to int input, or visa
818 * -------+---------+-------+-
822 * To convert from an adreno bool (uint) to nir, use:
824 * absneg.s dst, (neg)src
826 * To convert back in the other direction:
828 * absneg.s dst, (abs)arc
830 * The CP step can clean up the absneg.s that cancel each other
831 * out, and with a slight bit of extra cleverness (to recognize
832 * the instructions which produce either a 0 or 1) can eliminate
833 * the absneg.s's completely when an instruction that wants
834 * 0/1 consumes the result. For example, when a nir 'bcsel'
835 * consumes the result of 'feq'. So we should be able to get by
836 * without a boolean resolve step, and without incuring any
837 * extra penalty in instruction count.
840 /* NIR bool -> native (adreno): */
841 static struct ir3_instruction
*
842 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
844 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
847 /* native (adreno) -> NIR bool: */
848 static struct ir3_instruction
*
849 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
851 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
855 * alu/sfu instructions:
859 emit_alu(struct ir3_context
*ctx
, nir_alu_instr
*alu
)
861 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
862 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
863 struct ir3_block
*b
= ctx
->block
;
864 unsigned dst_sz
, wrmask
;
866 if (alu
->dest
.dest
.is_ssa
) {
867 dst_sz
= alu
->dest
.dest
.ssa
.num_components
;
868 wrmask
= (1 << dst_sz
) - 1;
870 dst_sz
= alu
->dest
.dest
.reg
.reg
->num_components
;
871 wrmask
= alu
->dest
.write_mask
;
874 dst
= get_dst(ctx
, &alu
->dest
.dest
, dst_sz
);
876 /* Vectors are special in that they have non-scalarized writemasks,
877 * and just take the first swizzle channel for each argument in
878 * order into each writemask channel.
880 if ((alu
->op
== nir_op_vec2
) ||
881 (alu
->op
== nir_op_vec3
) ||
882 (alu
->op
== nir_op_vec4
)) {
884 for (int i
= 0; i
< info
->num_inputs
; i
++) {
885 nir_alu_src
*asrc
= &alu
->src
[i
];
887 compile_assert(ctx
, !asrc
->abs
);
888 compile_assert(ctx
, !asrc
->negate
);
890 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
892 src
[i
] = create_immed(ctx
->block
, 0);
893 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
896 put_dst(ctx
, &alu
->dest
.dest
);
900 /* We also get mov's with more than one component for mov's so
901 * handle those specially:
903 if ((alu
->op
== nir_op_imov
) || (alu
->op
== nir_op_fmov
)) {
904 type_t type
= (alu
->op
== nir_op_imov
) ? TYPE_U32
: TYPE_F32
;
905 nir_alu_src
*asrc
= &alu
->src
[0];
906 struct ir3_instruction
*const *src0
= get_src(ctx
, &asrc
->src
);
908 for (unsigned i
= 0; i
< dst_sz
; i
++) {
909 if (wrmask
& (1 << i
)) {
910 dst
[i
] = ir3_MOV(b
, src0
[asrc
->swizzle
[i
]], type
);
916 put_dst(ctx
, &alu
->dest
.dest
);
920 /* General case: We can just grab the one used channel per src. */
921 for (int i
= 0; i
< info
->num_inputs
; i
++) {
922 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
923 nir_alu_src
*asrc
= &alu
->src
[i
];
925 compile_assert(ctx
, !asrc
->abs
);
926 compile_assert(ctx
, !asrc
->negate
);
928 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
930 compile_assert(ctx
, src
[i
]);
935 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_S32
);
938 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_U32
);
941 dst
[0] = ir3_COV(b
, src
[0], TYPE_S32
, TYPE_F32
);
944 dst
[0] = ir3_COV(b
, src
[0], TYPE_U32
, TYPE_F32
);
947 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
948 dst
[0]->cat2
.condition
= IR3_COND_NE
;
949 dst
[0] = ir3_n2b(b
, dst
[0]);
952 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
955 dst
[0] = ir3_b2n(b
, src
[0]);
958 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
959 dst
[0]->cat2
.condition
= IR3_COND_NE
;
960 dst
[0] = ir3_n2b(b
, dst
[0]);
964 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
967 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
970 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
973 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
976 /* if there is just a single use of the src, and it supports
977 * (sat) bit, we can just fold the (sat) flag back to the
978 * src instruction and create a mov. This is easier for cp
981 * TODO probably opc_cat==4 is ok too
983 if (alu
->src
[0].src
.is_ssa
&&
984 (list_length(&alu
->src
[0].src
.ssa
->uses
) == 1) &&
985 ((opc_cat(src
[0]->opc
) == 2) || (opc_cat(src
[0]->opc
) == 3))) {
986 src
[0]->flags
|= IR3_INSTR_SAT
;
987 dst
[0] = ir3_MOV(b
, src
[0], TYPE_U32
);
989 /* otherwise generate a max.f that saturates.. blob does
990 * similar (generating a cat2 mov using max.f)
992 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[0], 0);
993 dst
[0]->flags
|= IR3_INSTR_SAT
;
997 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
1000 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
1003 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
1006 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
1009 dst
[0] = ir3_DSX(b
, src
[0], 0);
1010 dst
[0]->cat5
.type
= TYPE_F32
;
1013 dst
[0] = ir3_DSY(b
, src
[0], 0);
1014 dst
[0]->cat5
.type
= TYPE_F32
;
1018 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1019 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1020 dst
[0] = ir3_n2b(b
, dst
[0]);
1023 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1024 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1025 dst
[0] = ir3_n2b(b
, dst
[0]);
1028 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1029 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1030 dst
[0] = ir3_n2b(b
, dst
[0]);
1033 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1034 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1035 dst
[0] = ir3_n2b(b
, dst
[0]);
1038 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
1041 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
1044 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
1046 case nir_op_fround_even
:
1047 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
1050 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
1054 dst
[0] = ir3_SIN(b
, src
[0], 0);
1057 dst
[0] = ir3_COS(b
, src
[0], 0);
1060 dst
[0] = ir3_RSQ(b
, src
[0], 0);
1063 dst
[0] = ir3_RCP(b
, src
[0], 0);
1066 dst
[0] = ir3_LOG2(b
, src
[0], 0);
1069 dst
[0] = ir3_EXP2(b
, src
[0], 0);
1072 dst
[0] = ir3_SQRT(b
, src
[0], 0);
1076 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
1079 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
1082 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
1085 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
1088 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
1091 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
1094 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
1098 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
1099 * mull.u tmp0, a, b ; mul low, i.e. al * bl
1100 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
1101 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
1103 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
1104 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
1105 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
1108 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
1111 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
1114 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
1117 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
1120 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
1122 case nir_op_isign
: {
1123 /* maybe this would be sane to lower in nir.. */
1124 struct ir3_instruction
*neg
, *pos
;
1126 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1127 neg
->cat2
.condition
= IR3_COND_LT
;
1129 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1130 pos
->cat2
.condition
= IR3_COND_GT
;
1132 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
1137 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
1140 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
1143 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
1146 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1147 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1148 dst
[0] = ir3_n2b(b
, dst
[0]);
1151 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1152 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1153 dst
[0] = ir3_n2b(b
, dst
[0]);
1156 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1157 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1158 dst
[0] = ir3_n2b(b
, dst
[0]);
1161 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1162 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1163 dst
[0] = ir3_n2b(b
, dst
[0]);
1166 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1167 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1168 dst
[0] = ir3_n2b(b
, dst
[0]);
1171 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1172 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1173 dst
[0] = ir3_n2b(b
, dst
[0]);
1177 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, ir3_b2n(b
, src
[0]), 0, src
[2], 0);
1180 case nir_op_bit_count
:
1181 dst
[0] = ir3_CBITS_B(b
, src
[0], 0);
1183 case nir_op_ifind_msb
: {
1184 struct ir3_instruction
*cmp
;
1185 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
1186 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
1187 cmp
->cat2
.condition
= IR3_COND_GE
;
1188 dst
[0] = ir3_SEL_B32(b
,
1189 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1193 case nir_op_ufind_msb
:
1194 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
1195 dst
[0] = ir3_SEL_B32(b
,
1196 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1197 src
[0], 0, dst
[0], 0);
1199 case nir_op_find_lsb
:
1200 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1201 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
1203 case nir_op_bitfield_reverse
:
1204 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1208 compile_error(ctx
, "Unhandled ALU op: %s\n",
1209 nir_op_infos
[alu
->op
].name
);
1213 put_dst(ctx
, &alu
->dest
.dest
);
1216 /* handles direct/indirect UBO reads: */
1218 emit_intrinsic_load_ubo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1219 struct ir3_instruction
**dst
)
1221 struct ir3_block
*b
= ctx
->block
;
1222 struct ir3_instruction
*base_lo
, *base_hi
, *addr
, *src0
, *src1
;
1223 nir_const_value
*const_offset
;
1224 /* UBO addresses are the first driver params: */
1225 unsigned ubo
= regid(ctx
->so
->constbase
.ubo
, 0);
1226 const unsigned ptrsz
= pointer_size(ctx
);
1230 /* First src is ubo index, which could either be an immed or not: */
1231 src0
= get_src(ctx
, &intr
->src
[0])[0];
1232 if (is_same_type_mov(src0
) &&
1233 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1234 base_lo
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
));
1235 base_hi
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
) + 1);
1237 base_lo
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
, 4));
1238 base_hi
= create_uniform_indirect(ctx
, ubo
+ 1, get_addr(ctx
, src0
, 4));
1241 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
1244 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1246 off
+= const_offset
->u32
[0];
1248 /* For load_ubo_indirect, second src is indirect offset: */
1249 src1
= get_src(ctx
, &intr
->src
[1])[0];
1251 /* and add offset to addr: */
1252 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1255 /* if offset is to large to encode in the ldg, split it out: */
1256 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1257 /* split out the minimal amount to improve the odds that
1258 * cp can fit the immediate in the add.s instruction:
1260 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1261 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1266 struct ir3_instruction
*carry
;
1268 /* handle 32b rollover, ie:
1269 * if (addr < base_lo)
1272 carry
= ir3_CMPS_U(b
, addr
, 0, base_lo
, 0);
1273 carry
->cat2
.condition
= IR3_COND_LT
;
1274 base_hi
= ir3_ADD_S(b
, base_hi
, 0, carry
, 0);
1276 addr
= create_collect(ctx
, (struct ir3_instruction
*[]){ addr
, base_hi
}, 2);
1279 for (int i
= 0; i
< intr
->num_components
; i
++) {
1280 struct ir3_instruction
*load
=
1281 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1282 load
->cat6
.type
= TYPE_U32
;
1283 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
1288 /* src[] = { buffer_index, offset }. No const_index */
1290 emit_intrinsic_load_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1291 struct ir3_instruction
**dst
)
1293 struct ir3_block
*b
= ctx
->block
;
1294 struct ir3_instruction
*ldgb
, *src0
, *src1
, *offset
;
1295 nir_const_value
*const_offset
;
1297 /* can this be non-const buffer_index? how do we handle that? */
1298 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1299 compile_assert(ctx
, const_offset
);
1301 offset
= get_src(ctx
, &intr
->src
[1])[0];
1303 /* src0 is uvec2(offset*4, 0), src1 is offset.. nir already *= 4: */
1304 src0
= create_collect(ctx
, (struct ir3_instruction
*[]){
1308 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1310 ldgb
= ir3_LDGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1312 ldgb
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1313 ldgb
->cat6
.iim_val
= intr
->num_components
;
1315 ldgb
->cat6
.type
= TYPE_U32
;
1316 ldgb
->barrier_class
= IR3_BARRIER_BUFFER_R
;
1317 ldgb
->barrier_conflict
= IR3_BARRIER_BUFFER_W
;
1319 split_dest(b
, dst
, ldgb
, 0, intr
->num_components
);
1322 /* src[] = { value, block_index, offset }. const_index[] = { write_mask } */
1324 emit_intrinsic_store_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1326 struct ir3_block
*b
= ctx
->block
;
1327 struct ir3_instruction
*stgb
, *src0
, *src1
, *src2
, *offset
;
1328 nir_const_value
*const_offset
;
1329 /* TODO handle wrmask properly, see _store_shared().. but I think
1330 * it is more a PITA than that, since blob ends up loading the
1331 * masked components and writing them back out.
1333 unsigned wrmask
= intr
->const_index
[0];
1334 unsigned ncomp
= ffs(~wrmask
) - 1;
1336 /* can this be non-const buffer_index? how do we handle that? */
1337 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1338 compile_assert(ctx
, const_offset
);
1340 offset
= get_src(ctx
, &intr
->src
[2])[0];
1342 /* src0 is value, src1 is offset, src2 is uvec2(offset*4, 0)..
1345 src0
= create_collect(ctx
, get_src(ctx
, &intr
->src
[0]), ncomp
);
1346 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1347 src2
= create_collect(ctx
, (struct ir3_instruction
*[]){
1352 stgb
= ir3_STGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1353 src0
, 0, src1
, 0, src2
, 0);
1354 stgb
->cat6
.iim_val
= ncomp
;
1356 stgb
->cat6
.type
= TYPE_U32
;
1357 stgb
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1358 stgb
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1360 array_insert(b
, b
->keeps
, stgb
);
1363 /* src[] = { block_index } */
1365 emit_intrinsic_ssbo_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1366 struct ir3_instruction
**dst
)
1368 /* SSBO size stored as a const starting at ssbo_sizes: */
1369 unsigned blk_idx
= nir_src_as_const_value(intr
->src
[0])->u32
[0];
1370 unsigned idx
= regid(ctx
->so
->constbase
.ssbo_sizes
, 0) +
1371 ctx
->so
->const_layout
.ssbo_size
.off
[blk_idx
];
1373 debug_assert(ctx
->so
->const_layout
.ssbo_size
.mask
& (1 << blk_idx
));
1375 dst
[0] = create_uniform(ctx
, idx
);
1379 * SSBO atomic intrinsics
1381 * All of the SSBO atomic memory operations read a value from memory,
1382 * compute a new value using one of the operations below, write the new
1383 * value to memory, and return the original value read.
1385 * All operations take 3 sources except CompSwap that takes 4. These
1386 * sources represent:
1388 * 0: The SSBO buffer index.
1389 * 1: The offset into the SSBO buffer of the variable that the atomic
1390 * operation will operate on.
1391 * 2: The data parameter to the atomic function (i.e. the value to add
1392 * in ssbo_atomic_add, etc).
1393 * 3: For CompSwap only: the second data parameter.
1395 static struct ir3_instruction
*
1396 emit_intrinsic_atomic_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1398 struct ir3_block
*b
= ctx
->block
;
1399 struct ir3_instruction
*atomic
, *ssbo
, *src0
, *src1
, *src2
, *offset
;
1400 nir_const_value
*const_offset
;
1401 type_t type
= TYPE_U32
;
1403 /* can this be non-const buffer_index? how do we handle that? */
1404 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1405 compile_assert(ctx
, const_offset
);
1406 ssbo
= create_immed(b
, const_offset
->u32
[0]);
1408 offset
= get_src(ctx
, &intr
->src
[1])[0];
1410 /* src0 is data (or uvec2(data, compare))
1412 * src2 is uvec2(offset*4, 0) (appears to be 64b byte offset)
1414 * Note that nir already multiplies the offset by four
1416 src0
= get_src(ctx
, &intr
->src
[2])[0];
1417 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1418 src2
= create_collect(ctx
, (struct ir3_instruction
*[]){
1423 switch (intr
->intrinsic
) {
1424 case nir_intrinsic_ssbo_atomic_add
:
1425 atomic
= ir3_ATOMIC_ADD_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1427 case nir_intrinsic_ssbo_atomic_imin
:
1428 atomic
= ir3_ATOMIC_MIN_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1431 case nir_intrinsic_ssbo_atomic_umin
:
1432 atomic
= ir3_ATOMIC_MIN_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1434 case nir_intrinsic_ssbo_atomic_imax
:
1435 atomic
= ir3_ATOMIC_MAX_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1438 case nir_intrinsic_ssbo_atomic_umax
:
1439 atomic
= ir3_ATOMIC_MAX_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1441 case nir_intrinsic_ssbo_atomic_and
:
1442 atomic
= ir3_ATOMIC_AND_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1444 case nir_intrinsic_ssbo_atomic_or
:
1445 atomic
= ir3_ATOMIC_OR_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1447 case nir_intrinsic_ssbo_atomic_xor
:
1448 atomic
= ir3_ATOMIC_XOR_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1450 case nir_intrinsic_ssbo_atomic_exchange
:
1451 atomic
= ir3_ATOMIC_XCHG_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1453 case nir_intrinsic_ssbo_atomic_comp_swap
:
1454 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
1455 src0
= create_collect(ctx
, (struct ir3_instruction
*[]){
1457 get_src(ctx
, &intr
->src
[3])[0],
1459 atomic
= ir3_ATOMIC_CMPXCHG_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1465 atomic
->cat6
.iim_val
= 1;
1467 atomic
->cat6
.type
= type
;
1468 atomic
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1469 atomic
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1471 /* even if nothing consume the result, we can't DCE the instruction: */
1472 array_insert(b
, b
->keeps
, atomic
);
1477 /* src[] = { offset }. const_index[] = { base } */
1479 emit_intrinsic_load_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1480 struct ir3_instruction
**dst
)
1482 struct ir3_block
*b
= ctx
->block
;
1483 struct ir3_instruction
*ldl
, *offset
;
1486 offset
= get_src(ctx
, &intr
->src
[0])[0];
1487 base
= nir_intrinsic_base(intr
);
1489 ldl
= ir3_LDL(b
, offset
, 0, create_immed(b
, intr
->num_components
), 0);
1490 ldl
->cat6
.src_offset
= base
;
1491 ldl
->cat6
.type
= TYPE_U32
;
1492 ldl
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1494 ldl
->barrier_class
= IR3_BARRIER_SHARED_R
;
1495 ldl
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
1497 split_dest(b
, dst
, ldl
, 0, intr
->num_components
);
1500 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
1502 emit_intrinsic_store_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1504 struct ir3_block
*b
= ctx
->block
;
1505 struct ir3_instruction
*stl
, *offset
;
1506 struct ir3_instruction
* const *value
;
1507 unsigned base
, wrmask
;
1509 value
= get_src(ctx
, &intr
->src
[0]);
1510 offset
= get_src(ctx
, &intr
->src
[1])[0];
1512 base
= nir_intrinsic_base(intr
);
1513 wrmask
= nir_intrinsic_write_mask(intr
);
1515 /* Combine groups of consecutive enabled channels in one write
1516 * message. We use ffs to find the first enabled channel and then ffs on
1517 * the bit-inverse, down-shifted writemask to determine the length of
1518 * the block of enabled bits.
1520 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
1523 unsigned first_component
= ffs(wrmask
) - 1;
1524 unsigned length
= ffs(~(wrmask
>> first_component
)) - 1;
1526 stl
= ir3_STL(b
, offset
, 0,
1527 create_collect(ctx
, &value
[first_component
], length
), 0,
1528 create_immed(b
, length
), 0);
1529 stl
->cat6
.dst_offset
= first_component
+ base
;
1530 stl
->cat6
.type
= TYPE_U32
;
1531 stl
->barrier_class
= IR3_BARRIER_SHARED_W
;
1532 stl
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1534 array_insert(b
, b
->keeps
, stl
);
1536 /* Clear the bits in the writemask that we just wrote, then try
1537 * again to see if more channels are left.
1539 wrmask
&= (15 << (first_component
+ length
));
1544 * CS shared variable atomic intrinsics
1546 * All of the shared variable atomic memory operations read a value from
1547 * memory, compute a new value using one of the operations below, write the
1548 * new value to memory, and return the original value read.
1550 * All operations take 2 sources except CompSwap that takes 3. These
1551 * sources represent:
1553 * 0: The offset into the shared variable storage region that the atomic
1554 * operation will operate on.
1555 * 1: The data parameter to the atomic function (i.e. the value to add
1556 * in shared_atomic_add, etc).
1557 * 2: For CompSwap only: the second data parameter.
1559 static struct ir3_instruction
*
1560 emit_intrinsic_atomic_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1562 struct ir3_block
*b
= ctx
->block
;
1563 struct ir3_instruction
*atomic
, *src0
, *src1
;
1564 type_t type
= TYPE_U32
;
1566 src0
= get_src(ctx
, &intr
->src
[0])[0]; /* offset */
1567 src1
= get_src(ctx
, &intr
->src
[1])[0]; /* value */
1569 switch (intr
->intrinsic
) {
1570 case nir_intrinsic_shared_atomic_add
:
1571 atomic
= ir3_ATOMIC_ADD(b
, src0
, 0, src1
, 0);
1573 case nir_intrinsic_shared_atomic_imin
:
1574 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1577 case nir_intrinsic_shared_atomic_umin
:
1578 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1580 case nir_intrinsic_shared_atomic_imax
:
1581 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1584 case nir_intrinsic_shared_atomic_umax
:
1585 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1587 case nir_intrinsic_shared_atomic_and
:
1588 atomic
= ir3_ATOMIC_AND(b
, src0
, 0, src1
, 0);
1590 case nir_intrinsic_shared_atomic_or
:
1591 atomic
= ir3_ATOMIC_OR(b
, src0
, 0, src1
, 0);
1593 case nir_intrinsic_shared_atomic_xor
:
1594 atomic
= ir3_ATOMIC_XOR(b
, src0
, 0, src1
, 0);
1596 case nir_intrinsic_shared_atomic_exchange
:
1597 atomic
= ir3_ATOMIC_XCHG(b
, src0
, 0, src1
, 0);
1599 case nir_intrinsic_shared_atomic_comp_swap
:
1600 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1601 src1
= create_collect(ctx
, (struct ir3_instruction
*[]){
1602 get_src(ctx
, &intr
->src
[2])[0],
1605 atomic
= ir3_ATOMIC_CMPXCHG(b
, src0
, 0, src1
, 0);
1611 atomic
->cat6
.iim_val
= 1;
1613 atomic
->cat6
.type
= type
;
1614 atomic
->barrier_class
= IR3_BARRIER_SHARED_W
;
1615 atomic
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1617 /* even if nothing consume the result, we can't DCE the instruction: */
1618 array_insert(b
, b
->keeps
, atomic
);
1623 /* Images get mapped into SSBO/image state (for store/atomic) and texture
1624 * state block (for load). To simplify things, invert the image id and
1625 * map it from end of state block, ie. image 0 becomes num-1, image 1
1626 * becomes num-2, etc. This potentially avoids needing to re-emit texture
1627 * state when switching shaders.
1629 * TODO is max # of samplers and SSBOs the same. This shouldn't be hard-
1630 * coded. Also, since all the gl shader stages (ie. everything but CS)
1631 * share the same SSBO/image state block, this might require some more
1632 * logic if we supported images in anything other than FS..
1635 get_image_slot(struct ir3_context
*ctx
, const nir_variable
*var
)
1637 /* TODO figure out real limit per generation, and don't hardcode: */
1638 const unsigned max_samplers
= 16;
1639 return max_samplers
- var
->data
.driver_location
- 1;
1643 get_image_coords(const nir_variable
*var
)
1645 switch (glsl_get_sampler_dim(glsl_without_array(var
->type
))) {
1646 case GLSL_SAMPLER_DIM_1D
:
1647 case GLSL_SAMPLER_DIM_BUF
:
1650 case GLSL_SAMPLER_DIM_2D
:
1651 case GLSL_SAMPLER_DIM_RECT
:
1652 case GLSL_SAMPLER_DIM_EXTERNAL
:
1653 case GLSL_SAMPLER_DIM_MS
:
1655 case GLSL_SAMPLER_DIM_3D
:
1656 case GLSL_SAMPLER_DIM_CUBE
:
1659 unreachable("bad sampler dim");
1665 get_image_type(const nir_variable
*var
)
1667 switch (glsl_get_sampler_result_type(glsl_without_array(var
->type
))) {
1668 case GLSL_TYPE_UINT
:
1672 case GLSL_TYPE_FLOAT
:
1675 unreachable("bad sampler type.");
1680 static struct ir3_instruction
*
1681 get_image_offset(struct ir3_context
*ctx
, const nir_variable
*var
,
1682 struct ir3_instruction
* const *coords
, bool byteoff
)
1684 struct ir3_block
*b
= ctx
->block
;
1685 struct ir3_instruction
*offset
;
1686 unsigned ncoords
= get_image_coords(var
);
1688 /* to calculate the byte offset (yes, uggg) we need (up to) three
1689 * const values to know the bytes per pixel, and y and z stride:
1691 unsigned cb
= regid(ctx
->so
->constbase
.image_dims
, 0) +
1692 ctx
->so
->const_layout
.image_dims
.off
[var
->data
.driver_location
];
1694 debug_assert(ctx
->so
->const_layout
.image_dims
.mask
&
1695 (1 << var
->data
.driver_location
));
1697 /* offset = coords.x * bytes_per_pixel: */
1698 offset
= ir3_MUL_S(b
, coords
[0], 0, create_uniform(ctx
, cb
+ 0), 0);
1700 /* offset += coords.y * y_pitch: */
1701 offset
= ir3_MAD_S24(b
, create_uniform(ctx
, cb
+ 1), 0,
1702 coords
[1], 0, offset
, 0);
1705 /* offset += coords.z * z_pitch: */
1706 offset
= ir3_MAD_S24(b
, create_uniform(ctx
, cb
+ 2), 0,
1707 coords
[2], 0, offset
, 0);
1711 /* Some cases, like atomics, seem to use dword offset instead
1712 * of byte offsets.. blob just puts an extra shr.b in there
1715 offset
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1718 return create_collect(ctx
, (struct ir3_instruction
*[]){
1724 /* src[] = { coord, sample_index }. const_index[] = {} */
1726 emit_intrinsic_load_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1727 struct ir3_instruction
**dst
)
1729 struct ir3_block
*b
= ctx
->block
;
1730 const nir_variable
*var
= intr
->variables
[0]->var
;
1731 struct ir3_instruction
*sam
;
1732 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[0]);
1733 unsigned ncoords
= get_image_coords(var
);
1734 unsigned tex_idx
= get_image_slot(ctx
, var
);
1735 type_t type
= get_image_type(var
);
1739 flags
|= IR3_INSTR_3D
;
1741 sam
= ir3_SAM(b
, OPC_ISAM
, type
, TGSI_WRITEMASK_XYZW
, flags
,
1742 tex_idx
, tex_idx
, create_collect(ctx
, coords
, ncoords
), NULL
);
1744 sam
->barrier_class
= IR3_BARRIER_IMAGE_R
;
1745 sam
->barrier_conflict
= IR3_BARRIER_IMAGE_W
;
1747 split_dest(b
, dst
, sam
, 0, 4);
1750 /* src[] = { coord, sample_index, value }. const_index[] = {} */
1752 emit_intrinsic_store_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1754 struct ir3_block
*b
= ctx
->block
;
1755 const nir_variable
*var
= intr
->variables
[0]->var
;
1756 struct ir3_instruction
*stib
, *offset
;
1757 struct ir3_instruction
* const *value
= get_src(ctx
, &intr
->src
[2]);
1758 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[0]);
1759 unsigned ncoords
= get_image_coords(var
);
1760 unsigned tex_idx
= get_image_slot(ctx
, var
);
1764 * src2 is 64b byte offset
1767 offset
= get_image_offset(ctx
, var
, coords
, true);
1769 /* NOTE: stib seems to take byte offset, but stgb.typed can be used
1770 * too and takes a dword offset.. not quite sure yet why blob uses
1771 * one over the other in various cases.
1774 stib
= ir3_STIB(b
, create_immed(b
, tex_idx
), 0,
1775 create_collect(ctx
, value
, 4), 0,
1776 create_collect(ctx
, coords
, ncoords
), 0,
1778 stib
->cat6
.iim_val
= 4;
1779 stib
->cat6
.d
= ncoords
;
1780 stib
->cat6
.type
= get_image_type(var
);
1781 stib
->cat6
.typed
= true;
1782 stib
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1783 stib
->barrier_conflict
= IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
;
1785 array_insert(b
, b
->keeps
, stib
);
1789 emit_intrinsic_image_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1790 struct ir3_instruction
**dst
)
1792 struct ir3_block
*b
= ctx
->block
;
1793 const nir_variable
*var
= intr
->variables
[0]->var
;
1794 unsigned ncoords
= get_image_coords(var
);
1795 unsigned tex_idx
= get_image_slot(ctx
, var
);
1796 struct ir3_instruction
*sam
, *lod
;
1800 flags
= IR3_INSTR_3D
;
1802 lod
= create_immed(b
, 0);
1803 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
1804 tex_idx
, tex_idx
, lod
, NULL
);
1806 split_dest(b
, dst
, sam
, 0, ncoords
);
1809 /* src[] = { coord, sample_index, value, compare }. const_index[] = {} */
1810 static struct ir3_instruction
*
1811 emit_intrinsic_atomic_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1813 struct ir3_block
*b
= ctx
->block
;
1814 const nir_variable
*var
= intr
->variables
[0]->var
;
1815 struct ir3_instruction
*atomic
, *image
, *src0
, *src1
, *src2
;
1816 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[0]);
1817 unsigned ncoords
= get_image_coords(var
);
1819 image
= create_immed(b
, get_image_slot(ctx
, var
));
1821 /* src0 is value (or uvec2(value, compare))
1823 * src2 is 64b byte offset
1825 src0
= get_src(ctx
, &intr
->src
[2])[0];
1826 src1
= create_collect(ctx
, coords
, ncoords
);
1827 src2
= get_image_offset(ctx
, var
, coords
, false);
1829 switch (intr
->intrinsic
) {
1830 case nir_intrinsic_image_var_atomic_add
:
1831 atomic
= ir3_ATOMIC_ADD_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1833 case nir_intrinsic_image_var_atomic_min
:
1834 atomic
= ir3_ATOMIC_MIN_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1836 case nir_intrinsic_image_var_atomic_max
:
1837 atomic
= ir3_ATOMIC_MAX_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1839 case nir_intrinsic_image_var_atomic_and
:
1840 atomic
= ir3_ATOMIC_AND_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1842 case nir_intrinsic_image_var_atomic_or
:
1843 atomic
= ir3_ATOMIC_OR_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1845 case nir_intrinsic_image_var_atomic_xor
:
1846 atomic
= ir3_ATOMIC_XOR_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1848 case nir_intrinsic_image_var_atomic_exchange
:
1849 atomic
= ir3_ATOMIC_XCHG_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1851 case nir_intrinsic_image_var_atomic_comp_swap
:
1852 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
1853 src0
= create_collect(ctx
, (struct ir3_instruction
*[]){
1855 get_src(ctx
, &intr
->src
[3])[0],
1857 atomic
= ir3_ATOMIC_CMPXCHG_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
1863 atomic
->cat6
.iim_val
= 1;
1864 atomic
->cat6
.d
= ncoords
;
1865 atomic
->cat6
.type
= get_image_type(var
);
1866 atomic
->cat6
.typed
= true;
1867 atomic
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1868 atomic
->barrier_conflict
= IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
;
1870 /* even if nothing consume the result, we can't DCE the instruction: */
1871 array_insert(b
, b
->keeps
, atomic
);
1877 emit_intrinsic_barrier(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1879 struct ir3_block
*b
= ctx
->block
;
1880 struct ir3_instruction
*barrier
;
1882 switch (intr
->intrinsic
) {
1883 case nir_intrinsic_barrier
:
1884 barrier
= ir3_BAR(b
);
1885 barrier
->cat7
.g
= true;
1886 barrier
->cat7
.l
= true;
1887 barrier
->flags
= IR3_INSTR_SS
| IR3_INSTR_SY
;
1888 barrier
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1890 case nir_intrinsic_memory_barrier
:
1891 barrier
= ir3_FENCE(b
);
1892 barrier
->cat7
.g
= true;
1893 barrier
->cat7
.r
= true;
1894 barrier
->cat7
.w
= true;
1895 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
|
1896 IR3_BARRIER_BUFFER_W
;
1897 barrier
->barrier_conflict
=
1898 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1899 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1901 case nir_intrinsic_memory_barrier_atomic_counter
:
1902 case nir_intrinsic_memory_barrier_buffer
:
1903 barrier
= ir3_FENCE(b
);
1904 barrier
->cat7
.g
= true;
1905 barrier
->cat7
.r
= true;
1906 barrier
->cat7
.w
= true;
1907 barrier
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1908 barrier
->barrier_conflict
= IR3_BARRIER_BUFFER_R
|
1909 IR3_BARRIER_BUFFER_W
;
1911 case nir_intrinsic_memory_barrier_image
:
1912 // TODO double check if this should have .g set
1913 barrier
= ir3_FENCE(b
);
1914 barrier
->cat7
.g
= true;
1915 barrier
->cat7
.r
= true;
1916 barrier
->cat7
.w
= true;
1917 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1918 barrier
->barrier_conflict
= IR3_BARRIER_IMAGE_R
|
1919 IR3_BARRIER_IMAGE_W
;
1921 case nir_intrinsic_memory_barrier_shared
:
1922 barrier
= ir3_FENCE(b
);
1923 barrier
->cat7
.g
= true;
1924 barrier
->cat7
.l
= true;
1925 barrier
->cat7
.r
= true;
1926 barrier
->cat7
.w
= true;
1927 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
;
1928 barrier
->barrier_conflict
= IR3_BARRIER_SHARED_R
|
1929 IR3_BARRIER_SHARED_W
;
1931 case nir_intrinsic_group_memory_barrier
:
1932 barrier
= ir3_FENCE(b
);
1933 barrier
->cat7
.g
= true;
1934 barrier
->cat7
.l
= true;
1935 barrier
->cat7
.r
= true;
1936 barrier
->cat7
.w
= true;
1937 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
|
1938 IR3_BARRIER_IMAGE_W
|
1939 IR3_BARRIER_BUFFER_W
;
1940 barrier
->barrier_conflict
=
1941 IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
|
1942 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1943 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1949 /* make sure barrier doesn't get DCE'd */
1950 array_insert(b
, b
->keeps
, barrier
);
1953 static void add_sysval_input_compmask(struct ir3_context
*ctx
,
1954 gl_system_value slot
, unsigned compmask
,
1955 struct ir3_instruction
*instr
)
1957 struct ir3_shader_variant
*so
= ctx
->so
;
1958 unsigned r
= regid(so
->inputs_count
, 0);
1959 unsigned n
= so
->inputs_count
++;
1961 so
->inputs
[n
].sysval
= true;
1962 so
->inputs
[n
].slot
= slot
;
1963 so
->inputs
[n
].compmask
= compmask
;
1964 so
->inputs
[n
].regid
= r
;
1965 so
->inputs
[n
].interpolate
= INTERP_MODE_FLAT
;
1968 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
1969 ctx
->ir
->inputs
[r
] = instr
;
1972 static void add_sysval_input(struct ir3_context
*ctx
, gl_system_value slot
,
1973 struct ir3_instruction
*instr
)
1975 add_sysval_input_compmask(ctx
, slot
, 0x1, instr
);
1979 emit_intrinsic(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1981 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1982 struct ir3_instruction
**dst
;
1983 struct ir3_instruction
* const *src
;
1984 struct ir3_block
*b
= ctx
->block
;
1985 nir_const_value
*const_offset
;
1988 if (info
->has_dest
) {
1990 if (info
->dest_components
)
1991 n
= info
->dest_components
;
1993 n
= intr
->num_components
;
1994 dst
= get_dst(ctx
, &intr
->dest
, n
);
1999 switch (intr
->intrinsic
) {
2000 case nir_intrinsic_load_uniform
:
2001 idx
= nir_intrinsic_base(intr
);
2002 const_offset
= nir_src_as_const_value(intr
->src
[0]);
2004 idx
+= const_offset
->u32
[0];
2005 for (int i
= 0; i
< intr
->num_components
; i
++) {
2006 unsigned n
= idx
* 4 + i
;
2007 dst
[i
] = create_uniform(ctx
, n
);
2010 src
= get_src(ctx
, &intr
->src
[0]);
2011 for (int i
= 0; i
< intr
->num_components
; i
++) {
2012 int n
= idx
* 4 + i
;
2013 dst
[i
] = create_uniform_indirect(ctx
, n
,
2014 get_addr(ctx
, src
[0], 4));
2016 /* NOTE: if relative addressing is used, we set
2017 * constlen in the compiler (to worst-case value)
2018 * since we don't know in the assembler what the max
2019 * addr reg value can be:
2021 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
2024 case nir_intrinsic_load_ubo
:
2025 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
2027 case nir_intrinsic_load_input
:
2028 idx
= nir_intrinsic_base(intr
);
2029 comp
= nir_intrinsic_component(intr
);
2030 const_offset
= nir_src_as_const_value(intr
->src
[0]);
2032 idx
+= const_offset
->u32
[0];
2033 for (int i
= 0; i
< intr
->num_components
; i
++) {
2034 unsigned n
= idx
* 4 + i
+ comp
;
2035 dst
[i
] = ctx
->ir
->inputs
[n
];
2038 src
= get_src(ctx
, &intr
->src
[0]);
2039 struct ir3_instruction
*collect
=
2040 create_collect(ctx
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
2041 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0], 4);
2042 for (int i
= 0; i
< intr
->num_components
; i
++) {
2043 unsigned n
= idx
* 4 + i
+ comp
;
2044 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
2049 case nir_intrinsic_load_ssbo
:
2050 emit_intrinsic_load_ssbo(ctx
, intr
, dst
);
2052 case nir_intrinsic_store_ssbo
:
2053 emit_intrinsic_store_ssbo(ctx
, intr
);
2055 case nir_intrinsic_get_buffer_size
:
2056 emit_intrinsic_ssbo_size(ctx
, intr
, dst
);
2058 case nir_intrinsic_ssbo_atomic_add
:
2059 case nir_intrinsic_ssbo_atomic_imin
:
2060 case nir_intrinsic_ssbo_atomic_umin
:
2061 case nir_intrinsic_ssbo_atomic_imax
:
2062 case nir_intrinsic_ssbo_atomic_umax
:
2063 case nir_intrinsic_ssbo_atomic_and
:
2064 case nir_intrinsic_ssbo_atomic_or
:
2065 case nir_intrinsic_ssbo_atomic_xor
:
2066 case nir_intrinsic_ssbo_atomic_exchange
:
2067 case nir_intrinsic_ssbo_atomic_comp_swap
:
2068 dst
[0] = emit_intrinsic_atomic_ssbo(ctx
, intr
);
2070 case nir_intrinsic_load_shared
:
2071 emit_intrinsic_load_shared(ctx
, intr
, dst
);
2073 case nir_intrinsic_store_shared
:
2074 emit_intrinsic_store_shared(ctx
, intr
);
2076 case nir_intrinsic_shared_atomic_add
:
2077 case nir_intrinsic_shared_atomic_imin
:
2078 case nir_intrinsic_shared_atomic_umin
:
2079 case nir_intrinsic_shared_atomic_imax
:
2080 case nir_intrinsic_shared_atomic_umax
:
2081 case nir_intrinsic_shared_atomic_and
:
2082 case nir_intrinsic_shared_atomic_or
:
2083 case nir_intrinsic_shared_atomic_xor
:
2084 case nir_intrinsic_shared_atomic_exchange
:
2085 case nir_intrinsic_shared_atomic_comp_swap
:
2086 dst
[0] = emit_intrinsic_atomic_shared(ctx
, intr
);
2088 case nir_intrinsic_image_var_load
:
2089 emit_intrinsic_load_image(ctx
, intr
, dst
);
2091 case nir_intrinsic_image_var_store
:
2092 emit_intrinsic_store_image(ctx
, intr
);
2094 case nir_intrinsic_image_var_size
:
2095 emit_intrinsic_image_size(ctx
, intr
, dst
);
2097 case nir_intrinsic_image_var_atomic_add
:
2098 case nir_intrinsic_image_var_atomic_min
:
2099 case nir_intrinsic_image_var_atomic_max
:
2100 case nir_intrinsic_image_var_atomic_and
:
2101 case nir_intrinsic_image_var_atomic_or
:
2102 case nir_intrinsic_image_var_atomic_xor
:
2103 case nir_intrinsic_image_var_atomic_exchange
:
2104 case nir_intrinsic_image_var_atomic_comp_swap
:
2105 dst
[0] = emit_intrinsic_atomic_image(ctx
, intr
);
2107 case nir_intrinsic_barrier
:
2108 case nir_intrinsic_memory_barrier
:
2109 case nir_intrinsic_group_memory_barrier
:
2110 case nir_intrinsic_memory_barrier_atomic_counter
:
2111 case nir_intrinsic_memory_barrier_buffer
:
2112 case nir_intrinsic_memory_barrier_image
:
2113 case nir_intrinsic_memory_barrier_shared
:
2114 emit_intrinsic_barrier(ctx
, intr
);
2115 /* note that blk ptr no longer valid, make that obvious: */
2118 case nir_intrinsic_store_output
:
2119 idx
= nir_intrinsic_base(intr
);
2120 comp
= nir_intrinsic_component(intr
);
2121 const_offset
= nir_src_as_const_value(intr
->src
[1]);
2122 compile_assert(ctx
, const_offset
!= NULL
);
2123 idx
+= const_offset
->u32
[0];
2125 src
= get_src(ctx
, &intr
->src
[0]);
2126 for (int i
= 0; i
< intr
->num_components
; i
++) {
2127 unsigned n
= idx
* 4 + i
+ comp
;
2128 ctx
->ir
->outputs
[n
] = src
[i
];
2131 case nir_intrinsic_load_base_vertex
:
2132 if (!ctx
->basevertex
) {
2133 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
2134 add_sysval_input(ctx
, SYSTEM_VALUE_BASE_VERTEX
,
2137 dst
[0] = ctx
->basevertex
;
2139 case nir_intrinsic_load_vertex_id_zero_base
:
2140 case nir_intrinsic_load_vertex_id
:
2141 if (!ctx
->vertex_id
) {
2142 gl_system_value sv
= (intr
->intrinsic
== nir_intrinsic_load_vertex_id
) ?
2143 SYSTEM_VALUE_VERTEX_ID
: SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
;
2144 ctx
->vertex_id
= create_input(b
, 0);
2145 add_sysval_input(ctx
, sv
, ctx
->vertex_id
);
2147 dst
[0] = ctx
->vertex_id
;
2149 case nir_intrinsic_load_instance_id
:
2150 if (!ctx
->instance_id
) {
2151 ctx
->instance_id
= create_input(b
, 0);
2152 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
2155 dst
[0] = ctx
->instance_id
;
2157 case nir_intrinsic_load_user_clip_plane
:
2158 idx
= nir_intrinsic_ucp_id(intr
);
2159 for (int i
= 0; i
< intr
->num_components
; i
++) {
2160 unsigned n
= idx
* 4 + i
;
2161 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
2164 case nir_intrinsic_load_front_face
:
2165 if (!ctx
->frag_face
) {
2166 ctx
->so
->frag_face
= true;
2167 ctx
->frag_face
= create_input(b
, 0);
2168 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
2170 /* for fragface, we get -1 for back and 0 for front. However this is
2171 * the inverse of what nir expects (where ~0 is true).
2173 dst
[0] = ir3_COV(b
, ctx
->frag_face
, TYPE_S16
, TYPE_S32
);
2174 dst
[0] = ir3_NOT_B(b
, dst
[0], 0);
2176 case nir_intrinsic_load_local_invocation_id
:
2177 if (!ctx
->local_invocation_id
) {
2178 ctx
->local_invocation_id
= create_input_compmask(b
, 0, 0x7);
2179 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
,
2180 0x7, ctx
->local_invocation_id
);
2182 split_dest(b
, dst
, ctx
->local_invocation_id
, 0, 3);
2184 case nir_intrinsic_load_work_group_id
:
2185 if (!ctx
->work_group_id
) {
2186 ctx
->work_group_id
= create_input_compmask(b
, 0, 0x7);
2187 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_WORK_GROUP_ID
,
2188 0x7, ctx
->work_group_id
);
2189 ctx
->work_group_id
->regs
[0]->flags
|= IR3_REG_HIGH
;
2191 split_dest(b
, dst
, ctx
->work_group_id
, 0, 3);
2193 case nir_intrinsic_load_num_work_groups
:
2194 for (int i
= 0; i
< intr
->num_components
; i
++) {
2195 dst
[i
] = create_driver_param(ctx
, IR3_DP_NUM_WORK_GROUPS_X
+ i
);
2198 case nir_intrinsic_load_local_group_size
:
2199 for (int i
= 0; i
< intr
->num_components
; i
++) {
2200 dst
[i
] = create_driver_param(ctx
, IR3_DP_LOCAL_GROUP_SIZE_X
+ i
);
2203 case nir_intrinsic_discard_if
:
2204 case nir_intrinsic_discard
: {
2205 struct ir3_instruction
*cond
, *kill
;
2207 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
2208 /* conditional discard: */
2209 src
= get_src(ctx
, &intr
->src
[0]);
2210 cond
= ir3_b2n(b
, src
[0]);
2212 /* unconditional discard: */
2213 cond
= create_immed(b
, 1);
2216 /* NOTE: only cmps.*.* can write p0.x: */
2217 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
2218 cond
->cat2
.condition
= IR3_COND_NE
;
2220 /* condition always goes in predicate register: */
2221 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2223 kill
= ir3_KILL(b
, cond
, 0);
2224 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
2226 array_insert(b
, b
->keeps
, kill
);
2227 ctx
->so
->has_kill
= true;
2232 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
2233 nir_intrinsic_infos
[intr
->intrinsic
].name
);
2238 put_dst(ctx
, &intr
->dest
);
2242 emit_load_const(struct ir3_context
*ctx
, nir_load_const_instr
*instr
)
2244 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
2245 instr
->def
.num_components
);
2246 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
2247 dst
[i
] = create_immed(ctx
->block
, instr
->value
.u32
[i
]);
2251 emit_undef(struct ir3_context
*ctx
, nir_ssa_undef_instr
*undef
)
2253 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
2254 undef
->def
.num_components
);
2255 /* backend doesn't want undefined instructions, so just plug
2258 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
2259 dst
[i
] = create_immed(ctx
->block
, fui(0.0));
2263 * texture fetch/sample instructions:
2267 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
2269 unsigned coords
, flags
= 0;
2271 /* note: would use tex->coord_components.. except txs.. also,
2272 * since array index goes after shadow ref, we don't want to
2275 switch (tex
->sampler_dim
) {
2276 case GLSL_SAMPLER_DIM_1D
:
2277 case GLSL_SAMPLER_DIM_BUF
:
2280 case GLSL_SAMPLER_DIM_2D
:
2281 case GLSL_SAMPLER_DIM_RECT
:
2282 case GLSL_SAMPLER_DIM_EXTERNAL
:
2283 case GLSL_SAMPLER_DIM_MS
:
2286 case GLSL_SAMPLER_DIM_3D
:
2287 case GLSL_SAMPLER_DIM_CUBE
:
2289 flags
|= IR3_INSTR_3D
;
2292 unreachable("bad sampler_dim");
2295 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2296 flags
|= IR3_INSTR_S
;
2298 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
2299 flags
|= IR3_INSTR_A
;
2306 emit_tex(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2308 struct ir3_block
*b
= ctx
->block
;
2309 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
2310 struct ir3_instruction
* const *coord
, * const *off
, * const *ddx
, * const *ddy
;
2311 struct ir3_instruction
*lod
, *compare
, *proj
;
2312 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
2313 unsigned i
, coords
, flags
;
2314 unsigned nsrc0
= 0, nsrc1
= 0;
2318 coord
= off
= ddx
= ddy
= NULL
;
2319 lod
= proj
= compare
= NULL
;
2321 /* TODO: might just be one component for gathers? */
2322 dst
= get_dst(ctx
, &tex
->dest
, 4);
2324 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
2325 switch (tex
->src
[i
].src_type
) {
2326 case nir_tex_src_coord
:
2327 coord
= get_src(ctx
, &tex
->src
[i
].src
);
2329 case nir_tex_src_bias
:
2330 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2333 case nir_tex_src_lod
:
2334 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2337 case nir_tex_src_comparator
: /* shadow comparator */
2338 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2340 case nir_tex_src_projector
:
2341 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2344 case nir_tex_src_offset
:
2345 off
= get_src(ctx
, &tex
->src
[i
].src
);
2348 case nir_tex_src_ddx
:
2349 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
2351 case nir_tex_src_ddy
:
2352 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
2355 compile_error(ctx
, "Unhandled NIR tex src type: %d\n",
2356 tex
->src
[i
].src_type
);
2362 case nir_texop_tex
: opc
= OPC_SAM
; break;
2363 case nir_texop_txb
: opc
= OPC_SAMB
; break;
2364 case nir_texop_txl
: opc
= OPC_SAML
; break;
2365 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
2366 case nir_texop_txf
: opc
= OPC_ISAML
; break;
2367 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
2369 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2370 * what blob does, seems gather is broken?), and a3xx did
2371 * not support it (but probably could also emulate).
2373 switch (tex
->component
) {
2374 case 0: opc
= OPC_GATHER4R
; break;
2375 case 1: opc
= OPC_GATHER4G
; break;
2376 case 2: opc
= OPC_GATHER4B
; break;
2377 case 3: opc
= OPC_GATHER4A
; break;
2380 case nir_texop_txf_ms
:
2382 case nir_texop_query_levels
:
2383 case nir_texop_texture_samples
:
2384 case nir_texop_samples_identical
:
2385 case nir_texop_txf_ms_mcs
:
2386 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
2390 tex_info(tex
, &flags
, &coords
);
2393 * lay out the first argument in the proper order:
2394 * - actual coordinates first
2395 * - shadow reference
2398 * - starting at offset 4, dpdx.xy, dpdy.xy
2400 * bias/lod go into the second arg
2403 /* insert tex coords: */
2404 for (i
= 0; i
< coords
; i
++)
2409 /* scale up integer coords for TXF based on the LOD */
2410 if (ctx
->unminify_coords
&& (opc
== OPC_ISAML
)) {
2412 for (i
= 0; i
< coords
; i
++)
2413 src0
[i
] = ir3_SHL_B(b
, src0
[i
], 0, lod
, 0);
2417 /* hw doesn't do 1d, so we treat it as 2d with
2418 * height of 1, and patch up the y coord.
2419 * TODO: y coord should be (int)0 in some cases..
2421 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
2424 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2425 src0
[nsrc0
++] = compare
;
2427 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
) {
2428 struct ir3_instruction
*idx
= coord
[coords
];
2430 /* the array coord for cube arrays needs 0.5 added to it */
2431 if (ctx
->array_index_add_half
&& (opc
!= OPC_ISAML
))
2432 idx
= ir3_ADD_F(b
, idx
, 0, create_immed(b
, fui(0.5)), 0);
2434 src0
[nsrc0
++] = idx
;
2438 src0
[nsrc0
++] = proj
;
2439 flags
|= IR3_INSTR_P
;
2442 /* pad to 4, then ddx/ddy: */
2443 if (tex
->op
== nir_texop_txd
) {
2445 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2446 for (i
= 0; i
< coords
; i
++)
2447 src0
[nsrc0
++] = ddx
[i
];
2449 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2450 for (i
= 0; i
< coords
; i
++)
2451 src0
[nsrc0
++] = ddy
[i
];
2453 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2457 * second argument (if applicable):
2462 if (has_off
| has_lod
| has_bias
) {
2464 unsigned off_coords
= coords
;
2465 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2467 for (i
= 0; i
< off_coords
; i
++)
2468 src1
[nsrc1
++] = off
[i
];
2470 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
2471 flags
|= IR3_INSTR_O
;
2474 if (has_lod
| has_bias
)
2475 src1
[nsrc1
++] = lod
;
2478 switch (tex
->dest_type
) {
2479 case nir_type_invalid
:
2480 case nir_type_float
:
2491 unreachable("bad dest_type");
2494 if (opc
== OPC_GETLOD
)
2497 unsigned tex_idx
= tex
->texture_index
;
2499 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex_idx
);
2501 struct ir3_instruction
*col0
= create_collect(ctx
, src0
, nsrc0
);
2502 struct ir3_instruction
*col1
= create_collect(ctx
, src1
, nsrc1
);
2504 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
, flags
,
2505 tex_idx
, tex_idx
, col0
, col1
);
2507 if ((ctx
->astc_srgb
& (1 << tex_idx
)) && !nir_tex_instr_is_query(tex
)) {
2508 /* only need first 3 components: */
2509 sam
->regs
[0]->wrmask
= 0x7;
2510 split_dest(b
, dst
, sam
, 0, 3);
2512 /* we need to sample the alpha separately with a non-ASTC
2515 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_W
, flags
,
2516 tex_idx
, tex_idx
, col0
, col1
);
2518 array_insert(ctx
->ir
, ctx
->ir
->astc_srgb
, sam
);
2520 /* fixup .w component: */
2521 split_dest(b
, &dst
[3], sam
, 3, 1);
2523 /* normal (non-workaround) case: */
2524 split_dest(b
, dst
, sam
, 0, 4);
2527 /* GETLOD returns results in 4.8 fixed point */
2528 if (opc
== OPC_GETLOD
) {
2529 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
2531 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
2532 for (i
= 0; i
< 2; i
++) {
2533 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_U32
, TYPE_F32
), 0,
2538 put_dst(ctx
, &tex
->dest
);
2542 emit_tex_query_levels(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2544 struct ir3_block
*b
= ctx
->block
;
2545 struct ir3_instruction
**dst
, *sam
;
2547 dst
= get_dst(ctx
, &tex
->dest
, 1);
2549 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
2550 tex
->texture_index
, tex
->texture_index
, NULL
, NULL
);
2552 /* even though there is only one component, since it ends
2553 * up in .z rather than .x, we need a split_dest()
2555 split_dest(b
, dst
, sam
, 0, 3);
2557 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2558 * the value in TEX_CONST_0 is zero-based.
2560 if (ctx
->levels_add_one
)
2561 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
2563 put_dst(ctx
, &tex
->dest
);
2567 emit_tex_txs(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2569 struct ir3_block
*b
= ctx
->block
;
2570 struct ir3_instruction
**dst
, *sam
;
2571 struct ir3_instruction
*lod
;
2572 unsigned flags
, coords
;
2574 tex_info(tex
, &flags
, &coords
);
2576 /* Actually we want the number of dimensions, not coordinates. This
2577 * distinction only matters for cubes.
2579 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2582 dst
= get_dst(ctx
, &tex
->dest
, 4);
2584 compile_assert(ctx
, tex
->num_srcs
== 1);
2585 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
2587 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
2589 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
2590 tex
->texture_index
, tex
->texture_index
, lod
, NULL
);
2592 split_dest(b
, dst
, sam
, 0, 4);
2594 /* Array size actually ends up in .w rather than .z. This doesn't
2595 * matter for miplevel 0, but for higher mips the value in z is
2596 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2597 * returned, which means that we have to add 1 to it for arrays.
2599 if (tex
->is_array
) {
2600 if (ctx
->levels_add_one
) {
2601 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
2603 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
2607 put_dst(ctx
, &tex
->dest
);
2611 emit_jump(struct ir3_context
*ctx
, nir_jump_instr
*jump
)
2613 switch (jump
->type
) {
2614 case nir_jump_break
:
2615 case nir_jump_continue
:
2616 case nir_jump_return
:
2617 /* I *think* we can simply just ignore this, and use the
2618 * successor block link to figure out where we need to
2619 * jump to for break/continue
2623 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
2629 emit_instr(struct ir3_context
*ctx
, nir_instr
*instr
)
2631 switch (instr
->type
) {
2632 case nir_instr_type_alu
:
2633 emit_alu(ctx
, nir_instr_as_alu(instr
));
2635 case nir_instr_type_intrinsic
:
2636 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2638 case nir_instr_type_load_const
:
2639 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2641 case nir_instr_type_ssa_undef
:
2642 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
2644 case nir_instr_type_tex
: {
2645 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
2646 /* couple tex instructions get special-cased:
2650 emit_tex_txs(ctx
, tex
);
2652 case nir_texop_query_levels
:
2653 emit_tex_query_levels(ctx
, tex
);
2661 case nir_instr_type_jump
:
2662 emit_jump(ctx
, nir_instr_as_jump(instr
));
2664 case nir_instr_type_phi
:
2665 /* we have converted phi webs to regs in NIR by now */
2666 compile_error(ctx
, "Unexpected NIR instruction type: %d\n", instr
->type
);
2668 case nir_instr_type_call
:
2669 case nir_instr_type_parallel_copy
:
2670 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
2675 static struct ir3_block
*
2676 get_block(struct ir3_context
*ctx
, const nir_block
*nblock
)
2678 struct ir3_block
*block
;
2679 struct hash_entry
*hentry
;
2680 struct set_entry
*sentry
;
2683 hentry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
2685 return hentry
->data
;
2687 block
= ir3_block_create(ctx
->ir
);
2688 block
->nblock
= nblock
;
2689 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
2691 block
->predecessors_count
= nblock
->predecessors
->entries
;
2692 block
->predecessors
= ralloc_array_size(block
,
2693 sizeof(block
->predecessors
[0]), block
->predecessors_count
);
2695 set_foreach(nblock
->predecessors
, sentry
) {
2696 block
->predecessors
[i
++] = get_block(ctx
, sentry
->key
);
2703 emit_block(struct ir3_context
*ctx
, nir_block
*nblock
)
2705 struct ir3_block
*block
= get_block(ctx
, nblock
);
2707 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
2708 if (nblock
->successors
[i
]) {
2709 block
->successors
[i
] =
2710 get_block(ctx
, nblock
->successors
[i
]);
2715 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
2717 /* re-emit addr register in each block if needed: */
2718 for (int i
= 0; i
< ARRAY_SIZE(ctx
->addr_ht
); i
++) {
2719 _mesa_hash_table_destroy(ctx
->addr_ht
[i
], NULL
);
2720 ctx
->addr_ht
[i
] = NULL
;
2723 nir_foreach_instr(instr
, nblock
) {
2724 emit_instr(ctx
, instr
);
2730 static void emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
);
2733 emit_if(struct ir3_context
*ctx
, nir_if
*nif
)
2735 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
2737 ctx
->block
->condition
=
2738 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
2740 emit_cf_list(ctx
, &nif
->then_list
);
2741 emit_cf_list(ctx
, &nif
->else_list
);
2745 emit_loop(struct ir3_context
*ctx
, nir_loop
*nloop
)
2747 emit_cf_list(ctx
, &nloop
->body
);
2751 emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
)
2753 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2754 switch (node
->type
) {
2755 case nir_cf_node_block
:
2756 emit_block(ctx
, nir_cf_node_as_block(node
));
2758 case nir_cf_node_if
:
2759 emit_if(ctx
, nir_cf_node_as_if(node
));
2761 case nir_cf_node_loop
:
2762 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2764 case nir_cf_node_function
:
2765 compile_error(ctx
, "TODO\n");
2771 /* emit stream-out code. At this point, the current block is the original
2772 * (nir) end block, and nir ensures that all flow control paths terminate
2773 * into the end block. We re-purpose the original end block to generate
2774 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2775 * block holding stream-out write instructions, followed by the new end
2779 * p0.x = (vtxcnt < maxvtxcnt)
2780 * // succs: blockStreamOut, blockNewEnd
2783 * ... stream-out instructions ...
2784 * // succs: blockNewEnd
2790 emit_stream_out(struct ir3_context
*ctx
)
2792 struct ir3_shader_variant
*v
= ctx
->so
;
2793 struct ir3
*ir
= ctx
->ir
;
2794 struct pipe_stream_output_info
*strmout
=
2795 &ctx
->so
->shader
->stream_output
;
2796 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
2797 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
2798 struct ir3_instruction
*bases
[PIPE_MAX_SO_BUFFERS
];
2800 /* create vtxcnt input in input block at top of shader,
2801 * so that it is seen as live over the entire duration
2804 vtxcnt
= create_input(ctx
->in_block
, 0);
2805 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
2807 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
2809 /* at this point, we are at the original 'end' block,
2810 * re-purpose this block to stream-out condition, then
2811 * append stream-out block and new-end block
2813 orig_end_block
= ctx
->block
;
2815 // TODO these blocks need to update predecessors..
2816 // maybe w/ store_global intrinsic, we could do this
2817 // stuff in nir->nir pass
2819 stream_out_block
= ir3_block_create(ir
);
2820 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
2822 new_end_block
= ir3_block_create(ir
);
2823 list_addtail(&new_end_block
->node
, &ir
->block_list
);
2825 orig_end_block
->successors
[0] = stream_out_block
;
2826 orig_end_block
->successors
[1] = new_end_block
;
2827 stream_out_block
->successors
[0] = new_end_block
;
2829 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2830 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
2831 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2832 cond
->cat2
.condition
= IR3_COND_LT
;
2834 /* condition goes on previous block to the conditional,
2835 * since it is used to pick which of the two successor
2838 orig_end_block
->condition
= cond
;
2840 /* switch to stream_out_block to generate the stream-out
2843 ctx
->block
= stream_out_block
;
2845 /* Calculate base addresses based on vtxcnt. Instructions
2846 * generated for bases not used in following loop will be
2847 * stripped out in the backend.
2849 for (unsigned i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
2850 unsigned stride
= strmout
->stride
[i
];
2851 struct ir3_instruction
*base
, *off
;
2853 base
= create_uniform(ctx
, regid(v
->constbase
.tfbo
, i
));
2855 /* 24-bit should be enough: */
2856 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
2857 create_immed(ctx
->block
, stride
* 4), 0);
2859 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
2862 /* Generate the per-output store instructions: */
2863 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
2864 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
2865 unsigned c
= j
+ strmout
->output
[i
].start_component
;
2866 struct ir3_instruction
*base
, *out
, *stg
;
2868 base
= bases
[strmout
->output
[i
].output_buffer
];
2869 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
2871 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
2872 create_immed(ctx
->block
, 1), 0);
2873 stg
->cat6
.type
= TYPE_U32
;
2874 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
2876 array_insert(ctx
->block
, ctx
->block
->keeps
, stg
);
2880 /* and finally switch to the new_end_block: */
2881 ctx
->block
= new_end_block
;
2885 emit_function(struct ir3_context
*ctx
, nir_function_impl
*impl
)
2887 nir_metadata_require(impl
, nir_metadata_block_index
);
2889 emit_cf_list(ctx
, &impl
->body
);
2890 emit_block(ctx
, impl
->end_block
);
2892 /* at this point, we should have a single empty block,
2893 * into which we emit the 'end' instruction.
2895 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
2897 /* If stream-out (aka transform-feedback) enabled, emit the
2898 * stream-out instructions, followed by a new empty block (into
2899 * which the 'end' instruction lands).
2901 * NOTE: it is done in this order, rather than inserting before
2902 * we emit end_block, because NIR guarantees that all blocks
2903 * flow into end_block, and that end_block has no successors.
2904 * So by re-purposing end_block as the first block of stream-
2905 * out, we guarantee that all exit paths flow into the stream-
2908 if ((ctx
->compiler
->gpu_id
< 500) &&
2909 (ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
2910 !ctx
->so
->key
.binning_pass
) {
2911 debug_assert(ctx
->so
->type
== SHADER_VERTEX
);
2912 emit_stream_out(ctx
);
2915 ir3_END(ctx
->block
);
2919 setup_input(struct ir3_context
*ctx
, nir_variable
*in
)
2921 struct ir3_shader_variant
*so
= ctx
->so
;
2922 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
2923 unsigned ncomp
= glsl_get_components(in
->type
);
2924 unsigned n
= in
->data
.driver_location
;
2925 unsigned slot
= in
->data
.location
;
2927 DBG("; in: slot=%u, len=%ux%u, drvloc=%u",
2928 slot
, array_len
, ncomp
, n
);
2930 /* let's pretend things other than vec4 don't exist: */
2931 ncomp
= MAX2(ncomp
, 4);
2932 compile_assert(ctx
, ncomp
== 4);
2934 so
->inputs
[n
].slot
= slot
;
2935 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
2936 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2937 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
2939 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2940 for (int i
= 0; i
< ncomp
; i
++) {
2941 struct ir3_instruction
*instr
= NULL
;
2942 unsigned idx
= (n
* 4) + i
;
2944 if (slot
== VARYING_SLOT_POS
) {
2945 so
->inputs
[n
].bary
= false;
2946 so
->frag_coord
= true;
2947 instr
= create_frag_coord(ctx
, i
);
2948 } else if (slot
== VARYING_SLOT_PNTC
) {
2949 /* see for example st_get_generic_varying_index().. this is
2950 * maybe a bit mesa/st specific. But we need things to line
2951 * up for this in fdN_program:
2952 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2953 * if (emit->sprite_coord_enable & texmask) {
2957 so
->inputs
[n
].slot
= VARYING_SLOT_VAR8
;
2958 so
->inputs
[n
].bary
= true;
2959 instr
= create_frag_input(ctx
, false);
2961 bool use_ldlv
= false;
2963 /* detect the special case for front/back colors where
2964 * we need to do flat vs smooth shading depending on
2967 if (in
->data
.interpolation
== INTERP_MODE_NONE
) {
2969 case VARYING_SLOT_COL0
:
2970 case VARYING_SLOT_COL1
:
2971 case VARYING_SLOT_BFC0
:
2972 case VARYING_SLOT_BFC1
:
2973 so
->inputs
[n
].rasterflat
= true;
2980 if (ctx
->flat_bypass
) {
2981 if ((so
->inputs
[n
].interpolate
== INTERP_MODE_FLAT
) ||
2982 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
2986 so
->inputs
[n
].bary
= true;
2988 instr
= create_frag_input(ctx
, use_ldlv
);
2991 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
2993 ctx
->ir
->inputs
[idx
] = instr
;
2995 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2996 for (int i
= 0; i
< ncomp
; i
++) {
2997 unsigned idx
= (n
* 4) + i
;
2998 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
2999 ctx
->ir
->inputs
[idx
] = create_input(ctx
->block
, idx
);
3002 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3005 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
3006 so
->total_in
+= ncomp
;
3011 setup_output(struct ir3_context
*ctx
, nir_variable
*out
)
3013 struct ir3_shader_variant
*so
= ctx
->so
;
3014 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
3015 unsigned ncomp
= glsl_get_components(out
->type
);
3016 unsigned n
= out
->data
.driver_location
;
3017 unsigned slot
= out
->data
.location
;
3020 DBG("; out: slot=%u, len=%ux%u, drvloc=%u",
3021 slot
, array_len
, ncomp
, n
);
3023 /* let's pretend things other than vec4 don't exist: */
3024 ncomp
= MAX2(ncomp
, 4);
3025 compile_assert(ctx
, ncomp
== 4);
3027 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3029 case FRAG_RESULT_DEPTH
:
3030 comp
= 2; /* tgsi will write to .z component */
3031 so
->writes_pos
= true;
3033 case FRAG_RESULT_COLOR
:
3037 if (slot
>= FRAG_RESULT_DATA0
)
3039 compile_error(ctx
, "unknown FS output name: %s\n",
3040 gl_frag_result_name(slot
));
3042 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
3044 case VARYING_SLOT_POS
:
3045 so
->writes_pos
= true;
3047 case VARYING_SLOT_PSIZ
:
3048 so
->writes_psize
= true;
3050 case VARYING_SLOT_COL0
:
3051 case VARYING_SLOT_COL1
:
3052 case VARYING_SLOT_BFC0
:
3053 case VARYING_SLOT_BFC1
:
3054 case VARYING_SLOT_FOGC
:
3055 case VARYING_SLOT_CLIP_DIST0
:
3056 case VARYING_SLOT_CLIP_DIST1
:
3057 case VARYING_SLOT_CLIP_VERTEX
:
3060 if (slot
>= VARYING_SLOT_VAR0
)
3062 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
3064 compile_error(ctx
, "unknown VS output name: %s\n",
3065 gl_varying_slot_name(slot
));
3068 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3071 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
3073 so
->outputs
[n
].slot
= slot
;
3074 so
->outputs
[n
].regid
= regid(n
, comp
);
3075 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
3077 for (int i
= 0; i
< ncomp
; i
++) {
3078 unsigned idx
= (n
* 4) + i
;
3079 compile_assert(ctx
, idx
< ctx
->ir
->noutputs
);
3080 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
3085 max_drvloc(struct exec_list
*vars
)
3088 nir_foreach_variable(var
, vars
) {
3089 drvloc
= MAX2(drvloc
, (int)var
->data
.driver_location
);
3094 static const unsigned max_sysvals
[SHADER_MAX
] = {
3095 [SHADER_VERTEX
] = 16,
3096 [SHADER_COMPUTE
] = 16, // TODO how many do we actually need?
3100 emit_instructions(struct ir3_context
*ctx
)
3102 unsigned ninputs
, noutputs
;
3103 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
3105 ninputs
= (max_drvloc(&ctx
->s
->inputs
) + 1) * 4;
3106 noutputs
= (max_drvloc(&ctx
->s
->outputs
) + 1) * 4;
3108 /* we need to leave room for sysvals:
3110 ninputs
+= max_sysvals
[ctx
->so
->type
];
3112 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
3114 /* Create inputs in first block: */
3115 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
3116 ctx
->in_block
= ctx
->block
;
3117 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
3119 ninputs
-= max_sysvals
[ctx
->so
->type
];
3121 /* for fragment shader, we have a single input register (usually
3122 * r0.xy) which is used as the base for bary.f varying fetch instrs:
3124 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3125 // TODO maybe a helper for fi since we need it a few places..
3126 struct ir3_instruction
*instr
;
3127 instr
= ir3_instr_create(ctx
->block
, OPC_META_FI
);
3128 ir3_reg_create(instr
, 0, 0);
3129 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.x */
3130 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.y */
3131 ctx
->frag_pos
= instr
;
3135 nir_foreach_variable(var
, &ctx
->s
->inputs
) {
3136 setup_input(ctx
, var
);
3139 /* Setup outputs: */
3140 nir_foreach_variable(var
, &ctx
->s
->outputs
) {
3141 setup_output(ctx
, var
);
3144 /* Setup registers (which should only be arrays): */
3145 nir_foreach_register(reg
, &ctx
->s
->registers
) {
3146 declare_array(ctx
, reg
);
3149 /* NOTE: need to do something more clever when we support >1 fxn */
3150 nir_foreach_register(reg
, &fxn
->registers
) {
3151 declare_array(ctx
, reg
);
3153 /* And emit the body: */
3155 emit_function(ctx
, fxn
);
3158 /* from NIR perspective, we actually have inputs. But most of the "inputs"
3159 * for a fragment shader are just bary.f instructions. The *actual* inputs
3160 * from the hw perspective are the frag_pos and optionally frag_coord and
3164 fixup_frag_inputs(struct ir3_context
*ctx
)
3166 struct ir3_shader_variant
*so
= ctx
->so
;
3167 struct ir3
*ir
= ctx
->ir
;
3168 struct ir3_instruction
**inputs
;
3169 struct ir3_instruction
*instr
;
3174 n
= 4; /* always have frag_pos */
3175 n
+= COND(so
->frag_face
, 4);
3176 n
+= COND(so
->frag_coord
, 4);
3178 inputs
= ir3_alloc(ctx
->ir
, n
* (sizeof(struct ir3_instruction
*)));
3180 if (so
->frag_face
) {
3181 /* this ultimately gets assigned to hr0.x so doesn't conflict
3182 * with frag_coord/frag_pos..
3184 inputs
[ir
->ninputs
++] = ctx
->frag_face
;
3185 ctx
->frag_face
->regs
[0]->num
= 0;
3187 /* remaining channels not used, but let's avoid confusing
3188 * other parts that expect inputs to come in groups of vec4
3190 inputs
[ir
->ninputs
++] = NULL
;
3191 inputs
[ir
->ninputs
++] = NULL
;
3192 inputs
[ir
->ninputs
++] = NULL
;
3195 /* since we don't know where to set the regid for frag_coord,
3196 * we have to use r0.x for it. But we don't want to *always*
3197 * use r1.x for frag_pos as that could increase the register
3198 * footprint on simple shaders:
3200 if (so
->frag_coord
) {
3201 ctx
->frag_coord
[0]->regs
[0]->num
= regid
++;
3202 ctx
->frag_coord
[1]->regs
[0]->num
= regid
++;
3203 ctx
->frag_coord
[2]->regs
[0]->num
= regid
++;
3204 ctx
->frag_coord
[3]->regs
[0]->num
= regid
++;
3206 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[0];
3207 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[1];
3208 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[2];
3209 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[3];
3212 /* we always have frag_pos: */
3213 so
->pos_regid
= regid
;
3216 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
3217 instr
->regs
[0]->num
= regid
++;
3218 inputs
[ir
->ninputs
++] = instr
;
3219 ctx
->frag_pos
->regs
[1]->instr
= instr
;
3222 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
3223 instr
->regs
[0]->num
= regid
++;
3224 inputs
[ir
->ninputs
++] = instr
;
3225 ctx
->frag_pos
->regs
[2]->instr
= instr
;
3227 ir
->inputs
= inputs
;
3230 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3231 * need to assign the tex state indexes for these after we know the
3235 fixup_astc_srgb(struct ir3_context
*ctx
)
3237 struct ir3_shader_variant
*so
= ctx
->so
;
3238 /* indexed by original tex idx, value is newly assigned alpha sampler
3239 * state tex idx. Zero is invalid since there is at least one sampler
3242 unsigned alt_tex_state
[16] = {0};
3243 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
3246 so
->astc_srgb
.base
= tex_idx
;
3248 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
3249 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
3251 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
3253 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
3254 /* assign new alternate/alpha tex state slot: */
3255 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
3256 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
3257 so
->astc_srgb
.count
++;
3260 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
3265 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
3266 struct ir3_shader_variant
*so
)
3268 struct ir3_context
*ctx
;
3270 struct ir3_instruction
**inputs
;
3271 unsigned i
, j
, actual_in
, inloc
;
3272 int ret
= 0, max_bary
;
3276 ctx
= compile_init(compiler
, so
);
3278 DBG("INIT failed!");
3283 emit_instructions(ctx
);
3286 DBG("EMIT failed!");
3291 ir
= so
->ir
= ctx
->ir
;
3293 /* keep track of the inputs from TGSI perspective.. */
3294 inputs
= ir
->inputs
;
3296 /* but fixup actual inputs for frag shader: */
3297 if (so
->type
== SHADER_FRAGMENT
)
3298 fixup_frag_inputs(ctx
);
3300 /* at this point, for binning pass, throw away unneeded outputs: */
3301 if (so
->key
.binning_pass
) {
3302 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
3303 unsigned slot
= so
->outputs
[i
].slot
;
3305 /* throw away everything but first position/psize */
3306 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
3308 so
->outputs
[j
] = so
->outputs
[i
];
3309 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
3310 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
3311 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
3312 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
3317 so
->outputs_count
= j
;
3318 ir
->noutputs
= j
* 4;
3321 /* if we want half-precision outputs, mark the output registers
3324 if (so
->key
.half_precision
) {
3325 for (i
= 0; i
< ir
->noutputs
; i
++) {
3326 struct ir3_instruction
*out
= ir
->outputs
[i
];
3331 /* if frag shader writes z, that needs to be full precision: */
3332 if (so
->outputs
[i
/4].slot
== FRAG_RESULT_DEPTH
)
3335 out
->regs
[0]->flags
|= IR3_REG_HALF
;
3336 /* output could be a fanout (ie. texture fetch output)
3337 * in which case we need to propagate the half-reg flag
3338 * up to the definer so that RA sees it:
3340 if (out
->opc
== OPC_META_FO
) {
3341 out
= out
->regs
[1]->instr
;
3342 out
->regs
[0]->flags
|= IR3_REG_HALF
;
3345 if (out
->opc
== OPC_MOV
) {
3346 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
3351 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3352 printf("BEFORE CP:\n");
3358 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3359 printf("BEFORE GROUPING:\n");
3363 ir3_sched_add_deps(ir
);
3365 /* Group left/right neighbors, inserting mov's where needed to
3370 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3371 printf("AFTER GROUPING:\n");
3377 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3378 printf("AFTER DEPTH:\n");
3382 ret
= ir3_sched(ir
);
3384 DBG("SCHED failed!");
3388 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3389 printf("AFTER SCHED:\n");
3393 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
3399 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3400 printf("AFTER RA:\n");
3404 /* fixup input/outputs: */
3405 for (i
= 0; i
< so
->outputs_count
; i
++) {
3406 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
3409 /* Note that some or all channels of an input may be unused: */
3412 for (i
= 0; i
< so
->inputs_count
; i
++) {
3413 unsigned j
, regid
= ~0, compmask
= 0, maxcomp
= 0;
3414 so
->inputs
[i
].ncomp
= 0;
3415 so
->inputs
[i
].inloc
= inloc
;
3416 for (j
= 0; j
< 4; j
++) {
3417 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
3418 if (in
&& !(in
->flags
& IR3_INSTR_UNUSED
)) {
3419 compmask
|= (1 << j
);
3420 regid
= in
->regs
[0]->num
- j
;
3422 so
->inputs
[i
].ncomp
++;
3423 if ((so
->type
== SHADER_FRAGMENT
) && so
->inputs
[i
].bary
) {
3425 assert(in
->regs
[1]->flags
& IR3_REG_IMMED
);
3426 in
->regs
[1]->iim_val
= inloc
+ j
;
3431 if ((so
->type
== SHADER_FRAGMENT
) && compmask
&& so
->inputs
[i
].bary
) {
3433 so
->inputs
[i
].compmask
= (1 << maxcomp
) - 1;
3435 } else if (!so
->inputs
[i
].sysval
){
3436 so
->inputs
[i
].compmask
= compmask
;
3438 so
->inputs
[i
].regid
= regid
;
3442 fixup_astc_srgb(ctx
);
3444 /* We need to do legalize after (for frag shader's) the "bary.f"
3445 * offsets (inloc) have been assigned.
3447 ir3_legalize(ir
, &so
->has_samp
, &so
->has_ssbo
, &max_bary
);
3449 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3450 printf("AFTER LEGALIZE:\n");
3454 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3455 if (so
->type
== SHADER_VERTEX
)
3456 so
->total_in
= actual_in
;
3458 so
->total_in
= max_bary
+ 1;
3463 ir3_destroy(so
->ir
);