2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
34 #include "freedreno_util.h"
36 #include "ir3_compiler.h"
37 #include "ir3_shader.h"
40 #include "instr-a3xx.h"
45 struct ir3_compiler
*compiler
;
49 struct nir_instr
*cur_instr
; /* current instruction, just for debug */
52 struct ir3_shader_variant
*so
;
54 struct ir3_block
*block
; /* the current block */
55 struct ir3_block
*in_block
; /* block created for shader inputs */
57 nir_function_impl
*impl
;
59 /* For fragment shaders, varyings are not actual shader inputs,
60 * instead the hw passes a varying-coord which is used with
63 * But NIR doesn't know that, it still declares varyings as
64 * inputs. So we do all the input tracking normally and fix
65 * things up after compile_instructions()
67 * NOTE that frag_vcoord is the hardware position (possibly it
68 * is actually an index or tag or some such.. it is *not*
69 * values that can be directly used for gl_FragCoord..)
71 struct ir3_instruction
*frag_vcoord
;
73 /* for fragment shaders, for gl_FrontFacing and gl_FragCoord: */
74 struct ir3_instruction
*frag_face
, *frag_coord
;
76 /* For vertex shaders, keep track of the system values sources */
77 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
79 /* For fragment shaders: */
80 struct ir3_instruction
*samp_id
, *samp_mask_in
;
82 /* Compute shader inputs: */
83 struct ir3_instruction
*local_invocation_id
, *work_group_id
;
85 /* mapping from nir_register to defining instruction: */
86 struct hash_table
*def_ht
;
90 /* a common pattern for indirect addressing is to request the
91 * same address register multiple times. To avoid generating
92 * duplicate instruction sequences (which our backend does not
93 * try to clean up, since that should be done as the NIR stage)
94 * we cache the address value generated for a given src value:
96 * Note that we have to cache these per alignment, since same
97 * src used for an array of vec1 cannot be also used for an
100 struct hash_table
*addr_ht
[4];
102 /* last dst array, for indirect we need to insert a var-store.
104 struct ir3_instruction
**last_dst
;
107 /* maps nir_block to ir3_block, mostly for the purposes of
108 * figuring out the blocks successors
110 struct hash_table
*block_ht
;
112 /* on a4xx, bitmask of samplers which need astc+srgb workaround: */
115 unsigned samples
; /* bitmask of x,y sample shifts */
117 unsigned max_texture_index
;
119 /* set if we encounter something we can't handle yet, so we
120 * can bail cleanly and fallback to TGSI compiler f/e
125 /* gpu pointer size in units of 32bit registers/slots */
126 static unsigned pointer_size(struct ir3_context
*ctx
)
128 return (ctx
->compiler
->gpu_id
>= 500) ? 2 : 1;
131 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
132 static struct ir3_block
* get_block(struct ir3_context
*ctx
, const nir_block
*nblock
);
135 static struct ir3_context
*
136 compile_init(struct ir3_compiler
*compiler
,
137 struct ir3_shader_variant
*so
)
139 struct ir3_context
*ctx
= rzalloc(NULL
, struct ir3_context
);
141 if (compiler
->gpu_id
>= 400) {
142 if (so
->type
== MESA_SHADER_VERTEX
) {
143 ctx
->astc_srgb
= so
->key
.vastc_srgb
;
144 } else if (so
->type
== MESA_SHADER_FRAGMENT
) {
145 ctx
->astc_srgb
= so
->key
.fastc_srgb
;
149 if (so
->type
== MESA_SHADER_VERTEX
) {
150 ctx
->samples
= so
->key
.vsamples
;
151 } else if (so
->type
== MESA_SHADER_FRAGMENT
) {
152 ctx
->samples
= so
->key
.fsamples
;
156 ctx
->compiler
= compiler
;
158 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
159 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
160 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
161 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
163 /* TODO: maybe generate some sort of bitmask of what key
164 * lowers vs what shader has (ie. no need to lower
165 * texture clamp lowering if no texture sample instrs)..
166 * although should be done further up the stack to avoid
167 * creating duplicate variants..
170 if (ir3_key_lowers_nir(&so
->key
)) {
171 nir_shader
*s
= nir_shader_clone(ctx
, so
->shader
->nir
);
172 ctx
->s
= ir3_optimize_nir(so
->shader
, s
, &so
->key
);
174 /* fast-path for shader key that lowers nothing in NIR: */
175 ctx
->s
= so
->shader
->nir
;
178 /* this needs to be the last pass run, so do this here instead of
179 * in ir3_optimize_nir():
181 NIR_PASS_V(ctx
->s
, nir_lower_locals_to_regs
);
182 NIR_PASS_V(ctx
->s
, nir_convert_from_ssa
, true);
184 if (ir3_shader_debug
& IR3_DBG_DISASM
) {
185 DBG("dump nir%dv%d: type=%d, k={cts=%u,hp=%u}",
186 so
->shader
->id
, so
->id
, so
->type
,
187 so
->key
.color_two_side
, so
->key
.half_precision
);
188 nir_print_shader(ctx
->s
, stdout
);
191 if (shader_debug_enabled(so
->type
)) {
192 fprintf(stderr
, "NIR (final form) for %s shader:\n",
193 _mesa_shader_stage_to_string(so
->type
));
194 nir_print_shader(ctx
->s
, stderr
);
197 ir3_nir_scan_driver_consts(ctx
->s
, &so
->const_layout
);
199 so
->num_uniforms
= ctx
->s
->num_uniforms
;
200 so
->num_ubos
= ctx
->s
->info
.num_ubos
;
202 /* Layout of constant registers, each section aligned to vec4. Note
203 * that pointer size (ubo, etc) changes depending on generation.
208 * if (vertex shader) {
209 * driver params (IR3_DP_*)
210 * if (stream_output.num_outputs > 0)
211 * stream-out addresses
215 * Immediates go last mostly because they are inserted in the CP pass
216 * after the nir -> ir3 frontend.
218 unsigned constoff
= align(ctx
->s
->num_uniforms
, 4);
219 unsigned ptrsz
= pointer_size(ctx
);
221 memset(&so
->constbase
, ~0, sizeof(so
->constbase
));
223 if (so
->num_ubos
> 0) {
224 so
->constbase
.ubo
= constoff
;
225 constoff
+= align(ctx
->s
->info
.num_ubos
* ptrsz
, 4) / 4;
228 if (so
->const_layout
.ssbo_size
.count
> 0) {
229 unsigned cnt
= so
->const_layout
.ssbo_size
.count
;
230 so
->constbase
.ssbo_sizes
= constoff
;
231 constoff
+= align(cnt
, 4) / 4;
234 if (so
->const_layout
.image_dims
.count
> 0) {
235 unsigned cnt
= so
->const_layout
.image_dims
.count
;
236 so
->constbase
.image_dims
= constoff
;
237 constoff
+= align(cnt
, 4) / 4;
240 unsigned num_driver_params
= 0;
241 if (so
->type
== MESA_SHADER_VERTEX
) {
242 num_driver_params
= IR3_DP_VS_COUNT
;
243 } else if (so
->type
== MESA_SHADER_COMPUTE
) {
244 num_driver_params
= IR3_DP_CS_COUNT
;
247 so
->constbase
.driver_param
= constoff
;
248 constoff
+= align(num_driver_params
, 4) / 4;
250 if ((so
->type
== MESA_SHADER_VERTEX
) &&
251 (compiler
->gpu_id
< 500) &&
252 so
->shader
->stream_output
.num_outputs
> 0) {
253 so
->constbase
.tfbo
= constoff
;
254 constoff
+= align(PIPE_MAX_SO_BUFFERS
* ptrsz
, 4) / 4;
257 so
->constbase
.immediate
= constoff
;
263 compile_error(struct ir3_context
*ctx
, const char *format
, ...)
265 struct hash_table
*errors
= NULL
;
267 va_start(ap
, format
);
268 if (ctx
->cur_instr
) {
269 errors
= _mesa_hash_table_create(NULL
,
271 _mesa_key_pointer_equal
);
272 char *msg
= ralloc_vasprintf(errors
, format
, ap
);
273 _mesa_hash_table_insert(errors
, ctx
->cur_instr
, msg
);
275 _debug_vprintf(format
, ap
);
278 nir_print_shader_annotated(ctx
->s
, stdout
, errors
);
284 #define compile_assert(ctx, cond) do { \
285 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
289 compile_free(struct ir3_context
*ctx
)
295 declare_array(struct ir3_context
*ctx
, nir_register
*reg
)
297 struct ir3_array
*arr
= rzalloc(ctx
, struct ir3_array
);
298 arr
->id
= ++ctx
->num_arrays
;
299 /* NOTE: sometimes we get non array regs, for example for arrays of
300 * length 1. See fs-const-array-of-struct-of-array.shader_test. So
301 * treat a non-array as if it was an array of length 1.
303 * It would be nice if there was a nir pass to convert arrays of
306 arr
->length
= reg
->num_components
* MAX2(1, reg
->num_array_elems
);
307 compile_assert(ctx
, arr
->length
> 0);
309 list_addtail(&arr
->node
, &ctx
->ir
->array_list
);
312 static struct ir3_array
*
313 get_array(struct ir3_context
*ctx
, nir_register
*reg
)
315 list_for_each_entry (struct ir3_array
, arr
, &ctx
->ir
->array_list
, node
) {
319 compile_error(ctx
, "bogus reg: %s\n", reg
->name
);
323 /* relative (indirect) if address!=NULL */
324 static struct ir3_instruction
*
325 create_array_load(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
326 struct ir3_instruction
*address
)
328 struct ir3_block
*block
= ctx
->block
;
329 struct ir3_instruction
*mov
;
330 struct ir3_register
*src
;
332 mov
= ir3_instr_create(block
, OPC_MOV
);
333 mov
->cat1
.src_type
= TYPE_U32
;
334 mov
->cat1
.dst_type
= TYPE_U32
;
335 mov
->barrier_class
= IR3_BARRIER_ARRAY_R
;
336 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_W
;
337 ir3_reg_create(mov
, 0, 0);
338 src
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
339 COND(address
, IR3_REG_RELATIV
));
340 src
->instr
= arr
->last_write
;
341 src
->size
= arr
->length
;
342 src
->array
.id
= arr
->id
;
343 src
->array
.offset
= n
;
346 ir3_instr_set_address(mov
, address
);
351 /* relative (indirect) if address!=NULL */
353 create_array_store(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
354 struct ir3_instruction
*src
, struct ir3_instruction
*address
)
356 struct ir3_block
*block
= ctx
->block
;
357 struct ir3_instruction
*mov
;
358 struct ir3_register
*dst
;
360 /* if not relative store, don't create an extra mov, since that
361 * ends up being difficult for cp to remove.
366 src
->barrier_class
|= IR3_BARRIER_ARRAY_W
;
367 src
->barrier_conflict
|= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
369 dst
->flags
|= IR3_REG_ARRAY
;
370 dst
->instr
= arr
->last_write
;
371 dst
->size
= arr
->length
;
372 dst
->array
.id
= arr
->id
;
373 dst
->array
.offset
= n
;
375 arr
->last_write
= src
;
377 array_insert(block
, block
->keeps
, src
);
382 mov
= ir3_instr_create(block
, OPC_MOV
);
383 mov
->cat1
.src_type
= TYPE_U32
;
384 mov
->cat1
.dst_type
= TYPE_U32
;
385 mov
->barrier_class
= IR3_BARRIER_ARRAY_W
;
386 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
387 dst
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
388 COND(address
, IR3_REG_RELATIV
));
389 dst
->instr
= arr
->last_write
;
390 dst
->size
= arr
->length
;
391 dst
->array
.id
= arr
->id
;
392 dst
->array
.offset
= n
;
393 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
396 ir3_instr_set_address(mov
, address
);
398 arr
->last_write
= mov
;
400 /* the array store may only matter to something in an earlier
401 * block (ie. loops), but since arrays are not in SSA, depth
402 * pass won't know this.. so keep all array stores:
404 array_insert(block
, block
->keeps
, mov
);
407 static inline type_t
utype_for_size(unsigned bit_size
)
410 case 32: return TYPE_U32
;
411 case 16: return TYPE_U16
;
412 case 8: return TYPE_U8
;
413 default: unreachable("bad bitsize"); return ~0;
417 static inline type_t
utype_src(nir_src src
)
418 { return utype_for_size(nir_src_bit_size(src
)); }
420 static inline type_t
utype_dst(nir_dest dst
)
421 { return utype_for_size(nir_dest_bit_size(dst
)); }
423 /* allocate a n element value array (to be populated by caller) and
426 static struct ir3_instruction
**
427 get_dst_ssa(struct ir3_context
*ctx
, nir_ssa_def
*dst
, unsigned n
)
429 struct ir3_instruction
**value
=
430 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
431 _mesa_hash_table_insert(ctx
->def_ht
, dst
, value
);
435 static struct ir3_instruction
**
436 get_dst(struct ir3_context
*ctx
, nir_dest
*dst
, unsigned n
)
438 struct ir3_instruction
**value
;
441 value
= get_dst_ssa(ctx
, &dst
->ssa
, n
);
443 value
= ralloc_array(ctx
, struct ir3_instruction
*, n
);
446 /* NOTE: in non-ssa case, we don't really need to store last_dst
447 * but this helps us catch cases where put_dst() call is forgotten
449 compile_assert(ctx
, !ctx
->last_dst
);
450 ctx
->last_dst
= value
;
456 static struct ir3_instruction
* get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
);
458 static struct ir3_instruction
* const *
459 get_src(struct ir3_context
*ctx
, nir_src
*src
)
462 struct hash_entry
*entry
;
463 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
464 compile_assert(ctx
, entry
);
467 nir_register
*reg
= src
->reg
.reg
;
468 struct ir3_array
*arr
= get_array(ctx
, reg
);
469 unsigned num_components
= arr
->r
->num_components
;
470 struct ir3_instruction
*addr
= NULL
;
471 struct ir3_instruction
**value
=
472 ralloc_array(ctx
, struct ir3_instruction
*, num_components
);
474 if (src
->reg
.indirect
)
475 addr
= get_addr(ctx
, get_src(ctx
, src
->reg
.indirect
)[0],
476 reg
->num_components
);
478 for (unsigned i
= 0; i
< num_components
; i
++) {
479 unsigned n
= src
->reg
.base_offset
* reg
->num_components
+ i
;
480 compile_assert(ctx
, n
< arr
->length
);
481 value
[i
] = create_array_load(ctx
, arr
, n
, addr
);
489 put_dst(struct ir3_context
*ctx
, nir_dest
*dst
)
491 unsigned bit_size
= nir_dest_bit_size(*dst
);
494 for (unsigned i
= 0; i
< ctx
->last_dst_n
; i
++) {
495 struct ir3_instruction
*dst
= ctx
->last_dst
[i
];
496 dst
->regs
[0]->flags
|= IR3_REG_HALF
;
497 if (ctx
->last_dst
[i
]->opc
== OPC_META_FO
)
498 dst
->regs
[1]->instr
->regs
[0]->flags
|= IR3_REG_HALF
;
503 nir_register
*reg
= dst
->reg
.reg
;
504 struct ir3_array
*arr
= get_array(ctx
, reg
);
505 unsigned num_components
= ctx
->last_dst_n
;
506 struct ir3_instruction
*addr
= NULL
;
508 if (dst
->reg
.indirect
)
509 addr
= get_addr(ctx
, get_src(ctx
, dst
->reg
.indirect
)[0],
510 reg
->num_components
);
512 for (unsigned i
= 0; i
< num_components
; i
++) {
513 unsigned n
= dst
->reg
.base_offset
* reg
->num_components
+ i
;
514 compile_assert(ctx
, n
< arr
->length
);
515 if (!ctx
->last_dst
[i
])
517 create_array_store(ctx
, arr
, n
, ctx
->last_dst
[i
], addr
);
520 ralloc_free(ctx
->last_dst
);
522 ctx
->last_dst
= NULL
;
526 static struct ir3_instruction
*
527 create_immed_typed(struct ir3_block
*block
, uint32_t val
, type_t type
)
529 struct ir3_instruction
*mov
;
530 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
532 mov
= ir3_instr_create(block
, OPC_MOV
);
533 mov
->cat1
.src_type
= type
;
534 mov
->cat1
.dst_type
= type
;
535 ir3_reg_create(mov
, 0, flags
);
536 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
541 static struct ir3_instruction
*
542 create_immed(struct ir3_block
*block
, uint32_t val
)
544 return create_immed_typed(block
, val
, TYPE_U32
);
547 static struct ir3_instruction
*
548 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
, int align
)
550 struct ir3_instruction
*instr
, *immed
;
552 /* TODO in at least some cases, the backend could probably be
553 * made clever enough to propagate IR3_REG_HALF..
555 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
556 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
563 /* src *= 2 => src <<= 1: */
564 immed
= create_immed(block
, 1);
565 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
567 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
568 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
569 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
573 immed
= create_immed(block
, 3);
574 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
576 instr
= ir3_MULL_U(block
, instr
, 0, immed
, 0);
577 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
578 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
581 /* src *= 4 => src <<= 2: */
582 immed
= create_immed(block
, 2);
583 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
585 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
586 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
587 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
590 unreachable("bad align");
594 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
595 instr
->regs
[0]->num
= regid(REG_A0
, 0);
596 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
597 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
602 /* caches addr values to avoid generating multiple cov/shl/mova
603 * sequences for each use of a given NIR level src as address
605 static struct ir3_instruction
*
606 get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
)
608 struct ir3_instruction
*addr
;
609 unsigned idx
= align
- 1;
611 compile_assert(ctx
, idx
< ARRAY_SIZE(ctx
->addr_ht
));
613 if (!ctx
->addr_ht
[idx
]) {
614 ctx
->addr_ht
[idx
] = _mesa_hash_table_create(ctx
,
615 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
617 struct hash_entry
*entry
;
618 entry
= _mesa_hash_table_search(ctx
->addr_ht
[idx
], src
);
623 addr
= create_addr(ctx
->block
, src
, align
);
624 _mesa_hash_table_insert(ctx
->addr_ht
[idx
], src
, addr
);
629 static struct ir3_instruction
*
630 get_predicate(struct ir3_context
*ctx
, struct ir3_instruction
*src
)
632 struct ir3_block
*b
= ctx
->block
;
633 struct ir3_instruction
*cond
;
635 /* NOTE: only cmps.*.* can write p0.x: */
636 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
637 cond
->cat2
.condition
= IR3_COND_NE
;
639 /* condition always goes in predicate register: */
640 cond
->regs
[0]->num
= regid(REG_P0
, 0);
645 static struct ir3_instruction
*
646 create_uniform(struct ir3_context
*ctx
, unsigned n
)
648 struct ir3_instruction
*mov
;
650 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
651 /* TODO get types right? */
652 mov
->cat1
.src_type
= TYPE_F32
;
653 mov
->cat1
.dst_type
= TYPE_F32
;
654 ir3_reg_create(mov
, 0, 0);
655 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
660 static struct ir3_instruction
*
661 create_uniform_indirect(struct ir3_context
*ctx
, int n
,
662 struct ir3_instruction
*address
)
664 struct ir3_instruction
*mov
;
666 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
667 mov
->cat1
.src_type
= TYPE_U32
;
668 mov
->cat1
.dst_type
= TYPE_U32
;
669 ir3_reg_create(mov
, 0, 0);
670 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
672 ir3_instr_set_address(mov
, address
);
677 static struct ir3_instruction
*
678 create_collect(struct ir3_context
*ctx
, struct ir3_instruction
*const *arr
,
681 struct ir3_block
*block
= ctx
->block
;
682 struct ir3_instruction
*collect
;
687 unsigned flags
= arr
[0]->regs
[0]->flags
& IR3_REG_HALF
;
689 collect
= ir3_instr_create2(block
, OPC_META_FI
, 1 + arrsz
);
690 ir3_reg_create(collect
, 0, flags
); /* dst */
691 for (unsigned i
= 0; i
< arrsz
; i
++) {
692 struct ir3_instruction
*elem
= arr
[i
];
694 /* Since arrays are pre-colored in RA, we can't assume that
695 * things will end up in the right place. (Ie. if a collect
696 * joins elements from two different arrays.) So insert an
699 * We could possibly skip this if all the collected elements
700 * are contiguous elements in a single array.. not sure how
701 * likely that is to happen.
703 * Fixes a problem with glamor shaders, that in effect do
710 * color = texture2D(tex, texcoord);
712 * In this case, texcoord will end up as nir registers (which
713 * translate to ir3 array's of length 1. And we can't assume
714 * the two (or more) arrays will get allocated in consecutive
718 if (elem
->regs
[0]->flags
& IR3_REG_ARRAY
) {
719 type_t type
= (flags
& IR3_REG_HALF
) ? TYPE_U16
: TYPE_U32
;
720 elem
= ir3_MOV(block
, elem
, type
);
723 compile_assert(ctx
, (elem
->regs
[0]->flags
& IR3_REG_HALF
) == flags
);
724 ir3_reg_create(collect
, 0, IR3_REG_SSA
| flags
)->instr
= elem
;
730 static struct ir3_instruction
*
731 create_indirect_load(struct ir3_context
*ctx
, unsigned arrsz
, int n
,
732 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
734 struct ir3_block
*block
= ctx
->block
;
735 struct ir3_instruction
*mov
;
736 struct ir3_register
*src
;
738 mov
= ir3_instr_create(block
, OPC_MOV
);
739 mov
->cat1
.src_type
= TYPE_U32
;
740 mov
->cat1
.dst_type
= TYPE_U32
;
741 ir3_reg_create(mov
, 0, 0);
742 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
743 src
->instr
= collect
;
745 src
->array
.offset
= n
;
747 ir3_instr_set_address(mov
, address
);
752 static struct ir3_instruction
*
753 create_input_compmask(struct ir3_context
*ctx
, unsigned n
, unsigned compmask
)
755 struct ir3_instruction
*in
;
757 in
= ir3_instr_create(ctx
->in_block
, OPC_META_INPUT
);
758 in
->inout
.block
= ctx
->in_block
;
759 ir3_reg_create(in
, n
, 0);
761 in
->regs
[0]->wrmask
= compmask
;
766 static struct ir3_instruction
*
767 create_input(struct ir3_context
*ctx
, unsigned n
)
769 return create_input_compmask(ctx
, n
, 0x1);
772 static struct ir3_instruction
*
773 create_frag_input(struct ir3_context
*ctx
, bool use_ldlv
)
775 struct ir3_block
*block
= ctx
->block
;
776 struct ir3_instruction
*instr
;
777 /* actual inloc is assigned and fixed up later: */
778 struct ir3_instruction
*inloc
= create_immed(block
, 0);
781 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
782 instr
->cat6
.type
= TYPE_U32
;
783 instr
->cat6
.iim_val
= 1;
785 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_vcoord
, 0);
786 instr
->regs
[2]->wrmask
= 0x3;
792 static struct ir3_instruction
*
793 create_driver_param(struct ir3_context
*ctx
, enum ir3_driver_param dp
)
795 /* first four vec4 sysval's reserved for UBOs: */
796 /* NOTE: dp is in scalar, but there can be >4 dp components: */
797 unsigned n
= ctx
->so
->constbase
.driver_param
;
798 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
799 return create_uniform(ctx
, r
);
802 /* helper for instructions that produce multiple consecutive scalar
803 * outputs which need to have a split/fanout meta instruction inserted
806 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
807 struct ir3_instruction
*src
, unsigned base
, unsigned n
)
809 struct ir3_instruction
*prev
= NULL
;
811 if ((n
== 1) && (src
->regs
[0]->wrmask
== 0x1)) {
816 for (int i
= 0, j
= 0; i
< n
; i
++) {
817 struct ir3_instruction
*split
= ir3_instr_create(block
, OPC_META_FO
);
818 ir3_reg_create(split
, 0, IR3_REG_SSA
);
819 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
820 split
->fo
.off
= i
+ base
;
823 split
->cp
.left
= prev
;
824 split
->cp
.left_cnt
++;
825 prev
->cp
.right
= split
;
826 prev
->cp
.right_cnt
++;
830 if (src
->regs
[0]->wrmask
& (1 << (i
+ base
)))
836 * Adreno uses uint rather than having dedicated bool type,
837 * which (potentially) requires some conversion, in particular
838 * when using output of an bool instr to int input, or visa
842 * -------+---------+-------+-
846 * To convert from an adreno bool (uint) to nir, use:
848 * absneg.s dst, (neg)src
850 * To convert back in the other direction:
852 * absneg.s dst, (abs)arc
854 * The CP step can clean up the absneg.s that cancel each other
855 * out, and with a slight bit of extra cleverness (to recognize
856 * the instructions which produce either a 0 or 1) can eliminate
857 * the absneg.s's completely when an instruction that wants
858 * 0/1 consumes the result. For example, when a nir 'bcsel'
859 * consumes the result of 'feq'. So we should be able to get by
860 * without a boolean resolve step, and without incuring any
861 * extra penalty in instruction count.
864 /* NIR bool -> native (adreno): */
865 static struct ir3_instruction
*
866 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
868 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
871 /* native (adreno) -> NIR bool: */
872 static struct ir3_instruction
*
873 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
875 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
879 * alu/sfu instructions:
882 static struct ir3_instruction
*
883 create_cov(struct ir3_context
*ctx
, struct ir3_instruction
*src
,
884 unsigned src_bitsize
, nir_op op
)
886 type_t src_type
, dst_type
;
890 case nir_op_f2f16_rtne
:
891 case nir_op_f2f16_rtz
:
899 switch (src_bitsize
) {
907 compile_error(ctx
, "invalid src bit size: %u", src_bitsize
);
916 switch (src_bitsize
) {
927 compile_error(ctx
, "invalid src bit size: %u", src_bitsize
);
936 switch (src_bitsize
) {
947 compile_error(ctx
, "invalid src bit size: %u", src_bitsize
);
952 compile_error(ctx
, "invalid conversion op: %u", op
);
962 case nir_op_f2f16_rtne
:
963 case nir_op_f2f16_rtz
:
965 /* TODO how to handle rounding mode? */
1002 compile_error(ctx
, "invalid conversion op: %u", op
);
1005 return ir3_COV(ctx
->block
, src
, src_type
, dst_type
);
1009 emit_alu(struct ir3_context
*ctx
, nir_alu_instr
*alu
)
1011 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
1012 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
1013 unsigned bs
[info
->num_inputs
]; /* bit size */
1014 struct ir3_block
*b
= ctx
->block
;
1015 unsigned dst_sz
, wrmask
;
1017 if (alu
->dest
.dest
.is_ssa
) {
1018 dst_sz
= alu
->dest
.dest
.ssa
.num_components
;
1019 wrmask
= (1 << dst_sz
) - 1;
1021 dst_sz
= alu
->dest
.dest
.reg
.reg
->num_components
;
1022 wrmask
= alu
->dest
.write_mask
;
1025 dst
= get_dst(ctx
, &alu
->dest
.dest
, dst_sz
);
1027 /* Vectors are special in that they have non-scalarized writemasks,
1028 * and just take the first swizzle channel for each argument in
1029 * order into each writemask channel.
1031 if ((alu
->op
== nir_op_vec2
) ||
1032 (alu
->op
== nir_op_vec3
) ||
1033 (alu
->op
== nir_op_vec4
)) {
1035 for (int i
= 0; i
< info
->num_inputs
; i
++) {
1036 nir_alu_src
*asrc
= &alu
->src
[i
];
1038 compile_assert(ctx
, !asrc
->abs
);
1039 compile_assert(ctx
, !asrc
->negate
);
1041 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
1043 src
[i
] = create_immed(ctx
->block
, 0);
1044 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
1047 put_dst(ctx
, &alu
->dest
.dest
);
1051 /* We also get mov's with more than one component for mov's so
1052 * handle those specially:
1054 if ((alu
->op
== nir_op_imov
) || (alu
->op
== nir_op_fmov
)) {
1055 type_t type
= (alu
->op
== nir_op_imov
) ? TYPE_U32
: TYPE_F32
;
1056 nir_alu_src
*asrc
= &alu
->src
[0];
1057 struct ir3_instruction
*const *src0
= get_src(ctx
, &asrc
->src
);
1059 for (unsigned i
= 0; i
< dst_sz
; i
++) {
1060 if (wrmask
& (1 << i
)) {
1061 dst
[i
] = ir3_MOV(b
, src0
[asrc
->swizzle
[i
]], type
);
1067 put_dst(ctx
, &alu
->dest
.dest
);
1071 /* General case: We can just grab the one used channel per src. */
1072 for (int i
= 0; i
< info
->num_inputs
; i
++) {
1073 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
1074 nir_alu_src
*asrc
= &alu
->src
[i
];
1076 compile_assert(ctx
, !asrc
->abs
);
1077 compile_assert(ctx
, !asrc
->negate
);
1079 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
1080 bs
[i
] = nir_src_bit_size(asrc
->src
);
1082 compile_assert(ctx
, src
[i
]);
1087 case nir_op_f2f16_rtne
:
1088 case nir_op_f2f16_rtz
:
1106 dst
[0] = create_cov(ctx
, src
[0], bs
[0], alu
->op
);
1109 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
1110 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1111 dst
[0] = ir3_n2b(b
, dst
[0]);
1114 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
1117 dst
[0] = ir3_b2n(b
, src
[0]);
1120 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1121 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1122 dst
[0] = ir3_n2b(b
, dst
[0]);
1126 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
1129 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
1132 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
1135 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
1138 /* if there is just a single use of the src, and it supports
1139 * (sat) bit, we can just fold the (sat) flag back to the
1140 * src instruction and create a mov. This is easier for cp
1143 * TODO probably opc_cat==4 is ok too
1145 if (alu
->src
[0].src
.is_ssa
&&
1146 (list_length(&alu
->src
[0].src
.ssa
->uses
) == 1) &&
1147 ((opc_cat(src
[0]->opc
) == 2) || (opc_cat(src
[0]->opc
) == 3))) {
1148 src
[0]->flags
|= IR3_INSTR_SAT
;
1149 dst
[0] = ir3_MOV(b
, src
[0], TYPE_U32
);
1151 /* otherwise generate a max.f that saturates.. blob does
1152 * similar (generating a cat2 mov using max.f)
1154 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[0], 0);
1155 dst
[0]->flags
|= IR3_INSTR_SAT
;
1159 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
1162 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
1165 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
1168 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
1171 dst
[0] = ir3_DSX(b
, src
[0], 0);
1172 dst
[0]->cat5
.type
= TYPE_F32
;
1175 dst
[0] = ir3_DSY(b
, src
[0], 0);
1176 dst
[0]->cat5
.type
= TYPE_F32
;
1180 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1181 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1182 dst
[0] = ir3_n2b(b
, dst
[0]);
1185 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1186 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1187 dst
[0] = ir3_n2b(b
, dst
[0]);
1190 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1191 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1192 dst
[0] = ir3_n2b(b
, dst
[0]);
1195 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1196 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1197 dst
[0] = ir3_n2b(b
, dst
[0]);
1200 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
1203 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
1206 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
1208 case nir_op_fround_even
:
1209 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
1212 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
1216 dst
[0] = ir3_SIN(b
, src
[0], 0);
1219 dst
[0] = ir3_COS(b
, src
[0], 0);
1222 dst
[0] = ir3_RSQ(b
, src
[0], 0);
1225 dst
[0] = ir3_RCP(b
, src
[0], 0);
1228 dst
[0] = ir3_LOG2(b
, src
[0], 0);
1231 dst
[0] = ir3_EXP2(b
, src
[0], 0);
1234 dst
[0] = ir3_SQRT(b
, src
[0], 0);
1238 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
1241 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
1244 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
1247 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
1250 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
1253 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
1256 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
1260 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
1261 * mull.u tmp0, a, b ; mul low, i.e. al * bl
1262 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
1263 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
1265 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
1266 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
1267 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
1270 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
1273 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
1276 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
1279 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
1282 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
1284 case nir_op_isign
: {
1285 /* maybe this would be sane to lower in nir.. */
1286 struct ir3_instruction
*neg
, *pos
;
1288 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1289 neg
->cat2
.condition
= IR3_COND_LT
;
1291 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1292 pos
->cat2
.condition
= IR3_COND_GT
;
1294 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
1299 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
1302 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
1305 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
1308 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1309 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1310 dst
[0] = ir3_n2b(b
, dst
[0]);
1313 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1314 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1315 dst
[0] = ir3_n2b(b
, dst
[0]);
1318 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1319 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1320 dst
[0] = ir3_n2b(b
, dst
[0]);
1323 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1324 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1325 dst
[0] = ir3_n2b(b
, dst
[0]);
1328 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1329 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1330 dst
[0] = ir3_n2b(b
, dst
[0]);
1333 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1334 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1335 dst
[0] = ir3_n2b(b
, dst
[0]);
1338 case nir_op_bcsel
: {
1339 struct ir3_instruction
*cond
= ir3_b2n(b
, src
[0]);
1340 compile_assert(ctx
, bs
[1] == bs
[2]);
1341 /* the boolean condition is 32b even if src[1] and src[2] are
1342 * half-precision, but sel.b16 wants all three src's to be the
1346 cond
= ir3_COV(b
, cond
, TYPE_U32
, TYPE_U16
);
1347 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, cond
, 0, src
[2], 0);
1350 case nir_op_bit_count
:
1351 dst
[0] = ir3_CBITS_B(b
, src
[0], 0);
1353 case nir_op_ifind_msb
: {
1354 struct ir3_instruction
*cmp
;
1355 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
1356 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
1357 cmp
->cat2
.condition
= IR3_COND_GE
;
1358 dst
[0] = ir3_SEL_B32(b
,
1359 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1363 case nir_op_ufind_msb
:
1364 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
1365 dst
[0] = ir3_SEL_B32(b
,
1366 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1367 src
[0], 0, dst
[0], 0);
1369 case nir_op_find_lsb
:
1370 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1371 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
1373 case nir_op_bitfield_reverse
:
1374 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1378 compile_error(ctx
, "Unhandled ALU op: %s\n",
1379 nir_op_infos
[alu
->op
].name
);
1383 put_dst(ctx
, &alu
->dest
.dest
);
1386 /* handles direct/indirect UBO reads: */
1388 emit_intrinsic_load_ubo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1389 struct ir3_instruction
**dst
)
1391 struct ir3_block
*b
= ctx
->block
;
1392 struct ir3_instruction
*base_lo
, *base_hi
, *addr
, *src0
, *src1
;
1393 nir_const_value
*const_offset
;
1394 /* UBO addresses are the first driver params: */
1395 unsigned ubo
= regid(ctx
->so
->constbase
.ubo
, 0);
1396 const unsigned ptrsz
= pointer_size(ctx
);
1400 /* First src is ubo index, which could either be an immed or not: */
1401 src0
= get_src(ctx
, &intr
->src
[0])[0];
1402 if (is_same_type_mov(src0
) &&
1403 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1404 base_lo
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
));
1405 base_hi
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
) + 1);
1407 base_lo
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
, 4));
1408 base_hi
= create_uniform_indirect(ctx
, ubo
+ 1, get_addr(ctx
, src0
, 4));
1411 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
1414 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1416 off
+= const_offset
->u32
[0];
1418 /* For load_ubo_indirect, second src is indirect offset: */
1419 src1
= get_src(ctx
, &intr
->src
[1])[0];
1421 /* and add offset to addr: */
1422 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1425 /* if offset is to large to encode in the ldg, split it out: */
1426 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1427 /* split out the minimal amount to improve the odds that
1428 * cp can fit the immediate in the add.s instruction:
1430 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1431 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1436 struct ir3_instruction
*carry
;
1438 /* handle 32b rollover, ie:
1439 * if (addr < base_lo)
1442 carry
= ir3_CMPS_U(b
, addr
, 0, base_lo
, 0);
1443 carry
->cat2
.condition
= IR3_COND_LT
;
1444 base_hi
= ir3_ADD_S(b
, base_hi
, 0, carry
, 0);
1446 addr
= create_collect(ctx
, (struct ir3_instruction
*[]){ addr
, base_hi
}, 2);
1449 for (int i
= 0; i
< intr
->num_components
; i
++) {
1450 struct ir3_instruction
*load
=
1451 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1452 load
->cat6
.type
= TYPE_U32
;
1453 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
1458 /* src[] = { buffer_index, offset }. No const_index */
1460 emit_intrinsic_load_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1461 struct ir3_instruction
**dst
)
1463 struct ir3_block
*b
= ctx
->block
;
1464 struct ir3_instruction
*ldgb
, *src0
, *src1
, *offset
;
1465 nir_const_value
*const_offset
;
1467 /* can this be non-const buffer_index? how do we handle that? */
1468 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1469 compile_assert(ctx
, const_offset
);
1471 offset
= get_src(ctx
, &intr
->src
[1])[0];
1473 /* src0 is uvec2(offset*4, 0), src1 is offset.. nir already *= 4: */
1474 src0
= create_collect(ctx
, (struct ir3_instruction
*[]){
1478 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1480 ldgb
= ir3_LDGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1482 ldgb
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1483 ldgb
->cat6
.iim_val
= intr
->num_components
;
1485 ldgb
->cat6
.type
= TYPE_U32
;
1486 ldgb
->barrier_class
= IR3_BARRIER_BUFFER_R
;
1487 ldgb
->barrier_conflict
= IR3_BARRIER_BUFFER_W
;
1489 split_dest(b
, dst
, ldgb
, 0, intr
->num_components
);
1492 /* src[] = { value, block_index, offset }. const_index[] = { write_mask } */
1494 emit_intrinsic_store_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1496 struct ir3_block
*b
= ctx
->block
;
1497 struct ir3_instruction
*stgb
, *src0
, *src1
, *src2
, *offset
;
1498 nir_const_value
*const_offset
;
1499 /* TODO handle wrmask properly, see _store_shared().. but I think
1500 * it is more a PITA than that, since blob ends up loading the
1501 * masked components and writing them back out.
1503 unsigned wrmask
= intr
->const_index
[0];
1504 unsigned ncomp
= ffs(~wrmask
) - 1;
1506 /* can this be non-const buffer_index? how do we handle that? */
1507 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1508 compile_assert(ctx
, const_offset
);
1510 offset
= get_src(ctx
, &intr
->src
[2])[0];
1512 /* src0 is value, src1 is offset, src2 is uvec2(offset*4, 0)..
1515 src0
= create_collect(ctx
, get_src(ctx
, &intr
->src
[0]), ncomp
);
1516 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1517 src2
= create_collect(ctx
, (struct ir3_instruction
*[]){
1522 stgb
= ir3_STGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1523 src0
, 0, src1
, 0, src2
, 0);
1524 stgb
->cat6
.iim_val
= ncomp
;
1526 stgb
->cat6
.type
= TYPE_U32
;
1527 stgb
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1528 stgb
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1530 array_insert(b
, b
->keeps
, stgb
);
1533 /* src[] = { block_index } */
1535 emit_intrinsic_ssbo_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1536 struct ir3_instruction
**dst
)
1538 /* SSBO size stored as a const starting at ssbo_sizes: */
1539 unsigned blk_idx
= nir_src_as_const_value(intr
->src
[0])->u32
[0];
1540 unsigned idx
= regid(ctx
->so
->constbase
.ssbo_sizes
, 0) +
1541 ctx
->so
->const_layout
.ssbo_size
.off
[blk_idx
];
1543 debug_assert(ctx
->so
->const_layout
.ssbo_size
.mask
& (1 << blk_idx
));
1545 dst
[0] = create_uniform(ctx
, idx
);
1549 * SSBO atomic intrinsics
1551 * All of the SSBO atomic memory operations read a value from memory,
1552 * compute a new value using one of the operations below, write the new
1553 * value to memory, and return the original value read.
1555 * All operations take 3 sources except CompSwap that takes 4. These
1556 * sources represent:
1558 * 0: The SSBO buffer index.
1559 * 1: The offset into the SSBO buffer of the variable that the atomic
1560 * operation will operate on.
1561 * 2: The data parameter to the atomic function (i.e. the value to add
1562 * in ssbo_atomic_add, etc).
1563 * 3: For CompSwap only: the second data parameter.
1565 static struct ir3_instruction
*
1566 emit_intrinsic_atomic_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1568 struct ir3_block
*b
= ctx
->block
;
1569 struct ir3_instruction
*atomic
, *ssbo
, *src0
, *src1
, *src2
, *offset
;
1570 nir_const_value
*const_offset
;
1571 type_t type
= TYPE_U32
;
1573 /* can this be non-const buffer_index? how do we handle that? */
1574 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1575 compile_assert(ctx
, const_offset
);
1576 ssbo
= create_immed(b
, const_offset
->u32
[0]);
1578 offset
= get_src(ctx
, &intr
->src
[1])[0];
1580 /* src0 is data (or uvec2(data, compare))
1582 * src2 is uvec2(offset*4, 0) (appears to be 64b byte offset)
1584 * Note that nir already multiplies the offset by four
1586 src0
= get_src(ctx
, &intr
->src
[2])[0];
1587 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1588 src2
= create_collect(ctx
, (struct ir3_instruction
*[]){
1593 switch (intr
->intrinsic
) {
1594 case nir_intrinsic_ssbo_atomic_add
:
1595 atomic
= ir3_ATOMIC_ADD_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1597 case nir_intrinsic_ssbo_atomic_imin
:
1598 atomic
= ir3_ATOMIC_MIN_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1601 case nir_intrinsic_ssbo_atomic_umin
:
1602 atomic
= ir3_ATOMIC_MIN_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1604 case nir_intrinsic_ssbo_atomic_imax
:
1605 atomic
= ir3_ATOMIC_MAX_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1608 case nir_intrinsic_ssbo_atomic_umax
:
1609 atomic
= ir3_ATOMIC_MAX_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1611 case nir_intrinsic_ssbo_atomic_and
:
1612 atomic
= ir3_ATOMIC_AND_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1614 case nir_intrinsic_ssbo_atomic_or
:
1615 atomic
= ir3_ATOMIC_OR_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1617 case nir_intrinsic_ssbo_atomic_xor
:
1618 atomic
= ir3_ATOMIC_XOR_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1620 case nir_intrinsic_ssbo_atomic_exchange
:
1621 atomic
= ir3_ATOMIC_XCHG_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1623 case nir_intrinsic_ssbo_atomic_comp_swap
:
1624 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
1625 src0
= create_collect(ctx
, (struct ir3_instruction
*[]){
1626 get_src(ctx
, &intr
->src
[3])[0],
1629 atomic
= ir3_ATOMIC_CMPXCHG_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1635 atomic
->cat6
.iim_val
= 1;
1637 atomic
->cat6
.type
= type
;
1638 atomic
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1639 atomic
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1641 /* even if nothing consume the result, we can't DCE the instruction: */
1642 array_insert(b
, b
->keeps
, atomic
);
1647 /* src[] = { offset }. const_index[] = { base } */
1649 emit_intrinsic_load_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1650 struct ir3_instruction
**dst
)
1652 struct ir3_block
*b
= ctx
->block
;
1653 struct ir3_instruction
*ldl
, *offset
;
1656 offset
= get_src(ctx
, &intr
->src
[0])[0];
1657 base
= nir_intrinsic_base(intr
);
1659 ldl
= ir3_LDL(b
, offset
, 0, create_immed(b
, intr
->num_components
), 0);
1660 ldl
->cat6
.src_offset
= base
;
1661 ldl
->cat6
.type
= utype_dst(intr
->dest
);
1662 ldl
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1664 ldl
->barrier_class
= IR3_BARRIER_SHARED_R
;
1665 ldl
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
1667 split_dest(b
, dst
, ldl
, 0, intr
->num_components
);
1670 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
1672 emit_intrinsic_store_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1674 struct ir3_block
*b
= ctx
->block
;
1675 struct ir3_instruction
*stl
, *offset
;
1676 struct ir3_instruction
* const *value
;
1677 unsigned base
, wrmask
;
1679 value
= get_src(ctx
, &intr
->src
[0]);
1680 offset
= get_src(ctx
, &intr
->src
[1])[0];
1682 base
= nir_intrinsic_base(intr
);
1683 wrmask
= nir_intrinsic_write_mask(intr
);
1685 /* Combine groups of consecutive enabled channels in one write
1686 * message. We use ffs to find the first enabled channel and then ffs on
1687 * the bit-inverse, down-shifted writemask to determine the length of
1688 * the block of enabled bits.
1690 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
1693 unsigned first_component
= ffs(wrmask
) - 1;
1694 unsigned length
= ffs(~(wrmask
>> first_component
)) - 1;
1696 stl
= ir3_STL(b
, offset
, 0,
1697 create_collect(ctx
, &value
[first_component
], length
), 0,
1698 create_immed(b
, length
), 0);
1699 stl
->cat6
.dst_offset
= first_component
+ base
;
1700 stl
->cat6
.type
= utype_src(intr
->src
[0]);
1701 stl
->barrier_class
= IR3_BARRIER_SHARED_W
;
1702 stl
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1704 array_insert(b
, b
->keeps
, stl
);
1706 /* Clear the bits in the writemask that we just wrote, then try
1707 * again to see if more channels are left.
1709 wrmask
&= (15 << (first_component
+ length
));
1714 * CS shared variable atomic intrinsics
1716 * All of the shared variable atomic memory operations read a value from
1717 * memory, compute a new value using one of the operations below, write the
1718 * new value to memory, and return the original value read.
1720 * All operations take 2 sources except CompSwap that takes 3. These
1721 * sources represent:
1723 * 0: The offset into the shared variable storage region that the atomic
1724 * operation will operate on.
1725 * 1: The data parameter to the atomic function (i.e. the value to add
1726 * in shared_atomic_add, etc).
1727 * 2: For CompSwap only: the second data parameter.
1729 static struct ir3_instruction
*
1730 emit_intrinsic_atomic_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1732 struct ir3_block
*b
= ctx
->block
;
1733 struct ir3_instruction
*atomic
, *src0
, *src1
;
1734 type_t type
= TYPE_U32
;
1736 src0
= get_src(ctx
, &intr
->src
[0])[0]; /* offset */
1737 src1
= get_src(ctx
, &intr
->src
[1])[0]; /* value */
1739 switch (intr
->intrinsic
) {
1740 case nir_intrinsic_shared_atomic_add
:
1741 atomic
= ir3_ATOMIC_ADD(b
, src0
, 0, src1
, 0);
1743 case nir_intrinsic_shared_atomic_imin
:
1744 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1747 case nir_intrinsic_shared_atomic_umin
:
1748 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1750 case nir_intrinsic_shared_atomic_imax
:
1751 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1754 case nir_intrinsic_shared_atomic_umax
:
1755 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1757 case nir_intrinsic_shared_atomic_and
:
1758 atomic
= ir3_ATOMIC_AND(b
, src0
, 0, src1
, 0);
1760 case nir_intrinsic_shared_atomic_or
:
1761 atomic
= ir3_ATOMIC_OR(b
, src0
, 0, src1
, 0);
1763 case nir_intrinsic_shared_atomic_xor
:
1764 atomic
= ir3_ATOMIC_XOR(b
, src0
, 0, src1
, 0);
1766 case nir_intrinsic_shared_atomic_exchange
:
1767 atomic
= ir3_ATOMIC_XCHG(b
, src0
, 0, src1
, 0);
1769 case nir_intrinsic_shared_atomic_comp_swap
:
1770 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1771 src1
= create_collect(ctx
, (struct ir3_instruction
*[]){
1772 get_src(ctx
, &intr
->src
[2])[0],
1775 atomic
= ir3_ATOMIC_CMPXCHG(b
, src0
, 0, src1
, 0);
1781 atomic
->cat6
.iim_val
= 1;
1783 atomic
->cat6
.type
= type
;
1784 atomic
->barrier_class
= IR3_BARRIER_SHARED_W
;
1785 atomic
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1787 /* even if nothing consume the result, we can't DCE the instruction: */
1788 array_insert(b
, b
->keeps
, atomic
);
1793 /* Images get mapped into SSBO/image state (for store/atomic) and texture
1794 * state block (for load). To simplify things, invert the image id and
1795 * map it from end of state block, ie. image 0 becomes num-1, image 1
1796 * becomes num-2, etc. This potentially avoids needing to re-emit texture
1797 * state when switching shaders.
1799 * TODO is max # of samplers and SSBOs the same. This shouldn't be hard-
1800 * coded. Also, since all the gl shader stages (ie. everything but CS)
1801 * share the same SSBO/image state block, this might require some more
1802 * logic if we supported images in anything other than FS..
1805 get_image_slot(struct ir3_context
*ctx
, nir_deref_instr
*deref
)
1807 unsigned int loc
= 0;
1808 unsigned inner_size
= 1;
1810 while (deref
->deref_type
!= nir_deref_type_var
) {
1811 assert(deref
->deref_type
== nir_deref_type_array
);
1812 nir_const_value
*const_index
= nir_src_as_const_value(deref
->arr
.index
);
1813 assert(const_index
);
1815 /* Go to the next instruction */
1816 deref
= nir_deref_instr_parent(deref
);
1818 assert(glsl_type_is_array(deref
->type
));
1819 const unsigned array_len
= glsl_get_length(deref
->type
);
1820 loc
+= MIN2(const_index
->u32
[0], array_len
- 1) * inner_size
;
1822 /* Update the inner size */
1823 inner_size
*= array_len
;
1826 loc
+= deref
->var
->data
.driver_location
;
1828 /* TODO figure out real limit per generation, and don't hardcode: */
1829 const unsigned max_samplers
= 16;
1830 return max_samplers
- loc
- 1;
1833 /* see tex_info() for equiv logic for texture instructions.. it would be
1834 * nice if this could be better unified..
1837 get_image_coords(const nir_variable
*var
, unsigned *flagsp
)
1839 const struct glsl_type
*type
= glsl_without_array(var
->type
);
1840 unsigned coords
, flags
= 0;
1842 switch (glsl_get_sampler_dim(type
)) {
1843 case GLSL_SAMPLER_DIM_1D
:
1844 case GLSL_SAMPLER_DIM_BUF
:
1847 case GLSL_SAMPLER_DIM_2D
:
1848 case GLSL_SAMPLER_DIM_RECT
:
1849 case GLSL_SAMPLER_DIM_EXTERNAL
:
1850 case GLSL_SAMPLER_DIM_MS
:
1853 case GLSL_SAMPLER_DIM_3D
:
1854 case GLSL_SAMPLER_DIM_CUBE
:
1855 flags
|= IR3_INSTR_3D
;
1859 unreachable("bad sampler dim");
1863 if (glsl_sampler_type_is_array(type
)) {
1864 /* note: unlike tex_info(), adjust # of coords to include array idx: */
1866 flags
|= IR3_INSTR_A
;
1876 get_image_type(const nir_variable
*var
)
1878 switch (glsl_get_sampler_result_type(glsl_without_array(var
->type
))) {
1879 case GLSL_TYPE_UINT
:
1883 case GLSL_TYPE_FLOAT
:
1886 unreachable("bad sampler type.");
1891 static struct ir3_instruction
*
1892 get_image_offset(struct ir3_context
*ctx
, const nir_variable
*var
,
1893 struct ir3_instruction
* const *coords
, bool byteoff
)
1895 struct ir3_block
*b
= ctx
->block
;
1896 struct ir3_instruction
*offset
;
1897 unsigned ncoords
= get_image_coords(var
, NULL
);
1899 /* to calculate the byte offset (yes, uggg) we need (up to) three
1900 * const values to know the bytes per pixel, and y and z stride:
1902 unsigned cb
= regid(ctx
->so
->constbase
.image_dims
, 0) +
1903 ctx
->so
->const_layout
.image_dims
.off
[var
->data
.driver_location
];
1905 debug_assert(ctx
->so
->const_layout
.image_dims
.mask
&
1906 (1 << var
->data
.driver_location
));
1908 /* offset = coords.x * bytes_per_pixel: */
1909 offset
= ir3_MUL_S(b
, coords
[0], 0, create_uniform(ctx
, cb
+ 0), 0);
1911 /* offset += coords.y * y_pitch: */
1912 offset
= ir3_MAD_S24(b
, create_uniform(ctx
, cb
+ 1), 0,
1913 coords
[1], 0, offset
, 0);
1916 /* offset += coords.z * z_pitch: */
1917 offset
= ir3_MAD_S24(b
, create_uniform(ctx
, cb
+ 2), 0,
1918 coords
[2], 0, offset
, 0);
1922 /* Some cases, like atomics, seem to use dword offset instead
1923 * of byte offsets.. blob just puts an extra shr.b in there
1926 offset
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1929 return create_collect(ctx
, (struct ir3_instruction
*[]){
1935 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1937 emit_intrinsic_load_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1938 struct ir3_instruction
**dst
)
1940 struct ir3_block
*b
= ctx
->block
;
1941 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
1942 struct ir3_instruction
*sam
;
1943 struct ir3_instruction
* const *src0
= get_src(ctx
, &intr
->src
[1]);
1944 struct ir3_instruction
*coords
[4];
1945 unsigned flags
, ncoords
= get_image_coords(var
, &flags
);
1946 unsigned tex_idx
= get_image_slot(ctx
, nir_src_as_deref(intr
->src
[0]));
1947 type_t type
= get_image_type(var
);
1949 /* hmm, this seems a bit odd, but it is what blob does and (at least
1950 * a5xx) just faults on bogus addresses otherwise:
1952 if (flags
& IR3_INSTR_3D
) {
1953 flags
&= ~IR3_INSTR_3D
;
1954 flags
|= IR3_INSTR_A
;
1957 for (unsigned i
= 0; i
< ncoords
; i
++)
1958 coords
[i
] = src0
[i
];
1961 coords
[ncoords
++] = create_immed(b
, 0);
1963 sam
= ir3_SAM(b
, OPC_ISAM
, type
, TGSI_WRITEMASK_XYZW
, flags
,
1964 tex_idx
, tex_idx
, create_collect(ctx
, coords
, ncoords
), NULL
);
1966 sam
->barrier_class
= IR3_BARRIER_IMAGE_R
;
1967 sam
->barrier_conflict
= IR3_BARRIER_IMAGE_W
;
1969 split_dest(b
, dst
, sam
, 0, 4);
1972 /* src[] = { deref, coord, sample_index, value }. const_index[] = {} */
1974 emit_intrinsic_store_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1976 struct ir3_block
*b
= ctx
->block
;
1977 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
1978 struct ir3_instruction
*stib
, *offset
;
1979 struct ir3_instruction
* const *value
= get_src(ctx
, &intr
->src
[3]);
1980 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[1]);
1981 unsigned ncoords
= get_image_coords(var
, NULL
);
1982 unsigned tex_idx
= get_image_slot(ctx
, nir_src_as_deref(intr
->src
[0]));
1986 * src2 is 64b byte offset
1989 offset
= get_image_offset(ctx
, var
, coords
, true);
1991 /* NOTE: stib seems to take byte offset, but stgb.typed can be used
1992 * too and takes a dword offset.. not quite sure yet why blob uses
1993 * one over the other in various cases.
1996 stib
= ir3_STIB(b
, create_immed(b
, tex_idx
), 0,
1997 create_collect(ctx
, value
, 4), 0,
1998 create_collect(ctx
, coords
, ncoords
), 0,
2000 stib
->cat6
.iim_val
= 4;
2001 stib
->cat6
.d
= ncoords
;
2002 stib
->cat6
.type
= get_image_type(var
);
2003 stib
->cat6
.typed
= true;
2004 stib
->barrier_class
= IR3_BARRIER_IMAGE_W
;
2005 stib
->barrier_conflict
= IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
;
2007 array_insert(b
, b
->keeps
, stib
);
2011 emit_intrinsic_image_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
2012 struct ir3_instruction
**dst
)
2014 struct ir3_block
*b
= ctx
->block
;
2015 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
2016 unsigned tex_idx
= get_image_slot(ctx
, nir_src_as_deref(intr
->src
[0]));
2017 struct ir3_instruction
*sam
, *lod
;
2018 unsigned flags
, ncoords
= get_image_coords(var
, &flags
);
2020 lod
= create_immed(b
, 0);
2021 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
2022 tex_idx
, tex_idx
, lod
, NULL
);
2024 /* Array size actually ends up in .w rather than .z. This doesn't
2025 * matter for miplevel 0, but for higher mips the value in z is
2026 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2027 * returned, which means that we have to add 1 to it for arrays for
2030 * Note use a temporary dst and then copy, since the size of the dst
2031 * array that is passed in is based on nir's understanding of the
2032 * result size, not the hardware's
2034 struct ir3_instruction
*tmp
[4];
2036 split_dest(b
, tmp
, sam
, 0, 4);
2038 /* get_size instruction returns size in bytes instead of texels
2039 * for imageBuffer, so we need to divide it by the pixel size
2040 * of the image format.
2042 * TODO: This is at least true on a5xx. Check other gens.
2044 enum glsl_sampler_dim dim
=
2045 glsl_get_sampler_dim(glsl_without_array(var
->type
));
2046 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
2047 /* Since all the possible values the divisor can take are
2048 * power-of-two (4, 8, or 16), the division is implemented
2050 * During shader setup, the log2 of the image format's
2051 * bytes-per-pixel should have been emitted in 2nd slot of
2052 * image_dims. See ir3_shader::emit_image_dims().
2054 unsigned cb
= regid(ctx
->so
->constbase
.image_dims
, 0) +
2055 ctx
->so
->const_layout
.image_dims
.off
[var
->data
.driver_location
];
2056 struct ir3_instruction
*aux
= create_uniform(ctx
, cb
+ 1);
2058 tmp
[0] = ir3_SHR_B(b
, tmp
[0], 0, aux
, 0);
2061 for (unsigned i
= 0; i
< ncoords
; i
++)
2064 if (flags
& IR3_INSTR_A
) {
2065 if (ctx
->compiler
->levels_add_one
) {
2066 dst
[ncoords
-1] = ir3_ADD_U(b
, tmp
[3], 0, create_immed(b
, 1), 0);
2068 dst
[ncoords
-1] = ir3_MOV(b
, tmp
[3], TYPE_U32
);
2073 /* src[] = { deref, coord, sample_index, value, compare }. const_index[] = {} */
2074 static struct ir3_instruction
*
2075 emit_intrinsic_atomic_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
2077 struct ir3_block
*b
= ctx
->block
;
2078 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
2079 struct ir3_instruction
*atomic
, *image
, *src0
, *src1
, *src2
;
2080 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[1]);
2081 unsigned ncoords
= get_image_coords(var
, NULL
);
2083 image
= create_immed(b
, get_image_slot(ctx
, nir_src_as_deref(intr
->src
[0])));
2085 /* src0 is value (or uvec2(value, compare))
2087 * src2 is 64b byte offset
2089 src0
= get_src(ctx
, &intr
->src
[3])[0];
2090 src1
= create_collect(ctx
, coords
, ncoords
);
2091 src2
= get_image_offset(ctx
, var
, coords
, false);
2093 switch (intr
->intrinsic
) {
2094 case nir_intrinsic_image_deref_atomic_add
:
2095 atomic
= ir3_ATOMIC_ADD_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2097 case nir_intrinsic_image_deref_atomic_min
:
2098 atomic
= ir3_ATOMIC_MIN_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2100 case nir_intrinsic_image_deref_atomic_max
:
2101 atomic
= ir3_ATOMIC_MAX_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2103 case nir_intrinsic_image_deref_atomic_and
:
2104 atomic
= ir3_ATOMIC_AND_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2106 case nir_intrinsic_image_deref_atomic_or
:
2107 atomic
= ir3_ATOMIC_OR_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2109 case nir_intrinsic_image_deref_atomic_xor
:
2110 atomic
= ir3_ATOMIC_XOR_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2112 case nir_intrinsic_image_deref_atomic_exchange
:
2113 atomic
= ir3_ATOMIC_XCHG_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2115 case nir_intrinsic_image_deref_atomic_comp_swap
:
2116 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
2117 src0
= create_collect(ctx
, (struct ir3_instruction
*[]){
2118 get_src(ctx
, &intr
->src
[4])[0],
2121 atomic
= ir3_ATOMIC_CMPXCHG_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2127 atomic
->cat6
.iim_val
= 1;
2128 atomic
->cat6
.d
= ncoords
;
2129 atomic
->cat6
.type
= get_image_type(var
);
2130 atomic
->cat6
.typed
= true;
2131 atomic
->barrier_class
= IR3_BARRIER_IMAGE_W
;
2132 atomic
->barrier_conflict
= IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
;
2134 /* even if nothing consume the result, we can't DCE the instruction: */
2135 array_insert(b
, b
->keeps
, atomic
);
2141 emit_intrinsic_barrier(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
2143 struct ir3_block
*b
= ctx
->block
;
2144 struct ir3_instruction
*barrier
;
2146 switch (intr
->intrinsic
) {
2147 case nir_intrinsic_barrier
:
2148 barrier
= ir3_BAR(b
);
2149 barrier
->cat7
.g
= true;
2150 barrier
->cat7
.l
= true;
2151 barrier
->flags
= IR3_INSTR_SS
| IR3_INSTR_SY
;
2152 barrier
->barrier_class
= IR3_BARRIER_EVERYTHING
;
2154 case nir_intrinsic_memory_barrier
:
2155 barrier
= ir3_FENCE(b
);
2156 barrier
->cat7
.g
= true;
2157 barrier
->cat7
.r
= true;
2158 barrier
->cat7
.w
= true;
2159 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
|
2160 IR3_BARRIER_BUFFER_W
;
2161 barrier
->barrier_conflict
=
2162 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
2163 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
2165 case nir_intrinsic_memory_barrier_atomic_counter
:
2166 case nir_intrinsic_memory_barrier_buffer
:
2167 barrier
= ir3_FENCE(b
);
2168 barrier
->cat7
.g
= true;
2169 barrier
->cat7
.r
= true;
2170 barrier
->cat7
.w
= true;
2171 barrier
->barrier_class
= IR3_BARRIER_BUFFER_W
;
2172 barrier
->barrier_conflict
= IR3_BARRIER_BUFFER_R
|
2173 IR3_BARRIER_BUFFER_W
;
2175 case nir_intrinsic_memory_barrier_image
:
2176 // TODO double check if this should have .g set
2177 barrier
= ir3_FENCE(b
);
2178 barrier
->cat7
.g
= true;
2179 barrier
->cat7
.r
= true;
2180 barrier
->cat7
.w
= true;
2181 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
;
2182 barrier
->barrier_conflict
= IR3_BARRIER_IMAGE_R
|
2183 IR3_BARRIER_IMAGE_W
;
2185 case nir_intrinsic_memory_barrier_shared
:
2186 barrier
= ir3_FENCE(b
);
2187 barrier
->cat7
.g
= true;
2188 barrier
->cat7
.l
= true;
2189 barrier
->cat7
.r
= true;
2190 barrier
->cat7
.w
= true;
2191 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
;
2192 barrier
->barrier_conflict
= IR3_BARRIER_SHARED_R
|
2193 IR3_BARRIER_SHARED_W
;
2195 case nir_intrinsic_group_memory_barrier
:
2196 barrier
= ir3_FENCE(b
);
2197 barrier
->cat7
.g
= true;
2198 barrier
->cat7
.l
= true;
2199 barrier
->cat7
.r
= true;
2200 barrier
->cat7
.w
= true;
2201 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
|
2202 IR3_BARRIER_IMAGE_W
|
2203 IR3_BARRIER_BUFFER_W
;
2204 barrier
->barrier_conflict
=
2205 IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
|
2206 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
2207 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
2213 /* make sure barrier doesn't get DCE'd */
2214 array_insert(b
, b
->keeps
, barrier
);
2217 static void add_sysval_input_compmask(struct ir3_context
*ctx
,
2218 gl_system_value slot
, unsigned compmask
,
2219 struct ir3_instruction
*instr
)
2221 struct ir3_shader_variant
*so
= ctx
->so
;
2222 unsigned r
= regid(so
->inputs_count
, 0);
2223 unsigned n
= so
->inputs_count
++;
2225 so
->inputs
[n
].sysval
= true;
2226 so
->inputs
[n
].slot
= slot
;
2227 so
->inputs
[n
].compmask
= compmask
;
2228 so
->inputs
[n
].regid
= r
;
2229 so
->inputs
[n
].interpolate
= INTERP_MODE_FLAT
;
2232 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
2233 ctx
->ir
->inputs
[r
] = instr
;
2236 static void add_sysval_input(struct ir3_context
*ctx
, gl_system_value slot
,
2237 struct ir3_instruction
*instr
)
2239 add_sysval_input_compmask(ctx
, slot
, 0x1, instr
);
2243 emit_intrinsic(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
2245 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
2246 struct ir3_instruction
**dst
;
2247 struct ir3_instruction
* const *src
;
2248 struct ir3_block
*b
= ctx
->block
;
2249 nir_const_value
*const_offset
;
2252 if (info
->has_dest
) {
2253 unsigned n
= nir_intrinsic_dest_components(intr
);
2254 dst
= get_dst(ctx
, &intr
->dest
, n
);
2259 switch (intr
->intrinsic
) {
2260 case nir_intrinsic_load_uniform
:
2261 idx
= nir_intrinsic_base(intr
);
2262 const_offset
= nir_src_as_const_value(intr
->src
[0]);
2264 idx
+= const_offset
->u32
[0];
2265 for (int i
= 0; i
< intr
->num_components
; i
++) {
2266 unsigned n
= idx
* 4 + i
;
2267 dst
[i
] = create_uniform(ctx
, n
);
2270 src
= get_src(ctx
, &intr
->src
[0]);
2271 for (int i
= 0; i
< intr
->num_components
; i
++) {
2272 int n
= idx
* 4 + i
;
2273 dst
[i
] = create_uniform_indirect(ctx
, n
,
2274 get_addr(ctx
, src
[0], 4));
2276 /* NOTE: if relative addressing is used, we set
2277 * constlen in the compiler (to worst-case value)
2278 * since we don't know in the assembler what the max
2279 * addr reg value can be:
2281 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
2284 case nir_intrinsic_load_ubo
:
2285 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
2287 case nir_intrinsic_load_input
:
2288 idx
= nir_intrinsic_base(intr
);
2289 comp
= nir_intrinsic_component(intr
);
2290 const_offset
= nir_src_as_const_value(intr
->src
[0]);
2292 idx
+= const_offset
->u32
[0];
2293 for (int i
= 0; i
< intr
->num_components
; i
++) {
2294 unsigned n
= idx
* 4 + i
+ comp
;
2295 dst
[i
] = ctx
->ir
->inputs
[n
];
2298 src
= get_src(ctx
, &intr
->src
[0]);
2299 struct ir3_instruction
*collect
=
2300 create_collect(ctx
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
2301 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0], 4);
2302 for (int i
= 0; i
< intr
->num_components
; i
++) {
2303 unsigned n
= idx
* 4 + i
+ comp
;
2304 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
2309 case nir_intrinsic_load_ssbo
:
2310 emit_intrinsic_load_ssbo(ctx
, intr
, dst
);
2312 case nir_intrinsic_store_ssbo
:
2313 emit_intrinsic_store_ssbo(ctx
, intr
);
2315 case nir_intrinsic_get_buffer_size
:
2316 emit_intrinsic_ssbo_size(ctx
, intr
, dst
);
2318 case nir_intrinsic_ssbo_atomic_add
:
2319 case nir_intrinsic_ssbo_atomic_imin
:
2320 case nir_intrinsic_ssbo_atomic_umin
:
2321 case nir_intrinsic_ssbo_atomic_imax
:
2322 case nir_intrinsic_ssbo_atomic_umax
:
2323 case nir_intrinsic_ssbo_atomic_and
:
2324 case nir_intrinsic_ssbo_atomic_or
:
2325 case nir_intrinsic_ssbo_atomic_xor
:
2326 case nir_intrinsic_ssbo_atomic_exchange
:
2327 case nir_intrinsic_ssbo_atomic_comp_swap
:
2328 dst
[0] = emit_intrinsic_atomic_ssbo(ctx
, intr
);
2330 case nir_intrinsic_load_shared
:
2331 emit_intrinsic_load_shared(ctx
, intr
, dst
);
2333 case nir_intrinsic_store_shared
:
2334 emit_intrinsic_store_shared(ctx
, intr
);
2336 case nir_intrinsic_shared_atomic_add
:
2337 case nir_intrinsic_shared_atomic_imin
:
2338 case nir_intrinsic_shared_atomic_umin
:
2339 case nir_intrinsic_shared_atomic_imax
:
2340 case nir_intrinsic_shared_atomic_umax
:
2341 case nir_intrinsic_shared_atomic_and
:
2342 case nir_intrinsic_shared_atomic_or
:
2343 case nir_intrinsic_shared_atomic_xor
:
2344 case nir_intrinsic_shared_atomic_exchange
:
2345 case nir_intrinsic_shared_atomic_comp_swap
:
2346 dst
[0] = emit_intrinsic_atomic_shared(ctx
, intr
);
2348 case nir_intrinsic_image_deref_load
:
2349 emit_intrinsic_load_image(ctx
, intr
, dst
);
2351 case nir_intrinsic_image_deref_store
:
2352 emit_intrinsic_store_image(ctx
, intr
);
2354 case nir_intrinsic_image_deref_size
:
2355 emit_intrinsic_image_size(ctx
, intr
, dst
);
2357 case nir_intrinsic_image_deref_atomic_add
:
2358 case nir_intrinsic_image_deref_atomic_min
:
2359 case nir_intrinsic_image_deref_atomic_max
:
2360 case nir_intrinsic_image_deref_atomic_and
:
2361 case nir_intrinsic_image_deref_atomic_or
:
2362 case nir_intrinsic_image_deref_atomic_xor
:
2363 case nir_intrinsic_image_deref_atomic_exchange
:
2364 case nir_intrinsic_image_deref_atomic_comp_swap
:
2365 dst
[0] = emit_intrinsic_atomic_image(ctx
, intr
);
2367 case nir_intrinsic_barrier
:
2368 case nir_intrinsic_memory_barrier
:
2369 case nir_intrinsic_group_memory_barrier
:
2370 case nir_intrinsic_memory_barrier_atomic_counter
:
2371 case nir_intrinsic_memory_barrier_buffer
:
2372 case nir_intrinsic_memory_barrier_image
:
2373 case nir_intrinsic_memory_barrier_shared
:
2374 emit_intrinsic_barrier(ctx
, intr
);
2375 /* note that blk ptr no longer valid, make that obvious: */
2378 case nir_intrinsic_store_output
:
2379 idx
= nir_intrinsic_base(intr
);
2380 comp
= nir_intrinsic_component(intr
);
2381 const_offset
= nir_src_as_const_value(intr
->src
[1]);
2382 compile_assert(ctx
, const_offset
!= NULL
);
2383 idx
+= const_offset
->u32
[0];
2385 src
= get_src(ctx
, &intr
->src
[0]);
2386 for (int i
= 0; i
< intr
->num_components
; i
++) {
2387 unsigned n
= idx
* 4 + i
+ comp
;
2388 ctx
->ir
->outputs
[n
] = src
[i
];
2391 case nir_intrinsic_load_base_vertex
:
2392 case nir_intrinsic_load_first_vertex
:
2393 if (!ctx
->basevertex
) {
2394 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
2395 add_sysval_input(ctx
, SYSTEM_VALUE_FIRST_VERTEX
, ctx
->basevertex
);
2397 dst
[0] = ctx
->basevertex
;
2399 case nir_intrinsic_load_vertex_id_zero_base
:
2400 case nir_intrinsic_load_vertex_id
:
2401 if (!ctx
->vertex_id
) {
2402 gl_system_value sv
= (intr
->intrinsic
== nir_intrinsic_load_vertex_id
) ?
2403 SYSTEM_VALUE_VERTEX_ID
: SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
;
2404 ctx
->vertex_id
= create_input(ctx
, 0);
2405 add_sysval_input(ctx
, sv
, ctx
->vertex_id
);
2407 dst
[0] = ctx
->vertex_id
;
2409 case nir_intrinsic_load_instance_id
:
2410 if (!ctx
->instance_id
) {
2411 ctx
->instance_id
= create_input(ctx
, 0);
2412 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
2415 dst
[0] = ctx
->instance_id
;
2417 case nir_intrinsic_load_sample_id
:
2418 case nir_intrinsic_load_sample_id_no_per_sample
:
2419 if (!ctx
->samp_id
) {
2420 ctx
->samp_id
= create_input(ctx
, 0);
2421 ctx
->samp_id
->regs
[0]->flags
|= IR3_REG_HALF
;
2422 add_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_ID
,
2425 dst
[0] = ir3_COV(b
, ctx
->samp_id
, TYPE_U16
, TYPE_U32
);
2427 case nir_intrinsic_load_sample_mask_in
:
2428 if (!ctx
->samp_mask_in
) {
2429 ctx
->samp_mask_in
= create_input(ctx
, 0);
2430 add_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_MASK_IN
,
2433 dst
[0] = ctx
->samp_mask_in
;
2435 case nir_intrinsic_load_user_clip_plane
:
2436 idx
= nir_intrinsic_ucp_id(intr
);
2437 for (int i
= 0; i
< intr
->num_components
; i
++) {
2438 unsigned n
= idx
* 4 + i
;
2439 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
2442 case nir_intrinsic_load_front_face
:
2443 if (!ctx
->frag_face
) {
2444 ctx
->so
->frag_face
= true;
2445 ctx
->frag_face
= create_input(ctx
, 0);
2446 add_sysval_input(ctx
, SYSTEM_VALUE_FRONT_FACE
, ctx
->frag_face
);
2447 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
2449 /* for fragface, we get -1 for back and 0 for front. However this is
2450 * the inverse of what nir expects (where ~0 is true).
2452 dst
[0] = ir3_COV(b
, ctx
->frag_face
, TYPE_S16
, TYPE_S32
);
2453 dst
[0] = ir3_NOT_B(b
, dst
[0], 0);
2455 case nir_intrinsic_load_local_invocation_id
:
2456 if (!ctx
->local_invocation_id
) {
2457 ctx
->local_invocation_id
= create_input_compmask(ctx
, 0, 0x7);
2458 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
,
2459 0x7, ctx
->local_invocation_id
);
2461 split_dest(b
, dst
, ctx
->local_invocation_id
, 0, 3);
2463 case nir_intrinsic_load_work_group_id
:
2464 if (!ctx
->work_group_id
) {
2465 ctx
->work_group_id
= create_input_compmask(ctx
, 0, 0x7);
2466 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_WORK_GROUP_ID
,
2467 0x7, ctx
->work_group_id
);
2468 ctx
->work_group_id
->regs
[0]->flags
|= IR3_REG_HIGH
;
2470 split_dest(b
, dst
, ctx
->work_group_id
, 0, 3);
2472 case nir_intrinsic_load_num_work_groups
:
2473 for (int i
= 0; i
< intr
->num_components
; i
++) {
2474 dst
[i
] = create_driver_param(ctx
, IR3_DP_NUM_WORK_GROUPS_X
+ i
);
2477 case nir_intrinsic_load_local_group_size
:
2478 for (int i
= 0; i
< intr
->num_components
; i
++) {
2479 dst
[i
] = create_driver_param(ctx
, IR3_DP_LOCAL_GROUP_SIZE_X
+ i
);
2482 case nir_intrinsic_discard_if
:
2483 case nir_intrinsic_discard
: {
2484 struct ir3_instruction
*cond
, *kill
;
2486 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
2487 /* conditional discard: */
2488 src
= get_src(ctx
, &intr
->src
[0]);
2489 cond
= ir3_b2n(b
, src
[0]);
2491 /* unconditional discard: */
2492 cond
= create_immed(b
, 1);
2495 /* NOTE: only cmps.*.* can write p0.x: */
2496 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
2497 cond
->cat2
.condition
= IR3_COND_NE
;
2499 /* condition always goes in predicate register: */
2500 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2502 kill
= ir3_KILL(b
, cond
, 0);
2503 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
2505 array_insert(b
, b
->keeps
, kill
);
2506 ctx
->so
->has_kill
= true;
2511 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
2512 nir_intrinsic_infos
[intr
->intrinsic
].name
);
2517 put_dst(ctx
, &intr
->dest
);
2521 emit_load_const(struct ir3_context
*ctx
, nir_load_const_instr
*instr
)
2523 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
2524 instr
->def
.num_components
);
2525 type_t type
= (instr
->def
.bit_size
< 32) ? TYPE_U16
: TYPE_U32
;
2527 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
2528 dst
[i
] = create_immed_typed(ctx
->block
, instr
->value
.u32
[i
], type
);
2532 emit_undef(struct ir3_context
*ctx
, nir_ssa_undef_instr
*undef
)
2534 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
2535 undef
->def
.num_components
);
2536 type_t type
= (undef
->def
.bit_size
< 32) ? TYPE_U16
: TYPE_U32
;
2538 /* backend doesn't want undefined instructions, so just plug
2541 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
2542 dst
[i
] = create_immed_typed(ctx
->block
, fui(0.0), type
);
2546 * texture fetch/sample instructions:
2550 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
2552 unsigned coords
, flags
= 0;
2554 /* note: would use tex->coord_components.. except txs.. also,
2555 * since array index goes after shadow ref, we don't want to
2558 switch (tex
->sampler_dim
) {
2559 case GLSL_SAMPLER_DIM_1D
:
2560 case GLSL_SAMPLER_DIM_BUF
:
2563 case GLSL_SAMPLER_DIM_2D
:
2564 case GLSL_SAMPLER_DIM_RECT
:
2565 case GLSL_SAMPLER_DIM_EXTERNAL
:
2566 case GLSL_SAMPLER_DIM_MS
:
2569 case GLSL_SAMPLER_DIM_3D
:
2570 case GLSL_SAMPLER_DIM_CUBE
:
2572 flags
|= IR3_INSTR_3D
;
2575 unreachable("bad sampler_dim");
2578 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2579 flags
|= IR3_INSTR_S
;
2581 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
2582 flags
|= IR3_INSTR_A
;
2589 emit_tex(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2591 struct ir3_block
*b
= ctx
->block
;
2592 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
2593 struct ir3_instruction
* const *coord
, * const *off
, * const *ddx
, * const *ddy
;
2594 struct ir3_instruction
*lod
, *compare
, *proj
, *sample_index
;
2595 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
2596 unsigned i
, coords
, flags
;
2597 unsigned nsrc0
= 0, nsrc1
= 0;
2601 coord
= off
= ddx
= ddy
= NULL
;
2602 lod
= proj
= compare
= sample_index
= NULL
;
2604 /* TODO: might just be one component for gathers? */
2605 dst
= get_dst(ctx
, &tex
->dest
, 4);
2607 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
2608 switch (tex
->src
[i
].src_type
) {
2609 case nir_tex_src_coord
:
2610 coord
= get_src(ctx
, &tex
->src
[i
].src
);
2612 case nir_tex_src_bias
:
2613 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2616 case nir_tex_src_lod
:
2617 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2620 case nir_tex_src_comparator
: /* shadow comparator */
2621 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2623 case nir_tex_src_projector
:
2624 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2627 case nir_tex_src_offset
:
2628 off
= get_src(ctx
, &tex
->src
[i
].src
);
2631 case nir_tex_src_ddx
:
2632 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
2634 case nir_tex_src_ddy
:
2635 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
2637 case nir_tex_src_ms_index
:
2638 sample_index
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2641 compile_error(ctx
, "Unhandled NIR tex src type: %d\n",
2642 tex
->src
[i
].src_type
);
2648 case nir_texop_tex
: opc
= has_lod
? OPC_SAML
: OPC_SAM
; break;
2649 case nir_texop_txb
: opc
= OPC_SAMB
; break;
2650 case nir_texop_txl
: opc
= OPC_SAML
; break;
2651 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
2652 case nir_texop_txf
: opc
= OPC_ISAML
; break;
2653 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
2655 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2656 * what blob does, seems gather is broken?), and a3xx did
2657 * not support it (but probably could also emulate).
2659 switch (tex
->component
) {
2660 case 0: opc
= OPC_GATHER4R
; break;
2661 case 1: opc
= OPC_GATHER4G
; break;
2662 case 2: opc
= OPC_GATHER4B
; break;
2663 case 3: opc
= OPC_GATHER4A
; break;
2666 case nir_texop_txf_ms
: opc
= OPC_ISAMM
; break;
2668 case nir_texop_query_levels
:
2669 case nir_texop_texture_samples
:
2670 case nir_texop_samples_identical
:
2671 case nir_texop_txf_ms_mcs
:
2672 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
2676 tex_info(tex
, &flags
, &coords
);
2679 * lay out the first argument in the proper order:
2680 * - actual coordinates first
2681 * - shadow reference
2684 * - starting at offset 4, dpdx.xy, dpdy.xy
2686 * bias/lod go into the second arg
2689 /* insert tex coords: */
2690 for (i
= 0; i
< coords
; i
++)
2695 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2696 * with scaled x coord according to requested sample:
2698 if (tex
->op
== nir_texop_txf_ms
) {
2699 if (ctx
->compiler
->txf_ms_with_isaml
) {
2700 /* the samples are laid out in x dimension as
2702 * x_ms = (x << ms) + sample_index;
2704 struct ir3_instruction
*ms
;
2705 ms
= create_immed(b
, (ctx
->samples
>> (2 * tex
->texture_index
)) & 3);
2707 src0
[0] = ir3_SHL_B(b
, src0
[0], 0, ms
, 0);
2708 src0
[0] = ir3_ADD_U(b
, src0
[0], 0, sample_index
, 0);
2712 src0
[nsrc0
++] = sample_index
;
2716 /* scale up integer coords for TXF based on the LOD */
2717 if (ctx
->compiler
->unminify_coords
&& (opc
== OPC_ISAML
)) {
2719 for (i
= 0; i
< coords
; i
++)
2720 src0
[i
] = ir3_SHL_B(b
, src0
[i
], 0, lod
, 0);
2724 /* hw doesn't do 1d, so we treat it as 2d with
2725 * height of 1, and patch up the y coord.
2726 * TODO: y coord should be (int)0 in some cases..
2728 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
2731 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2732 src0
[nsrc0
++] = compare
;
2734 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
) {
2735 struct ir3_instruction
*idx
= coord
[coords
];
2737 /* the array coord for cube arrays needs 0.5 added to it */
2738 if (ctx
->compiler
->array_index_add_half
&& (opc
!= OPC_ISAML
))
2739 idx
= ir3_ADD_F(b
, idx
, 0, create_immed(b
, fui(0.5)), 0);
2741 src0
[nsrc0
++] = idx
;
2745 src0
[nsrc0
++] = proj
;
2746 flags
|= IR3_INSTR_P
;
2749 /* pad to 4, then ddx/ddy: */
2750 if (tex
->op
== nir_texop_txd
) {
2752 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2753 for (i
= 0; i
< coords
; i
++)
2754 src0
[nsrc0
++] = ddx
[i
];
2756 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2757 for (i
= 0; i
< coords
; i
++)
2758 src0
[nsrc0
++] = ddy
[i
];
2760 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2764 * second argument (if applicable):
2769 if (has_off
| has_lod
| has_bias
) {
2771 unsigned off_coords
= coords
;
2772 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2774 for (i
= 0; i
< off_coords
; i
++)
2775 src1
[nsrc1
++] = off
[i
];
2777 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
2778 flags
|= IR3_INSTR_O
;
2781 if (has_lod
| has_bias
)
2782 src1
[nsrc1
++] = lod
;
2785 switch (tex
->dest_type
) {
2786 case nir_type_invalid
:
2787 case nir_type_float
:
2798 unreachable("bad dest_type");
2801 if (opc
== OPC_GETLOD
)
2804 unsigned tex_idx
= tex
->texture_index
;
2806 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex_idx
);
2808 struct ir3_instruction
*col0
= create_collect(ctx
, src0
, nsrc0
);
2809 struct ir3_instruction
*col1
= create_collect(ctx
, src1
, nsrc1
);
2811 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
, flags
,
2812 tex_idx
, tex_idx
, col0
, col1
);
2814 if ((ctx
->astc_srgb
& (1 << tex_idx
)) && !nir_tex_instr_is_query(tex
)) {
2815 /* only need first 3 components: */
2816 sam
->regs
[0]->wrmask
= 0x7;
2817 split_dest(b
, dst
, sam
, 0, 3);
2819 /* we need to sample the alpha separately with a non-ASTC
2822 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_W
, flags
,
2823 tex_idx
, tex_idx
, col0
, col1
);
2825 array_insert(ctx
->ir
, ctx
->ir
->astc_srgb
, sam
);
2827 /* fixup .w component: */
2828 split_dest(b
, &dst
[3], sam
, 3, 1);
2830 /* normal (non-workaround) case: */
2831 split_dest(b
, dst
, sam
, 0, 4);
2834 /* GETLOD returns results in 4.8 fixed point */
2835 if (opc
== OPC_GETLOD
) {
2836 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
2838 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
2839 for (i
= 0; i
< 2; i
++) {
2840 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_U32
, TYPE_F32
), 0,
2845 put_dst(ctx
, &tex
->dest
);
2849 emit_tex_query_levels(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2851 struct ir3_block
*b
= ctx
->block
;
2852 struct ir3_instruction
**dst
, *sam
;
2854 dst
= get_dst(ctx
, &tex
->dest
, 1);
2856 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
2857 tex
->texture_index
, tex
->texture_index
, NULL
, NULL
);
2859 /* even though there is only one component, since it ends
2860 * up in .z rather than .x, we need a split_dest()
2862 split_dest(b
, dst
, sam
, 0, 3);
2864 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2865 * the value in TEX_CONST_0 is zero-based.
2867 if (ctx
->compiler
->levels_add_one
)
2868 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
2870 put_dst(ctx
, &tex
->dest
);
2874 emit_tex_txs(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2876 struct ir3_block
*b
= ctx
->block
;
2877 struct ir3_instruction
**dst
, *sam
;
2878 struct ir3_instruction
*lod
;
2879 unsigned flags
, coords
;
2881 tex_info(tex
, &flags
, &coords
);
2883 /* Actually we want the number of dimensions, not coordinates. This
2884 * distinction only matters for cubes.
2886 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2889 dst
= get_dst(ctx
, &tex
->dest
, 4);
2891 compile_assert(ctx
, tex
->num_srcs
== 1);
2892 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
2894 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
2896 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
2897 tex
->texture_index
, tex
->texture_index
, lod
, NULL
);
2899 split_dest(b
, dst
, sam
, 0, 4);
2901 /* Array size actually ends up in .w rather than .z. This doesn't
2902 * matter for miplevel 0, but for higher mips the value in z is
2903 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2904 * returned, which means that we have to add 1 to it for arrays.
2906 if (tex
->is_array
) {
2907 if (ctx
->compiler
->levels_add_one
) {
2908 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
2910 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
2914 put_dst(ctx
, &tex
->dest
);
2918 emit_jump(struct ir3_context
*ctx
, nir_jump_instr
*jump
)
2920 switch (jump
->type
) {
2921 case nir_jump_break
:
2922 case nir_jump_continue
:
2923 case nir_jump_return
:
2924 /* I *think* we can simply just ignore this, and use the
2925 * successor block link to figure out where we need to
2926 * jump to for break/continue
2930 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
2936 emit_instr(struct ir3_context
*ctx
, nir_instr
*instr
)
2938 switch (instr
->type
) {
2939 case nir_instr_type_alu
:
2940 emit_alu(ctx
, nir_instr_as_alu(instr
));
2942 case nir_instr_type_deref
:
2943 /* ignored, handled as part of the intrinsic they are src to */
2945 case nir_instr_type_intrinsic
:
2946 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2948 case nir_instr_type_load_const
:
2949 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2951 case nir_instr_type_ssa_undef
:
2952 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
2954 case nir_instr_type_tex
: {
2955 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
2956 /* couple tex instructions get special-cased:
2960 emit_tex_txs(ctx
, tex
);
2962 case nir_texop_query_levels
:
2963 emit_tex_query_levels(ctx
, tex
);
2971 case nir_instr_type_jump
:
2972 emit_jump(ctx
, nir_instr_as_jump(instr
));
2974 case nir_instr_type_phi
:
2975 /* we have converted phi webs to regs in NIR by now */
2976 compile_error(ctx
, "Unexpected NIR instruction type: %d\n", instr
->type
);
2978 case nir_instr_type_call
:
2979 case nir_instr_type_parallel_copy
:
2980 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
2985 static struct ir3_block
*
2986 get_block(struct ir3_context
*ctx
, const nir_block
*nblock
)
2988 struct ir3_block
*block
;
2989 struct hash_entry
*hentry
;
2992 hentry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
2994 return hentry
->data
;
2996 block
= ir3_block_create(ctx
->ir
);
2997 block
->nblock
= nblock
;
2998 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
3000 block
->predecessors_count
= nblock
->predecessors
->entries
;
3001 block
->predecessors
= ralloc_array_size(block
,
3002 sizeof(block
->predecessors
[0]), block
->predecessors_count
);
3004 set_foreach(nblock
->predecessors
, sentry
) {
3005 block
->predecessors
[i
++] = get_block(ctx
, sentry
->key
);
3012 emit_block(struct ir3_context
*ctx
, nir_block
*nblock
)
3014 struct ir3_block
*block
= get_block(ctx
, nblock
);
3016 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
3017 if (nblock
->successors
[i
]) {
3018 block
->successors
[i
] =
3019 get_block(ctx
, nblock
->successors
[i
]);
3024 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
3026 /* re-emit addr register in each block if needed: */
3027 for (int i
= 0; i
< ARRAY_SIZE(ctx
->addr_ht
); i
++) {
3028 _mesa_hash_table_destroy(ctx
->addr_ht
[i
], NULL
);
3029 ctx
->addr_ht
[i
] = NULL
;
3032 nir_foreach_instr(instr
, nblock
) {
3033 ctx
->cur_instr
= instr
;
3034 emit_instr(ctx
, instr
);
3035 ctx
->cur_instr
= NULL
;
3041 static void emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
);
3044 emit_if(struct ir3_context
*ctx
, nir_if
*nif
)
3046 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
3048 ctx
->block
->condition
=
3049 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
3051 emit_cf_list(ctx
, &nif
->then_list
);
3052 emit_cf_list(ctx
, &nif
->else_list
);
3056 emit_loop(struct ir3_context
*ctx
, nir_loop
*nloop
)
3058 emit_cf_list(ctx
, &nloop
->body
);
3062 emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
)
3064 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
3065 switch (node
->type
) {
3066 case nir_cf_node_block
:
3067 emit_block(ctx
, nir_cf_node_as_block(node
));
3069 case nir_cf_node_if
:
3070 emit_if(ctx
, nir_cf_node_as_if(node
));
3072 case nir_cf_node_loop
:
3073 emit_loop(ctx
, nir_cf_node_as_loop(node
));
3075 case nir_cf_node_function
:
3076 compile_error(ctx
, "TODO\n");
3082 /* emit stream-out code. At this point, the current block is the original
3083 * (nir) end block, and nir ensures that all flow control paths terminate
3084 * into the end block. We re-purpose the original end block to generate
3085 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
3086 * block holding stream-out write instructions, followed by the new end
3090 * p0.x = (vtxcnt < maxvtxcnt)
3091 * // succs: blockStreamOut, blockNewEnd
3094 * ... stream-out instructions ...
3095 * // succs: blockNewEnd
3101 emit_stream_out(struct ir3_context
*ctx
)
3103 struct ir3_shader_variant
*v
= ctx
->so
;
3104 struct ir3
*ir
= ctx
->ir
;
3105 struct pipe_stream_output_info
*strmout
=
3106 &ctx
->so
->shader
->stream_output
;
3107 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
3108 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
3109 struct ir3_instruction
*bases
[PIPE_MAX_SO_BUFFERS
];
3111 /* create vtxcnt input in input block at top of shader,
3112 * so that it is seen as live over the entire duration
3115 vtxcnt
= create_input(ctx
, 0);
3116 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
3118 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
3120 /* at this point, we are at the original 'end' block,
3121 * re-purpose this block to stream-out condition, then
3122 * append stream-out block and new-end block
3124 orig_end_block
= ctx
->block
;
3126 // TODO these blocks need to update predecessors..
3127 // maybe w/ store_global intrinsic, we could do this
3128 // stuff in nir->nir pass
3130 stream_out_block
= ir3_block_create(ir
);
3131 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
3133 new_end_block
= ir3_block_create(ir
);
3134 list_addtail(&new_end_block
->node
, &ir
->block_list
);
3136 orig_end_block
->successors
[0] = stream_out_block
;
3137 orig_end_block
->successors
[1] = new_end_block
;
3138 stream_out_block
->successors
[0] = new_end_block
;
3140 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
3141 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
3142 cond
->regs
[0]->num
= regid(REG_P0
, 0);
3143 cond
->cat2
.condition
= IR3_COND_LT
;
3145 /* condition goes on previous block to the conditional,
3146 * since it is used to pick which of the two successor
3149 orig_end_block
->condition
= cond
;
3151 /* switch to stream_out_block to generate the stream-out
3154 ctx
->block
= stream_out_block
;
3156 /* Calculate base addresses based on vtxcnt. Instructions
3157 * generated for bases not used in following loop will be
3158 * stripped out in the backend.
3160 for (unsigned i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
3161 unsigned stride
= strmout
->stride
[i
];
3162 struct ir3_instruction
*base
, *off
;
3164 base
= create_uniform(ctx
, regid(v
->constbase
.tfbo
, i
));
3166 /* 24-bit should be enough: */
3167 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
3168 create_immed(ctx
->block
, stride
* 4), 0);
3170 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
3173 /* Generate the per-output store instructions: */
3174 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
3175 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
3176 unsigned c
= j
+ strmout
->output
[i
].start_component
;
3177 struct ir3_instruction
*base
, *out
, *stg
;
3179 base
= bases
[strmout
->output
[i
].output_buffer
];
3180 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
3182 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
3183 create_immed(ctx
->block
, 1), 0);
3184 stg
->cat6
.type
= TYPE_U32
;
3185 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
3187 array_insert(ctx
->block
, ctx
->block
->keeps
, stg
);
3191 /* and finally switch to the new_end_block: */
3192 ctx
->block
= new_end_block
;
3196 emit_function(struct ir3_context
*ctx
, nir_function_impl
*impl
)
3198 nir_metadata_require(impl
, nir_metadata_block_index
);
3200 emit_cf_list(ctx
, &impl
->body
);
3201 emit_block(ctx
, impl
->end_block
);
3203 /* at this point, we should have a single empty block,
3204 * into which we emit the 'end' instruction.
3206 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
3208 /* If stream-out (aka transform-feedback) enabled, emit the
3209 * stream-out instructions, followed by a new empty block (into
3210 * which the 'end' instruction lands).
3212 * NOTE: it is done in this order, rather than inserting before
3213 * we emit end_block, because NIR guarantees that all blocks
3214 * flow into end_block, and that end_block has no successors.
3215 * So by re-purposing end_block as the first block of stream-
3216 * out, we guarantee that all exit paths flow into the stream-
3219 if ((ctx
->compiler
->gpu_id
< 500) &&
3220 (ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
3221 !ctx
->so
->binning_pass
) {
3222 debug_assert(ctx
->so
->type
== MESA_SHADER_VERTEX
);
3223 emit_stream_out(ctx
);
3226 ir3_END(ctx
->block
);
3229 static struct ir3_instruction
*
3230 create_frag_coord(struct ir3_context
*ctx
, unsigned comp
)
3232 struct ir3_block
*block
= ctx
->block
;
3233 struct ir3_instruction
*instr
;
3235 if (!ctx
->frag_coord
) {
3236 ctx
->frag_coord
= create_input_compmask(ctx
, 0, 0xf);
3237 /* defer add_sysval_input() until after all inputs created */
3240 split_dest(block
, &instr
, ctx
->frag_coord
, comp
, 1);
3245 /* for frag_coord, we get unsigned values.. we need
3246 * to subtract (integer) 8 and divide by 16 (right-
3247 * shift by 4) then convert to float:
3251 * mov.u32f32 dst, tmp
3254 instr
= ir3_SUB_S(block
, instr
, 0,
3255 create_immed(block
, 8), 0);
3256 instr
= ir3_SHR_B(block
, instr
, 0,
3257 create_immed(block
, 4), 0);
3258 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
3264 /* seems that we can use these as-is: */
3270 setup_input(struct ir3_context
*ctx
, nir_variable
*in
)
3272 struct ir3_shader_variant
*so
= ctx
->so
;
3273 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
3274 unsigned ncomp
= glsl_get_components(in
->type
);
3275 unsigned n
= in
->data
.driver_location
;
3276 unsigned slot
= in
->data
.location
;
3278 DBG("; in: slot=%u, len=%ux%u, drvloc=%u",
3279 slot
, array_len
, ncomp
, n
);
3281 /* let's pretend things other than vec4 don't exist: */
3282 ncomp
= MAX2(ncomp
, 4);
3284 /* skip unread inputs, we could end up with (for example), unsplit
3285 * matrix/etc inputs in the case they are not read, so just silently
3291 compile_assert(ctx
, ncomp
== 4);
3293 so
->inputs
[n
].slot
= slot
;
3294 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
3295 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
3296 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
3298 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
3299 for (int i
= 0; i
< ncomp
; i
++) {
3300 struct ir3_instruction
*instr
= NULL
;
3301 unsigned idx
= (n
* 4) + i
;
3303 if (slot
== VARYING_SLOT_POS
) {
3304 so
->inputs
[n
].bary
= false;
3305 so
->frag_coord
= true;
3306 instr
= create_frag_coord(ctx
, i
);
3307 } else if (slot
== VARYING_SLOT_PNTC
) {
3308 /* see for example st_nir_fixup_varying_slots().. this is
3309 * maybe a bit mesa/st specific. But we need things to line
3310 * up for this in fdN_program:
3311 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
3312 * if (emit->sprite_coord_enable & texmask) {
3316 so
->inputs
[n
].slot
= VARYING_SLOT_VAR8
;
3317 so
->inputs
[n
].bary
= true;
3318 instr
= create_frag_input(ctx
, false);
3320 bool use_ldlv
= false;
3322 /* detect the special case for front/back colors where
3323 * we need to do flat vs smooth shading depending on
3326 if (in
->data
.interpolation
== INTERP_MODE_NONE
) {
3328 case VARYING_SLOT_COL0
:
3329 case VARYING_SLOT_COL1
:
3330 case VARYING_SLOT_BFC0
:
3331 case VARYING_SLOT_BFC1
:
3332 so
->inputs
[n
].rasterflat
= true;
3339 if (ctx
->compiler
->flat_bypass
) {
3340 if ((so
->inputs
[n
].interpolate
== INTERP_MODE_FLAT
) ||
3341 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
3345 so
->inputs
[n
].bary
= true;
3347 instr
= create_frag_input(ctx
, use_ldlv
);
3350 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
3352 ctx
->ir
->inputs
[idx
] = instr
;
3354 } else if (ctx
->so
->type
== MESA_SHADER_VERTEX
) {
3355 for (int i
= 0; i
< ncomp
; i
++) {
3356 unsigned idx
= (n
* 4) + i
;
3357 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
3358 ctx
->ir
->inputs
[idx
] = create_input(ctx
, idx
);
3361 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3364 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== MESA_SHADER_VERTEX
)) {
3365 so
->total_in
+= ncomp
;
3370 setup_output(struct ir3_context
*ctx
, nir_variable
*out
)
3372 struct ir3_shader_variant
*so
= ctx
->so
;
3373 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
3374 unsigned ncomp
= glsl_get_components(out
->type
);
3375 unsigned n
= out
->data
.driver_location
;
3376 unsigned slot
= out
->data
.location
;
3379 DBG("; out: slot=%u, len=%ux%u, drvloc=%u",
3380 slot
, array_len
, ncomp
, n
);
3382 /* let's pretend things other than vec4 don't exist: */
3383 ncomp
= MAX2(ncomp
, 4);
3384 compile_assert(ctx
, ncomp
== 4);
3386 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
3388 case FRAG_RESULT_DEPTH
:
3389 comp
= 2; /* tgsi will write to .z component */
3390 so
->writes_pos
= true;
3392 case FRAG_RESULT_COLOR
:
3396 if (slot
>= FRAG_RESULT_DATA0
)
3398 compile_error(ctx
, "unknown FS output name: %s\n",
3399 gl_frag_result_name(slot
));
3401 } else if (ctx
->so
->type
== MESA_SHADER_VERTEX
) {
3403 case VARYING_SLOT_POS
:
3404 so
->writes_pos
= true;
3406 case VARYING_SLOT_PSIZ
:
3407 so
->writes_psize
= true;
3409 case VARYING_SLOT_COL0
:
3410 case VARYING_SLOT_COL1
:
3411 case VARYING_SLOT_BFC0
:
3412 case VARYING_SLOT_BFC1
:
3413 case VARYING_SLOT_FOGC
:
3414 case VARYING_SLOT_CLIP_DIST0
:
3415 case VARYING_SLOT_CLIP_DIST1
:
3416 case VARYING_SLOT_CLIP_VERTEX
:
3419 if (slot
>= VARYING_SLOT_VAR0
)
3421 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
3423 compile_error(ctx
, "unknown VS output name: %s\n",
3424 gl_varying_slot_name(slot
));
3427 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3430 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
3432 so
->outputs
[n
].slot
= slot
;
3433 so
->outputs
[n
].regid
= regid(n
, comp
);
3434 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
3436 for (int i
= 0; i
< ncomp
; i
++) {
3437 unsigned idx
= (n
* 4) + i
;
3438 compile_assert(ctx
, idx
< ctx
->ir
->noutputs
);
3439 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
3444 max_drvloc(struct exec_list
*vars
)
3447 nir_foreach_variable(var
, vars
) {
3448 drvloc
= MAX2(drvloc
, (int)var
->data
.driver_location
);
3453 static const unsigned max_sysvals
[] = {
3454 [MESA_SHADER_FRAGMENT
] = 24, // TODO
3455 [MESA_SHADER_VERTEX
] = 16,
3456 [MESA_SHADER_COMPUTE
] = 16, // TODO how many do we actually need?
3460 emit_instructions(struct ir3_context
*ctx
)
3462 unsigned ninputs
, noutputs
;
3463 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
3465 ninputs
= (max_drvloc(&ctx
->s
->inputs
) + 1) * 4;
3466 noutputs
= (max_drvloc(&ctx
->s
->outputs
) + 1) * 4;
3468 /* we need to leave room for sysvals:
3470 ninputs
+= max_sysvals
[ctx
->so
->type
];
3472 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
3474 /* Create inputs in first block: */
3475 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
3476 ctx
->in_block
= ctx
->block
;
3477 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
3479 ninputs
-= max_sysvals
[ctx
->so
->type
];
3481 /* for fragment shader, the vcoord input register is used as the
3482 * base for bary.f varying fetch instrs:
3484 struct ir3_instruction
*vcoord
= NULL
;
3485 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
3486 struct ir3_instruction
*xy
[2];
3488 vcoord
= create_input_compmask(ctx
, 0, 0x3);
3489 split_dest(ctx
->block
, xy
, vcoord
, 0, 2);
3491 ctx
->frag_vcoord
= create_collect(ctx
, xy
, 2);
3495 nir_foreach_variable(var
, &ctx
->s
->inputs
) {
3496 setup_input(ctx
, var
);
3499 /* Defer add_sysval_input() stuff until after setup_inputs(),
3500 * because sysvals need to be appended after varyings:
3503 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_VARYING_COORD
,
3507 if (ctx
->frag_coord
) {
3508 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_FRAG_COORD
,
3509 0xf, ctx
->frag_coord
);
3512 /* Setup outputs: */
3513 nir_foreach_variable(var
, &ctx
->s
->outputs
) {
3514 setup_output(ctx
, var
);
3517 /* Setup registers (which should only be arrays): */
3518 nir_foreach_register(reg
, &ctx
->s
->registers
) {
3519 declare_array(ctx
, reg
);
3522 /* NOTE: need to do something more clever when we support >1 fxn */
3523 nir_foreach_register(reg
, &fxn
->registers
) {
3524 declare_array(ctx
, reg
);
3526 /* And emit the body: */
3528 emit_function(ctx
, fxn
);
3531 /* from NIR perspective, we actually have varying inputs. But the varying
3532 * inputs, from an IR standpoint, are just bary.f/ldlv instructions. The
3533 * only actual inputs are the sysvals.
3536 fixup_frag_inputs(struct ir3_context
*ctx
)
3538 struct ir3_shader_variant
*so
= ctx
->so
;
3539 struct ir3
*ir
= ctx
->ir
;
3542 /* sysvals should appear at the end of the inputs, drop everything else: */
3543 while ((i
< so
->inputs_count
) && !so
->inputs
[i
].sysval
)
3546 /* at IR level, inputs are always blocks of 4 scalars: */
3549 ir
->inputs
= &ir
->inputs
[i
];
3553 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3554 * need to assign the tex state indexes for these after we know the
3558 fixup_astc_srgb(struct ir3_context
*ctx
)
3560 struct ir3_shader_variant
*so
= ctx
->so
;
3561 /* indexed by original tex idx, value is newly assigned alpha sampler
3562 * state tex idx. Zero is invalid since there is at least one sampler
3565 unsigned alt_tex_state
[16] = {0};
3566 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
3569 so
->astc_srgb
.base
= tex_idx
;
3571 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
3572 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
3574 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
3576 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
3577 /* assign new alternate/alpha tex state slot: */
3578 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
3579 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
3580 so
->astc_srgb
.count
++;
3583 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
3588 fixup_binning_pass(struct ir3_context
*ctx
)
3590 struct ir3_shader_variant
*so
= ctx
->so
;
3591 struct ir3
*ir
= ctx
->ir
;
3594 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
3595 unsigned slot
= so
->outputs
[i
].slot
;
3597 /* throw away everything but first position/psize */
3598 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
3600 so
->outputs
[j
] = so
->outputs
[i
];
3601 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
3602 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
3603 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
3604 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
3609 so
->outputs_count
= j
;
3610 ir
->noutputs
= j
* 4;
3614 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
3615 struct ir3_shader_variant
*so
)
3617 struct ir3_context
*ctx
;
3619 struct ir3_instruction
**inputs
;
3620 unsigned i
, actual_in
, inloc
;
3621 int ret
= 0, max_bary
;
3625 ctx
= compile_init(compiler
, so
);
3627 DBG("INIT failed!");
3632 emit_instructions(ctx
);
3635 DBG("EMIT failed!");
3640 ir
= so
->ir
= ctx
->ir
;
3642 /* keep track of the inputs from TGSI perspective.. */
3643 inputs
= ir
->inputs
;
3645 /* but fixup actual inputs for frag shader: */
3646 if (so
->type
== MESA_SHADER_FRAGMENT
)
3647 fixup_frag_inputs(ctx
);
3649 /* at this point, for binning pass, throw away unneeded outputs: */
3650 if (so
->binning_pass
&& (ctx
->compiler
->gpu_id
< 600))
3651 fixup_binning_pass(ctx
);
3653 /* if we want half-precision outputs, mark the output registers
3656 if (so
->key
.half_precision
) {
3657 for (i
= 0; i
< ir
->noutputs
; i
++) {
3658 struct ir3_instruction
*out
= ir
->outputs
[i
];
3663 /* if frag shader writes z, that needs to be full precision: */
3664 if (so
->outputs
[i
/4].slot
== FRAG_RESULT_DEPTH
)
3667 out
->regs
[0]->flags
|= IR3_REG_HALF
;
3668 /* output could be a fanout (ie. texture fetch output)
3669 * in which case we need to propagate the half-reg flag
3670 * up to the definer so that RA sees it:
3672 if (out
->opc
== OPC_META_FO
) {
3673 out
= out
->regs
[1]->instr
;
3674 out
->regs
[0]->flags
|= IR3_REG_HALF
;
3677 if (out
->opc
== OPC_MOV
) {
3678 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
3683 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
3684 printf("BEFORE CP:\n");
3690 /* at this point, for binning pass, throw away unneeded outputs:
3691 * Note that for a6xx and later, we do this after ir3_cp to ensure
3692 * that the uniform/constant layout for BS and VS matches, so that
3693 * we can re-use same VS_CONST state group.
3695 if (so
->binning_pass
&& (ctx
->compiler
->gpu_id
>= 600))
3696 fixup_binning_pass(ctx
);
3698 /* Insert mov if there's same instruction for each output.
3699 * eg. dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_expression.vertex.sampler2dshadow
3701 for (int i
= ir
->noutputs
- 1; i
>= 0; i
--) {
3702 if (!ir
->outputs
[i
])
3704 for (unsigned j
= 0; j
< i
; j
++) {
3705 if (ir
->outputs
[i
] == ir
->outputs
[j
]) {
3707 ir3_MOV(ir
->outputs
[i
]->block
, ir
->outputs
[i
], TYPE_F32
);
3712 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
3713 printf("BEFORE GROUPING:\n");
3717 ir3_sched_add_deps(ir
);
3719 /* Group left/right neighbors, inserting mov's where needed to
3724 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
3725 printf("AFTER GROUPING:\n");
3731 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
3732 printf("AFTER DEPTH:\n");
3736 ret
= ir3_sched(ir
);
3738 DBG("SCHED failed!");
3742 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
3743 printf("AFTER SCHED:\n");
3747 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
3753 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
3754 printf("AFTER RA:\n");
3758 /* fixup input/outputs: */
3759 for (i
= 0; i
< so
->outputs_count
; i
++) {
3760 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
3763 /* Note that some or all channels of an input may be unused: */
3766 for (i
= 0; i
< so
->inputs_count
; i
++) {
3767 unsigned j
, reg
= regid(63,0), compmask
= 0, maxcomp
= 0;
3768 so
->inputs
[i
].ncomp
= 0;
3769 so
->inputs
[i
].inloc
= inloc
;
3770 for (j
= 0; j
< 4; j
++) {
3771 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
3772 if (in
&& !(in
->flags
& IR3_INSTR_UNUSED
)) {
3773 compmask
|= (1 << j
);
3774 reg
= in
->regs
[0]->num
- j
;
3776 so
->inputs
[i
].ncomp
++;
3777 if ((so
->type
== MESA_SHADER_FRAGMENT
) && so
->inputs
[i
].bary
) {
3779 assert(in
->regs
[1]->flags
& IR3_REG_IMMED
);
3780 in
->regs
[1]->iim_val
= inloc
+ j
;
3785 if ((so
->type
== MESA_SHADER_FRAGMENT
) && compmask
&& so
->inputs
[i
].bary
) {
3787 so
->inputs
[i
].compmask
= (1 << maxcomp
) - 1;
3789 } else if (!so
->inputs
[i
].sysval
) {
3790 so
->inputs
[i
].compmask
= compmask
;
3792 so
->inputs
[i
].regid
= reg
;
3796 fixup_astc_srgb(ctx
);
3798 /* We need to do legalize after (for frag shader's) the "bary.f"
3799 * offsets (inloc) have been assigned.
3801 ir3_legalize(ir
, &so
->num_samp
, &so
->has_ssbo
, &max_bary
);
3803 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
3804 printf("AFTER LEGALIZE:\n");
3808 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3809 if (so
->type
== MESA_SHADER_VERTEX
)
3810 so
->total_in
= actual_in
;
3812 so
->total_in
= max_bary
+ 1;
3817 ir3_destroy(so
->ir
);