1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
36 #include "freedreno_util.h"
38 #include "ir3_compiler.h"
39 #include "ir3_shader.h"
42 #include "instr-a3xx.h"
47 struct ir3_compiler
*compiler
;
52 struct ir3_shader_variant
*so
;
54 struct ir3_block
*block
; /* the current block */
55 struct ir3_block
*in_block
; /* block created for shader inputs */
57 nir_function_impl
*impl
;
59 /* For fragment shaders, from the hw perspective the only
60 * actual input is r0.xy position register passed to bary.f.
61 * But TGSI doesn't know that, it still declares things as
62 * IN[] registers. So we do all the input tracking normally
63 * and fix things up after compile_instructions()
65 * NOTE that frag_pos is the hardware position (possibly it
66 * is actually an index or tag or some such.. it is *not*
67 * values that can be directly used for gl_FragCoord..)
69 struct ir3_instruction
*frag_pos
, *frag_face
, *frag_coord
[4];
71 /* For vertex shaders, keep track of the system values sources */
72 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
74 /* Compute shader inputs: */
75 struct ir3_instruction
*local_invocation_id
, *work_group_id
;
77 /* For SSBO's and atomics, we need to preserve order, such
78 * that reads don't overtake writes, and the order of writes
79 * is preserved. Atomics are considered as a write.
81 * To do this, we track last write and last access, in a
82 * similar way to ir3_array. But since we don't know whether
83 * the same SSBO is bound to multiple slots, so we simply
84 * track this globally rather than per-SSBO.
86 * TODO should we track this per block instead? I guess it
87 * shouldn't matter much?
89 struct ir3_instruction
*last_write
, *last_access
;
91 /* mapping from nir_register to defining instruction: */
92 struct hash_table
*def_ht
;
96 /* a common pattern for indirect addressing is to request the
97 * same address register multiple times. To avoid generating
98 * duplicate instruction sequences (which our backend does not
99 * try to clean up, since that should be done as the NIR stage)
100 * we cache the address value generated for a given src value:
102 * Note that we have to cache these per alignment, since same
103 * src used for an array of vec1 cannot be also used for an
106 struct hash_table
*addr_ht
[4];
108 /* last dst array, for indirect we need to insert a var-store.
110 struct ir3_instruction
**last_dst
;
113 /* maps nir_block to ir3_block, mostly for the purposes of
114 * figuring out the blocks successors
116 struct hash_table
*block_ht
;
118 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
119 * so we need to use ldlv.u32 to load the varying directly:
123 /* on a3xx, we need to add one to # of array levels:
127 /* on a3xx, we need to scale up integer coords for isaml based
130 bool unminify_coords
;
132 /* on a4xx, for array textures we need to add 0.5 to the array
135 bool array_index_add_half
;
137 /* on a4xx, bitmask of samplers which need astc+srgb workaround: */
140 unsigned max_texture_index
;
142 /* set if we encounter something we can't handle yet, so we
143 * can bail cleanly and fallback to TGSI compiler f/e
148 /* gpu pointer size in units of 32bit registers/slots */
149 static unsigned pointer_size(struct ir3_context
*ctx
)
151 return (ctx
->compiler
->gpu_id
>= 500) ? 2 : 1;
154 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
155 static struct ir3_block
* get_block(struct ir3_context
*ctx
, nir_block
*nblock
);
158 static struct ir3_context
*
159 compile_init(struct ir3_compiler
*compiler
,
160 struct ir3_shader_variant
*so
)
162 struct ir3_context
*ctx
= rzalloc(NULL
, struct ir3_context
);
164 if (compiler
->gpu_id
>= 400) {
165 /* need special handling for "flat" */
166 ctx
->flat_bypass
= true;
167 ctx
->levels_add_one
= false;
168 ctx
->unminify_coords
= false;
169 ctx
->array_index_add_half
= true;
171 if (so
->type
== SHADER_VERTEX
)
172 ctx
->astc_srgb
= so
->key
.vastc_srgb
;
173 else if (so
->type
== SHADER_FRAGMENT
)
174 ctx
->astc_srgb
= so
->key
.fastc_srgb
;
177 /* no special handling for "flat" */
178 ctx
->flat_bypass
= false;
179 ctx
->levels_add_one
= true;
180 ctx
->unminify_coords
= true;
181 ctx
->array_index_add_half
= false;
184 ctx
->compiler
= compiler
;
187 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
188 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
189 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
190 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
192 /* TODO: maybe generate some sort of bitmask of what key
193 * lowers vs what shader has (ie. no need to lower
194 * texture clamp lowering if no texture sample instrs)..
195 * although should be done further up the stack to avoid
196 * creating duplicate variants..
199 if (ir3_key_lowers_nir(&so
->key
)) {
200 nir_shader
*s
= nir_shader_clone(ctx
, so
->shader
->nir
);
201 ctx
->s
= ir3_optimize_nir(so
->shader
, s
, &so
->key
);
203 /* fast-path for shader key that lowers nothing in NIR: */
204 ctx
->s
= so
->shader
->nir
;
207 /* this needs to be the last pass run, so do this here instead of
208 * in ir3_optimize_nir():
210 NIR_PASS_V(ctx
->s
, nir_lower_locals_to_regs
);
212 if (fd_mesa_debug
& FD_DBG_DISASM
) {
213 DBG("dump nir%dv%d: type=%d, k={bp=%u,cts=%u,hp=%u}",
214 so
->shader
->id
, so
->id
, so
->type
,
215 so
->key
.binning_pass
, so
->key
.color_two_side
,
216 so
->key
.half_precision
);
217 nir_print_shader(ctx
->s
, stdout
);
220 ir3_nir_scan_driver_consts(ctx
->s
, &so
->const_layout
);
222 so
->num_uniforms
= ctx
->s
->num_uniforms
;
223 so
->num_ubos
= ctx
->s
->info
.num_ubos
;
225 /* Layout of constant registers, each section aligned to vec4. Note
226 * that pointer size (ubo, etc) changes depending on generation.
231 * if (vertex shader) {
232 * driver params (IR3_DP_*)
233 * if (stream_output.num_outputs > 0)
234 * stream-out addresses
238 * Immediates go last mostly because they are inserted in the CP pass
239 * after the nir -> ir3 frontend.
241 unsigned constoff
= align(ctx
->s
->num_uniforms
, 4);
242 unsigned ptrsz
= pointer_size(ctx
);
244 memset(&so
->constbase
, ~0, sizeof(so
->constbase
));
246 if (so
->num_ubos
> 0) {
247 so
->constbase
.ubo
= constoff
;
248 constoff
+= align(ctx
->s
->info
.num_ubos
* ptrsz
, 4) / 4;
251 if (so
->const_layout
.ssbo_size
.count
> 0) {
252 unsigned cnt
= so
->const_layout
.ssbo_size
.count
;
253 so
->constbase
.ssbo_sizes
= constoff
;
254 constoff
+= align(cnt
, 4) / 4;
257 unsigned num_driver_params
= 0;
258 if (so
->type
== SHADER_VERTEX
) {
259 num_driver_params
= IR3_DP_VS_COUNT
;
260 } else if (so
->type
== SHADER_COMPUTE
) {
261 num_driver_params
= IR3_DP_CS_COUNT
;
264 so
->constbase
.driver_param
= constoff
;
265 constoff
+= align(num_driver_params
, 4) / 4;
267 if ((so
->type
== SHADER_VERTEX
) &&
268 (compiler
->gpu_id
< 500) &&
269 so
->shader
->stream_output
.num_outputs
> 0) {
270 so
->constbase
.tfbo
= constoff
;
271 constoff
+= align(PIPE_MAX_SO_BUFFERS
* ptrsz
, 4) / 4;
274 so
->constbase
.immediate
= constoff
;
280 compile_error(struct ir3_context
*ctx
, const char *format
, ...)
283 va_start(ap
, format
);
284 _debug_vprintf(format
, ap
);
286 nir_print_shader(ctx
->s
, stdout
);
291 #define compile_assert(ctx, cond) do { \
292 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
296 compile_free(struct ir3_context
*ctx
)
302 declare_array(struct ir3_context
*ctx
, nir_register
*reg
)
304 struct ir3_array
*arr
= rzalloc(ctx
, struct ir3_array
);
305 arr
->id
= ++ctx
->num_arrays
;
306 /* NOTE: sometimes we get non array regs, for example for arrays of
307 * length 1. See fs-const-array-of-struct-of-array.shader_test. So
308 * treat a non-array as if it was an array of length 1.
310 * It would be nice if there was a nir pass to convert arrays of
313 arr
->length
= reg
->num_components
* MAX2(1, reg
->num_array_elems
);
314 compile_assert(ctx
, arr
->length
> 0);
316 list_addtail(&arr
->node
, &ctx
->ir
->array_list
);
319 static struct ir3_array
*
320 get_array(struct ir3_context
*ctx
, nir_register
*reg
)
322 list_for_each_entry (struct ir3_array
, arr
, &ctx
->ir
->array_list
, node
) {
326 compile_error(ctx
, "bogus reg: %s\n", reg
->name
);
330 /* relative (indirect) if address!=NULL */
331 static struct ir3_instruction
*
332 create_array_load(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
333 struct ir3_instruction
*address
)
335 struct ir3_block
*block
= ctx
->block
;
336 struct ir3_instruction
*mov
;
337 struct ir3_register
*src
;
339 mov
= ir3_instr_create(block
, OPC_MOV
);
340 mov
->cat1
.src_type
= TYPE_U32
;
341 mov
->cat1
.dst_type
= TYPE_U32
;
342 ir3_reg_create(mov
, 0, 0);
343 src
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
344 COND(address
, IR3_REG_RELATIV
));
345 src
->instr
= arr
->last_write
;
346 src
->size
= arr
->length
;
347 src
->array
.id
= arr
->id
;
348 src
->array
.offset
= n
;
351 ir3_instr_set_address(mov
, address
);
353 arr
->last_access
= mov
;
358 /* relative (indirect) if address!=NULL */
359 static struct ir3_instruction
*
360 create_array_store(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
361 struct ir3_instruction
*src
, struct ir3_instruction
*address
)
363 struct ir3_block
*block
= ctx
->block
;
364 struct ir3_instruction
*mov
;
365 struct ir3_register
*dst
;
367 mov
= ir3_instr_create(block
, OPC_MOV
);
368 mov
->cat1
.src_type
= TYPE_U32
;
369 mov
->cat1
.dst_type
= TYPE_U32
;
370 dst
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
371 COND(address
, IR3_REG_RELATIV
));
372 dst
->instr
= arr
->last_access
;
373 dst
->size
= arr
->length
;
374 dst
->array
.id
= arr
->id
;
375 dst
->array
.offset
= n
;
376 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
379 ir3_instr_set_address(mov
, address
);
381 arr
->last_write
= arr
->last_access
= mov
;
386 /* allocate a n element value array (to be populated by caller) and
389 static struct ir3_instruction
**
390 get_dst_ssa(struct ir3_context
*ctx
, nir_ssa_def
*dst
, unsigned n
)
392 struct ir3_instruction
**value
=
393 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
394 _mesa_hash_table_insert(ctx
->def_ht
, dst
, value
);
398 static struct ir3_instruction
**
399 get_dst(struct ir3_context
*ctx
, nir_dest
*dst
, unsigned n
)
401 struct ir3_instruction
**value
;
404 value
= get_dst_ssa(ctx
, &dst
->ssa
, n
);
406 value
= ralloc_array(ctx
, struct ir3_instruction
*, n
);
409 /* NOTE: in non-ssa case, we don't really need to store last_dst
410 * but this helps us catch cases where put_dst() call is forgotten
412 compile_assert(ctx
, !ctx
->last_dst
);
413 ctx
->last_dst
= value
;
419 static struct ir3_instruction
* get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
);
421 static struct ir3_instruction
* const *
422 get_src(struct ir3_context
*ctx
, nir_src
*src
)
425 struct hash_entry
*entry
;
426 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
427 compile_assert(ctx
, entry
);
430 nir_register
*reg
= src
->reg
.reg
;
431 struct ir3_array
*arr
= get_array(ctx
, reg
);
432 unsigned num_components
= arr
->r
->num_components
;
433 struct ir3_instruction
*addr
= NULL
;
434 struct ir3_instruction
**value
=
435 ralloc_array(ctx
, struct ir3_instruction
*, num_components
);
437 if (src
->reg
.indirect
)
438 addr
= get_addr(ctx
, get_src(ctx
, src
->reg
.indirect
)[0],
439 reg
->num_components
);
441 for (unsigned i
= 0; i
< num_components
; i
++) {
442 unsigned n
= src
->reg
.base_offset
* reg
->num_components
+ i
;
443 compile_assert(ctx
, n
< arr
->length
);
444 value
[i
] = create_array_load(ctx
, arr
, n
, addr
);
452 put_dst(struct ir3_context
*ctx
, nir_dest
*dst
)
455 nir_register
*reg
= dst
->reg
.reg
;
456 struct ir3_array
*arr
= get_array(ctx
, reg
);
457 unsigned num_components
= ctx
->last_dst_n
;
458 struct ir3_instruction
*addr
= NULL
;
460 if (dst
->reg
.indirect
)
461 addr
= get_addr(ctx
, get_src(ctx
, dst
->reg
.indirect
)[0],
462 reg
->num_components
);
464 for (unsigned i
= 0; i
< num_components
; i
++) {
465 unsigned n
= dst
->reg
.base_offset
* reg
->num_components
+ i
;
466 compile_assert(ctx
, n
< arr
->length
);
467 if (!ctx
->last_dst
[i
])
469 create_array_store(ctx
, arr
, n
, ctx
->last_dst
[i
], addr
);
472 ralloc_free(ctx
->last_dst
);
474 ctx
->last_dst
= NULL
;
478 static struct ir3_instruction
*
479 create_immed(struct ir3_block
*block
, uint32_t val
)
481 struct ir3_instruction
*mov
;
483 mov
= ir3_instr_create(block
, OPC_MOV
);
484 mov
->cat1
.src_type
= TYPE_U32
;
485 mov
->cat1
.dst_type
= TYPE_U32
;
486 ir3_reg_create(mov
, 0, 0);
487 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
492 static struct ir3_instruction
*
493 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
, int align
)
495 struct ir3_instruction
*instr
, *immed
;
497 /* TODO in at least some cases, the backend could probably be
498 * made clever enough to propagate IR3_REG_HALF..
500 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
501 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
508 /* src *= 2 => src <<= 1: */
509 immed
= create_immed(block
, 1);
510 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
512 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
513 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
514 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
518 immed
= create_immed(block
, 3);
519 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
521 instr
= ir3_MULL_U(block
, instr
, 0, immed
, 0);
522 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
523 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
526 /* src *= 4 => src <<= 2: */
527 immed
= create_immed(block
, 2);
528 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
530 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
531 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
532 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
535 unreachable("bad align");
539 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
540 instr
->regs
[0]->num
= regid(REG_A0
, 0);
541 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
542 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
547 /* caches addr values to avoid generating multiple cov/shl/mova
548 * sequences for each use of a given NIR level src as address
550 static struct ir3_instruction
*
551 get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
)
553 struct ir3_instruction
*addr
;
554 unsigned idx
= align
- 1;
556 compile_assert(ctx
, idx
< ARRAY_SIZE(ctx
->addr_ht
));
558 if (!ctx
->addr_ht
[idx
]) {
559 ctx
->addr_ht
[idx
] = _mesa_hash_table_create(ctx
,
560 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
562 struct hash_entry
*entry
;
563 entry
= _mesa_hash_table_search(ctx
->addr_ht
[idx
], src
);
568 addr
= create_addr(ctx
->block
, src
, align
);
569 _mesa_hash_table_insert(ctx
->addr_ht
[idx
], src
, addr
);
574 static struct ir3_instruction
*
575 get_predicate(struct ir3_context
*ctx
, struct ir3_instruction
*src
)
577 struct ir3_block
*b
= ctx
->block
;
578 struct ir3_instruction
*cond
;
580 /* NOTE: only cmps.*.* can write p0.x: */
581 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
582 cond
->cat2
.condition
= IR3_COND_NE
;
584 /* condition always goes in predicate register: */
585 cond
->regs
[0]->num
= regid(REG_P0
, 0);
590 static struct ir3_instruction
*
591 create_uniform(struct ir3_context
*ctx
, unsigned n
)
593 struct ir3_instruction
*mov
;
595 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
596 /* TODO get types right? */
597 mov
->cat1
.src_type
= TYPE_F32
;
598 mov
->cat1
.dst_type
= TYPE_F32
;
599 ir3_reg_create(mov
, 0, 0);
600 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
605 static struct ir3_instruction
*
606 create_uniform_indirect(struct ir3_context
*ctx
, int n
,
607 struct ir3_instruction
*address
)
609 struct ir3_instruction
*mov
;
611 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
612 mov
->cat1
.src_type
= TYPE_U32
;
613 mov
->cat1
.dst_type
= TYPE_U32
;
614 ir3_reg_create(mov
, 0, 0);
615 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
617 ir3_instr_set_address(mov
, address
);
622 static struct ir3_instruction
*
623 create_collect(struct ir3_block
*block
, struct ir3_instruction
*const *arr
,
626 struct ir3_instruction
*collect
;
631 collect
= ir3_instr_create2(block
, OPC_META_FI
, 1 + arrsz
);
632 ir3_reg_create(collect
, 0, 0); /* dst */
633 for (unsigned i
= 0; i
< arrsz
; i
++)
634 ir3_reg_create(collect
, 0, IR3_REG_SSA
)->instr
= arr
[i
];
639 static struct ir3_instruction
*
640 create_indirect_load(struct ir3_context
*ctx
, unsigned arrsz
, int n
,
641 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
643 struct ir3_block
*block
= ctx
->block
;
644 struct ir3_instruction
*mov
;
645 struct ir3_register
*src
;
647 mov
= ir3_instr_create(block
, OPC_MOV
);
648 mov
->cat1
.src_type
= TYPE_U32
;
649 mov
->cat1
.dst_type
= TYPE_U32
;
650 ir3_reg_create(mov
, 0, 0);
651 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
652 src
->instr
= collect
;
654 src
->array
.offset
= n
;
656 ir3_instr_set_address(mov
, address
);
661 static struct ir3_instruction
*
662 create_input_compmask(struct ir3_block
*block
, unsigned n
, unsigned compmask
)
664 struct ir3_instruction
*in
;
666 in
= ir3_instr_create(block
, OPC_META_INPUT
);
667 in
->inout
.block
= block
;
668 ir3_reg_create(in
, n
, 0);
670 in
->regs
[0]->wrmask
= compmask
;
675 static struct ir3_instruction
*
676 create_input(struct ir3_block
*block
, unsigned n
)
678 return create_input_compmask(block
, n
, 0x1);
681 static struct ir3_instruction
*
682 create_frag_input(struct ir3_context
*ctx
, bool use_ldlv
)
684 struct ir3_block
*block
= ctx
->block
;
685 struct ir3_instruction
*instr
;
686 /* actual inloc is assigned and fixed up later: */
687 struct ir3_instruction
*inloc
= create_immed(block
, 0);
690 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
691 instr
->cat6
.type
= TYPE_U32
;
692 instr
->cat6
.iim_val
= 1;
694 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_pos
, 0);
695 instr
->regs
[2]->wrmask
= 0x3;
701 static struct ir3_instruction
*
702 create_frag_coord(struct ir3_context
*ctx
, unsigned comp
)
704 struct ir3_block
*block
= ctx
->block
;
705 struct ir3_instruction
*instr
;
707 compile_assert(ctx
, !ctx
->frag_coord
[comp
]);
709 ctx
->frag_coord
[comp
] = create_input(ctx
->block
, 0);
714 /* for frag_coord, we get unsigned values.. we need
715 * to subtract (integer) 8 and divide by 16 (right-
716 * shift by 4) then convert to float:
720 * mov.u32f32 dst, tmp
723 instr
= ir3_SUB_S(block
, ctx
->frag_coord
[comp
], 0,
724 create_immed(block
, 8), 0);
725 instr
= ir3_SHR_B(block
, instr
, 0,
726 create_immed(block
, 4), 0);
727 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
733 /* seems that we can use these as-is: */
734 return ctx
->frag_coord
[comp
];
738 static struct ir3_instruction
*
739 create_driver_param(struct ir3_context
*ctx
, enum ir3_driver_param dp
)
741 /* first four vec4 sysval's reserved for UBOs: */
742 /* NOTE: dp is in scalar, but there can be >4 dp components: */
743 unsigned n
= ctx
->so
->constbase
.driver_param
;
744 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
745 return create_uniform(ctx
, r
);
748 /* helper for instructions that produce multiple consecutive scalar
749 * outputs which need to have a split/fanout meta instruction inserted
752 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
753 struct ir3_instruction
*src
, unsigned base
, unsigned n
)
755 struct ir3_instruction
*prev
= NULL
;
756 for (int i
= 0, j
= 0; i
< n
; i
++) {
757 struct ir3_instruction
*split
= ir3_instr_create(block
, OPC_META_FO
);
758 ir3_reg_create(split
, 0, IR3_REG_SSA
);
759 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
760 split
->fo
.off
= i
+ base
;
763 split
->cp
.left
= prev
;
764 split
->cp
.left_cnt
++;
765 prev
->cp
.right
= split
;
766 prev
->cp
.right_cnt
++;
770 if (src
->regs
[0]->wrmask
& (1 << (i
+ base
)))
776 * Adreno uses uint rather than having dedicated bool type,
777 * which (potentially) requires some conversion, in particular
778 * when using output of an bool instr to int input, or visa
782 * -------+---------+-------+-
786 * To convert from an adreno bool (uint) to nir, use:
788 * absneg.s dst, (neg)src
790 * To convert back in the other direction:
792 * absneg.s dst, (abs)arc
794 * The CP step can clean up the absneg.s that cancel each other
795 * out, and with a slight bit of extra cleverness (to recognize
796 * the instructions which produce either a 0 or 1) can eliminate
797 * the absneg.s's completely when an instruction that wants
798 * 0/1 consumes the result. For example, when a nir 'bcsel'
799 * consumes the result of 'feq'. So we should be able to get by
800 * without a boolean resolve step, and without incuring any
801 * extra penalty in instruction count.
804 /* NIR bool -> native (adreno): */
805 static struct ir3_instruction
*
806 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
808 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
811 /* native (adreno) -> NIR bool: */
812 static struct ir3_instruction
*
813 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
815 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
819 * alu/sfu instructions:
823 emit_alu(struct ir3_context
*ctx
, nir_alu_instr
*alu
)
825 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
826 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
827 struct ir3_block
*b
= ctx
->block
;
828 unsigned dst_sz
, wrmask
;
830 if (alu
->dest
.dest
.is_ssa
) {
831 dst_sz
= alu
->dest
.dest
.ssa
.num_components
;
832 wrmask
= (1 << dst_sz
) - 1;
834 dst_sz
= alu
->dest
.dest
.reg
.reg
->num_components
;
835 wrmask
= alu
->dest
.write_mask
;
838 dst
= get_dst(ctx
, &alu
->dest
.dest
, dst_sz
);
840 /* Vectors are special in that they have non-scalarized writemasks,
841 * and just take the first swizzle channel for each argument in
842 * order into each writemask channel.
844 if ((alu
->op
== nir_op_vec2
) ||
845 (alu
->op
== nir_op_vec3
) ||
846 (alu
->op
== nir_op_vec4
)) {
848 for (int i
= 0; i
< info
->num_inputs
; i
++) {
849 nir_alu_src
*asrc
= &alu
->src
[i
];
851 compile_assert(ctx
, !asrc
->abs
);
852 compile_assert(ctx
, !asrc
->negate
);
854 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
856 src
[i
] = create_immed(ctx
->block
, 0);
857 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
860 put_dst(ctx
, &alu
->dest
.dest
);
864 /* We also get mov's with more than one component for mov's so
865 * handle those specially:
867 if ((alu
->op
== nir_op_imov
) || (alu
->op
== nir_op_fmov
)) {
868 type_t type
= (alu
->op
== nir_op_imov
) ? TYPE_U32
: TYPE_F32
;
869 nir_alu_src
*asrc
= &alu
->src
[0];
870 struct ir3_instruction
*const *src0
= get_src(ctx
, &asrc
->src
);
872 for (unsigned i
= 0; i
< dst_sz
; i
++) {
873 if (wrmask
& (1 << i
)) {
874 dst
[i
] = ir3_MOV(b
, src0
[asrc
->swizzle
[i
]], type
);
880 put_dst(ctx
, &alu
->dest
.dest
);
884 compile_assert(ctx
, alu
->dest
.dest
.is_ssa
);
886 /* General case: We can just grab the one used channel per src. */
887 for (int i
= 0; i
< info
->num_inputs
; i
++) {
888 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
889 nir_alu_src
*asrc
= &alu
->src
[i
];
891 compile_assert(ctx
, !asrc
->abs
);
892 compile_assert(ctx
, !asrc
->negate
);
894 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
896 compile_assert(ctx
, src
[i
]);
901 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_S32
);
904 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_U32
);
907 dst
[0] = ir3_COV(b
, src
[0], TYPE_S32
, TYPE_F32
);
910 dst
[0] = ir3_COV(b
, src
[0], TYPE_U32
, TYPE_F32
);
913 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
914 dst
[0]->cat2
.condition
= IR3_COND_NE
;
915 dst
[0] = ir3_n2b(b
, dst
[0]);
918 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
921 dst
[0] = ir3_b2n(b
, src
[0]);
924 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
925 dst
[0]->cat2
.condition
= IR3_COND_NE
;
926 dst
[0] = ir3_n2b(b
, dst
[0]);
930 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
933 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
936 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
939 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
942 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
945 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
948 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
951 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
954 dst
[0] = ir3_DSX(b
, src
[0], 0);
955 dst
[0]->cat5
.type
= TYPE_F32
;
958 dst
[0] = ir3_DSY(b
, src
[0], 0);
959 dst
[0]->cat5
.type
= TYPE_F32
;
963 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
964 dst
[0]->cat2
.condition
= IR3_COND_LT
;
965 dst
[0] = ir3_n2b(b
, dst
[0]);
968 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
969 dst
[0]->cat2
.condition
= IR3_COND_GE
;
970 dst
[0] = ir3_n2b(b
, dst
[0]);
973 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
974 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
975 dst
[0] = ir3_n2b(b
, dst
[0]);
978 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
979 dst
[0]->cat2
.condition
= IR3_COND_NE
;
980 dst
[0] = ir3_n2b(b
, dst
[0]);
983 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
986 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
989 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
991 case nir_op_fround_even
:
992 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
995 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
999 dst
[0] = ir3_SIN(b
, src
[0], 0);
1002 dst
[0] = ir3_COS(b
, src
[0], 0);
1005 dst
[0] = ir3_RSQ(b
, src
[0], 0);
1008 dst
[0] = ir3_RCP(b
, src
[0], 0);
1011 dst
[0] = ir3_LOG2(b
, src
[0], 0);
1014 dst
[0] = ir3_EXP2(b
, src
[0], 0);
1017 dst
[0] = ir3_SQRT(b
, src
[0], 0);
1021 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
1024 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
1027 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
1030 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
1033 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
1036 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
1039 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
1043 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
1044 * mull.u tmp0, a, b ; mul low, i.e. al * bl
1045 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
1046 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
1048 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
1049 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
1050 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
1053 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
1056 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
1059 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
1062 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
1065 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
1067 case nir_op_isign
: {
1068 /* maybe this would be sane to lower in nir.. */
1069 struct ir3_instruction
*neg
, *pos
;
1071 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1072 neg
->cat2
.condition
= IR3_COND_LT
;
1074 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1075 pos
->cat2
.condition
= IR3_COND_GT
;
1077 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
1082 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
1085 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
1088 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
1091 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1092 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1093 dst
[0] = ir3_n2b(b
, dst
[0]);
1096 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1097 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1098 dst
[0] = ir3_n2b(b
, dst
[0]);
1101 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1102 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1103 dst
[0] = ir3_n2b(b
, dst
[0]);
1106 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1107 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1108 dst
[0] = ir3_n2b(b
, dst
[0]);
1111 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1112 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1113 dst
[0] = ir3_n2b(b
, dst
[0]);
1116 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1117 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1118 dst
[0] = ir3_n2b(b
, dst
[0]);
1122 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, ir3_b2n(b
, src
[0]), 0, src
[2], 0);
1125 case nir_op_bit_count
:
1126 dst
[0] = ir3_CBITS_B(b
, src
[0], 0);
1128 case nir_op_ifind_msb
: {
1129 struct ir3_instruction
*cmp
;
1130 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
1131 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
1132 cmp
->cat2
.condition
= IR3_COND_GE
;
1133 dst
[0] = ir3_SEL_B32(b
,
1134 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1138 case nir_op_ufind_msb
:
1139 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
1140 dst
[0] = ir3_SEL_B32(b
,
1141 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1142 src
[0], 0, dst
[0], 0);
1144 case nir_op_find_lsb
:
1145 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1146 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
1148 case nir_op_bitfield_reverse
:
1149 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1153 compile_error(ctx
, "Unhandled ALU op: %s\n",
1154 nir_op_infos
[alu
->op
].name
);
1158 put_dst(ctx
, &alu
->dest
.dest
);
1161 /* handles direct/indirect UBO reads: */
1163 emit_intrinsic_load_ubo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1164 struct ir3_instruction
**dst
)
1166 struct ir3_block
*b
= ctx
->block
;
1167 struct ir3_instruction
*base_lo
, *base_hi
, *addr
, *src0
, *src1
;
1168 nir_const_value
*const_offset
;
1169 /* UBO addresses are the first driver params: */
1170 unsigned ubo
= regid(ctx
->so
->constbase
.ubo
, 0);
1171 const unsigned ptrsz
= pointer_size(ctx
);
1175 /* First src is ubo index, which could either be an immed or not: */
1176 src0
= get_src(ctx
, &intr
->src
[0])[0];
1177 if (is_same_type_mov(src0
) &&
1178 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1179 base_lo
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
));
1180 base_hi
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
) + 1);
1182 base_lo
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
, 4));
1183 base_hi
= create_uniform_indirect(ctx
, ubo
+ 1, get_addr(ctx
, src0
, 4));
1186 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
1189 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1191 off
+= const_offset
->u32
[0];
1193 /* For load_ubo_indirect, second src is indirect offset: */
1194 src1
= get_src(ctx
, &intr
->src
[1])[0];
1196 /* and add offset to addr: */
1197 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1200 /* if offset is to large to encode in the ldg, split it out: */
1201 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1202 /* split out the minimal amount to improve the odds that
1203 * cp can fit the immediate in the add.s instruction:
1205 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1206 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1211 struct ir3_instruction
*carry
;
1213 /* handle 32b rollover, ie:
1214 * if (addr < base_lo)
1217 carry
= ir3_CMPS_U(b
, addr
, 0, base_lo
, 0);
1218 carry
->cat2
.condition
= IR3_COND_LT
;
1219 base_hi
= ir3_ADD_S(b
, base_hi
, 0, carry
, 0);
1221 addr
= create_collect(b
, (struct ir3_instruction
*[]){ addr
, base_hi
}, 2);
1224 for (int i
= 0; i
< intr
->num_components
; i
++) {
1225 struct ir3_instruction
*load
=
1226 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1227 load
->cat6
.type
= TYPE_U32
;
1228 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
1234 mark_ssbo_read(struct ir3_context
*ctx
, struct ir3_instruction
*instr
)
1236 instr
->regs
[0]->instr
= ctx
->last_write
;
1237 instr
->regs
[0]->flags
|= IR3_REG_SSA
;
1238 ctx
->last_access
= instr
;
1242 mark_ssbo_write(struct ir3_context
*ctx
, struct ir3_instruction
*instr
)
1244 instr
->regs
[0]->instr
= ctx
->last_access
;
1245 instr
->regs
[0]->flags
|= IR3_REG_SSA
;
1246 ctx
->last_write
= ctx
->last_access
= instr
;
1250 emit_intrinsic_load_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1251 struct ir3_instruction
**dst
)
1253 struct ir3_block
*b
= ctx
->block
;
1254 struct ir3_instruction
*ldgb
, *src0
, *src1
, *offset
;
1255 nir_const_value
*const_offset
;
1257 /* can this be non-const buffer_index? how do we handle that? */
1258 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1259 compile_assert(ctx
, const_offset
);
1261 offset
= get_src(ctx
, &intr
->src
[1])[0];
1263 /* src0 is uvec2(offset*4, 0), src1 is offset.. nir already *= 4: */
1264 src0
= create_collect(b
, (struct ir3_instruction
*[]){
1268 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1270 ldgb
= ir3_LDGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1272 ldgb
->regs
[0]->wrmask
= (1 << intr
->num_components
) - 1;
1273 ldgb
->cat6
.iim_val
= intr
->num_components
;
1274 ldgb
->cat6
.type
= TYPE_U32
;
1275 mark_ssbo_read(ctx
, ldgb
);
1277 split_dest(b
, dst
, ldgb
, 0, intr
->num_components
);
1280 /* src[] = { value, block_index, offset }. const_index[] = { write_mask } */
1282 emit_intrinsic_store_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1284 struct ir3_block
*b
= ctx
->block
;
1285 struct ir3_instruction
*stgb
, *src0
, *src1
, *src2
, *offset
;
1286 nir_const_value
*const_offset
;
1287 unsigned ncomp
= ffs(~intr
->const_index
[0]) - 1;
1289 /* can this be non-const buffer_index? how do we handle that? */
1290 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1291 compile_assert(ctx
, const_offset
);
1293 offset
= get_src(ctx
, &intr
->src
[2])[0];
1295 /* src0 is value, src1 is offset, src2 is uvec2(offset*4, 0)..
1298 src0
= create_collect(b
, get_src(ctx
, &intr
->src
[0]), ncomp
);
1299 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1300 src2
= create_collect(b
, (struct ir3_instruction
*[]){
1305 stgb
= ir3_STGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1306 src0
, 0, src1
, 0, src2
, 0);
1307 stgb
->cat6
.iim_val
= ncomp
;
1308 stgb
->cat6
.type
= TYPE_U32
;
1309 mark_ssbo_write(ctx
, stgb
);
1311 array_insert(b
, b
->keeps
, stgb
);
1314 /* src[] = { block_index } */
1316 emit_intrinsic_ssbo_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1317 struct ir3_instruction
**dst
)
1319 /* SSBO size stored as a const starting at ssbo_sizes: */
1320 unsigned blk_idx
= nir_src_as_const_value(intr
->src
[0])->u32
[0];
1321 unsigned idx
= regid(ctx
->so
->constbase
.ssbo_sizes
, 0) +
1322 ctx
->so
->const_layout
.ssbo_size
.off
[blk_idx
];
1324 debug_assert(ctx
->so
->const_layout
.ssbo_size
.mask
& (1 << blk_idx
));
1326 dst
[0] = create_uniform(ctx
, idx
);
1329 static struct ir3_instruction
*
1330 emit_intrinsic_atomic(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1332 struct ir3_block
*b
= ctx
->block
;
1333 struct ir3_instruction
*atomic
, *ssbo
, *src0
, *src1
, *src2
, *offset
;
1334 nir_const_value
*const_offset
;
1335 type_t type
= TYPE_U32
;
1337 /* can this be non-const buffer_index? how do we handle that? */
1338 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1339 compile_assert(ctx
, const_offset
);
1340 ssbo
= create_immed(b
, const_offset
->u32
[0]);
1342 offset
= get_src(ctx
, &intr
->src
[1])[0];
1344 /* src0 is data (or uvec2(data, compare)
1346 * src2 is uvec2(offset*4, 0)
1348 * Note that nir already multiplies the offset by four
1350 src0
= get_src(ctx
, &intr
->src
[2])[0];
1351 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1352 src2
= create_collect(b
, (struct ir3_instruction
*[]){
1357 switch (intr
->intrinsic
) {
1358 case nir_intrinsic_ssbo_atomic_add
:
1359 atomic
= ir3_ATOMIC_ADD(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1361 case nir_intrinsic_ssbo_atomic_imin
:
1362 atomic
= ir3_ATOMIC_MIN(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1365 case nir_intrinsic_ssbo_atomic_umin
:
1366 atomic
= ir3_ATOMIC_MIN(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1368 case nir_intrinsic_ssbo_atomic_imax
:
1369 atomic
= ir3_ATOMIC_MAX(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1372 case nir_intrinsic_ssbo_atomic_umax
:
1373 atomic
= ir3_ATOMIC_MAX(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1375 case nir_intrinsic_ssbo_atomic_and
:
1376 atomic
= ir3_ATOMIC_AND(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1378 case nir_intrinsic_ssbo_atomic_or
:
1379 atomic
= ir3_ATOMIC_OR(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1381 case nir_intrinsic_ssbo_atomic_xor
:
1382 atomic
= ir3_ATOMIC_XOR(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1384 case nir_intrinsic_ssbo_atomic_exchange
:
1385 atomic
= ir3_ATOMIC_XCHG(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1387 case nir_intrinsic_ssbo_atomic_comp_swap
:
1388 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
1389 src0
= create_collect(b
, (struct ir3_instruction
*[]){
1391 get_src(ctx
, &intr
->src
[3])[0],
1393 atomic
= ir3_ATOMIC_CMPXCHG(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1399 atomic
->cat6
.iim_val
= 1;
1400 atomic
->cat6
.type
= type
;
1401 mark_ssbo_write(ctx
, atomic
);
1403 /* even if nothing consume the result, we can't DCE the instruction: */
1404 array_insert(b
, b
->keeps
, atomic
);
1409 static void add_sysval_input_compmask(struct ir3_context
*ctx
,
1410 gl_system_value slot
, unsigned compmask
,
1411 struct ir3_instruction
*instr
)
1413 struct ir3_shader_variant
*so
= ctx
->so
;
1414 unsigned r
= regid(so
->inputs_count
, 0);
1415 unsigned n
= so
->inputs_count
++;
1417 so
->inputs
[n
].sysval
= true;
1418 so
->inputs
[n
].slot
= slot
;
1419 so
->inputs
[n
].compmask
= compmask
;
1420 so
->inputs
[n
].regid
= r
;
1421 so
->inputs
[n
].interpolate
= INTERP_MODE_FLAT
;
1424 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
1425 ctx
->ir
->inputs
[r
] = instr
;
1428 static void add_sysval_input(struct ir3_context
*ctx
, gl_system_value slot
,
1429 struct ir3_instruction
*instr
)
1431 add_sysval_input_compmask(ctx
, slot
, 0x1, instr
);
1435 emit_intrinsic(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1437 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1438 struct ir3_instruction
**dst
;
1439 struct ir3_instruction
* const *src
;
1440 struct ir3_block
*b
= ctx
->block
;
1441 nir_const_value
*const_offset
;
1444 if (info
->has_dest
) {
1446 if (info
->dest_components
)
1447 n
= info
->dest_components
;
1449 n
= intr
->num_components
;
1450 dst
= get_dst(ctx
, &intr
->dest
, n
);
1455 switch (intr
->intrinsic
) {
1456 case nir_intrinsic_load_uniform
:
1457 idx
= nir_intrinsic_base(intr
);
1458 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1460 idx
+= const_offset
->u32
[0];
1461 for (int i
= 0; i
< intr
->num_components
; i
++) {
1462 unsigned n
= idx
* 4 + i
;
1463 dst
[i
] = create_uniform(ctx
, n
);
1466 src
= get_src(ctx
, &intr
->src
[0]);
1467 for (int i
= 0; i
< intr
->num_components
; i
++) {
1468 int n
= idx
* 4 + i
;
1469 dst
[i
] = create_uniform_indirect(ctx
, n
,
1470 get_addr(ctx
, src
[0], 4));
1472 /* NOTE: if relative addressing is used, we set
1473 * constlen in the compiler (to worst-case value)
1474 * since we don't know in the assembler what the max
1475 * addr reg value can be:
1477 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
1480 case nir_intrinsic_load_ubo
:
1481 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1483 case nir_intrinsic_load_input
:
1484 idx
= nir_intrinsic_base(intr
);
1485 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1487 idx
+= const_offset
->u32
[0];
1488 for (int i
= 0; i
< intr
->num_components
; i
++) {
1489 unsigned n
= idx
* 4 + i
;
1490 dst
[i
] = ctx
->ir
->inputs
[n
];
1493 src
= get_src(ctx
, &intr
->src
[0]);
1494 struct ir3_instruction
*collect
=
1495 create_collect(b
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
1496 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0], 4);
1497 for (int i
= 0; i
< intr
->num_components
; i
++) {
1498 unsigned n
= idx
* 4 + i
;
1499 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
1504 case nir_intrinsic_load_ssbo
:
1505 emit_intrinsic_load_ssbo(ctx
, intr
, dst
);
1507 case nir_intrinsic_store_ssbo
:
1508 emit_intrinsic_store_ssbo(ctx
, intr
);
1510 case nir_intrinsic_get_buffer_size
:
1511 emit_intrinsic_ssbo_size(ctx
, intr
, dst
);
1513 case nir_intrinsic_ssbo_atomic_add
:
1514 case nir_intrinsic_ssbo_atomic_imin
:
1515 case nir_intrinsic_ssbo_atomic_umin
:
1516 case nir_intrinsic_ssbo_atomic_imax
:
1517 case nir_intrinsic_ssbo_atomic_umax
:
1518 case nir_intrinsic_ssbo_atomic_and
:
1519 case nir_intrinsic_ssbo_atomic_or
:
1520 case nir_intrinsic_ssbo_atomic_xor
:
1521 case nir_intrinsic_ssbo_atomic_exchange
:
1522 case nir_intrinsic_ssbo_atomic_comp_swap
:
1523 if (info
->has_dest
) {
1524 dst
[0] = emit_intrinsic_atomic(ctx
, intr
);
1526 emit_intrinsic_atomic(ctx
, intr
);
1529 case nir_intrinsic_store_output
:
1530 idx
= nir_intrinsic_base(intr
);
1531 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1532 compile_assert(ctx
, const_offset
!= NULL
);
1533 idx
+= const_offset
->u32
[0];
1535 src
= get_src(ctx
, &intr
->src
[0]);
1536 for (int i
= 0; i
< intr
->num_components
; i
++) {
1537 unsigned n
= idx
* 4 + i
;
1538 ctx
->ir
->outputs
[n
] = src
[i
];
1541 case nir_intrinsic_load_base_vertex
:
1542 if (!ctx
->basevertex
) {
1543 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
1544 add_sysval_input(ctx
, SYSTEM_VALUE_BASE_VERTEX
,
1547 dst
[0] = ctx
->basevertex
;
1549 case nir_intrinsic_load_vertex_id_zero_base
:
1550 case nir_intrinsic_load_vertex_id
:
1551 if (!ctx
->vertex_id
) {
1552 gl_system_value sv
= (intr
->intrinsic
== nir_intrinsic_load_vertex_id
) ?
1553 SYSTEM_VALUE_VERTEX_ID
: SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
;
1554 ctx
->vertex_id
= create_input(b
, 0);
1555 add_sysval_input(ctx
, sv
, ctx
->vertex_id
);
1557 dst
[0] = ctx
->vertex_id
;
1559 case nir_intrinsic_load_instance_id
:
1560 if (!ctx
->instance_id
) {
1561 ctx
->instance_id
= create_input(b
, 0);
1562 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
1565 dst
[0] = ctx
->instance_id
;
1567 case nir_intrinsic_load_user_clip_plane
:
1568 idx
= nir_intrinsic_ucp_id(intr
);
1569 for (int i
= 0; i
< intr
->num_components
; i
++) {
1570 unsigned n
= idx
* 4 + i
;
1571 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
1574 case nir_intrinsic_load_front_face
:
1575 if (!ctx
->frag_face
) {
1576 ctx
->so
->frag_face
= true;
1577 ctx
->frag_face
= create_input(b
, 0);
1578 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
1580 /* for fragface, we get -1 for back and 0 for front. However this is
1581 * the inverse of what nir expects (where ~0 is true).
1583 dst
[0] = ir3_COV(b
, ctx
->frag_face
, TYPE_S16
, TYPE_S32
);
1584 dst
[0] = ir3_NOT_B(b
, dst
[0], 0);
1586 case nir_intrinsic_load_local_invocation_id
:
1587 if (!ctx
->local_invocation_id
) {
1588 ctx
->local_invocation_id
= create_input_compmask(b
, 0, 0x7);
1589 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
,
1590 0x7, ctx
->local_invocation_id
);
1592 split_dest(b
, dst
, ctx
->local_invocation_id
, 0, 3);
1594 case nir_intrinsic_load_work_group_id
:
1595 if (!ctx
->work_group_id
) {
1596 ctx
->work_group_id
= create_input_compmask(b
, 0, 0x7);
1597 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_WORK_GROUP_ID
,
1598 0x7, ctx
->work_group_id
);
1599 ctx
->work_group_id
->regs
[0]->flags
|= IR3_REG_HIGH
;
1601 split_dest(b
, dst
, ctx
->work_group_id
, 0, 3);
1603 case nir_intrinsic_load_num_work_groups
:
1604 for (int i
= 0; i
< intr
->num_components
; i
++) {
1605 dst
[i
] = create_driver_param(ctx
, IR3_DP_NUM_WORK_GROUPS_X
+ i
);
1608 case nir_intrinsic_discard_if
:
1609 case nir_intrinsic_discard
: {
1610 struct ir3_instruction
*cond
, *kill
;
1612 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
1613 /* conditional discard: */
1614 src
= get_src(ctx
, &intr
->src
[0]);
1615 cond
= ir3_b2n(b
, src
[0]);
1617 /* unconditional discard: */
1618 cond
= create_immed(b
, 1);
1621 /* NOTE: only cmps.*.* can write p0.x: */
1622 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1623 cond
->cat2
.condition
= IR3_COND_NE
;
1625 /* condition always goes in predicate register: */
1626 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1628 kill
= ir3_KILL(b
, cond
, 0);
1629 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
1631 array_insert(b
, b
->keeps
, kill
);
1632 ctx
->so
->has_kill
= true;
1637 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
1638 nir_intrinsic_infos
[intr
->intrinsic
].name
);
1643 put_dst(ctx
, &intr
->dest
);
1647 emit_load_const(struct ir3_context
*ctx
, nir_load_const_instr
*instr
)
1649 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
1650 instr
->def
.num_components
);
1651 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1652 dst
[i
] = create_immed(ctx
->block
, instr
->value
.u32
[i
]);
1656 emit_undef(struct ir3_context
*ctx
, nir_ssa_undef_instr
*undef
)
1658 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
1659 undef
->def
.num_components
);
1660 /* backend doesn't want undefined instructions, so just plug
1663 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
1664 dst
[i
] = create_immed(ctx
->block
, fui(0.0));
1668 * texture fetch/sample instructions:
1672 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
1674 unsigned coords
, flags
= 0;
1676 /* note: would use tex->coord_components.. except txs.. also,
1677 * since array index goes after shadow ref, we don't want to
1680 switch (tex
->sampler_dim
) {
1681 case GLSL_SAMPLER_DIM_1D
:
1682 case GLSL_SAMPLER_DIM_BUF
:
1685 case GLSL_SAMPLER_DIM_2D
:
1686 case GLSL_SAMPLER_DIM_RECT
:
1687 case GLSL_SAMPLER_DIM_EXTERNAL
:
1688 case GLSL_SAMPLER_DIM_MS
:
1691 case GLSL_SAMPLER_DIM_3D
:
1692 case GLSL_SAMPLER_DIM_CUBE
:
1694 flags
|= IR3_INSTR_3D
;
1697 unreachable("bad sampler_dim");
1700 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1701 flags
|= IR3_INSTR_S
;
1703 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
1704 flags
|= IR3_INSTR_A
;
1711 emit_tex(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
1713 struct ir3_block
*b
= ctx
->block
;
1714 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
1715 struct ir3_instruction
* const *coord
, * const *off
, * const *ddx
, * const *ddy
;
1716 struct ir3_instruction
*lod
, *compare
, *proj
;
1717 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
1718 unsigned i
, coords
, flags
;
1719 unsigned nsrc0
= 0, nsrc1
= 0;
1723 coord
= off
= ddx
= ddy
= NULL
;
1724 lod
= proj
= compare
= NULL
;
1726 /* TODO: might just be one component for gathers? */
1727 dst
= get_dst(ctx
, &tex
->dest
, 4);
1729 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
1730 switch (tex
->src
[i
].src_type
) {
1731 case nir_tex_src_coord
:
1732 coord
= get_src(ctx
, &tex
->src
[i
].src
);
1734 case nir_tex_src_bias
:
1735 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1738 case nir_tex_src_lod
:
1739 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1742 case nir_tex_src_comparator
: /* shadow comparator */
1743 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1745 case nir_tex_src_projector
:
1746 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1749 case nir_tex_src_offset
:
1750 off
= get_src(ctx
, &tex
->src
[i
].src
);
1753 case nir_tex_src_ddx
:
1754 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
1756 case nir_tex_src_ddy
:
1757 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
1760 compile_error(ctx
, "Unhandled NIR tex src type: %d\n",
1761 tex
->src
[i
].src_type
);
1767 case nir_texop_tex
: opc
= OPC_SAM
; break;
1768 case nir_texop_txb
: opc
= OPC_SAMB
; break;
1769 case nir_texop_txl
: opc
= OPC_SAML
; break;
1770 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
1771 case nir_texop_txf
: opc
= OPC_ISAML
; break;
1772 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
1773 case nir_texop_txf_ms
:
1776 case nir_texop_query_levels
:
1777 case nir_texop_texture_samples
:
1778 case nir_texop_samples_identical
:
1779 case nir_texop_txf_ms_mcs
:
1780 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
1784 tex_info(tex
, &flags
, &coords
);
1787 * lay out the first argument in the proper order:
1788 * - actual coordinates first
1789 * - shadow reference
1792 * - starting at offset 4, dpdx.xy, dpdy.xy
1794 * bias/lod go into the second arg
1797 /* insert tex coords: */
1798 for (i
= 0; i
< coords
; i
++)
1803 /* scale up integer coords for TXF based on the LOD */
1804 if (ctx
->unminify_coords
&& (opc
== OPC_ISAML
)) {
1806 for (i
= 0; i
< coords
; i
++)
1807 src0
[i
] = ir3_SHL_B(b
, src0
[i
], 0, lod
, 0);
1811 /* hw doesn't do 1d, so we treat it as 2d with
1812 * height of 1, and patch up the y coord.
1813 * TODO: y coord should be (int)0 in some cases..
1815 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
1818 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1819 src0
[nsrc0
++] = compare
;
1821 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
) {
1822 struct ir3_instruction
*idx
= coord
[coords
];
1824 /* the array coord for cube arrays needs 0.5 added to it */
1825 if (ctx
->array_index_add_half
&& (opc
!= OPC_ISAML
))
1826 idx
= ir3_ADD_F(b
, idx
, 0, create_immed(b
, fui(0.5)), 0);
1828 src0
[nsrc0
++] = idx
;
1832 src0
[nsrc0
++] = proj
;
1833 flags
|= IR3_INSTR_P
;
1836 /* pad to 4, then ddx/ddy: */
1837 if (tex
->op
== nir_texop_txd
) {
1839 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1840 for (i
= 0; i
< coords
; i
++)
1841 src0
[nsrc0
++] = ddx
[i
];
1843 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1844 for (i
= 0; i
< coords
; i
++)
1845 src0
[nsrc0
++] = ddy
[i
];
1847 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1851 * second argument (if applicable):
1856 if (has_off
| has_lod
| has_bias
) {
1858 for (i
= 0; i
< coords
; i
++)
1859 src1
[nsrc1
++] = off
[i
];
1861 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
1862 flags
|= IR3_INSTR_O
;
1865 if (has_lod
| has_bias
)
1866 src1
[nsrc1
++] = lod
;
1869 switch (tex
->dest_type
) {
1870 case nir_type_invalid
:
1871 case nir_type_float
:
1882 unreachable("bad dest_type");
1885 if (opc
== OPC_GETLOD
)
1888 unsigned tex_idx
= tex
->texture_index
;
1890 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex_idx
);
1892 struct ir3_instruction
*col0
= create_collect(b
, src0
, nsrc0
);
1893 struct ir3_instruction
*col1
= create_collect(b
, src1
, nsrc1
);
1895 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
, flags
,
1896 tex_idx
, tex_idx
, col0
, col1
);
1898 if ((ctx
->astc_srgb
& (1 << tex_idx
)) && !nir_tex_instr_is_query(tex
)) {
1899 /* only need first 3 components: */
1900 sam
->regs
[0]->wrmask
= 0x7;
1901 split_dest(b
, dst
, sam
, 0, 3);
1903 /* we need to sample the alpha separately with a non-ASTC
1906 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_W
, flags
,
1907 tex_idx
, tex_idx
, col0
, col1
);
1909 array_insert(ctx
->ir
, ctx
->ir
->astc_srgb
, sam
);
1911 /* fixup .w component: */
1912 split_dest(b
, &dst
[3], sam
, 3, 1);
1914 /* normal (non-workaround) case: */
1915 split_dest(b
, dst
, sam
, 0, 4);
1918 /* GETLOD returns results in 4.8 fixed point */
1919 if (opc
== OPC_GETLOD
) {
1920 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
1922 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
1923 for (i
= 0; i
< 2; i
++) {
1924 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_U32
, TYPE_F32
), 0,
1929 put_dst(ctx
, &tex
->dest
);
1933 emit_tex_query_levels(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
1935 struct ir3_block
*b
= ctx
->block
;
1936 struct ir3_instruction
**dst
, *sam
;
1938 dst
= get_dst(ctx
, &tex
->dest
, 1);
1940 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
1941 tex
->texture_index
, tex
->texture_index
, NULL
, NULL
);
1943 /* even though there is only one component, since it ends
1944 * up in .z rather than .x, we need a split_dest()
1946 split_dest(b
, dst
, sam
, 0, 3);
1948 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1949 * the value in TEX_CONST_0 is zero-based.
1951 if (ctx
->levels_add_one
)
1952 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
1954 put_dst(ctx
, &tex
->dest
);
1958 emit_tex_txs(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
1960 struct ir3_block
*b
= ctx
->block
;
1961 struct ir3_instruction
**dst
, *sam
;
1962 struct ir3_instruction
*lod
;
1963 unsigned flags
, coords
;
1965 tex_info(tex
, &flags
, &coords
);
1967 /* Actually we want the number of dimensions, not coordinates. This
1968 * distinction only matters for cubes.
1970 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
1973 dst
= get_dst(ctx
, &tex
->dest
, 4);
1975 compile_assert(ctx
, tex
->num_srcs
== 1);
1976 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
1978 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
1980 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
1981 tex
->texture_index
, tex
->texture_index
, lod
, NULL
);
1983 split_dest(b
, dst
, sam
, 0, 4);
1985 /* Array size actually ends up in .w rather than .z. This doesn't
1986 * matter for miplevel 0, but for higher mips the value in z is
1987 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1988 * returned, which means that we have to add 1 to it for arrays.
1990 if (tex
->is_array
) {
1991 if (ctx
->levels_add_one
) {
1992 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
1994 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
1998 put_dst(ctx
, &tex
->dest
);
2002 emit_phi(struct ir3_context
*ctx
, nir_phi_instr
*nphi
)
2004 struct ir3_instruction
*phi
, **dst
;
2006 /* NOTE: phi's should be lowered to scalar at this point */
2007 compile_assert(ctx
, nphi
->dest
.ssa
.num_components
== 1);
2009 dst
= get_dst(ctx
, &nphi
->dest
, 1);
2011 phi
= ir3_instr_create2(ctx
->block
, OPC_META_PHI
,
2012 1 + exec_list_length(&nphi
->srcs
));
2013 ir3_reg_create(phi
, 0, 0); /* dst */
2014 phi
->phi
.nphi
= nphi
;
2018 put_dst(ctx
, &nphi
->dest
);
2021 /* phi instructions are left partially constructed. We don't resolve
2022 * their srcs until the end of the block, since (eg. loops) one of
2023 * the phi's srcs might be defined after the phi due to back edges in
2027 resolve_phis(struct ir3_context
*ctx
, struct ir3_block
*block
)
2029 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
2030 nir_phi_instr
*nphi
;
2032 /* phi's only come at start of block: */
2033 if (instr
->opc
!= OPC_META_PHI
)
2036 if (!instr
->phi
.nphi
)
2039 nphi
= instr
->phi
.nphi
;
2040 instr
->phi
.nphi
= NULL
;
2042 foreach_list_typed(nir_phi_src
, nsrc
, node
, &nphi
->srcs
) {
2043 struct ir3_instruction
*src
= get_src(ctx
, &nsrc
->src
)[0];
2045 /* NOTE: src might not be in the same block as it comes from
2046 * according to the phi.. but in the end the backend assumes
2047 * it will be able to assign the same register to each (which
2048 * only works if it is assigned in the src block), so insert
2049 * an extra mov to make sure the phi src is assigned in the
2050 * block it comes from:
2052 src
= ir3_MOV(get_block(ctx
, nsrc
->pred
), src
, TYPE_U32
);
2054 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
2060 emit_jump(struct ir3_context
*ctx
, nir_jump_instr
*jump
)
2062 switch (jump
->type
) {
2063 case nir_jump_break
:
2064 case nir_jump_continue
:
2065 /* I *think* we can simply just ignore this, and use the
2066 * successor block link to figure out where we need to
2067 * jump to for break/continue
2071 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
2077 emit_instr(struct ir3_context
*ctx
, nir_instr
*instr
)
2079 switch (instr
->type
) {
2080 case nir_instr_type_alu
:
2081 emit_alu(ctx
, nir_instr_as_alu(instr
));
2083 case nir_instr_type_intrinsic
:
2084 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2086 case nir_instr_type_load_const
:
2087 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2089 case nir_instr_type_ssa_undef
:
2090 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
2092 case nir_instr_type_tex
: {
2093 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
2094 /* couple tex instructions get special-cased:
2098 emit_tex_txs(ctx
, tex
);
2100 case nir_texop_query_levels
:
2101 emit_tex_query_levels(ctx
, tex
);
2109 case nir_instr_type_phi
:
2110 emit_phi(ctx
, nir_instr_as_phi(instr
));
2112 case nir_instr_type_jump
:
2113 emit_jump(ctx
, nir_instr_as_jump(instr
));
2115 case nir_instr_type_call
:
2116 case nir_instr_type_parallel_copy
:
2117 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
2122 static struct ir3_block
*
2123 get_block(struct ir3_context
*ctx
, nir_block
*nblock
)
2125 struct ir3_block
*block
;
2126 struct hash_entry
*entry
;
2127 entry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
2131 block
= ir3_block_create(ctx
->ir
);
2132 block
->nblock
= nblock
;
2133 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
2139 emit_block(struct ir3_context
*ctx
, nir_block
*nblock
)
2141 struct ir3_block
*block
= get_block(ctx
, nblock
);
2143 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
2144 if (nblock
->successors
[i
]) {
2145 block
->successors
[i
] =
2146 get_block(ctx
, nblock
->successors
[i
]);
2151 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
2153 /* re-emit addr register in each block if needed: */
2154 for (int i
= 0; i
< ARRAY_SIZE(ctx
->addr_ht
); i
++) {
2155 _mesa_hash_table_destroy(ctx
->addr_ht
[i
], NULL
);
2156 ctx
->addr_ht
[i
] = NULL
;
2159 nir_foreach_instr(instr
, nblock
) {
2160 emit_instr(ctx
, instr
);
2166 static void emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
);
2169 emit_if(struct ir3_context
*ctx
, nir_if
*nif
)
2171 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
2173 ctx
->block
->condition
=
2174 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
2176 emit_cf_list(ctx
, &nif
->then_list
);
2177 emit_cf_list(ctx
, &nif
->else_list
);
2181 emit_loop(struct ir3_context
*ctx
, nir_loop
*nloop
)
2183 emit_cf_list(ctx
, &nloop
->body
);
2187 emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
)
2189 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2190 switch (node
->type
) {
2191 case nir_cf_node_block
:
2192 emit_block(ctx
, nir_cf_node_as_block(node
));
2194 case nir_cf_node_if
:
2195 emit_if(ctx
, nir_cf_node_as_if(node
));
2197 case nir_cf_node_loop
:
2198 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2200 case nir_cf_node_function
:
2201 compile_error(ctx
, "TODO\n");
2207 /* emit stream-out code. At this point, the current block is the original
2208 * (nir) end block, and nir ensures that all flow control paths terminate
2209 * into the end block. We re-purpose the original end block to generate
2210 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2211 * block holding stream-out write instructions, followed by the new end
2215 * p0.x = (vtxcnt < maxvtxcnt)
2216 * // succs: blockStreamOut, blockNewEnd
2219 * ... stream-out instructions ...
2220 * // succs: blockNewEnd
2226 emit_stream_out(struct ir3_context
*ctx
)
2228 struct ir3_shader_variant
*v
= ctx
->so
;
2229 struct ir3
*ir
= ctx
->ir
;
2230 struct pipe_stream_output_info
*strmout
=
2231 &ctx
->so
->shader
->stream_output
;
2232 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
2233 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
2234 struct ir3_instruction
*bases
[PIPE_MAX_SO_BUFFERS
];
2236 /* create vtxcnt input in input block at top of shader,
2237 * so that it is seen as live over the entire duration
2240 vtxcnt
= create_input(ctx
->in_block
, 0);
2241 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
2243 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
2245 /* at this point, we are at the original 'end' block,
2246 * re-purpose this block to stream-out condition, then
2247 * append stream-out block and new-end block
2249 orig_end_block
= ctx
->block
;
2251 stream_out_block
= ir3_block_create(ir
);
2252 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
2254 new_end_block
= ir3_block_create(ir
);
2255 list_addtail(&new_end_block
->node
, &ir
->block_list
);
2257 orig_end_block
->successors
[0] = stream_out_block
;
2258 orig_end_block
->successors
[1] = new_end_block
;
2259 stream_out_block
->successors
[0] = new_end_block
;
2261 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2262 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
2263 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2264 cond
->cat2
.condition
= IR3_COND_LT
;
2266 /* condition goes on previous block to the conditional,
2267 * since it is used to pick which of the two successor
2270 orig_end_block
->condition
= cond
;
2272 /* switch to stream_out_block to generate the stream-out
2275 ctx
->block
= stream_out_block
;
2277 /* Calculate base addresses based on vtxcnt. Instructions
2278 * generated for bases not used in following loop will be
2279 * stripped out in the backend.
2281 for (unsigned i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
2282 unsigned stride
= strmout
->stride
[i
];
2283 struct ir3_instruction
*base
, *off
;
2285 base
= create_uniform(ctx
, regid(v
->constbase
.tfbo
, i
));
2287 /* 24-bit should be enough: */
2288 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
2289 create_immed(ctx
->block
, stride
* 4), 0);
2291 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
2294 /* Generate the per-output store instructions: */
2295 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
2296 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
2297 unsigned c
= j
+ strmout
->output
[i
].start_component
;
2298 struct ir3_instruction
*base
, *out
, *stg
;
2300 base
= bases
[strmout
->output
[i
].output_buffer
];
2301 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
2303 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
2304 create_immed(ctx
->block
, 1), 0);
2305 stg
->cat6
.type
= TYPE_U32
;
2306 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
2308 array_insert(ctx
->block
, ctx
->block
->keeps
, stg
);
2312 /* and finally switch to the new_end_block: */
2313 ctx
->block
= new_end_block
;
2317 emit_function(struct ir3_context
*ctx
, nir_function_impl
*impl
)
2319 nir_metadata_require(impl
, nir_metadata_block_index
);
2321 emit_cf_list(ctx
, &impl
->body
);
2322 emit_block(ctx
, impl
->end_block
);
2324 /* at this point, we should have a single empty block,
2325 * into which we emit the 'end' instruction.
2327 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
2329 /* If stream-out (aka transform-feedback) enabled, emit the
2330 * stream-out instructions, followed by a new empty block (into
2331 * which the 'end' instruction lands).
2333 * NOTE: it is done in this order, rather than inserting before
2334 * we emit end_block, because NIR guarantees that all blocks
2335 * flow into end_block, and that end_block has no successors.
2336 * So by re-purposing end_block as the first block of stream-
2337 * out, we guarantee that all exit paths flow into the stream-
2340 if ((ctx
->compiler
->gpu_id
< 500) &&
2341 (ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
2342 !ctx
->so
->key
.binning_pass
) {
2343 debug_assert(ctx
->so
->type
== SHADER_VERTEX
);
2344 emit_stream_out(ctx
);
2347 ir3_END(ctx
->block
);
2351 setup_input(struct ir3_context
*ctx
, nir_variable
*in
)
2353 struct ir3_shader_variant
*so
= ctx
->so
;
2354 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
2355 unsigned ncomp
= glsl_get_components(in
->type
);
2356 unsigned n
= in
->data
.driver_location
;
2357 unsigned slot
= in
->data
.location
;
2359 DBG("; in: slot=%u, len=%ux%u, drvloc=%u",
2360 slot
, array_len
, ncomp
, n
);
2362 /* let's pretend things other than vec4 don't exist: */
2363 ncomp
= MAX2(ncomp
, 4);
2364 compile_assert(ctx
, ncomp
== 4);
2366 so
->inputs
[n
].slot
= slot
;
2367 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
2368 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2369 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
2371 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2372 for (int i
= 0; i
< ncomp
; i
++) {
2373 struct ir3_instruction
*instr
= NULL
;
2374 unsigned idx
= (n
* 4) + i
;
2376 if (slot
== VARYING_SLOT_POS
) {
2377 so
->inputs
[n
].bary
= false;
2378 so
->frag_coord
= true;
2379 instr
= create_frag_coord(ctx
, i
);
2380 } else if (slot
== VARYING_SLOT_PNTC
) {
2381 /* see for example st_get_generic_varying_index().. this is
2382 * maybe a bit mesa/st specific. But we need things to line
2383 * up for this in fdN_program:
2384 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2385 * if (emit->sprite_coord_enable & texmask) {
2389 so
->inputs
[n
].slot
= VARYING_SLOT_VAR8
;
2390 so
->inputs
[n
].bary
= true;
2391 instr
= create_frag_input(ctx
, false);
2393 bool use_ldlv
= false;
2395 /* detect the special case for front/back colors where
2396 * we need to do flat vs smooth shading depending on
2399 if (in
->data
.interpolation
== INTERP_MODE_NONE
) {
2401 case VARYING_SLOT_COL0
:
2402 case VARYING_SLOT_COL1
:
2403 case VARYING_SLOT_BFC0
:
2404 case VARYING_SLOT_BFC1
:
2405 so
->inputs
[n
].rasterflat
= true;
2412 if (ctx
->flat_bypass
) {
2413 if ((so
->inputs
[n
].interpolate
== INTERP_MODE_FLAT
) ||
2414 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
2418 so
->inputs
[n
].bary
= true;
2420 instr
= create_frag_input(ctx
, use_ldlv
);
2423 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
2425 ctx
->ir
->inputs
[idx
] = instr
;
2427 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2428 for (int i
= 0; i
< ncomp
; i
++) {
2429 unsigned idx
= (n
* 4) + i
;
2430 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
2431 ctx
->ir
->inputs
[idx
] = create_input(ctx
->block
, idx
);
2434 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2437 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
2438 so
->total_in
+= ncomp
;
2443 setup_output(struct ir3_context
*ctx
, nir_variable
*out
)
2445 struct ir3_shader_variant
*so
= ctx
->so
;
2446 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
2447 unsigned ncomp
= glsl_get_components(out
->type
);
2448 unsigned n
= out
->data
.driver_location
;
2449 unsigned slot
= out
->data
.location
;
2452 DBG("; out: slot=%u, len=%ux%u, drvloc=%u",
2453 slot
, array_len
, ncomp
, n
);
2455 /* let's pretend things other than vec4 don't exist: */
2456 ncomp
= MAX2(ncomp
, 4);
2457 compile_assert(ctx
, ncomp
== 4);
2459 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2461 case FRAG_RESULT_DEPTH
:
2462 comp
= 2; /* tgsi will write to .z component */
2463 so
->writes_pos
= true;
2465 case FRAG_RESULT_COLOR
:
2469 if (slot
>= FRAG_RESULT_DATA0
)
2471 compile_error(ctx
, "unknown FS output name: %s\n",
2472 gl_frag_result_name(slot
));
2474 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2476 case VARYING_SLOT_POS
:
2477 so
->writes_pos
= true;
2479 case VARYING_SLOT_PSIZ
:
2480 so
->writes_psize
= true;
2482 case VARYING_SLOT_COL0
:
2483 case VARYING_SLOT_COL1
:
2484 case VARYING_SLOT_BFC0
:
2485 case VARYING_SLOT_BFC1
:
2486 case VARYING_SLOT_FOGC
:
2487 case VARYING_SLOT_CLIP_DIST0
:
2488 case VARYING_SLOT_CLIP_DIST1
:
2489 case VARYING_SLOT_CLIP_VERTEX
:
2492 if (slot
>= VARYING_SLOT_VAR0
)
2494 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
2496 compile_error(ctx
, "unknown VS output name: %s\n",
2497 gl_varying_slot_name(slot
));
2500 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2503 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
2505 so
->outputs
[n
].slot
= slot
;
2506 so
->outputs
[n
].regid
= regid(n
, comp
);
2507 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
2509 for (int i
= 0; i
< ncomp
; i
++) {
2510 unsigned idx
= (n
* 4) + i
;
2511 compile_assert(ctx
, idx
< ctx
->ir
->noutputs
);
2512 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
2517 max_drvloc(struct exec_list
*vars
)
2520 nir_foreach_variable(var
, vars
) {
2521 drvloc
= MAX2(drvloc
, (int)var
->data
.driver_location
);
2526 static const unsigned max_sysvals
[SHADER_MAX
] = {
2527 [SHADER_VERTEX
] = 16,
2528 [SHADER_COMPUTE
] = 16, // TODO how many do we actually need?
2532 emit_instructions(struct ir3_context
*ctx
)
2534 unsigned ninputs
, noutputs
;
2535 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
2537 ninputs
= (max_drvloc(&ctx
->s
->inputs
) + 1) * 4;
2538 noutputs
= (max_drvloc(&ctx
->s
->outputs
) + 1) * 4;
2540 /* we need to leave room for sysvals:
2542 ninputs
+= max_sysvals
[ctx
->so
->type
];
2544 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
2546 /* Create inputs in first block: */
2547 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
2548 ctx
->in_block
= ctx
->block
;
2549 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
2551 ninputs
-= max_sysvals
[ctx
->so
->type
];
2553 /* for fragment shader, we have a single input register (usually
2554 * r0.xy) which is used as the base for bary.f varying fetch instrs:
2556 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2557 // TODO maybe a helper for fi since we need it a few places..
2558 struct ir3_instruction
*instr
;
2559 instr
= ir3_instr_create(ctx
->block
, OPC_META_FI
);
2560 ir3_reg_create(instr
, 0, 0);
2561 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.x */
2562 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.y */
2563 ctx
->frag_pos
= instr
;
2567 nir_foreach_variable(var
, &ctx
->s
->inputs
) {
2568 setup_input(ctx
, var
);
2571 /* Setup outputs: */
2572 nir_foreach_variable(var
, &ctx
->s
->outputs
) {
2573 setup_output(ctx
, var
);
2576 /* Setup registers (which should only be arrays): */
2577 nir_foreach_register(reg
, &ctx
->s
->registers
) {
2578 declare_array(ctx
, reg
);
2581 /* NOTE: need to do something more clever when we support >1 fxn */
2582 nir_foreach_register(reg
, &fxn
->registers
) {
2583 declare_array(ctx
, reg
);
2585 /* And emit the body: */
2587 emit_function(ctx
, fxn
);
2589 list_for_each_entry (struct ir3_block
, block
, &ctx
->ir
->block_list
, node
) {
2590 resolve_phis(ctx
, block
);
2594 /* from NIR perspective, we actually have inputs. But most of the "inputs"
2595 * for a fragment shader are just bary.f instructions. The *actual* inputs
2596 * from the hw perspective are the frag_pos and optionally frag_coord and
2600 fixup_frag_inputs(struct ir3_context
*ctx
)
2602 struct ir3_shader_variant
*so
= ctx
->so
;
2603 struct ir3
*ir
= ctx
->ir
;
2604 struct ir3_instruction
**inputs
;
2605 struct ir3_instruction
*instr
;
2610 n
= 4; /* always have frag_pos */
2611 n
+= COND(so
->frag_face
, 4);
2612 n
+= COND(so
->frag_coord
, 4);
2614 inputs
= ir3_alloc(ctx
->ir
, n
* (sizeof(struct ir3_instruction
*)));
2616 if (so
->frag_face
) {
2617 /* this ultimately gets assigned to hr0.x so doesn't conflict
2618 * with frag_coord/frag_pos..
2620 inputs
[ir
->ninputs
++] = ctx
->frag_face
;
2621 ctx
->frag_face
->regs
[0]->num
= 0;
2623 /* remaining channels not used, but let's avoid confusing
2624 * other parts that expect inputs to come in groups of vec4
2626 inputs
[ir
->ninputs
++] = NULL
;
2627 inputs
[ir
->ninputs
++] = NULL
;
2628 inputs
[ir
->ninputs
++] = NULL
;
2631 /* since we don't know where to set the regid for frag_coord,
2632 * we have to use r0.x for it. But we don't want to *always*
2633 * use r1.x for frag_pos as that could increase the register
2634 * footprint on simple shaders:
2636 if (so
->frag_coord
) {
2637 ctx
->frag_coord
[0]->regs
[0]->num
= regid
++;
2638 ctx
->frag_coord
[1]->regs
[0]->num
= regid
++;
2639 ctx
->frag_coord
[2]->regs
[0]->num
= regid
++;
2640 ctx
->frag_coord
[3]->regs
[0]->num
= regid
++;
2642 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[0];
2643 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[1];
2644 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[2];
2645 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[3];
2648 /* we always have frag_pos: */
2649 so
->pos_regid
= regid
;
2652 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2653 instr
->regs
[0]->num
= regid
++;
2654 inputs
[ir
->ninputs
++] = instr
;
2655 ctx
->frag_pos
->regs
[1]->instr
= instr
;
2658 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2659 instr
->regs
[0]->num
= regid
++;
2660 inputs
[ir
->ninputs
++] = instr
;
2661 ctx
->frag_pos
->regs
[2]->instr
= instr
;
2663 ir
->inputs
= inputs
;
2666 /* Fixup tex sampler state for astc/srgb workaround instructions. We
2667 * need to assign the tex state indexes for these after we know the
2671 fixup_astc_srgb(struct ir3_context
*ctx
)
2673 struct ir3_shader_variant
*so
= ctx
->so
;
2674 /* indexed by original tex idx, value is newly assigned alpha sampler
2675 * state tex idx. Zero is invalid since there is at least one sampler
2678 unsigned alt_tex_state
[16] = {0};
2679 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
2682 so
->astc_srgb
.base
= tex_idx
;
2684 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
2685 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
2687 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
2689 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
2690 /* assign new alternate/alpha tex state slot: */
2691 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
2692 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
2693 so
->astc_srgb
.count
++;
2696 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
2701 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
2702 struct ir3_shader_variant
*so
)
2704 struct ir3_context
*ctx
;
2706 struct ir3_instruction
**inputs
;
2707 unsigned i
, j
, actual_in
, inloc
;
2708 int ret
= 0, max_bary
;
2712 ctx
= compile_init(compiler
, so
);
2714 DBG("INIT failed!");
2719 emit_instructions(ctx
);
2722 DBG("EMIT failed!");
2727 ir
= so
->ir
= ctx
->ir
;
2729 /* keep track of the inputs from TGSI perspective.. */
2730 inputs
= ir
->inputs
;
2732 /* but fixup actual inputs for frag shader: */
2733 if (so
->type
== SHADER_FRAGMENT
)
2734 fixup_frag_inputs(ctx
);
2736 /* at this point, for binning pass, throw away unneeded outputs: */
2737 if (so
->key
.binning_pass
) {
2738 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
2739 unsigned slot
= so
->outputs
[i
].slot
;
2741 /* throw away everything but first position/psize */
2742 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
2744 so
->outputs
[j
] = so
->outputs
[i
];
2745 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
2746 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
2747 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
2748 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
2753 so
->outputs_count
= j
;
2754 ir
->noutputs
= j
* 4;
2757 /* if we want half-precision outputs, mark the output registers
2760 if (so
->key
.half_precision
) {
2761 for (i
= 0; i
< ir
->noutputs
; i
++) {
2762 struct ir3_instruction
*out
= ir
->outputs
[i
];
2767 /* if frag shader writes z, that needs to be full precision: */
2768 if (so
->outputs
[i
/4].slot
== FRAG_RESULT_DEPTH
)
2771 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2772 /* output could be a fanout (ie. texture fetch output)
2773 * in which case we need to propagate the half-reg flag
2774 * up to the definer so that RA sees it:
2776 if (out
->opc
== OPC_META_FO
) {
2777 out
= out
->regs
[1]->instr
;
2778 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2781 if (out
->opc
== OPC_MOV
) {
2782 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
2787 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2788 printf("BEFORE CP:\n");
2794 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2795 printf("BEFORE GROUPING:\n");
2799 /* Group left/right neighbors, inserting mov's where needed to
2806 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2807 printf("AFTER DEPTH:\n");
2811 ret
= ir3_sched(ir
);
2813 DBG("SCHED failed!");
2817 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2818 printf("AFTER SCHED:\n");
2822 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
2828 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2829 printf("AFTER RA:\n");
2833 /* fixup input/outputs: */
2834 for (i
= 0; i
< so
->outputs_count
; i
++) {
2835 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
2838 /* Note that some or all channels of an input may be unused: */
2841 for (i
= 0; i
< so
->inputs_count
; i
++) {
2842 unsigned j
, regid
= ~0, compmask
= 0, maxcomp
= 0;
2843 so
->inputs
[i
].ncomp
= 0;
2844 so
->inputs
[i
].inloc
= inloc
;
2845 for (j
= 0; j
< 4; j
++) {
2846 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
2847 if (in
&& !(in
->flags
& IR3_INSTR_UNUSED
)) {
2848 compmask
|= (1 << j
);
2849 regid
= in
->regs
[0]->num
- j
;
2851 so
->inputs
[i
].ncomp
++;
2852 if ((so
->type
== SHADER_FRAGMENT
) && so
->inputs
[i
].bary
) {
2854 assert(in
->regs
[1]->flags
& IR3_REG_IMMED
);
2855 in
->regs
[1]->iim_val
= inloc
+ j
;
2860 if ((so
->type
== SHADER_FRAGMENT
) && compmask
&& so
->inputs
[i
].bary
) {
2862 so
->inputs
[i
].compmask
= (1 << maxcomp
) - 1;
2865 so
->inputs
[i
].compmask
= compmask
;
2867 so
->inputs
[i
].regid
= regid
;
2871 fixup_astc_srgb(ctx
);
2873 /* We need to do legalize after (for frag shader's) the "bary.f"
2874 * offsets (inloc) have been assigned.
2876 ir3_legalize(ir
, &so
->has_samp
, &so
->has_ssbo
, &max_bary
);
2878 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2879 printf("AFTER LEGALIZE:\n");
2883 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
2884 if (so
->type
== SHADER_VERTEX
)
2885 so
->total_in
= actual_in
;
2887 so
->total_in
= max_bary
+ 1;
2892 ir3_destroy(so
->ir
);