1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
36 #include "freedreno_util.h"
38 #include "ir3_compiler.h"
39 #include "ir3_shader.h"
42 #include "instr-a3xx.h"
47 struct ir3_compiler
*compiler
;
52 struct ir3_shader_variant
*so
;
54 struct ir3_block
*block
; /* the current block */
55 struct ir3_block
*in_block
; /* block created for shader inputs */
57 nir_function_impl
*impl
;
59 /* For fragment shaders, from the hw perspective the only
60 * actual input is r0.xy position register passed to bary.f.
61 * But TGSI doesn't know that, it still declares things as
62 * IN[] registers. So we do all the input tracking normally
63 * and fix things up after compile_instructions()
65 * NOTE that frag_pos is the hardware position (possibly it
66 * is actually an index or tag or some such.. it is *not*
67 * values that can be directly used for gl_FragCoord..)
69 struct ir3_instruction
*frag_pos
, *frag_face
, *frag_coord
[4];
71 /* For vertex shaders, keep track of the system values sources */
72 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
74 /* For fragment shaders: */
75 struct ir3_instruction
*samp_id
, *samp_mask_in
;
77 /* Compute shader inputs: */
78 struct ir3_instruction
*local_invocation_id
, *work_group_id
;
80 /* mapping from nir_register to defining instruction: */
81 struct hash_table
*def_ht
;
85 /* a common pattern for indirect addressing is to request the
86 * same address register multiple times. To avoid generating
87 * duplicate instruction sequences (which our backend does not
88 * try to clean up, since that should be done as the NIR stage)
89 * we cache the address value generated for a given src value:
91 * Note that we have to cache these per alignment, since same
92 * src used for an array of vec1 cannot be also used for an
95 struct hash_table
*addr_ht
[4];
97 /* last dst array, for indirect we need to insert a var-store.
99 struct ir3_instruction
**last_dst
;
102 /* maps nir_block to ir3_block, mostly for the purposes of
103 * figuring out the blocks successors
105 struct hash_table
*block_ht
;
107 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
108 * so we need to use ldlv.u32 to load the varying directly:
112 /* on a3xx, we need to add one to # of array levels:
116 /* on a3xx, we need to scale up integer coords for isaml based
119 bool unminify_coords
;
121 /* on a3xx do txf_ms w/ isaml and scaled coords: */
122 bool txf_ms_with_isaml
;
124 /* on a4xx, for array textures we need to add 0.5 to the array
127 bool array_index_add_half
;
129 /* on a4xx, bitmask of samplers which need astc+srgb workaround: */
132 unsigned samples
; /* bitmask of x,y sample shifts */
134 unsigned max_texture_index
;
136 /* set if we encounter something we can't handle yet, so we
137 * can bail cleanly and fallback to TGSI compiler f/e
142 /* gpu pointer size in units of 32bit registers/slots */
143 static unsigned pointer_size(struct ir3_context
*ctx
)
145 return (ctx
->compiler
->gpu_id
>= 500) ? 2 : 1;
148 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
149 static struct ir3_block
* get_block(struct ir3_context
*ctx
, const nir_block
*nblock
);
152 static struct ir3_context
*
153 compile_init(struct ir3_compiler
*compiler
,
154 struct ir3_shader_variant
*so
)
156 struct ir3_context
*ctx
= rzalloc(NULL
, struct ir3_context
);
158 if (compiler
->gpu_id
>= 400) {
159 /* need special handling for "flat" */
160 ctx
->flat_bypass
= true;
161 ctx
->levels_add_one
= false;
162 ctx
->unminify_coords
= false;
163 ctx
->txf_ms_with_isaml
= false;
164 ctx
->array_index_add_half
= true;
166 if (so
->type
== SHADER_VERTEX
) {
167 ctx
->astc_srgb
= so
->key
.vastc_srgb
;
168 } else if (so
->type
== SHADER_FRAGMENT
) {
169 ctx
->astc_srgb
= so
->key
.fastc_srgb
;
173 /* no special handling for "flat" */
174 ctx
->flat_bypass
= false;
175 ctx
->levels_add_one
= true;
176 ctx
->unminify_coords
= true;
177 ctx
->txf_ms_with_isaml
= true;
178 ctx
->array_index_add_half
= false;
180 if (so
->type
== SHADER_VERTEX
) {
181 ctx
->samples
= so
->key
.vsamples
;
182 } else if (so
->type
== SHADER_FRAGMENT
) {
183 ctx
->samples
= so
->key
.fsamples
;
187 ctx
->compiler
= compiler
;
189 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
190 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
191 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
192 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
194 /* TODO: maybe generate some sort of bitmask of what key
195 * lowers vs what shader has (ie. no need to lower
196 * texture clamp lowering if no texture sample instrs)..
197 * although should be done further up the stack to avoid
198 * creating duplicate variants..
201 if (ir3_key_lowers_nir(&so
->key
)) {
202 nir_shader
*s
= nir_shader_clone(ctx
, so
->shader
->nir
);
203 ctx
->s
= ir3_optimize_nir(so
->shader
, s
, &so
->key
);
205 /* fast-path for shader key that lowers nothing in NIR: */
206 ctx
->s
= so
->shader
->nir
;
209 NIR_PASS_V(ctx
->s
, nir_lower_deref_instrs
, ~0);
211 /* this needs to be the last pass run, so do this here instead of
212 * in ir3_optimize_nir():
214 NIR_PASS_V(ctx
->s
, nir_lower_locals_to_regs
);
215 NIR_PASS_V(ctx
->s
, nir_convert_from_ssa
, true);
217 if (fd_mesa_debug
& FD_DBG_DISASM
) {
218 DBG("dump nir%dv%d: type=%d, k={bp=%u,cts=%u,hp=%u}",
219 so
->shader
->id
, so
->id
, so
->type
,
220 so
->key
.binning_pass
, so
->key
.color_two_side
,
221 so
->key
.half_precision
);
222 nir_print_shader(ctx
->s
, stdout
);
225 ir3_nir_scan_driver_consts(ctx
->s
, &so
->const_layout
);
227 so
->num_uniforms
= ctx
->s
->num_uniforms
;
228 so
->num_ubos
= ctx
->s
->info
.num_ubos
;
230 /* Layout of constant registers, each section aligned to vec4. Note
231 * that pointer size (ubo, etc) changes depending on generation.
236 * if (vertex shader) {
237 * driver params (IR3_DP_*)
238 * if (stream_output.num_outputs > 0)
239 * stream-out addresses
243 * Immediates go last mostly because they are inserted in the CP pass
244 * after the nir -> ir3 frontend.
246 unsigned constoff
= align(ctx
->s
->num_uniforms
, 4);
247 unsigned ptrsz
= pointer_size(ctx
);
249 memset(&so
->constbase
, ~0, sizeof(so
->constbase
));
251 if (so
->num_ubos
> 0) {
252 so
->constbase
.ubo
= constoff
;
253 constoff
+= align(ctx
->s
->info
.num_ubos
* ptrsz
, 4) / 4;
256 if (so
->const_layout
.ssbo_size
.count
> 0) {
257 unsigned cnt
= so
->const_layout
.ssbo_size
.count
;
258 so
->constbase
.ssbo_sizes
= constoff
;
259 constoff
+= align(cnt
, 4) / 4;
262 if (so
->const_layout
.image_dims
.count
> 0) {
263 unsigned cnt
= so
->const_layout
.image_dims
.count
;
264 so
->constbase
.image_dims
= constoff
;
265 constoff
+= align(cnt
, 4) / 4;
268 unsigned num_driver_params
= 0;
269 if (so
->type
== SHADER_VERTEX
) {
270 num_driver_params
= IR3_DP_VS_COUNT
;
271 } else if (so
->type
== SHADER_COMPUTE
) {
272 num_driver_params
= IR3_DP_CS_COUNT
;
275 so
->constbase
.driver_param
= constoff
;
276 constoff
+= align(num_driver_params
, 4) / 4;
278 if ((so
->type
== SHADER_VERTEX
) &&
279 (compiler
->gpu_id
< 500) &&
280 so
->shader
->stream_output
.num_outputs
> 0) {
281 so
->constbase
.tfbo
= constoff
;
282 constoff
+= align(PIPE_MAX_SO_BUFFERS
* ptrsz
, 4) / 4;
285 so
->constbase
.immediate
= constoff
;
291 compile_error(struct ir3_context
*ctx
, const char *format
, ...)
294 va_start(ap
, format
);
295 _debug_vprintf(format
, ap
);
297 nir_print_shader(ctx
->s
, stdout
);
302 #define compile_assert(ctx, cond) do { \
303 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
307 compile_free(struct ir3_context
*ctx
)
313 declare_array(struct ir3_context
*ctx
, nir_register
*reg
)
315 struct ir3_array
*arr
= rzalloc(ctx
, struct ir3_array
);
316 arr
->id
= ++ctx
->num_arrays
;
317 /* NOTE: sometimes we get non array regs, for example for arrays of
318 * length 1. See fs-const-array-of-struct-of-array.shader_test. So
319 * treat a non-array as if it was an array of length 1.
321 * It would be nice if there was a nir pass to convert arrays of
324 arr
->length
= reg
->num_components
* MAX2(1, reg
->num_array_elems
);
325 compile_assert(ctx
, arr
->length
> 0);
327 list_addtail(&arr
->node
, &ctx
->ir
->array_list
);
330 static struct ir3_array
*
331 get_array(struct ir3_context
*ctx
, nir_register
*reg
)
333 list_for_each_entry (struct ir3_array
, arr
, &ctx
->ir
->array_list
, node
) {
337 compile_error(ctx
, "bogus reg: %s\n", reg
->name
);
341 /* relative (indirect) if address!=NULL */
342 static struct ir3_instruction
*
343 create_array_load(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
344 struct ir3_instruction
*address
)
346 struct ir3_block
*block
= ctx
->block
;
347 struct ir3_instruction
*mov
;
348 struct ir3_register
*src
;
350 mov
= ir3_instr_create(block
, OPC_MOV
);
351 mov
->cat1
.src_type
= TYPE_U32
;
352 mov
->cat1
.dst_type
= TYPE_U32
;
353 mov
->barrier_class
= IR3_BARRIER_ARRAY_R
;
354 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_W
;
355 ir3_reg_create(mov
, 0, 0);
356 src
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
357 COND(address
, IR3_REG_RELATIV
));
358 src
->instr
= arr
->last_write
;
359 src
->size
= arr
->length
;
360 src
->array
.id
= arr
->id
;
361 src
->array
.offset
= n
;
364 ir3_instr_set_address(mov
, address
);
369 /* relative (indirect) if address!=NULL */
371 create_array_store(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
372 struct ir3_instruction
*src
, struct ir3_instruction
*address
)
374 struct ir3_block
*block
= ctx
->block
;
375 struct ir3_instruction
*mov
;
376 struct ir3_register
*dst
;
378 /* if not relative store, don't create an extra mov, since that
379 * ends up being difficult for cp to remove.
384 src
->barrier_class
|= IR3_BARRIER_ARRAY_W
;
385 src
->barrier_conflict
|= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
387 dst
->flags
|= IR3_REG_ARRAY
;
388 dst
->instr
= arr
->last_write
;
389 dst
->size
= arr
->length
;
390 dst
->array
.id
= arr
->id
;
391 dst
->array
.offset
= n
;
393 arr
->last_write
= src
;
395 array_insert(block
, block
->keeps
, src
);
400 mov
= ir3_instr_create(block
, OPC_MOV
);
401 mov
->cat1
.src_type
= TYPE_U32
;
402 mov
->cat1
.dst_type
= TYPE_U32
;
403 mov
->barrier_class
= IR3_BARRIER_ARRAY_W
;
404 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
405 dst
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
406 COND(address
, IR3_REG_RELATIV
));
407 dst
->instr
= arr
->last_write
;
408 dst
->size
= arr
->length
;
409 dst
->array
.id
= arr
->id
;
410 dst
->array
.offset
= n
;
411 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
414 ir3_instr_set_address(mov
, address
);
416 arr
->last_write
= mov
;
418 /* the array store may only matter to something in an earlier
419 * block (ie. loops), but since arrays are not in SSA, depth
420 * pass won't know this.. so keep all array stores:
422 array_insert(block
, block
->keeps
, mov
);
425 static inline type_t
utype_for_size(unsigned bit_size
)
428 case 32: return TYPE_U32
;
429 case 16: return TYPE_U16
;
430 case 8: return TYPE_U8
;
431 default: unreachable("bad bitsize"); return ~0;
435 static inline type_t
utype_src(nir_src src
)
436 { return utype_for_size(nir_src_bit_size(src
)); }
438 static inline type_t
utype_dst(nir_dest dst
)
439 { return utype_for_size(nir_dest_bit_size(dst
)); }
441 /* allocate a n element value array (to be populated by caller) and
444 static struct ir3_instruction
**
445 get_dst_ssa(struct ir3_context
*ctx
, nir_ssa_def
*dst
, unsigned n
)
447 struct ir3_instruction
**value
=
448 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
449 _mesa_hash_table_insert(ctx
->def_ht
, dst
, value
);
453 static struct ir3_instruction
**
454 get_dst(struct ir3_context
*ctx
, nir_dest
*dst
, unsigned n
)
456 struct ir3_instruction
**value
;
459 value
= get_dst_ssa(ctx
, &dst
->ssa
, n
);
461 value
= ralloc_array(ctx
, struct ir3_instruction
*, n
);
464 /* NOTE: in non-ssa case, we don't really need to store last_dst
465 * but this helps us catch cases where put_dst() call is forgotten
467 compile_assert(ctx
, !ctx
->last_dst
);
468 ctx
->last_dst
= value
;
474 static struct ir3_instruction
* get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
);
476 static struct ir3_instruction
* const *
477 get_src(struct ir3_context
*ctx
, nir_src
*src
)
480 struct hash_entry
*entry
;
481 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
482 compile_assert(ctx
, entry
);
485 nir_register
*reg
= src
->reg
.reg
;
486 struct ir3_array
*arr
= get_array(ctx
, reg
);
487 unsigned num_components
= arr
->r
->num_components
;
488 struct ir3_instruction
*addr
= NULL
;
489 struct ir3_instruction
**value
=
490 ralloc_array(ctx
, struct ir3_instruction
*, num_components
);
492 if (src
->reg
.indirect
)
493 addr
= get_addr(ctx
, get_src(ctx
, src
->reg
.indirect
)[0],
494 reg
->num_components
);
496 for (unsigned i
= 0; i
< num_components
; i
++) {
497 unsigned n
= src
->reg
.base_offset
* reg
->num_components
+ i
;
498 compile_assert(ctx
, n
< arr
->length
);
499 value
[i
] = create_array_load(ctx
, arr
, n
, addr
);
507 put_dst(struct ir3_context
*ctx
, nir_dest
*dst
)
509 unsigned bit_size
= nir_dest_bit_size(*dst
);
512 for (unsigned i
= 0; i
< ctx
->last_dst_n
; i
++) {
513 struct ir3_instruction
*dst
= ctx
->last_dst
[i
];
514 dst
->regs
[0]->flags
|= IR3_REG_HALF
;
515 if (ctx
->last_dst
[i
]->opc
== OPC_META_FO
)
516 dst
->regs
[1]->instr
->regs
[0]->flags
|= IR3_REG_HALF
;
521 nir_register
*reg
= dst
->reg
.reg
;
522 struct ir3_array
*arr
= get_array(ctx
, reg
);
523 unsigned num_components
= ctx
->last_dst_n
;
524 struct ir3_instruction
*addr
= NULL
;
526 if (dst
->reg
.indirect
)
527 addr
= get_addr(ctx
, get_src(ctx
, dst
->reg
.indirect
)[0],
528 reg
->num_components
);
530 for (unsigned i
= 0; i
< num_components
; i
++) {
531 unsigned n
= dst
->reg
.base_offset
* reg
->num_components
+ i
;
532 compile_assert(ctx
, n
< arr
->length
);
533 if (!ctx
->last_dst
[i
])
535 create_array_store(ctx
, arr
, n
, ctx
->last_dst
[i
], addr
);
538 ralloc_free(ctx
->last_dst
);
540 ctx
->last_dst
= NULL
;
544 static struct ir3_instruction
*
545 create_immed_typed(struct ir3_block
*block
, uint32_t val
, type_t type
)
547 struct ir3_instruction
*mov
;
548 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
550 mov
= ir3_instr_create(block
, OPC_MOV
);
551 mov
->cat1
.src_type
= type
;
552 mov
->cat1
.dst_type
= type
;
553 ir3_reg_create(mov
, 0, flags
);
554 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
559 static struct ir3_instruction
*
560 create_immed(struct ir3_block
*block
, uint32_t val
)
562 return create_immed_typed(block
, val
, TYPE_U32
);
565 static struct ir3_instruction
*
566 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
, int align
)
568 struct ir3_instruction
*instr
, *immed
;
570 /* TODO in at least some cases, the backend could probably be
571 * made clever enough to propagate IR3_REG_HALF..
573 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
574 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
581 /* src *= 2 => src <<= 1: */
582 immed
= create_immed(block
, 1);
583 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
585 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
586 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
587 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
591 immed
= create_immed(block
, 3);
592 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
594 instr
= ir3_MULL_U(block
, instr
, 0, immed
, 0);
595 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
596 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
599 /* src *= 4 => src <<= 2: */
600 immed
= create_immed(block
, 2);
601 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
603 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
604 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
605 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
608 unreachable("bad align");
612 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
613 instr
->regs
[0]->num
= regid(REG_A0
, 0);
614 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
615 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
620 /* caches addr values to avoid generating multiple cov/shl/mova
621 * sequences for each use of a given NIR level src as address
623 static struct ir3_instruction
*
624 get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
)
626 struct ir3_instruction
*addr
;
627 unsigned idx
= align
- 1;
629 compile_assert(ctx
, idx
< ARRAY_SIZE(ctx
->addr_ht
));
631 if (!ctx
->addr_ht
[idx
]) {
632 ctx
->addr_ht
[idx
] = _mesa_hash_table_create(ctx
,
633 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
635 struct hash_entry
*entry
;
636 entry
= _mesa_hash_table_search(ctx
->addr_ht
[idx
], src
);
641 addr
= create_addr(ctx
->block
, src
, align
);
642 _mesa_hash_table_insert(ctx
->addr_ht
[idx
], src
, addr
);
647 static struct ir3_instruction
*
648 get_predicate(struct ir3_context
*ctx
, struct ir3_instruction
*src
)
650 struct ir3_block
*b
= ctx
->block
;
651 struct ir3_instruction
*cond
;
653 /* NOTE: only cmps.*.* can write p0.x: */
654 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
655 cond
->cat2
.condition
= IR3_COND_NE
;
657 /* condition always goes in predicate register: */
658 cond
->regs
[0]->num
= regid(REG_P0
, 0);
663 static struct ir3_instruction
*
664 create_uniform(struct ir3_context
*ctx
, unsigned n
)
666 struct ir3_instruction
*mov
;
668 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
669 /* TODO get types right? */
670 mov
->cat1
.src_type
= TYPE_F32
;
671 mov
->cat1
.dst_type
= TYPE_F32
;
672 ir3_reg_create(mov
, 0, 0);
673 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
678 static struct ir3_instruction
*
679 create_uniform_indirect(struct ir3_context
*ctx
, int n
,
680 struct ir3_instruction
*address
)
682 struct ir3_instruction
*mov
;
684 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
685 mov
->cat1
.src_type
= TYPE_U32
;
686 mov
->cat1
.dst_type
= TYPE_U32
;
687 ir3_reg_create(mov
, 0, 0);
688 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
690 ir3_instr_set_address(mov
, address
);
695 static struct ir3_instruction
*
696 create_collect(struct ir3_context
*ctx
, struct ir3_instruction
*const *arr
,
699 struct ir3_block
*block
= ctx
->block
;
700 struct ir3_instruction
*collect
;
705 unsigned flags
= arr
[0]->regs
[0]->flags
& IR3_REG_HALF
;
707 collect
= ir3_instr_create2(block
, OPC_META_FI
, 1 + arrsz
);
708 ir3_reg_create(collect
, 0, flags
); /* dst */
709 for (unsigned i
= 0; i
< arrsz
; i
++) {
710 struct ir3_instruction
*elem
= arr
[i
];
712 /* Since arrays are pre-colored in RA, we can't assume that
713 * things will end up in the right place. (Ie. if a collect
714 * joins elements from two different arrays.) So insert an
717 * We could possibly skip this if all the collected elements
718 * are contiguous elements in a single array.. not sure how
719 * likely that is to happen.
721 * Fixes a problem with glamor shaders, that in effect do
728 * color = texture2D(tex, texcoord);
730 * In this case, texcoord will end up as nir registers (which
731 * translate to ir3 array's of length 1. And we can't assume
732 * the two (or more) arrays will get allocated in consecutive
736 if (elem
->regs
[0]->flags
& IR3_REG_ARRAY
) {
737 type_t type
= (flags
& IR3_REG_HALF
) ? TYPE_U16
: TYPE_U32
;
738 elem
= ir3_MOV(block
, elem
, type
);
741 compile_assert(ctx
, (elem
->regs
[0]->flags
& IR3_REG_HALF
) == flags
);
742 ir3_reg_create(collect
, 0, IR3_REG_SSA
| flags
)->instr
= elem
;
748 static struct ir3_instruction
*
749 create_indirect_load(struct ir3_context
*ctx
, unsigned arrsz
, int n
,
750 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
752 struct ir3_block
*block
= ctx
->block
;
753 struct ir3_instruction
*mov
;
754 struct ir3_register
*src
;
756 mov
= ir3_instr_create(block
, OPC_MOV
);
757 mov
->cat1
.src_type
= TYPE_U32
;
758 mov
->cat1
.dst_type
= TYPE_U32
;
759 ir3_reg_create(mov
, 0, 0);
760 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
761 src
->instr
= collect
;
763 src
->array
.offset
= n
;
765 ir3_instr_set_address(mov
, address
);
770 static struct ir3_instruction
*
771 create_input_compmask(struct ir3_block
*block
, unsigned n
, unsigned compmask
)
773 struct ir3_instruction
*in
;
775 in
= ir3_instr_create(block
, OPC_META_INPUT
);
776 in
->inout
.block
= block
;
777 ir3_reg_create(in
, n
, 0);
779 in
->regs
[0]->wrmask
= compmask
;
784 static struct ir3_instruction
*
785 create_input(struct ir3_block
*block
, unsigned n
)
787 return create_input_compmask(block
, n
, 0x1);
790 static struct ir3_instruction
*
791 create_frag_input(struct ir3_context
*ctx
, bool use_ldlv
)
793 struct ir3_block
*block
= ctx
->block
;
794 struct ir3_instruction
*instr
;
795 /* actual inloc is assigned and fixed up later: */
796 struct ir3_instruction
*inloc
= create_immed(block
, 0);
799 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
800 instr
->cat6
.type
= TYPE_U32
;
801 instr
->cat6
.iim_val
= 1;
803 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_pos
, 0);
804 instr
->regs
[2]->wrmask
= 0x3;
810 static struct ir3_instruction
*
811 create_frag_coord(struct ir3_context
*ctx
, unsigned comp
)
813 struct ir3_block
*block
= ctx
->block
;
814 struct ir3_instruction
*instr
;
816 compile_assert(ctx
, !ctx
->frag_coord
[comp
]);
818 ctx
->frag_coord
[comp
] = create_input(ctx
->block
, 0);
823 /* for frag_coord, we get unsigned values.. we need
824 * to subtract (integer) 8 and divide by 16 (right-
825 * shift by 4) then convert to float:
829 * mov.u32f32 dst, tmp
832 instr
= ir3_SUB_S(block
, ctx
->frag_coord
[comp
], 0,
833 create_immed(block
, 8), 0);
834 instr
= ir3_SHR_B(block
, instr
, 0,
835 create_immed(block
, 4), 0);
836 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
842 /* seems that we can use these as-is: */
843 return ctx
->frag_coord
[comp
];
847 static struct ir3_instruction
*
848 create_driver_param(struct ir3_context
*ctx
, enum ir3_driver_param dp
)
850 /* first four vec4 sysval's reserved for UBOs: */
851 /* NOTE: dp is in scalar, but there can be >4 dp components: */
852 unsigned n
= ctx
->so
->constbase
.driver_param
;
853 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
854 return create_uniform(ctx
, r
);
857 /* helper for instructions that produce multiple consecutive scalar
858 * outputs which need to have a split/fanout meta instruction inserted
861 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
862 struct ir3_instruction
*src
, unsigned base
, unsigned n
)
864 struct ir3_instruction
*prev
= NULL
;
866 if ((n
== 1) && (src
->regs
[0]->wrmask
== 0x1)) {
871 for (int i
= 0, j
= 0; i
< n
; i
++) {
872 struct ir3_instruction
*split
= ir3_instr_create(block
, OPC_META_FO
);
873 ir3_reg_create(split
, 0, IR3_REG_SSA
);
874 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
875 split
->fo
.off
= i
+ base
;
878 split
->cp
.left
= prev
;
879 split
->cp
.left_cnt
++;
880 prev
->cp
.right
= split
;
881 prev
->cp
.right_cnt
++;
885 if (src
->regs
[0]->wrmask
& (1 << (i
+ base
)))
891 * Adreno uses uint rather than having dedicated bool type,
892 * which (potentially) requires some conversion, in particular
893 * when using output of an bool instr to int input, or visa
897 * -------+---------+-------+-
901 * To convert from an adreno bool (uint) to nir, use:
903 * absneg.s dst, (neg)src
905 * To convert back in the other direction:
907 * absneg.s dst, (abs)arc
909 * The CP step can clean up the absneg.s that cancel each other
910 * out, and with a slight bit of extra cleverness (to recognize
911 * the instructions which produce either a 0 or 1) can eliminate
912 * the absneg.s's completely when an instruction that wants
913 * 0/1 consumes the result. For example, when a nir 'bcsel'
914 * consumes the result of 'feq'. So we should be able to get by
915 * without a boolean resolve step, and without incuring any
916 * extra penalty in instruction count.
919 /* NIR bool -> native (adreno): */
920 static struct ir3_instruction
*
921 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
923 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
926 /* native (adreno) -> NIR bool: */
927 static struct ir3_instruction
*
928 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
930 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
934 * alu/sfu instructions:
937 static struct ir3_instruction
*
938 create_cov(struct ir3_context
*ctx
, struct ir3_instruction
*src
,
939 unsigned src_bitsize
, nir_op op
)
941 type_t src_type
, dst_type
;
945 case nir_op_f2f16_rtne
:
946 case nir_op_f2f16_rtz
:
947 case nir_op_f2f16_undef
:
954 switch (src_bitsize
) {
962 compile_error(ctx
, "invalid src bit size: %u", src_bitsize
);
971 switch (src_bitsize
) {
982 compile_error(ctx
, "invalid src bit size: %u", src_bitsize
);
991 switch (src_bitsize
) {
1002 compile_error(ctx
, "invalid src bit size: %u", src_bitsize
);
1007 compile_error(ctx
, "invalid conversion op: %u", op
);
1014 dst_type
= TYPE_F32
;
1017 case nir_op_f2f16_rtne
:
1018 case nir_op_f2f16_rtz
:
1019 case nir_op_f2f16_undef
:
1020 /* TODO how to handle rounding mode? */
1023 dst_type
= TYPE_F16
;
1028 dst_type
= TYPE_S32
;
1033 dst_type
= TYPE_S16
;
1043 dst_type
= TYPE_U32
;
1048 dst_type
= TYPE_U16
;
1057 compile_error(ctx
, "invalid conversion op: %u", op
);
1060 return ir3_COV(ctx
->block
, src
, src_type
, dst_type
);
1064 emit_alu(struct ir3_context
*ctx
, nir_alu_instr
*alu
)
1066 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
1067 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
1068 unsigned bs
[info
->num_inputs
]; /* bit size */
1069 struct ir3_block
*b
= ctx
->block
;
1070 unsigned dst_sz
, wrmask
;
1072 if (alu
->dest
.dest
.is_ssa
) {
1073 dst_sz
= alu
->dest
.dest
.ssa
.num_components
;
1074 wrmask
= (1 << dst_sz
) - 1;
1076 dst_sz
= alu
->dest
.dest
.reg
.reg
->num_components
;
1077 wrmask
= alu
->dest
.write_mask
;
1080 dst
= get_dst(ctx
, &alu
->dest
.dest
, dst_sz
);
1082 /* Vectors are special in that they have non-scalarized writemasks,
1083 * and just take the first swizzle channel for each argument in
1084 * order into each writemask channel.
1086 if ((alu
->op
== nir_op_vec2
) ||
1087 (alu
->op
== nir_op_vec3
) ||
1088 (alu
->op
== nir_op_vec4
)) {
1090 for (int i
= 0; i
< info
->num_inputs
; i
++) {
1091 nir_alu_src
*asrc
= &alu
->src
[i
];
1093 compile_assert(ctx
, !asrc
->abs
);
1094 compile_assert(ctx
, !asrc
->negate
);
1096 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
1098 src
[i
] = create_immed(ctx
->block
, 0);
1099 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
1102 put_dst(ctx
, &alu
->dest
.dest
);
1106 /* We also get mov's with more than one component for mov's so
1107 * handle those specially:
1109 if ((alu
->op
== nir_op_imov
) || (alu
->op
== nir_op_fmov
)) {
1110 type_t type
= (alu
->op
== nir_op_imov
) ? TYPE_U32
: TYPE_F32
;
1111 nir_alu_src
*asrc
= &alu
->src
[0];
1112 struct ir3_instruction
*const *src0
= get_src(ctx
, &asrc
->src
);
1114 for (unsigned i
= 0; i
< dst_sz
; i
++) {
1115 if (wrmask
& (1 << i
)) {
1116 dst
[i
] = ir3_MOV(b
, src0
[asrc
->swizzle
[i
]], type
);
1122 put_dst(ctx
, &alu
->dest
.dest
);
1126 /* General case: We can just grab the one used channel per src. */
1127 for (int i
= 0; i
< info
->num_inputs
; i
++) {
1128 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
1129 nir_alu_src
*asrc
= &alu
->src
[i
];
1131 compile_assert(ctx
, !asrc
->abs
);
1132 compile_assert(ctx
, !asrc
->negate
);
1134 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
1135 bs
[i
] = nir_src_bit_size(asrc
->src
);
1137 compile_assert(ctx
, src
[i
]);
1142 case nir_op_f2f16_rtne
:
1143 case nir_op_f2f16_rtz
:
1144 case nir_op_f2f16_undef
:
1161 dst
[0] = create_cov(ctx
, src
[0], bs
[0], alu
->op
);
1164 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
1165 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1166 dst
[0] = ir3_n2b(b
, dst
[0]);
1169 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
1172 dst
[0] = ir3_b2n(b
, src
[0]);
1175 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1176 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1177 dst
[0] = ir3_n2b(b
, dst
[0]);
1181 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
1184 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
1187 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
1190 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
1193 /* if there is just a single use of the src, and it supports
1194 * (sat) bit, we can just fold the (sat) flag back to the
1195 * src instruction and create a mov. This is easier for cp
1198 * TODO probably opc_cat==4 is ok too
1200 if (alu
->src
[0].src
.is_ssa
&&
1201 (list_length(&alu
->src
[0].src
.ssa
->uses
) == 1) &&
1202 ((opc_cat(src
[0]->opc
) == 2) || (opc_cat(src
[0]->opc
) == 3))) {
1203 src
[0]->flags
|= IR3_INSTR_SAT
;
1204 dst
[0] = ir3_MOV(b
, src
[0], TYPE_U32
);
1206 /* otherwise generate a max.f that saturates.. blob does
1207 * similar (generating a cat2 mov using max.f)
1209 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[0], 0);
1210 dst
[0]->flags
|= IR3_INSTR_SAT
;
1214 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
1217 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
1220 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
1223 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
1226 dst
[0] = ir3_DSX(b
, src
[0], 0);
1227 dst
[0]->cat5
.type
= TYPE_F32
;
1230 dst
[0] = ir3_DSY(b
, src
[0], 0);
1231 dst
[0]->cat5
.type
= TYPE_F32
;
1235 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1236 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1237 dst
[0] = ir3_n2b(b
, dst
[0]);
1240 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1241 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1242 dst
[0] = ir3_n2b(b
, dst
[0]);
1245 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1246 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1247 dst
[0] = ir3_n2b(b
, dst
[0]);
1250 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1251 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1252 dst
[0] = ir3_n2b(b
, dst
[0]);
1255 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
1258 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
1261 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
1263 case nir_op_fround_even
:
1264 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
1267 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
1271 dst
[0] = ir3_SIN(b
, src
[0], 0);
1274 dst
[0] = ir3_COS(b
, src
[0], 0);
1277 dst
[0] = ir3_RSQ(b
, src
[0], 0);
1280 dst
[0] = ir3_RCP(b
, src
[0], 0);
1283 dst
[0] = ir3_LOG2(b
, src
[0], 0);
1286 dst
[0] = ir3_EXP2(b
, src
[0], 0);
1289 dst
[0] = ir3_SQRT(b
, src
[0], 0);
1293 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
1296 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
1299 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
1302 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
1305 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
1308 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
1311 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
1315 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
1316 * mull.u tmp0, a, b ; mul low, i.e. al * bl
1317 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
1318 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
1320 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
1321 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
1322 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
1325 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
1328 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
1331 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
1334 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
1337 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
1339 case nir_op_isign
: {
1340 /* maybe this would be sane to lower in nir.. */
1341 struct ir3_instruction
*neg
, *pos
;
1343 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1344 neg
->cat2
.condition
= IR3_COND_LT
;
1346 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1347 pos
->cat2
.condition
= IR3_COND_GT
;
1349 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
1354 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
1357 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
1360 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
1363 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1364 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1365 dst
[0] = ir3_n2b(b
, dst
[0]);
1368 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1369 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1370 dst
[0] = ir3_n2b(b
, dst
[0]);
1373 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1374 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1375 dst
[0] = ir3_n2b(b
, dst
[0]);
1378 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1379 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1380 dst
[0] = ir3_n2b(b
, dst
[0]);
1383 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1384 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1385 dst
[0] = ir3_n2b(b
, dst
[0]);
1388 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1389 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1390 dst
[0] = ir3_n2b(b
, dst
[0]);
1393 case nir_op_bcsel
: {
1394 struct ir3_instruction
*cond
= ir3_b2n(b
, src
[0]);
1395 compile_assert(ctx
, bs
[1] == bs
[2]);
1396 /* the boolean condition is 32b even if src[1] and src[2] are
1397 * half-precision, but sel.b16 wants all three src's to be the
1401 cond
= ir3_COV(b
, cond
, TYPE_U32
, TYPE_U16
);
1402 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, cond
, 0, src
[2], 0);
1405 case nir_op_bit_count
:
1406 dst
[0] = ir3_CBITS_B(b
, src
[0], 0);
1408 case nir_op_ifind_msb
: {
1409 struct ir3_instruction
*cmp
;
1410 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
1411 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
1412 cmp
->cat2
.condition
= IR3_COND_GE
;
1413 dst
[0] = ir3_SEL_B32(b
,
1414 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1418 case nir_op_ufind_msb
:
1419 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
1420 dst
[0] = ir3_SEL_B32(b
,
1421 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1422 src
[0], 0, dst
[0], 0);
1424 case nir_op_find_lsb
:
1425 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1426 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
1428 case nir_op_bitfield_reverse
:
1429 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1433 compile_error(ctx
, "Unhandled ALU op: %s\n",
1434 nir_op_infos
[alu
->op
].name
);
1438 put_dst(ctx
, &alu
->dest
.dest
);
1441 /* handles direct/indirect UBO reads: */
1443 emit_intrinsic_load_ubo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1444 struct ir3_instruction
**dst
)
1446 struct ir3_block
*b
= ctx
->block
;
1447 struct ir3_instruction
*base_lo
, *base_hi
, *addr
, *src0
, *src1
;
1448 nir_const_value
*const_offset
;
1449 /* UBO addresses are the first driver params: */
1450 unsigned ubo
= regid(ctx
->so
->constbase
.ubo
, 0);
1451 const unsigned ptrsz
= pointer_size(ctx
);
1455 /* First src is ubo index, which could either be an immed or not: */
1456 src0
= get_src(ctx
, &intr
->src
[0])[0];
1457 if (is_same_type_mov(src0
) &&
1458 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1459 base_lo
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
));
1460 base_hi
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
) + 1);
1462 base_lo
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
, 4));
1463 base_hi
= create_uniform_indirect(ctx
, ubo
+ 1, get_addr(ctx
, src0
, 4));
1466 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
1469 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1471 off
+= const_offset
->u32
[0];
1473 /* For load_ubo_indirect, second src is indirect offset: */
1474 src1
= get_src(ctx
, &intr
->src
[1])[0];
1476 /* and add offset to addr: */
1477 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1480 /* if offset is to large to encode in the ldg, split it out: */
1481 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1482 /* split out the minimal amount to improve the odds that
1483 * cp can fit the immediate in the add.s instruction:
1485 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1486 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1491 struct ir3_instruction
*carry
;
1493 /* handle 32b rollover, ie:
1494 * if (addr < base_lo)
1497 carry
= ir3_CMPS_U(b
, addr
, 0, base_lo
, 0);
1498 carry
->cat2
.condition
= IR3_COND_LT
;
1499 base_hi
= ir3_ADD_S(b
, base_hi
, 0, carry
, 0);
1501 addr
= create_collect(ctx
, (struct ir3_instruction
*[]){ addr
, base_hi
}, 2);
1504 for (int i
= 0; i
< intr
->num_components
; i
++) {
1505 struct ir3_instruction
*load
=
1506 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1507 load
->cat6
.type
= TYPE_U32
;
1508 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
1513 /* src[] = { buffer_index, offset }. No const_index */
1515 emit_intrinsic_load_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1516 struct ir3_instruction
**dst
)
1518 struct ir3_block
*b
= ctx
->block
;
1519 struct ir3_instruction
*ldgb
, *src0
, *src1
, *offset
;
1520 nir_const_value
*const_offset
;
1522 /* can this be non-const buffer_index? how do we handle that? */
1523 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1524 compile_assert(ctx
, const_offset
);
1526 offset
= get_src(ctx
, &intr
->src
[1])[0];
1528 /* src0 is uvec2(offset*4, 0), src1 is offset.. nir already *= 4: */
1529 src0
= create_collect(ctx
, (struct ir3_instruction
*[]){
1533 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1535 ldgb
= ir3_LDGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1537 ldgb
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1538 ldgb
->cat6
.iim_val
= intr
->num_components
;
1540 ldgb
->cat6
.type
= TYPE_U32
;
1541 ldgb
->barrier_class
= IR3_BARRIER_BUFFER_R
;
1542 ldgb
->barrier_conflict
= IR3_BARRIER_BUFFER_W
;
1544 split_dest(b
, dst
, ldgb
, 0, intr
->num_components
);
1547 /* src[] = { value, block_index, offset }. const_index[] = { write_mask } */
1549 emit_intrinsic_store_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1551 struct ir3_block
*b
= ctx
->block
;
1552 struct ir3_instruction
*stgb
, *src0
, *src1
, *src2
, *offset
;
1553 nir_const_value
*const_offset
;
1554 /* TODO handle wrmask properly, see _store_shared().. but I think
1555 * it is more a PITA than that, since blob ends up loading the
1556 * masked components and writing them back out.
1558 unsigned wrmask
= intr
->const_index
[0];
1559 unsigned ncomp
= ffs(~wrmask
) - 1;
1561 /* can this be non-const buffer_index? how do we handle that? */
1562 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1563 compile_assert(ctx
, const_offset
);
1565 offset
= get_src(ctx
, &intr
->src
[2])[0];
1567 /* src0 is value, src1 is offset, src2 is uvec2(offset*4, 0)..
1570 src0
= create_collect(ctx
, get_src(ctx
, &intr
->src
[0]), ncomp
);
1571 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1572 src2
= create_collect(ctx
, (struct ir3_instruction
*[]){
1577 stgb
= ir3_STGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1578 src0
, 0, src1
, 0, src2
, 0);
1579 stgb
->cat6
.iim_val
= ncomp
;
1581 stgb
->cat6
.type
= TYPE_U32
;
1582 stgb
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1583 stgb
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1585 array_insert(b
, b
->keeps
, stgb
);
1588 /* src[] = { block_index } */
1590 emit_intrinsic_ssbo_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1591 struct ir3_instruction
**dst
)
1593 /* SSBO size stored as a const starting at ssbo_sizes: */
1594 unsigned blk_idx
= nir_src_as_const_value(intr
->src
[0])->u32
[0];
1595 unsigned idx
= regid(ctx
->so
->constbase
.ssbo_sizes
, 0) +
1596 ctx
->so
->const_layout
.ssbo_size
.off
[blk_idx
];
1598 debug_assert(ctx
->so
->const_layout
.ssbo_size
.mask
& (1 << blk_idx
));
1600 dst
[0] = create_uniform(ctx
, idx
);
1604 * SSBO atomic intrinsics
1606 * All of the SSBO atomic memory operations read a value from memory,
1607 * compute a new value using one of the operations below, write the new
1608 * value to memory, and return the original value read.
1610 * All operations take 3 sources except CompSwap that takes 4. These
1611 * sources represent:
1613 * 0: The SSBO buffer index.
1614 * 1: The offset into the SSBO buffer of the variable that the atomic
1615 * operation will operate on.
1616 * 2: The data parameter to the atomic function (i.e. the value to add
1617 * in ssbo_atomic_add, etc).
1618 * 3: For CompSwap only: the second data parameter.
1620 static struct ir3_instruction
*
1621 emit_intrinsic_atomic_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1623 struct ir3_block
*b
= ctx
->block
;
1624 struct ir3_instruction
*atomic
, *ssbo
, *src0
, *src1
, *src2
, *offset
;
1625 nir_const_value
*const_offset
;
1626 type_t type
= TYPE_U32
;
1628 /* can this be non-const buffer_index? how do we handle that? */
1629 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1630 compile_assert(ctx
, const_offset
);
1631 ssbo
= create_immed(b
, const_offset
->u32
[0]);
1633 offset
= get_src(ctx
, &intr
->src
[1])[0];
1635 /* src0 is data (or uvec2(data, compare))
1637 * src2 is uvec2(offset*4, 0) (appears to be 64b byte offset)
1639 * Note that nir already multiplies the offset by four
1641 src0
= get_src(ctx
, &intr
->src
[2])[0];
1642 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1643 src2
= create_collect(ctx
, (struct ir3_instruction
*[]){
1648 switch (intr
->intrinsic
) {
1649 case nir_intrinsic_ssbo_atomic_add
:
1650 atomic
= ir3_ATOMIC_ADD_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1652 case nir_intrinsic_ssbo_atomic_imin
:
1653 atomic
= ir3_ATOMIC_MIN_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1656 case nir_intrinsic_ssbo_atomic_umin
:
1657 atomic
= ir3_ATOMIC_MIN_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1659 case nir_intrinsic_ssbo_atomic_imax
:
1660 atomic
= ir3_ATOMIC_MAX_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1663 case nir_intrinsic_ssbo_atomic_umax
:
1664 atomic
= ir3_ATOMIC_MAX_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1666 case nir_intrinsic_ssbo_atomic_and
:
1667 atomic
= ir3_ATOMIC_AND_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1669 case nir_intrinsic_ssbo_atomic_or
:
1670 atomic
= ir3_ATOMIC_OR_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1672 case nir_intrinsic_ssbo_atomic_xor
:
1673 atomic
= ir3_ATOMIC_XOR_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1675 case nir_intrinsic_ssbo_atomic_exchange
:
1676 atomic
= ir3_ATOMIC_XCHG_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1678 case nir_intrinsic_ssbo_atomic_comp_swap
:
1679 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
1680 src0
= create_collect(ctx
, (struct ir3_instruction
*[]){
1682 get_src(ctx
, &intr
->src
[3])[0],
1684 atomic
= ir3_ATOMIC_CMPXCHG_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1690 atomic
->cat6
.iim_val
= 1;
1692 atomic
->cat6
.type
= type
;
1693 atomic
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1694 atomic
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1696 /* even if nothing consume the result, we can't DCE the instruction: */
1697 array_insert(b
, b
->keeps
, atomic
);
1702 /* src[] = { offset }. const_index[] = { base } */
1704 emit_intrinsic_load_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1705 struct ir3_instruction
**dst
)
1707 struct ir3_block
*b
= ctx
->block
;
1708 struct ir3_instruction
*ldl
, *offset
;
1711 offset
= get_src(ctx
, &intr
->src
[0])[0];
1712 base
= nir_intrinsic_base(intr
);
1714 ldl
= ir3_LDL(b
, offset
, 0, create_immed(b
, intr
->num_components
), 0);
1715 ldl
->cat6
.src_offset
= base
;
1716 ldl
->cat6
.type
= utype_dst(intr
->dest
);
1717 ldl
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1719 ldl
->barrier_class
= IR3_BARRIER_SHARED_R
;
1720 ldl
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
1722 split_dest(b
, dst
, ldl
, 0, intr
->num_components
);
1725 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
1727 emit_intrinsic_store_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1729 struct ir3_block
*b
= ctx
->block
;
1730 struct ir3_instruction
*stl
, *offset
;
1731 struct ir3_instruction
* const *value
;
1732 unsigned base
, wrmask
;
1734 value
= get_src(ctx
, &intr
->src
[0]);
1735 offset
= get_src(ctx
, &intr
->src
[1])[0];
1737 base
= nir_intrinsic_base(intr
);
1738 wrmask
= nir_intrinsic_write_mask(intr
);
1740 /* Combine groups of consecutive enabled channels in one write
1741 * message. We use ffs to find the first enabled channel and then ffs on
1742 * the bit-inverse, down-shifted writemask to determine the length of
1743 * the block of enabled bits.
1745 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
1748 unsigned first_component
= ffs(wrmask
) - 1;
1749 unsigned length
= ffs(~(wrmask
>> first_component
)) - 1;
1751 stl
= ir3_STL(b
, offset
, 0,
1752 create_collect(ctx
, &value
[first_component
], length
), 0,
1753 create_immed(b
, length
), 0);
1754 stl
->cat6
.dst_offset
= first_component
+ base
;
1755 stl
->cat6
.type
= utype_src(intr
->src
[0]);
1756 stl
->barrier_class
= IR3_BARRIER_SHARED_W
;
1757 stl
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1759 array_insert(b
, b
->keeps
, stl
);
1761 /* Clear the bits in the writemask that we just wrote, then try
1762 * again to see if more channels are left.
1764 wrmask
&= (15 << (first_component
+ length
));
1769 * CS shared variable atomic intrinsics
1771 * All of the shared variable atomic memory operations read a value from
1772 * memory, compute a new value using one of the operations below, write the
1773 * new value to memory, and return the original value read.
1775 * All operations take 2 sources except CompSwap that takes 3. These
1776 * sources represent:
1778 * 0: The offset into the shared variable storage region that the atomic
1779 * operation will operate on.
1780 * 1: The data parameter to the atomic function (i.e. the value to add
1781 * in shared_atomic_add, etc).
1782 * 2: For CompSwap only: the second data parameter.
1784 static struct ir3_instruction
*
1785 emit_intrinsic_atomic_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1787 struct ir3_block
*b
= ctx
->block
;
1788 struct ir3_instruction
*atomic
, *src0
, *src1
;
1789 type_t type
= TYPE_U32
;
1791 src0
= get_src(ctx
, &intr
->src
[0])[0]; /* offset */
1792 src1
= get_src(ctx
, &intr
->src
[1])[0]; /* value */
1794 switch (intr
->intrinsic
) {
1795 case nir_intrinsic_shared_atomic_add
:
1796 atomic
= ir3_ATOMIC_ADD(b
, src0
, 0, src1
, 0);
1798 case nir_intrinsic_shared_atomic_imin
:
1799 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1802 case nir_intrinsic_shared_atomic_umin
:
1803 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1805 case nir_intrinsic_shared_atomic_imax
:
1806 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1809 case nir_intrinsic_shared_atomic_umax
:
1810 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1812 case nir_intrinsic_shared_atomic_and
:
1813 atomic
= ir3_ATOMIC_AND(b
, src0
, 0, src1
, 0);
1815 case nir_intrinsic_shared_atomic_or
:
1816 atomic
= ir3_ATOMIC_OR(b
, src0
, 0, src1
, 0);
1818 case nir_intrinsic_shared_atomic_xor
:
1819 atomic
= ir3_ATOMIC_XOR(b
, src0
, 0, src1
, 0);
1821 case nir_intrinsic_shared_atomic_exchange
:
1822 atomic
= ir3_ATOMIC_XCHG(b
, src0
, 0, src1
, 0);
1824 case nir_intrinsic_shared_atomic_comp_swap
:
1825 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1826 src1
= create_collect(ctx
, (struct ir3_instruction
*[]){
1827 get_src(ctx
, &intr
->src
[2])[0],
1830 atomic
= ir3_ATOMIC_CMPXCHG(b
, src0
, 0, src1
, 0);
1836 atomic
->cat6
.iim_val
= 1;
1838 atomic
->cat6
.type
= type
;
1839 atomic
->barrier_class
= IR3_BARRIER_SHARED_W
;
1840 atomic
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1842 /* even if nothing consume the result, we can't DCE the instruction: */
1843 array_insert(b
, b
->keeps
, atomic
);
1848 /* Images get mapped into SSBO/image state (for store/atomic) and texture
1849 * state block (for load). To simplify things, invert the image id and
1850 * map it from end of state block, ie. image 0 becomes num-1, image 1
1851 * becomes num-2, etc. This potentially avoids needing to re-emit texture
1852 * state when switching shaders.
1854 * TODO is max # of samplers and SSBOs the same. This shouldn't be hard-
1855 * coded. Also, since all the gl shader stages (ie. everything but CS)
1856 * share the same SSBO/image state block, this might require some more
1857 * logic if we supported images in anything other than FS..
1860 get_image_slot(struct ir3_context
*ctx
, const nir_deref_var
*deref
)
1862 const nir_variable
*var
= deref
->var
;
1863 unsigned int loc
= var
->data
.driver_location
;
1865 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
; tail
= tail
->child
) {
1866 compile_assert(ctx
, tail
->child
->deref_type
== nir_deref_type_array
);
1868 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1869 compile_assert(ctx
, deref_array
->deref_array_type
== nir_deref_array_type_direct
);
1871 const unsigned elem_sz
= glsl_count_attribute_slots(deref_array
->deref
.type
, false);
1872 const unsigned size
= glsl_get_length(tail
->type
);
1873 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1875 loc
+= base
* elem_sz
;
1878 /* TODO figure out real limit per generation, and don't hardcode: */
1879 const unsigned max_samplers
= 16;
1880 return max_samplers
- loc
- 1;
1883 /* see tex_info() for equiv logic for texture instructions.. it would be
1884 * nice if this could be better unified..
1887 get_image_coords(const nir_variable
*var
, unsigned *flagsp
)
1889 const struct glsl_type
*type
= glsl_without_array(var
->type
);
1890 unsigned coords
, flags
= 0;
1892 switch (glsl_get_sampler_dim(type
)) {
1893 case GLSL_SAMPLER_DIM_1D
:
1894 case GLSL_SAMPLER_DIM_BUF
:
1897 case GLSL_SAMPLER_DIM_2D
:
1898 case GLSL_SAMPLER_DIM_RECT
:
1899 case GLSL_SAMPLER_DIM_EXTERNAL
:
1900 case GLSL_SAMPLER_DIM_MS
:
1903 case GLSL_SAMPLER_DIM_3D
:
1904 case GLSL_SAMPLER_DIM_CUBE
:
1905 flags
|= IR3_INSTR_3D
;
1909 unreachable("bad sampler dim");
1913 if (glsl_sampler_type_is_array(type
)) {
1914 /* note: unlike tex_info(), adjust # of coords to include array idx: */
1916 flags
|= IR3_INSTR_A
;
1926 get_image_type(const nir_variable
*var
)
1928 switch (glsl_get_sampler_result_type(glsl_without_array(var
->type
))) {
1929 case GLSL_TYPE_UINT
:
1933 case GLSL_TYPE_FLOAT
:
1936 unreachable("bad sampler type.");
1941 static struct ir3_instruction
*
1942 get_image_offset(struct ir3_context
*ctx
, const nir_variable
*var
,
1943 struct ir3_instruction
* const *coords
, bool byteoff
)
1945 struct ir3_block
*b
= ctx
->block
;
1946 struct ir3_instruction
*offset
;
1947 unsigned ncoords
= get_image_coords(var
, NULL
);
1949 /* to calculate the byte offset (yes, uggg) we need (up to) three
1950 * const values to know the bytes per pixel, and y and z stride:
1952 unsigned cb
= regid(ctx
->so
->constbase
.image_dims
, 0) +
1953 ctx
->so
->const_layout
.image_dims
.off
[var
->data
.driver_location
];
1955 debug_assert(ctx
->so
->const_layout
.image_dims
.mask
&
1956 (1 << var
->data
.driver_location
));
1958 /* offset = coords.x * bytes_per_pixel: */
1959 offset
= ir3_MUL_S(b
, coords
[0], 0, create_uniform(ctx
, cb
+ 0), 0);
1961 /* offset += coords.y * y_pitch: */
1962 offset
= ir3_MAD_S24(b
, create_uniform(ctx
, cb
+ 1), 0,
1963 coords
[1], 0, offset
, 0);
1966 /* offset += coords.z * z_pitch: */
1967 offset
= ir3_MAD_S24(b
, create_uniform(ctx
, cb
+ 2), 0,
1968 coords
[2], 0, offset
, 0);
1972 /* Some cases, like atomics, seem to use dword offset instead
1973 * of byte offsets.. blob just puts an extra shr.b in there
1976 offset
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1979 return create_collect(ctx
, (struct ir3_instruction
*[]){
1985 /* src[] = { coord, sample_index }. const_index[] = {} */
1987 emit_intrinsic_load_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1988 struct ir3_instruction
**dst
)
1990 struct ir3_block
*b
= ctx
->block
;
1991 const nir_variable
*var
= intr
->variables
[0]->var
;
1992 struct ir3_instruction
*sam
;
1993 struct ir3_instruction
* const *src0
= get_src(ctx
, &intr
->src
[0]);
1994 struct ir3_instruction
*coords
[4];
1995 unsigned flags
, ncoords
= get_image_coords(var
, &flags
);
1996 unsigned tex_idx
= get_image_slot(ctx
, intr
->variables
[0]);
1997 type_t type
= get_image_type(var
);
1999 /* hmm, this seems a bit odd, but it is what blob does and (at least
2000 * a5xx) just faults on bogus addresses otherwise:
2002 if (flags
& IR3_INSTR_3D
) {
2003 flags
&= ~IR3_INSTR_3D
;
2004 flags
|= IR3_INSTR_A
;
2007 for (unsigned i
= 0; i
< ncoords
; i
++)
2008 coords
[i
] = src0
[i
];
2011 coords
[ncoords
++] = create_immed(b
, 0);
2013 sam
= ir3_SAM(b
, OPC_ISAM
, type
, TGSI_WRITEMASK_XYZW
, flags
,
2014 tex_idx
, tex_idx
, create_collect(ctx
, coords
, ncoords
), NULL
);
2016 sam
->barrier_class
= IR3_BARRIER_IMAGE_R
;
2017 sam
->barrier_conflict
= IR3_BARRIER_IMAGE_W
;
2019 split_dest(b
, dst
, sam
, 0, 4);
2022 /* src[] = { coord, sample_index, value }. const_index[] = {} */
2024 emit_intrinsic_store_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
2026 struct ir3_block
*b
= ctx
->block
;
2027 const nir_variable
*var
= intr
->variables
[0]->var
;
2028 struct ir3_instruction
*stib
, *offset
;
2029 struct ir3_instruction
* const *value
= get_src(ctx
, &intr
->src
[2]);
2030 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[0]);
2031 unsigned ncoords
= get_image_coords(var
, NULL
);
2032 unsigned tex_idx
= get_image_slot(ctx
, intr
->variables
[0]);
2036 * src2 is 64b byte offset
2039 offset
= get_image_offset(ctx
, var
, coords
, true);
2041 /* NOTE: stib seems to take byte offset, but stgb.typed can be used
2042 * too and takes a dword offset.. not quite sure yet why blob uses
2043 * one over the other in various cases.
2046 stib
= ir3_STIB(b
, create_immed(b
, tex_idx
), 0,
2047 create_collect(ctx
, value
, 4), 0,
2048 create_collect(ctx
, coords
, ncoords
), 0,
2050 stib
->cat6
.iim_val
= 4;
2051 stib
->cat6
.d
= ncoords
;
2052 stib
->cat6
.type
= get_image_type(var
);
2053 stib
->cat6
.typed
= true;
2054 stib
->barrier_class
= IR3_BARRIER_IMAGE_W
;
2055 stib
->barrier_conflict
= IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
;
2057 array_insert(b
, b
->keeps
, stib
);
2061 emit_intrinsic_image_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
2062 struct ir3_instruction
**dst
)
2064 struct ir3_block
*b
= ctx
->block
;
2065 const nir_variable
*var
= intr
->variables
[0]->var
;
2066 unsigned tex_idx
= get_image_slot(ctx
, intr
->variables
[0]);
2067 struct ir3_instruction
*sam
, *lod
;
2068 unsigned flags
, ncoords
= get_image_coords(var
, &flags
);
2070 lod
= create_immed(b
, 0);
2071 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
2072 tex_idx
, tex_idx
, lod
, NULL
);
2074 /* Array size actually ends up in .w rather than .z. This doesn't
2075 * matter for miplevel 0, but for higher mips the value in z is
2076 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2077 * returned, which means that we have to add 1 to it for arrays for
2080 * Note use a temporary dst and then copy, since the size of the dst
2081 * array that is passed in is based on nir's understanding of the
2082 * result size, not the hardware's
2084 struct ir3_instruction
*tmp
[4];
2086 split_dest(b
, tmp
, sam
, 0, 4);
2088 for (unsigned i
= 0; i
< ncoords
; i
++)
2091 if (flags
& IR3_INSTR_A
) {
2092 if (ctx
->levels_add_one
) {
2093 dst
[ncoords
-1] = ir3_ADD_U(b
, tmp
[3], 0, create_immed(b
, 1), 0);
2095 dst
[ncoords
-1] = ir3_MOV(b
, tmp
[3], TYPE_U32
);
2100 /* src[] = { coord, sample_index, value, compare }. const_index[] = {} */
2101 static struct ir3_instruction
*
2102 emit_intrinsic_atomic_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
2104 struct ir3_block
*b
= ctx
->block
;
2105 const nir_variable
*var
= intr
->variables
[0]->var
;
2106 struct ir3_instruction
*atomic
, *image
, *src0
, *src1
, *src2
;
2107 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[0]);
2108 unsigned ncoords
= get_image_coords(var
, NULL
);
2110 image
= create_immed(b
, get_image_slot(ctx
, intr
->variables
[0]));
2112 /* src0 is value (or uvec2(value, compare))
2114 * src2 is 64b byte offset
2116 src0
= get_src(ctx
, &intr
->src
[2])[0];
2117 src1
= create_collect(ctx
, coords
, ncoords
);
2118 src2
= get_image_offset(ctx
, var
, coords
, false);
2120 switch (intr
->intrinsic
) {
2121 case nir_intrinsic_image_var_atomic_add
:
2122 atomic
= ir3_ATOMIC_ADD_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2124 case nir_intrinsic_image_var_atomic_min
:
2125 atomic
= ir3_ATOMIC_MIN_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2127 case nir_intrinsic_image_var_atomic_max
:
2128 atomic
= ir3_ATOMIC_MAX_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2130 case nir_intrinsic_image_var_atomic_and
:
2131 atomic
= ir3_ATOMIC_AND_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2133 case nir_intrinsic_image_var_atomic_or
:
2134 atomic
= ir3_ATOMIC_OR_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2136 case nir_intrinsic_image_var_atomic_xor
:
2137 atomic
= ir3_ATOMIC_XOR_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2139 case nir_intrinsic_image_var_atomic_exchange
:
2140 atomic
= ir3_ATOMIC_XCHG_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2142 case nir_intrinsic_image_var_atomic_comp_swap
:
2143 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
2144 src0
= create_collect(ctx
, (struct ir3_instruction
*[]){
2146 get_src(ctx
, &intr
->src
[3])[0],
2148 atomic
= ir3_ATOMIC_CMPXCHG_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2154 atomic
->cat6
.iim_val
= 1;
2155 atomic
->cat6
.d
= ncoords
;
2156 atomic
->cat6
.type
= get_image_type(var
);
2157 atomic
->cat6
.typed
= true;
2158 atomic
->barrier_class
= IR3_BARRIER_IMAGE_W
;
2159 atomic
->barrier_conflict
= IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
;
2161 /* even if nothing consume the result, we can't DCE the instruction: */
2162 array_insert(b
, b
->keeps
, atomic
);
2168 emit_intrinsic_barrier(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
2170 struct ir3_block
*b
= ctx
->block
;
2171 struct ir3_instruction
*barrier
;
2173 switch (intr
->intrinsic
) {
2174 case nir_intrinsic_barrier
:
2175 barrier
= ir3_BAR(b
);
2176 barrier
->cat7
.g
= true;
2177 barrier
->cat7
.l
= true;
2178 barrier
->flags
= IR3_INSTR_SS
| IR3_INSTR_SY
;
2179 barrier
->barrier_class
= IR3_BARRIER_EVERYTHING
;
2181 case nir_intrinsic_memory_barrier
:
2182 barrier
= ir3_FENCE(b
);
2183 barrier
->cat7
.g
= true;
2184 barrier
->cat7
.r
= true;
2185 barrier
->cat7
.w
= true;
2186 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
|
2187 IR3_BARRIER_BUFFER_W
;
2188 barrier
->barrier_conflict
=
2189 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
2190 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
2192 case nir_intrinsic_memory_barrier_atomic_counter
:
2193 case nir_intrinsic_memory_barrier_buffer
:
2194 barrier
= ir3_FENCE(b
);
2195 barrier
->cat7
.g
= true;
2196 barrier
->cat7
.r
= true;
2197 barrier
->cat7
.w
= true;
2198 barrier
->barrier_class
= IR3_BARRIER_BUFFER_W
;
2199 barrier
->barrier_conflict
= IR3_BARRIER_BUFFER_R
|
2200 IR3_BARRIER_BUFFER_W
;
2202 case nir_intrinsic_memory_barrier_image
:
2203 // TODO double check if this should have .g set
2204 barrier
= ir3_FENCE(b
);
2205 barrier
->cat7
.g
= true;
2206 barrier
->cat7
.r
= true;
2207 barrier
->cat7
.w
= true;
2208 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
;
2209 barrier
->barrier_conflict
= IR3_BARRIER_IMAGE_R
|
2210 IR3_BARRIER_IMAGE_W
;
2212 case nir_intrinsic_memory_barrier_shared
:
2213 barrier
= ir3_FENCE(b
);
2214 barrier
->cat7
.g
= true;
2215 barrier
->cat7
.l
= true;
2216 barrier
->cat7
.r
= true;
2217 barrier
->cat7
.w
= true;
2218 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
;
2219 barrier
->barrier_conflict
= IR3_BARRIER_SHARED_R
|
2220 IR3_BARRIER_SHARED_W
;
2222 case nir_intrinsic_group_memory_barrier
:
2223 barrier
= ir3_FENCE(b
);
2224 barrier
->cat7
.g
= true;
2225 barrier
->cat7
.l
= true;
2226 barrier
->cat7
.r
= true;
2227 barrier
->cat7
.w
= true;
2228 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
|
2229 IR3_BARRIER_IMAGE_W
|
2230 IR3_BARRIER_BUFFER_W
;
2231 barrier
->barrier_conflict
=
2232 IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
|
2233 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
2234 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
2240 /* make sure barrier doesn't get DCE'd */
2241 array_insert(b
, b
->keeps
, barrier
);
2244 static void add_sysval_input_compmask(struct ir3_context
*ctx
,
2245 gl_system_value slot
, unsigned compmask
,
2246 struct ir3_instruction
*instr
)
2248 struct ir3_shader_variant
*so
= ctx
->so
;
2249 unsigned r
= regid(so
->inputs_count
, 0);
2250 unsigned n
= so
->inputs_count
++;
2252 so
->inputs
[n
].sysval
= true;
2253 so
->inputs
[n
].slot
= slot
;
2254 so
->inputs
[n
].compmask
= compmask
;
2255 so
->inputs
[n
].regid
= r
;
2256 so
->inputs
[n
].interpolate
= INTERP_MODE_FLAT
;
2259 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
2260 ctx
->ir
->inputs
[r
] = instr
;
2263 static void add_sysval_input(struct ir3_context
*ctx
, gl_system_value slot
,
2264 struct ir3_instruction
*instr
)
2266 add_sysval_input_compmask(ctx
, slot
, 0x1, instr
);
2270 emit_intrinsic(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
2272 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
2273 struct ir3_instruction
**dst
;
2274 struct ir3_instruction
* const *src
;
2275 struct ir3_block
*b
= ctx
->block
;
2276 nir_const_value
*const_offset
;
2279 if (info
->has_dest
) {
2280 unsigned n
= nir_intrinsic_dest_components(intr
);
2281 dst
= get_dst(ctx
, &intr
->dest
, n
);
2286 switch (intr
->intrinsic
) {
2287 case nir_intrinsic_load_uniform
:
2288 idx
= nir_intrinsic_base(intr
);
2289 const_offset
= nir_src_as_const_value(intr
->src
[0]);
2291 idx
+= const_offset
->u32
[0];
2292 for (int i
= 0; i
< intr
->num_components
; i
++) {
2293 unsigned n
= idx
* 4 + i
;
2294 dst
[i
] = create_uniform(ctx
, n
);
2297 src
= get_src(ctx
, &intr
->src
[0]);
2298 for (int i
= 0; i
< intr
->num_components
; i
++) {
2299 int n
= idx
* 4 + i
;
2300 dst
[i
] = create_uniform_indirect(ctx
, n
,
2301 get_addr(ctx
, src
[0], 4));
2303 /* NOTE: if relative addressing is used, we set
2304 * constlen in the compiler (to worst-case value)
2305 * since we don't know in the assembler what the max
2306 * addr reg value can be:
2308 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
2311 case nir_intrinsic_load_ubo
:
2312 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
2314 case nir_intrinsic_load_input
:
2315 idx
= nir_intrinsic_base(intr
);
2316 comp
= nir_intrinsic_component(intr
);
2317 const_offset
= nir_src_as_const_value(intr
->src
[0]);
2319 idx
+= const_offset
->u32
[0];
2320 for (int i
= 0; i
< intr
->num_components
; i
++) {
2321 unsigned n
= idx
* 4 + i
+ comp
;
2322 dst
[i
] = ctx
->ir
->inputs
[n
];
2325 src
= get_src(ctx
, &intr
->src
[0]);
2326 struct ir3_instruction
*collect
=
2327 create_collect(ctx
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
2328 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0], 4);
2329 for (int i
= 0; i
< intr
->num_components
; i
++) {
2330 unsigned n
= idx
* 4 + i
+ comp
;
2331 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
2336 case nir_intrinsic_load_ssbo
:
2337 emit_intrinsic_load_ssbo(ctx
, intr
, dst
);
2339 case nir_intrinsic_store_ssbo
:
2340 emit_intrinsic_store_ssbo(ctx
, intr
);
2342 case nir_intrinsic_get_buffer_size
:
2343 emit_intrinsic_ssbo_size(ctx
, intr
, dst
);
2345 case nir_intrinsic_ssbo_atomic_add
:
2346 case nir_intrinsic_ssbo_atomic_imin
:
2347 case nir_intrinsic_ssbo_atomic_umin
:
2348 case nir_intrinsic_ssbo_atomic_imax
:
2349 case nir_intrinsic_ssbo_atomic_umax
:
2350 case nir_intrinsic_ssbo_atomic_and
:
2351 case nir_intrinsic_ssbo_atomic_or
:
2352 case nir_intrinsic_ssbo_atomic_xor
:
2353 case nir_intrinsic_ssbo_atomic_exchange
:
2354 case nir_intrinsic_ssbo_atomic_comp_swap
:
2355 dst
[0] = emit_intrinsic_atomic_ssbo(ctx
, intr
);
2357 case nir_intrinsic_load_shared
:
2358 emit_intrinsic_load_shared(ctx
, intr
, dst
);
2360 case nir_intrinsic_store_shared
:
2361 emit_intrinsic_store_shared(ctx
, intr
);
2363 case nir_intrinsic_shared_atomic_add
:
2364 case nir_intrinsic_shared_atomic_imin
:
2365 case nir_intrinsic_shared_atomic_umin
:
2366 case nir_intrinsic_shared_atomic_imax
:
2367 case nir_intrinsic_shared_atomic_umax
:
2368 case nir_intrinsic_shared_atomic_and
:
2369 case nir_intrinsic_shared_atomic_or
:
2370 case nir_intrinsic_shared_atomic_xor
:
2371 case nir_intrinsic_shared_atomic_exchange
:
2372 case nir_intrinsic_shared_atomic_comp_swap
:
2373 dst
[0] = emit_intrinsic_atomic_shared(ctx
, intr
);
2375 case nir_intrinsic_image_var_load
:
2376 emit_intrinsic_load_image(ctx
, intr
, dst
);
2378 case nir_intrinsic_image_var_store
:
2379 emit_intrinsic_store_image(ctx
, intr
);
2381 case nir_intrinsic_image_var_size
:
2382 emit_intrinsic_image_size(ctx
, intr
, dst
);
2384 case nir_intrinsic_image_var_atomic_add
:
2385 case nir_intrinsic_image_var_atomic_min
:
2386 case nir_intrinsic_image_var_atomic_max
:
2387 case nir_intrinsic_image_var_atomic_and
:
2388 case nir_intrinsic_image_var_atomic_or
:
2389 case nir_intrinsic_image_var_atomic_xor
:
2390 case nir_intrinsic_image_var_atomic_exchange
:
2391 case nir_intrinsic_image_var_atomic_comp_swap
:
2392 dst
[0] = emit_intrinsic_atomic_image(ctx
, intr
);
2394 case nir_intrinsic_barrier
:
2395 case nir_intrinsic_memory_barrier
:
2396 case nir_intrinsic_group_memory_barrier
:
2397 case nir_intrinsic_memory_barrier_atomic_counter
:
2398 case nir_intrinsic_memory_barrier_buffer
:
2399 case nir_intrinsic_memory_barrier_image
:
2400 case nir_intrinsic_memory_barrier_shared
:
2401 emit_intrinsic_barrier(ctx
, intr
);
2402 /* note that blk ptr no longer valid, make that obvious: */
2405 case nir_intrinsic_store_output
:
2406 idx
= nir_intrinsic_base(intr
);
2407 comp
= nir_intrinsic_component(intr
);
2408 const_offset
= nir_src_as_const_value(intr
->src
[1]);
2409 compile_assert(ctx
, const_offset
!= NULL
);
2410 idx
+= const_offset
->u32
[0];
2412 src
= get_src(ctx
, &intr
->src
[0]);
2413 for (int i
= 0; i
< intr
->num_components
; i
++) {
2414 unsigned n
= idx
* 4 + i
+ comp
;
2415 ctx
->ir
->outputs
[n
] = src
[i
];
2418 case nir_intrinsic_load_base_vertex
:
2419 case nir_intrinsic_load_first_vertex
:
2420 if (!ctx
->basevertex
) {
2421 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
2422 add_sysval_input(ctx
, SYSTEM_VALUE_FIRST_VERTEX
, ctx
->basevertex
);
2424 dst
[0] = ctx
->basevertex
;
2426 case nir_intrinsic_load_vertex_id_zero_base
:
2427 case nir_intrinsic_load_vertex_id
:
2428 if (!ctx
->vertex_id
) {
2429 gl_system_value sv
= (intr
->intrinsic
== nir_intrinsic_load_vertex_id
) ?
2430 SYSTEM_VALUE_VERTEX_ID
: SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
;
2431 ctx
->vertex_id
= create_input(b
, 0);
2432 add_sysval_input(ctx
, sv
, ctx
->vertex_id
);
2434 dst
[0] = ctx
->vertex_id
;
2436 case nir_intrinsic_load_instance_id
:
2437 if (!ctx
->instance_id
) {
2438 ctx
->instance_id
= create_input(b
, 0);
2439 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
2442 dst
[0] = ctx
->instance_id
;
2444 case nir_intrinsic_load_sample_id
:
2445 if (!ctx
->samp_id
) {
2446 ctx
->samp_id
= create_input(b
, 0);
2447 ctx
->samp_id
->regs
[0]->flags
|= IR3_REG_HALF
;
2448 add_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_ID
,
2451 dst
[0] = ir3_COV(b
, ctx
->samp_id
, TYPE_U16
, TYPE_U32
);
2453 case nir_intrinsic_load_sample_mask_in
:
2454 if (!ctx
->samp_mask_in
) {
2455 ctx
->samp_mask_in
= create_input(b
, 0);
2456 add_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_MASK_IN
,
2459 dst
[0] = ctx
->samp_mask_in
;
2461 case nir_intrinsic_load_user_clip_plane
:
2462 idx
= nir_intrinsic_ucp_id(intr
);
2463 for (int i
= 0; i
< intr
->num_components
; i
++) {
2464 unsigned n
= idx
* 4 + i
;
2465 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
2468 case nir_intrinsic_load_front_face
:
2469 if (!ctx
->frag_face
) {
2470 ctx
->so
->frag_face
= true;
2471 ctx
->frag_face
= create_input(b
, 0);
2472 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
2474 /* for fragface, we get -1 for back and 0 for front. However this is
2475 * the inverse of what nir expects (where ~0 is true).
2477 dst
[0] = ir3_COV(b
, ctx
->frag_face
, TYPE_S16
, TYPE_S32
);
2478 dst
[0] = ir3_NOT_B(b
, dst
[0], 0);
2480 case nir_intrinsic_load_local_invocation_id
:
2481 if (!ctx
->local_invocation_id
) {
2482 ctx
->local_invocation_id
= create_input_compmask(b
, 0, 0x7);
2483 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
,
2484 0x7, ctx
->local_invocation_id
);
2486 split_dest(b
, dst
, ctx
->local_invocation_id
, 0, 3);
2488 case nir_intrinsic_load_work_group_id
:
2489 if (!ctx
->work_group_id
) {
2490 ctx
->work_group_id
= create_input_compmask(b
, 0, 0x7);
2491 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_WORK_GROUP_ID
,
2492 0x7, ctx
->work_group_id
);
2493 ctx
->work_group_id
->regs
[0]->flags
|= IR3_REG_HIGH
;
2495 split_dest(b
, dst
, ctx
->work_group_id
, 0, 3);
2497 case nir_intrinsic_load_num_work_groups
:
2498 for (int i
= 0; i
< intr
->num_components
; i
++) {
2499 dst
[i
] = create_driver_param(ctx
, IR3_DP_NUM_WORK_GROUPS_X
+ i
);
2502 case nir_intrinsic_load_local_group_size
:
2503 for (int i
= 0; i
< intr
->num_components
; i
++) {
2504 dst
[i
] = create_driver_param(ctx
, IR3_DP_LOCAL_GROUP_SIZE_X
+ i
);
2507 case nir_intrinsic_discard_if
:
2508 case nir_intrinsic_discard
: {
2509 struct ir3_instruction
*cond
, *kill
;
2511 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
2512 /* conditional discard: */
2513 src
= get_src(ctx
, &intr
->src
[0]);
2514 cond
= ir3_b2n(b
, src
[0]);
2516 /* unconditional discard: */
2517 cond
= create_immed(b
, 1);
2520 /* NOTE: only cmps.*.* can write p0.x: */
2521 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
2522 cond
->cat2
.condition
= IR3_COND_NE
;
2524 /* condition always goes in predicate register: */
2525 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2527 kill
= ir3_KILL(b
, cond
, 0);
2528 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
2530 array_insert(b
, b
->keeps
, kill
);
2531 ctx
->so
->has_kill
= true;
2536 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
2537 nir_intrinsic_infos
[intr
->intrinsic
].name
);
2542 put_dst(ctx
, &intr
->dest
);
2546 emit_load_const(struct ir3_context
*ctx
, nir_load_const_instr
*instr
)
2548 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
2549 instr
->def
.num_components
);
2550 type_t type
= (instr
->def
.bit_size
< 32) ? TYPE_U16
: TYPE_U32
;
2552 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
2553 dst
[i
] = create_immed_typed(ctx
->block
, instr
->value
.u32
[i
], type
);
2557 emit_undef(struct ir3_context
*ctx
, nir_ssa_undef_instr
*undef
)
2559 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
2560 undef
->def
.num_components
);
2561 type_t type
= (undef
->def
.bit_size
< 32) ? TYPE_U16
: TYPE_U32
;
2563 /* backend doesn't want undefined instructions, so just plug
2566 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
2567 dst
[i
] = create_immed_typed(ctx
->block
, fui(0.0), type
);
2571 * texture fetch/sample instructions:
2575 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
2577 unsigned coords
, flags
= 0;
2579 /* note: would use tex->coord_components.. except txs.. also,
2580 * since array index goes after shadow ref, we don't want to
2583 switch (tex
->sampler_dim
) {
2584 case GLSL_SAMPLER_DIM_1D
:
2585 case GLSL_SAMPLER_DIM_BUF
:
2588 case GLSL_SAMPLER_DIM_2D
:
2589 case GLSL_SAMPLER_DIM_RECT
:
2590 case GLSL_SAMPLER_DIM_EXTERNAL
:
2591 case GLSL_SAMPLER_DIM_MS
:
2594 case GLSL_SAMPLER_DIM_3D
:
2595 case GLSL_SAMPLER_DIM_CUBE
:
2597 flags
|= IR3_INSTR_3D
;
2600 unreachable("bad sampler_dim");
2603 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2604 flags
|= IR3_INSTR_S
;
2606 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
2607 flags
|= IR3_INSTR_A
;
2614 emit_tex(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2616 struct ir3_block
*b
= ctx
->block
;
2617 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
2618 struct ir3_instruction
* const *coord
, * const *off
, * const *ddx
, * const *ddy
;
2619 struct ir3_instruction
*lod
, *compare
, *proj
, *sample_index
;
2620 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
2621 unsigned i
, coords
, flags
;
2622 unsigned nsrc0
= 0, nsrc1
= 0;
2626 coord
= off
= ddx
= ddy
= NULL
;
2627 lod
= proj
= compare
= sample_index
= NULL
;
2629 /* TODO: might just be one component for gathers? */
2630 dst
= get_dst(ctx
, &tex
->dest
, 4);
2632 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
2633 switch (tex
->src
[i
].src_type
) {
2634 case nir_tex_src_coord
:
2635 coord
= get_src(ctx
, &tex
->src
[i
].src
);
2637 case nir_tex_src_bias
:
2638 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2641 case nir_tex_src_lod
:
2642 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2645 case nir_tex_src_comparator
: /* shadow comparator */
2646 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2648 case nir_tex_src_projector
:
2649 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2652 case nir_tex_src_offset
:
2653 off
= get_src(ctx
, &tex
->src
[i
].src
);
2656 case nir_tex_src_ddx
:
2657 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
2659 case nir_tex_src_ddy
:
2660 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
2662 case nir_tex_src_ms_index
:
2663 sample_index
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2666 compile_error(ctx
, "Unhandled NIR tex src type: %d\n",
2667 tex
->src
[i
].src_type
);
2673 case nir_texop_tex
: opc
= has_lod
? OPC_SAML
: OPC_SAM
; break;
2674 case nir_texop_txb
: opc
= OPC_SAMB
; break;
2675 case nir_texop_txl
: opc
= OPC_SAML
; break;
2676 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
2677 case nir_texop_txf
: opc
= OPC_ISAML
; break;
2678 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
2680 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2681 * what blob does, seems gather is broken?), and a3xx did
2682 * not support it (but probably could also emulate).
2684 switch (tex
->component
) {
2685 case 0: opc
= OPC_GATHER4R
; break;
2686 case 1: opc
= OPC_GATHER4G
; break;
2687 case 2: opc
= OPC_GATHER4B
; break;
2688 case 3: opc
= OPC_GATHER4A
; break;
2691 case nir_texop_txf_ms
: opc
= OPC_ISAMM
; break;
2693 case nir_texop_query_levels
:
2694 case nir_texop_texture_samples
:
2695 case nir_texop_samples_identical
:
2696 case nir_texop_txf_ms_mcs
:
2697 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
2701 tex_info(tex
, &flags
, &coords
);
2704 * lay out the first argument in the proper order:
2705 * - actual coordinates first
2706 * - shadow reference
2709 * - starting at offset 4, dpdx.xy, dpdy.xy
2711 * bias/lod go into the second arg
2714 /* insert tex coords: */
2715 for (i
= 0; i
< coords
; i
++)
2720 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2721 * with scaled x coord according to requested sample:
2723 if (tex
->op
== nir_texop_txf_ms
) {
2724 if (ctx
->txf_ms_with_isaml
) {
2725 /* the samples are laid out in x dimension as
2727 * x_ms = (x << ms) + sample_index;
2729 struct ir3_instruction
*ms
;
2730 ms
= create_immed(b
, (ctx
->samples
>> (2 * tex
->texture_index
)) & 3);
2732 src0
[0] = ir3_SHL_B(b
, src0
[0], 0, ms
, 0);
2733 src0
[0] = ir3_ADD_U(b
, src0
[0], 0, sample_index
, 0);
2737 src0
[nsrc0
++] = sample_index
;
2741 /* scale up integer coords for TXF based on the LOD */
2742 if (ctx
->unminify_coords
&& (opc
== OPC_ISAML
)) {
2744 for (i
= 0; i
< coords
; i
++)
2745 src0
[i
] = ir3_SHL_B(b
, src0
[i
], 0, lod
, 0);
2749 /* hw doesn't do 1d, so we treat it as 2d with
2750 * height of 1, and patch up the y coord.
2751 * TODO: y coord should be (int)0 in some cases..
2753 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
2756 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2757 src0
[nsrc0
++] = compare
;
2759 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
) {
2760 struct ir3_instruction
*idx
= coord
[coords
];
2762 /* the array coord for cube arrays needs 0.5 added to it */
2763 if (ctx
->array_index_add_half
&& (opc
!= OPC_ISAML
))
2764 idx
= ir3_ADD_F(b
, idx
, 0, create_immed(b
, fui(0.5)), 0);
2766 src0
[nsrc0
++] = idx
;
2770 src0
[nsrc0
++] = proj
;
2771 flags
|= IR3_INSTR_P
;
2774 /* pad to 4, then ddx/ddy: */
2775 if (tex
->op
== nir_texop_txd
) {
2777 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2778 for (i
= 0; i
< coords
; i
++)
2779 src0
[nsrc0
++] = ddx
[i
];
2781 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2782 for (i
= 0; i
< coords
; i
++)
2783 src0
[nsrc0
++] = ddy
[i
];
2785 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2789 * second argument (if applicable):
2794 if (has_off
| has_lod
| has_bias
) {
2796 unsigned off_coords
= coords
;
2797 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2799 for (i
= 0; i
< off_coords
; i
++)
2800 src1
[nsrc1
++] = off
[i
];
2802 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
2803 flags
|= IR3_INSTR_O
;
2806 if (has_lod
| has_bias
)
2807 src1
[nsrc1
++] = lod
;
2810 switch (tex
->dest_type
) {
2811 case nir_type_invalid
:
2812 case nir_type_float
:
2823 unreachable("bad dest_type");
2826 if (opc
== OPC_GETLOD
)
2829 unsigned tex_idx
= tex
->texture_index
;
2831 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex_idx
);
2833 struct ir3_instruction
*col0
= create_collect(ctx
, src0
, nsrc0
);
2834 struct ir3_instruction
*col1
= create_collect(ctx
, src1
, nsrc1
);
2836 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
, flags
,
2837 tex_idx
, tex_idx
, col0
, col1
);
2839 if ((ctx
->astc_srgb
& (1 << tex_idx
)) && !nir_tex_instr_is_query(tex
)) {
2840 /* only need first 3 components: */
2841 sam
->regs
[0]->wrmask
= 0x7;
2842 split_dest(b
, dst
, sam
, 0, 3);
2844 /* we need to sample the alpha separately with a non-ASTC
2847 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_W
, flags
,
2848 tex_idx
, tex_idx
, col0
, col1
);
2850 array_insert(ctx
->ir
, ctx
->ir
->astc_srgb
, sam
);
2852 /* fixup .w component: */
2853 split_dest(b
, &dst
[3], sam
, 3, 1);
2855 /* normal (non-workaround) case: */
2856 split_dest(b
, dst
, sam
, 0, 4);
2859 /* GETLOD returns results in 4.8 fixed point */
2860 if (opc
== OPC_GETLOD
) {
2861 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
2863 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
2864 for (i
= 0; i
< 2; i
++) {
2865 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_U32
, TYPE_F32
), 0,
2870 put_dst(ctx
, &tex
->dest
);
2874 emit_tex_query_levels(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2876 struct ir3_block
*b
= ctx
->block
;
2877 struct ir3_instruction
**dst
, *sam
;
2879 dst
= get_dst(ctx
, &tex
->dest
, 1);
2881 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
2882 tex
->texture_index
, tex
->texture_index
, NULL
, NULL
);
2884 /* even though there is only one component, since it ends
2885 * up in .z rather than .x, we need a split_dest()
2887 split_dest(b
, dst
, sam
, 0, 3);
2889 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2890 * the value in TEX_CONST_0 is zero-based.
2892 if (ctx
->levels_add_one
)
2893 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
2895 put_dst(ctx
, &tex
->dest
);
2899 emit_tex_txs(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2901 struct ir3_block
*b
= ctx
->block
;
2902 struct ir3_instruction
**dst
, *sam
;
2903 struct ir3_instruction
*lod
;
2904 unsigned flags
, coords
;
2906 tex_info(tex
, &flags
, &coords
);
2908 /* Actually we want the number of dimensions, not coordinates. This
2909 * distinction only matters for cubes.
2911 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2914 dst
= get_dst(ctx
, &tex
->dest
, 4);
2916 compile_assert(ctx
, tex
->num_srcs
== 1);
2917 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
2919 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
2921 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
2922 tex
->texture_index
, tex
->texture_index
, lod
, NULL
);
2924 split_dest(b
, dst
, sam
, 0, 4);
2926 /* Array size actually ends up in .w rather than .z. This doesn't
2927 * matter for miplevel 0, but for higher mips the value in z is
2928 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2929 * returned, which means that we have to add 1 to it for arrays.
2931 if (tex
->is_array
) {
2932 if (ctx
->levels_add_one
) {
2933 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
2935 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
2939 put_dst(ctx
, &tex
->dest
);
2943 emit_jump(struct ir3_context
*ctx
, nir_jump_instr
*jump
)
2945 switch (jump
->type
) {
2946 case nir_jump_break
:
2947 case nir_jump_continue
:
2948 case nir_jump_return
:
2949 /* I *think* we can simply just ignore this, and use the
2950 * successor block link to figure out where we need to
2951 * jump to for break/continue
2955 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
2961 emit_instr(struct ir3_context
*ctx
, nir_instr
*instr
)
2963 switch (instr
->type
) {
2964 case nir_instr_type_alu
:
2965 emit_alu(ctx
, nir_instr_as_alu(instr
));
2967 case nir_instr_type_intrinsic
:
2968 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2970 case nir_instr_type_load_const
:
2971 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2973 case nir_instr_type_ssa_undef
:
2974 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
2976 case nir_instr_type_tex
: {
2977 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
2978 /* couple tex instructions get special-cased:
2982 emit_tex_txs(ctx
, tex
);
2984 case nir_texop_query_levels
:
2985 emit_tex_query_levels(ctx
, tex
);
2993 case nir_instr_type_jump
:
2994 emit_jump(ctx
, nir_instr_as_jump(instr
));
2996 case nir_instr_type_phi
:
2997 /* we have converted phi webs to regs in NIR by now */
2998 compile_error(ctx
, "Unexpected NIR instruction type: %d\n", instr
->type
);
3000 case nir_instr_type_call
:
3001 case nir_instr_type_parallel_copy
:
3002 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
3007 static struct ir3_block
*
3008 get_block(struct ir3_context
*ctx
, const nir_block
*nblock
)
3010 struct ir3_block
*block
;
3011 struct hash_entry
*hentry
;
3012 struct set_entry
*sentry
;
3015 hentry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
3017 return hentry
->data
;
3019 block
= ir3_block_create(ctx
->ir
);
3020 block
->nblock
= nblock
;
3021 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
3023 block
->predecessors_count
= nblock
->predecessors
->entries
;
3024 block
->predecessors
= ralloc_array_size(block
,
3025 sizeof(block
->predecessors
[0]), block
->predecessors_count
);
3027 set_foreach(nblock
->predecessors
, sentry
) {
3028 block
->predecessors
[i
++] = get_block(ctx
, sentry
->key
);
3035 emit_block(struct ir3_context
*ctx
, nir_block
*nblock
)
3037 struct ir3_block
*block
= get_block(ctx
, nblock
);
3039 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
3040 if (nblock
->successors
[i
]) {
3041 block
->successors
[i
] =
3042 get_block(ctx
, nblock
->successors
[i
]);
3047 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
3049 /* re-emit addr register in each block if needed: */
3050 for (int i
= 0; i
< ARRAY_SIZE(ctx
->addr_ht
); i
++) {
3051 _mesa_hash_table_destroy(ctx
->addr_ht
[i
], NULL
);
3052 ctx
->addr_ht
[i
] = NULL
;
3055 nir_foreach_instr(instr
, nblock
) {
3056 emit_instr(ctx
, instr
);
3062 static void emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
);
3065 emit_if(struct ir3_context
*ctx
, nir_if
*nif
)
3067 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
3069 ctx
->block
->condition
=
3070 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
3072 emit_cf_list(ctx
, &nif
->then_list
);
3073 emit_cf_list(ctx
, &nif
->else_list
);
3077 emit_loop(struct ir3_context
*ctx
, nir_loop
*nloop
)
3079 emit_cf_list(ctx
, &nloop
->body
);
3083 emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
)
3085 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
3086 switch (node
->type
) {
3087 case nir_cf_node_block
:
3088 emit_block(ctx
, nir_cf_node_as_block(node
));
3090 case nir_cf_node_if
:
3091 emit_if(ctx
, nir_cf_node_as_if(node
));
3093 case nir_cf_node_loop
:
3094 emit_loop(ctx
, nir_cf_node_as_loop(node
));
3096 case nir_cf_node_function
:
3097 compile_error(ctx
, "TODO\n");
3103 /* emit stream-out code. At this point, the current block is the original
3104 * (nir) end block, and nir ensures that all flow control paths terminate
3105 * into the end block. We re-purpose the original end block to generate
3106 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
3107 * block holding stream-out write instructions, followed by the new end
3111 * p0.x = (vtxcnt < maxvtxcnt)
3112 * // succs: blockStreamOut, blockNewEnd
3115 * ... stream-out instructions ...
3116 * // succs: blockNewEnd
3122 emit_stream_out(struct ir3_context
*ctx
)
3124 struct ir3_shader_variant
*v
= ctx
->so
;
3125 struct ir3
*ir
= ctx
->ir
;
3126 struct pipe_stream_output_info
*strmout
=
3127 &ctx
->so
->shader
->stream_output
;
3128 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
3129 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
3130 struct ir3_instruction
*bases
[PIPE_MAX_SO_BUFFERS
];
3132 /* create vtxcnt input in input block at top of shader,
3133 * so that it is seen as live over the entire duration
3136 vtxcnt
= create_input(ctx
->in_block
, 0);
3137 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
3139 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
3141 /* at this point, we are at the original 'end' block,
3142 * re-purpose this block to stream-out condition, then
3143 * append stream-out block and new-end block
3145 orig_end_block
= ctx
->block
;
3147 // TODO these blocks need to update predecessors..
3148 // maybe w/ store_global intrinsic, we could do this
3149 // stuff in nir->nir pass
3151 stream_out_block
= ir3_block_create(ir
);
3152 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
3154 new_end_block
= ir3_block_create(ir
);
3155 list_addtail(&new_end_block
->node
, &ir
->block_list
);
3157 orig_end_block
->successors
[0] = stream_out_block
;
3158 orig_end_block
->successors
[1] = new_end_block
;
3159 stream_out_block
->successors
[0] = new_end_block
;
3161 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
3162 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
3163 cond
->regs
[0]->num
= regid(REG_P0
, 0);
3164 cond
->cat2
.condition
= IR3_COND_LT
;
3166 /* condition goes on previous block to the conditional,
3167 * since it is used to pick which of the two successor
3170 orig_end_block
->condition
= cond
;
3172 /* switch to stream_out_block to generate the stream-out
3175 ctx
->block
= stream_out_block
;
3177 /* Calculate base addresses based on vtxcnt. Instructions
3178 * generated for bases not used in following loop will be
3179 * stripped out in the backend.
3181 for (unsigned i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
3182 unsigned stride
= strmout
->stride
[i
];
3183 struct ir3_instruction
*base
, *off
;
3185 base
= create_uniform(ctx
, regid(v
->constbase
.tfbo
, i
));
3187 /* 24-bit should be enough: */
3188 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
3189 create_immed(ctx
->block
, stride
* 4), 0);
3191 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
3194 /* Generate the per-output store instructions: */
3195 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
3196 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
3197 unsigned c
= j
+ strmout
->output
[i
].start_component
;
3198 struct ir3_instruction
*base
, *out
, *stg
;
3200 base
= bases
[strmout
->output
[i
].output_buffer
];
3201 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
3203 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
3204 create_immed(ctx
->block
, 1), 0);
3205 stg
->cat6
.type
= TYPE_U32
;
3206 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
3208 array_insert(ctx
->block
, ctx
->block
->keeps
, stg
);
3212 /* and finally switch to the new_end_block: */
3213 ctx
->block
= new_end_block
;
3217 emit_function(struct ir3_context
*ctx
, nir_function_impl
*impl
)
3219 nir_metadata_require(impl
, nir_metadata_block_index
);
3221 emit_cf_list(ctx
, &impl
->body
);
3222 emit_block(ctx
, impl
->end_block
);
3224 /* at this point, we should have a single empty block,
3225 * into which we emit the 'end' instruction.
3227 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
3229 /* If stream-out (aka transform-feedback) enabled, emit the
3230 * stream-out instructions, followed by a new empty block (into
3231 * which the 'end' instruction lands).
3233 * NOTE: it is done in this order, rather than inserting before
3234 * we emit end_block, because NIR guarantees that all blocks
3235 * flow into end_block, and that end_block has no successors.
3236 * So by re-purposing end_block as the first block of stream-
3237 * out, we guarantee that all exit paths flow into the stream-
3240 if ((ctx
->compiler
->gpu_id
< 500) &&
3241 (ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
3242 !ctx
->so
->key
.binning_pass
) {
3243 debug_assert(ctx
->so
->type
== SHADER_VERTEX
);
3244 emit_stream_out(ctx
);
3247 ir3_END(ctx
->block
);
3251 setup_input(struct ir3_context
*ctx
, nir_variable
*in
)
3253 struct ir3_shader_variant
*so
= ctx
->so
;
3254 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
3255 unsigned ncomp
= glsl_get_components(in
->type
);
3256 unsigned n
= in
->data
.driver_location
;
3257 unsigned slot
= in
->data
.location
;
3259 DBG("; in: slot=%u, len=%ux%u, drvloc=%u",
3260 slot
, array_len
, ncomp
, n
);
3262 /* let's pretend things other than vec4 don't exist: */
3263 ncomp
= MAX2(ncomp
, 4);
3264 compile_assert(ctx
, ncomp
== 4);
3266 so
->inputs
[n
].slot
= slot
;
3267 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
3268 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
3269 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
3271 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3272 for (int i
= 0; i
< ncomp
; i
++) {
3273 struct ir3_instruction
*instr
= NULL
;
3274 unsigned idx
= (n
* 4) + i
;
3276 if (slot
== VARYING_SLOT_POS
) {
3277 so
->inputs
[n
].bary
= false;
3278 so
->frag_coord
= true;
3279 instr
= create_frag_coord(ctx
, i
);
3280 } else if (slot
== VARYING_SLOT_PNTC
) {
3281 /* see for example st_get_generic_varying_index().. this is
3282 * maybe a bit mesa/st specific. But we need things to line
3283 * up for this in fdN_program:
3284 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
3285 * if (emit->sprite_coord_enable & texmask) {
3289 so
->inputs
[n
].slot
= VARYING_SLOT_VAR8
;
3290 so
->inputs
[n
].bary
= true;
3291 instr
= create_frag_input(ctx
, false);
3293 bool use_ldlv
= false;
3295 /* detect the special case for front/back colors where
3296 * we need to do flat vs smooth shading depending on
3299 if (in
->data
.interpolation
== INTERP_MODE_NONE
) {
3301 case VARYING_SLOT_COL0
:
3302 case VARYING_SLOT_COL1
:
3303 case VARYING_SLOT_BFC0
:
3304 case VARYING_SLOT_BFC1
:
3305 so
->inputs
[n
].rasterflat
= true;
3312 if (ctx
->flat_bypass
) {
3313 if ((so
->inputs
[n
].interpolate
== INTERP_MODE_FLAT
) ||
3314 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
3318 so
->inputs
[n
].bary
= true;
3320 instr
= create_frag_input(ctx
, use_ldlv
);
3323 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
3325 ctx
->ir
->inputs
[idx
] = instr
;
3327 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
3328 for (int i
= 0; i
< ncomp
; i
++) {
3329 unsigned idx
= (n
* 4) + i
;
3330 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
3331 ctx
->ir
->inputs
[idx
] = create_input(ctx
->block
, idx
);
3334 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3337 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
3338 so
->total_in
+= ncomp
;
3343 setup_output(struct ir3_context
*ctx
, nir_variable
*out
)
3345 struct ir3_shader_variant
*so
= ctx
->so
;
3346 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
3347 unsigned ncomp
= glsl_get_components(out
->type
);
3348 unsigned n
= out
->data
.driver_location
;
3349 unsigned slot
= out
->data
.location
;
3352 DBG("; out: slot=%u, len=%ux%u, drvloc=%u",
3353 slot
, array_len
, ncomp
, n
);
3355 /* let's pretend things other than vec4 don't exist: */
3356 ncomp
= MAX2(ncomp
, 4);
3357 compile_assert(ctx
, ncomp
== 4);
3359 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3361 case FRAG_RESULT_DEPTH
:
3362 comp
= 2; /* tgsi will write to .z component */
3363 so
->writes_pos
= true;
3365 case FRAG_RESULT_COLOR
:
3369 if (slot
>= FRAG_RESULT_DATA0
)
3371 compile_error(ctx
, "unknown FS output name: %s\n",
3372 gl_frag_result_name(slot
));
3374 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
3376 case VARYING_SLOT_POS
:
3377 so
->writes_pos
= true;
3379 case VARYING_SLOT_PSIZ
:
3380 so
->writes_psize
= true;
3382 case VARYING_SLOT_COL0
:
3383 case VARYING_SLOT_COL1
:
3384 case VARYING_SLOT_BFC0
:
3385 case VARYING_SLOT_BFC1
:
3386 case VARYING_SLOT_FOGC
:
3387 case VARYING_SLOT_CLIP_DIST0
:
3388 case VARYING_SLOT_CLIP_DIST1
:
3389 case VARYING_SLOT_CLIP_VERTEX
:
3392 if (slot
>= VARYING_SLOT_VAR0
)
3394 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
3396 compile_error(ctx
, "unknown VS output name: %s\n",
3397 gl_varying_slot_name(slot
));
3400 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3403 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
3405 so
->outputs
[n
].slot
= slot
;
3406 so
->outputs
[n
].regid
= regid(n
, comp
);
3407 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
3409 for (int i
= 0; i
< ncomp
; i
++) {
3410 unsigned idx
= (n
* 4) + i
;
3411 compile_assert(ctx
, idx
< ctx
->ir
->noutputs
);
3412 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
3417 max_drvloc(struct exec_list
*vars
)
3420 nir_foreach_variable(var
, vars
) {
3421 drvloc
= MAX2(drvloc
, (int)var
->data
.driver_location
);
3426 static const unsigned max_sysvals
[SHADER_MAX
] = {
3427 [SHADER_FRAGMENT
] = 8,
3428 [SHADER_VERTEX
] = 16,
3429 [SHADER_COMPUTE
] = 16, // TODO how many do we actually need?
3433 emit_instructions(struct ir3_context
*ctx
)
3435 unsigned ninputs
, noutputs
;
3436 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
3438 ninputs
= (max_drvloc(&ctx
->s
->inputs
) + 1) * 4;
3439 noutputs
= (max_drvloc(&ctx
->s
->outputs
) + 1) * 4;
3441 /* we need to leave room for sysvals:
3443 ninputs
+= max_sysvals
[ctx
->so
->type
];
3445 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
3447 /* Create inputs in first block: */
3448 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
3449 ctx
->in_block
= ctx
->block
;
3450 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
3452 ninputs
-= max_sysvals
[ctx
->so
->type
];
3454 /* for fragment shader, we have a single input register (usually
3455 * r0.xy) which is used as the base for bary.f varying fetch instrs:
3457 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3458 // TODO maybe a helper for fi since we need it a few places..
3459 struct ir3_instruction
*instr
;
3460 instr
= ir3_instr_create(ctx
->block
, OPC_META_FI
);
3461 ir3_reg_create(instr
, 0, 0);
3462 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.x */
3463 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.y */
3464 ctx
->frag_pos
= instr
;
3468 nir_foreach_variable(var
, &ctx
->s
->inputs
) {
3469 setup_input(ctx
, var
);
3472 /* Setup outputs: */
3473 nir_foreach_variable(var
, &ctx
->s
->outputs
) {
3474 setup_output(ctx
, var
);
3477 /* Setup registers (which should only be arrays): */
3478 nir_foreach_register(reg
, &ctx
->s
->registers
) {
3479 declare_array(ctx
, reg
);
3482 /* NOTE: need to do something more clever when we support >1 fxn */
3483 nir_foreach_register(reg
, &fxn
->registers
) {
3484 declare_array(ctx
, reg
);
3486 /* And emit the body: */
3488 emit_function(ctx
, fxn
);
3491 /* from NIR perspective, we actually have inputs. But most of the "inputs"
3492 * for a fragment shader are just bary.f instructions. The *actual* inputs
3493 * from the hw perspective are the frag_pos and optionally frag_coord and
3497 fixup_frag_inputs(struct ir3_context
*ctx
)
3499 struct ir3_shader_variant
*so
= ctx
->so
;
3500 struct ir3
*ir
= ctx
->ir
;
3501 struct ir3_instruction
**inputs
;
3502 struct ir3_instruction
*instr
;
3507 n
= 4; /* always have frag_pos */
3508 n
+= COND(so
->frag_face
, 4);
3509 n
+= COND(so
->frag_coord
, 4);
3511 inputs
= ir3_alloc(ctx
->ir
, n
* (sizeof(struct ir3_instruction
*)));
3513 if (so
->frag_face
) {
3514 /* this ultimately gets assigned to hr0.x so doesn't conflict
3515 * with frag_coord/frag_pos..
3517 inputs
[ir
->ninputs
++] = ctx
->frag_face
;
3518 ctx
->frag_face
->regs
[0]->num
= 0;
3520 /* remaining channels not used, but let's avoid confusing
3521 * other parts that expect inputs to come in groups of vec4
3523 inputs
[ir
->ninputs
++] = NULL
;
3524 inputs
[ir
->ninputs
++] = NULL
;
3525 inputs
[ir
->ninputs
++] = NULL
;
3528 /* since we don't know where to set the regid for frag_coord,
3529 * we have to use r0.x for it. But we don't want to *always*
3530 * use r1.x for frag_pos as that could increase the register
3531 * footprint on simple shaders:
3533 if (so
->frag_coord
) {
3534 ctx
->frag_coord
[0]->regs
[0]->num
= regid
++;
3535 ctx
->frag_coord
[1]->regs
[0]->num
= regid
++;
3536 ctx
->frag_coord
[2]->regs
[0]->num
= regid
++;
3537 ctx
->frag_coord
[3]->regs
[0]->num
= regid
++;
3539 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[0];
3540 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[1];
3541 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[2];
3542 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[3];
3545 /* we always have frag_pos: */
3546 so
->pos_regid
= regid
;
3549 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
3550 instr
->regs
[0]->num
= regid
++;
3551 inputs
[ir
->ninputs
++] = instr
;
3552 ctx
->frag_pos
->regs
[1]->instr
= instr
;
3555 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
3556 instr
->regs
[0]->num
= regid
++;
3557 inputs
[ir
->ninputs
++] = instr
;
3558 ctx
->frag_pos
->regs
[2]->instr
= instr
;
3560 ir
->inputs
= inputs
;
3563 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3564 * need to assign the tex state indexes for these after we know the
3568 fixup_astc_srgb(struct ir3_context
*ctx
)
3570 struct ir3_shader_variant
*so
= ctx
->so
;
3571 /* indexed by original tex idx, value is newly assigned alpha sampler
3572 * state tex idx. Zero is invalid since there is at least one sampler
3575 unsigned alt_tex_state
[16] = {0};
3576 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
3579 so
->astc_srgb
.base
= tex_idx
;
3581 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
3582 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
3584 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
3586 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
3587 /* assign new alternate/alpha tex state slot: */
3588 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
3589 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
3590 so
->astc_srgb
.count
++;
3593 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
3598 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
3599 struct ir3_shader_variant
*so
)
3601 struct ir3_context
*ctx
;
3603 struct ir3_instruction
**inputs
;
3604 unsigned i
, j
, actual_in
, inloc
;
3605 int ret
= 0, max_bary
;
3609 ctx
= compile_init(compiler
, so
);
3611 DBG("INIT failed!");
3616 emit_instructions(ctx
);
3619 DBG("EMIT failed!");
3624 ir
= so
->ir
= ctx
->ir
;
3626 /* keep track of the inputs from TGSI perspective.. */
3627 inputs
= ir
->inputs
;
3629 /* but fixup actual inputs for frag shader: */
3630 if (so
->type
== SHADER_FRAGMENT
)
3631 fixup_frag_inputs(ctx
);
3633 /* at this point, for binning pass, throw away unneeded outputs: */
3634 if (so
->key
.binning_pass
) {
3635 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
3636 unsigned slot
= so
->outputs
[i
].slot
;
3638 /* throw away everything but first position/psize */
3639 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
3641 so
->outputs
[j
] = so
->outputs
[i
];
3642 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
3643 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
3644 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
3645 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
3650 so
->outputs_count
= j
;
3651 ir
->noutputs
= j
* 4;
3654 /* if we want half-precision outputs, mark the output registers
3657 if (so
->key
.half_precision
) {
3658 for (i
= 0; i
< ir
->noutputs
; i
++) {
3659 struct ir3_instruction
*out
= ir
->outputs
[i
];
3664 /* if frag shader writes z, that needs to be full precision: */
3665 if (so
->outputs
[i
/4].slot
== FRAG_RESULT_DEPTH
)
3668 out
->regs
[0]->flags
|= IR3_REG_HALF
;
3669 /* output could be a fanout (ie. texture fetch output)
3670 * in which case we need to propagate the half-reg flag
3671 * up to the definer so that RA sees it:
3673 if (out
->opc
== OPC_META_FO
) {
3674 out
= out
->regs
[1]->instr
;
3675 out
->regs
[0]->flags
|= IR3_REG_HALF
;
3678 if (out
->opc
== OPC_MOV
) {
3679 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
3684 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3685 printf("BEFORE CP:\n");
3691 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3692 printf("BEFORE GROUPING:\n");
3696 ir3_sched_add_deps(ir
);
3698 /* Group left/right neighbors, inserting mov's where needed to
3703 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3704 printf("AFTER GROUPING:\n");
3710 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3711 printf("AFTER DEPTH:\n");
3715 ret
= ir3_sched(ir
);
3717 DBG("SCHED failed!");
3721 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3722 printf("AFTER SCHED:\n");
3726 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
3732 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3733 printf("AFTER RA:\n");
3737 /* fixup input/outputs: */
3738 for (i
= 0; i
< so
->outputs_count
; i
++) {
3739 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
3742 /* Note that some or all channels of an input may be unused: */
3745 for (i
= 0; i
< so
->inputs_count
; i
++) {
3746 unsigned j
, regid
= ~0, compmask
= 0, maxcomp
= 0;
3747 so
->inputs
[i
].ncomp
= 0;
3748 so
->inputs
[i
].inloc
= inloc
;
3749 for (j
= 0; j
< 4; j
++) {
3750 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
3751 if (in
&& !(in
->flags
& IR3_INSTR_UNUSED
)) {
3752 compmask
|= (1 << j
);
3753 regid
= in
->regs
[0]->num
- j
;
3755 so
->inputs
[i
].ncomp
++;
3756 if ((so
->type
== SHADER_FRAGMENT
) && so
->inputs
[i
].bary
) {
3758 assert(in
->regs
[1]->flags
& IR3_REG_IMMED
);
3759 in
->regs
[1]->iim_val
= inloc
+ j
;
3764 if ((so
->type
== SHADER_FRAGMENT
) && compmask
&& so
->inputs
[i
].bary
) {
3766 so
->inputs
[i
].compmask
= (1 << maxcomp
) - 1;
3768 } else if (!so
->inputs
[i
].sysval
) {
3769 so
->inputs
[i
].compmask
= compmask
;
3771 so
->inputs
[i
].regid
= regid
;
3775 fixup_astc_srgb(ctx
);
3777 /* We need to do legalize after (for frag shader's) the "bary.f"
3778 * offsets (inloc) have been assigned.
3780 ir3_legalize(ir
, &so
->has_samp
, &so
->has_ssbo
, &max_bary
);
3782 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3783 printf("AFTER LEGALIZE:\n");
3787 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3788 if (so
->type
== SHADER_VERTEX
)
3789 so
->total_in
= actual_in
;
3791 so
->total_in
= max_bary
+ 1;
3796 ir3_destroy(so
->ir
);