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freedreno/ir3/nir: split out tex helpers
[mesa.git] / src / gallium / drivers / freedreno / ir3 / ir3_compiler_nir.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include <stdarg.h>
30
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
35 #include "tgsi/tgsi_lowering.h"
36 #include "tgsi/tgsi_strings.h"
37
38 #include "nir/tgsi_to_nir.h"
39 #include "glsl/shader_enums.h"
40
41 #include "freedreno_util.h"
42
43 #include "ir3_compiler.h"
44 #include "ir3_shader.h"
45
46 #include "instr-a3xx.h"
47 #include "ir3.h"
48
49
50 static struct ir3_instruction * create_immed(struct ir3_block *block, uint32_t val);
51
52 struct ir3_compile {
53 const struct tgsi_token *tokens;
54 struct nir_shader *s;
55
56 struct ir3 *ir;
57 struct ir3_shader_variant *so;
58
59 /* bitmask of which samplers are integer: */
60 uint16_t integer_s;
61
62 struct ir3_block *block;
63
64 /* For fragment shaders, from the hw perspective the only
65 * actual input is r0.xy position register passed to bary.f.
66 * But TGSI doesn't know that, it still declares things as
67 * IN[] registers. So we do all the input tracking normally
68 * and fix things up after compile_instructions()
69 *
70 * NOTE that frag_pos is the hardware position (possibly it
71 * is actually an index or tag or some such.. it is *not*
72 * values that can be directly used for gl_FragCoord..)
73 */
74 struct ir3_instruction *frag_pos, *frag_face, *frag_coord[4];
75
76 /* For vertex shaders, keep track of the system values sources */
77 struct ir3_instruction *vertex_id, *basevertex, *instance_id;
78
79 /* mapping from nir_register to defining instruction: */
80 struct hash_table *def_ht;
81
82 /* mapping from nir_variable to ir3_array: */
83 struct hash_table *var_ht;
84 unsigned num_arrays;
85
86 /* a common pattern for indirect addressing is to request the
87 * same address register multiple times. To avoid generating
88 * duplicate instruction sequences (which our backend does not
89 * try to clean up, since that should be done as the NIR stage)
90 * we cache the address value generated for a given src value:
91 */
92 struct hash_table *addr_ht;
93
94 /* for calculating input/output positions/linkages: */
95 unsigned next_inloc;
96
97 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
98 * so we need to use ldlv.u32 to load the varying directly:
99 */
100 bool flat_bypass;
101
102 /* for looking up which system value is which */
103 unsigned sysval_semantics[8];
104
105 /* list of kill instructions: */
106 struct ir3_instruction *kill[16];
107 unsigned int kill_count;
108
109 /* set if we encounter something we can't handle yet, so we
110 * can bail cleanly and fallback to TGSI compiler f/e
111 */
112 bool error;
113 };
114
115
116 static struct nir_shader *to_nir(const struct tgsi_token *tokens)
117 {
118 struct nir_shader_compiler_options options = {
119 .lower_fpow = true,
120 .lower_fsat = true,
121 .lower_scmp = true,
122 .lower_flrp = true,
123 .native_integers = true,
124 };
125 bool progress;
126
127 struct nir_shader *s = tgsi_to_nir(tokens, &options);
128
129 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
130 debug_printf("----------------------\n");
131 nir_print_shader(s, stdout);
132 debug_printf("----------------------\n");
133 }
134
135 nir_opt_global_to_local(s);
136 nir_convert_to_ssa(s);
137 nir_lower_idiv(s);
138
139 do {
140 progress = false;
141
142 nir_lower_vars_to_ssa(s);
143 nir_lower_alu_to_scalar(s);
144
145 progress |= nir_copy_prop(s);
146 progress |= nir_opt_dce(s);
147 progress |= nir_opt_cse(s);
148 progress |= nir_opt_peephole_select(s);
149 progress |= nir_opt_algebraic(s);
150 progress |= nir_opt_constant_folding(s);
151
152 } while (progress);
153
154 nir_remove_dead_variables(s);
155 nir_validate_shader(s);
156
157 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
158 debug_printf("----------------------\n");
159 nir_print_shader(s, stdout);
160 debug_printf("----------------------\n");
161 }
162
163 return s;
164 }
165
166 /* TODO nir doesn't lower everything for us yet, but ideally it would: */
167 static const struct tgsi_token *
168 lower_tgsi(const struct tgsi_token *tokens, struct ir3_shader_variant *so)
169 {
170 struct tgsi_shader_info info;
171 struct tgsi_lowering_config lconfig = {
172 .color_two_side = so->key.color_two_side,
173 .lower_FRC = true,
174 };
175
176 switch (so->type) {
177 case SHADER_FRAGMENT:
178 case SHADER_COMPUTE:
179 lconfig.saturate_s = so->key.fsaturate_s;
180 lconfig.saturate_t = so->key.fsaturate_t;
181 lconfig.saturate_r = so->key.fsaturate_r;
182 break;
183 case SHADER_VERTEX:
184 lconfig.saturate_s = so->key.vsaturate_s;
185 lconfig.saturate_t = so->key.vsaturate_t;
186 lconfig.saturate_r = so->key.vsaturate_r;
187 break;
188 }
189
190 if (!so->shader) {
191 /* hack for standalone compiler which does not have
192 * screen/context:
193 */
194 } else if (ir3_shader_gpuid(so->shader) >= 400) {
195 /* a4xx seems to have *no* sam.p */
196 lconfig.lower_TXP = ~0; /* lower all txp */
197 } else {
198 /* a3xx just needs to avoid sam.p for 3d tex */
199 lconfig.lower_TXP = (1 << TGSI_TEXTURE_3D);
200 }
201
202 return tgsi_transform_lowering(&lconfig, tokens, &info);
203 }
204
205 static struct ir3_compile *
206 compile_init(struct ir3_shader_variant *so,
207 const struct tgsi_token *tokens)
208 {
209 struct ir3_compile *ctx = rzalloc(NULL, struct ir3_compile);
210 const struct tgsi_token *lowered_tokens;
211
212 if (!so->shader) {
213 /* hack for standalone compiler which does not have
214 * screen/context:
215 */
216 } else if (ir3_shader_gpuid(so->shader) >= 400) {
217 /* need special handling for "flat" */
218 ctx->flat_bypass = true;
219 } else {
220 /* no special handling for "flat" */
221 ctx->flat_bypass = false;
222 }
223
224 switch (so->type) {
225 case SHADER_FRAGMENT:
226 case SHADER_COMPUTE:
227 ctx->integer_s = so->key.finteger_s;
228 break;
229 case SHADER_VERTEX:
230 ctx->integer_s = so->key.vinteger_s;
231 break;
232 }
233
234 ctx->ir = so->ir;
235 ctx->so = so;
236 ctx->next_inloc = 8;
237 ctx->def_ht = _mesa_hash_table_create(ctx,
238 _mesa_hash_pointer, _mesa_key_pointer_equal);
239 ctx->var_ht = _mesa_hash_table_create(ctx,
240 _mesa_hash_pointer, _mesa_key_pointer_equal);
241 ctx->addr_ht = _mesa_hash_table_create(ctx,
242 _mesa_hash_pointer, _mesa_key_pointer_equal);
243
244 lowered_tokens = lower_tgsi(tokens, so);
245 if (!lowered_tokens)
246 lowered_tokens = tokens;
247 ctx->s = to_nir(lowered_tokens);
248
249 if (lowered_tokens != tokens)
250 free((void *)lowered_tokens);
251
252 so->first_immediate = ctx->s->num_uniforms;
253 /* for now, now driver params: */
254 so->first_driver_param = so->first_immediate;
255
256 return ctx;
257 }
258
259 static void
260 compile_error(struct ir3_compile *ctx, const char *format, ...)
261 {
262 va_list ap;
263 va_start(ap, format);
264 _debug_vprintf(format, ap);
265 va_end(ap);
266 nir_print_shader(ctx->s, stdout);
267 ctx->error = true;
268 debug_assert(0);
269 }
270
271 #define compile_assert(ctx, cond) do { \
272 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
273 } while (0)
274
275 static void
276 compile_free(struct ir3_compile *ctx)
277 {
278 ralloc_free(ctx);
279 }
280
281
282 struct ir3_array {
283 unsigned length, aid;
284 struct ir3_instruction *arr[];
285 };
286
287 static void
288 declare_var(struct ir3_compile *ctx, nir_variable *var)
289 {
290 unsigned length = glsl_get_length(var->type) * 4; /* always vec4, at least with ttn */
291 struct ir3_array *arr = ralloc_size(ctx, sizeof(*arr) +
292 (length * sizeof(arr->arr[0])));
293 arr->length = length;
294 arr->aid = ++ctx->num_arrays;
295 _mesa_hash_table_insert(ctx->var_ht, var, arr);
296 }
297
298 static struct ir3_array *
299 get_var(struct ir3_compile *ctx, nir_variable *var)
300 {
301 struct hash_entry *entry = _mesa_hash_table_search(ctx->var_ht, var);
302 return entry->data;
303 }
304
305 /* allocate a n element value array (to be populated by caller) and
306 * insert in def_ht
307 */
308 static struct ir3_instruction **
309 __get_dst(struct ir3_compile *ctx, void *key, unsigned n)
310 {
311 struct ir3_instruction **value =
312 ralloc_array(ctx->def_ht, struct ir3_instruction *, n);
313 _mesa_hash_table_insert(ctx->def_ht, key, value);
314 return value;
315 }
316
317 static struct ir3_instruction **
318 get_dst(struct ir3_compile *ctx, nir_dest *dst, unsigned n)
319 {
320 if (dst->is_ssa) {
321 return __get_dst(ctx, &dst->ssa, n);
322 } else {
323 return __get_dst(ctx, dst->reg.reg, n);
324 }
325 }
326
327 static struct ir3_instruction **
328 get_dst_ssa(struct ir3_compile *ctx, nir_ssa_def *dst, unsigned n)
329 {
330 return __get_dst(ctx, dst, n);
331 }
332
333 static struct ir3_instruction **
334 get_src(struct ir3_compile *ctx, nir_src *src)
335 {
336 struct hash_entry *entry;
337 if (src->is_ssa) {
338 entry = _mesa_hash_table_search(ctx->def_ht, src->ssa);
339 } else {
340 entry = _mesa_hash_table_search(ctx->def_ht, src->reg.reg);
341 }
342 compile_assert(ctx, entry);
343 return entry->data;
344 }
345
346 static struct ir3_instruction *
347 create_immed(struct ir3_block *block, uint32_t val)
348 {
349 struct ir3_instruction *mov;
350
351 mov = ir3_instr_create(block, 1, 0);
352 mov->cat1.src_type = TYPE_U32;
353 mov->cat1.dst_type = TYPE_U32;
354 ir3_reg_create(mov, 0, 0);
355 ir3_reg_create(mov, 0, IR3_REG_IMMED)->uim_val = val;
356
357 return mov;
358 }
359
360 static struct ir3_instruction *
361 create_addr(struct ir3_block *block, struct ir3_instruction *src)
362 {
363 struct ir3_instruction *instr, *immed;
364
365 /* TODO in at least some cases, the backend could probably be
366 * made clever enough to propagate IR3_REG_HALF..
367 */
368 instr = ir3_COV(block, src, TYPE_U32, TYPE_S16);
369 instr->regs[0]->flags |= IR3_REG_HALF;
370
371 immed = create_immed(block, 2);
372 immed->regs[0]->flags |= IR3_REG_HALF;
373
374 instr = ir3_SHL_B(block, instr, 0, immed, 0);
375 instr->regs[0]->flags |= IR3_REG_HALF;
376 instr->regs[1]->flags |= IR3_REG_HALF;
377
378 instr = ir3_MOV(block, instr, TYPE_S16);
379 instr->regs[0]->flags |= IR3_REG_ADDR | IR3_REG_HALF;
380 instr->regs[1]->flags |= IR3_REG_HALF;
381
382 return instr;
383 }
384
385 /* caches addr values to avoid generating multiple cov/shl/mova
386 * sequences for each use of a given NIR level src as address
387 */
388 static struct ir3_instruction *
389 get_addr(struct ir3_compile *ctx, struct ir3_instruction *src)
390 {
391 struct ir3_instruction *addr;
392 struct hash_entry *entry;
393 entry = _mesa_hash_table_search(ctx->addr_ht, src);
394 if (entry)
395 return entry->data;
396
397 /* TODO do we need to cache per block? */
398 addr = create_addr(ctx->block, src);
399 _mesa_hash_table_insert(ctx->addr_ht, src, addr);
400
401 return addr;
402 }
403
404 static struct ir3_instruction *
405 create_uniform(struct ir3_compile *ctx, unsigned n)
406 {
407 struct ir3_instruction *mov;
408
409 mov = ir3_instr_create(ctx->block, 1, 0);
410 /* TODO get types right? */
411 mov->cat1.src_type = TYPE_F32;
412 mov->cat1.dst_type = TYPE_F32;
413 ir3_reg_create(mov, 0, 0);
414 ir3_reg_create(mov, n, IR3_REG_CONST);
415
416 return mov;
417 }
418
419 static struct ir3_instruction *
420 create_uniform_indirect(struct ir3_compile *ctx, unsigned n,
421 struct ir3_instruction *address)
422 {
423 struct ir3_instruction *mov;
424
425 mov = ir3_instr_create(ctx->block, 1, 0);
426 mov->cat1.src_type = TYPE_U32;
427 mov->cat1.dst_type = TYPE_U32;
428 ir3_reg_create(mov, 0, 0);
429 ir3_reg_create(mov, n, IR3_REG_CONST | IR3_REG_RELATIV);
430 mov->address = address;
431
432 array_insert(ctx->ir->indirects, mov);
433
434 return mov;
435 }
436
437 static struct ir3_instruction *
438 create_collect(struct ir3_block *block, struct ir3_instruction **arr,
439 unsigned arrsz)
440 {
441 struct ir3_instruction *collect;
442
443 if (arrsz == 0)
444 return NULL;
445
446 collect = ir3_instr_create2(block, -1, OPC_META_FI, 1 + arrsz);
447 ir3_reg_create(collect, 0, 0);
448 for (unsigned i = 0; i < arrsz; i++)
449 ir3_reg_create(collect, 0, IR3_REG_SSA)->instr = arr[i];
450
451 return collect;
452 }
453
454 static struct ir3_instruction *
455 create_indirect_load(struct ir3_compile *ctx, unsigned arrsz, unsigned n,
456 struct ir3_instruction *address, struct ir3_instruction *collect)
457 {
458 struct ir3_block *block = ctx->block;
459 struct ir3_instruction *mov;
460 struct ir3_register *src;
461
462 mov = ir3_instr_create(block, 1, 0);
463 mov->cat1.src_type = TYPE_U32;
464 mov->cat1.dst_type = TYPE_U32;
465 ir3_reg_create(mov, 0, 0);
466 src = ir3_reg_create(mov, 0, IR3_REG_SSA | IR3_REG_RELATIV);
467 src->instr = collect;
468 src->size = arrsz;
469 src->offset = n;
470 mov->address = address;
471
472 array_insert(ctx->ir->indirects, mov);
473
474 return mov;
475 }
476
477 static struct ir3_instruction *
478 create_indirect_store(struct ir3_compile *ctx, unsigned arrsz, unsigned n,
479 struct ir3_instruction *src, struct ir3_instruction *address,
480 struct ir3_instruction *collect)
481 {
482 struct ir3_block *block = ctx->block;
483 struct ir3_instruction *mov;
484 struct ir3_register *dst;
485
486 mov = ir3_instr_create(block, 1, 0);
487 mov->cat1.src_type = TYPE_U32;
488 mov->cat1.dst_type = TYPE_U32;
489 dst = ir3_reg_create(mov, 0, IR3_REG_RELATIV);
490 dst->size = arrsz;
491 dst->offset = n;
492 ir3_reg_create(mov, 0, IR3_REG_SSA)->instr = src;
493 mov->address = address;
494 mov->fanin = collect;
495
496 array_insert(ctx->ir->indirects, mov);
497
498 return mov;
499 }
500
501 static struct ir3_instruction *
502 create_input(struct ir3_block *block, struct ir3_instruction *instr,
503 unsigned n)
504 {
505 struct ir3_instruction *in;
506
507 in = ir3_instr_create(block, -1, OPC_META_INPUT);
508 in->inout.block = block;
509 ir3_reg_create(in, n, 0);
510 if (instr)
511 ir3_reg_create(in, 0, IR3_REG_SSA)->instr = instr;
512
513 return in;
514 }
515
516 static struct ir3_instruction *
517 create_frag_input(struct ir3_compile *ctx, unsigned n, bool use_ldlv)
518 {
519 struct ir3_block *block = ctx->block;
520 struct ir3_instruction *instr;
521 struct ir3_instruction *inloc = create_immed(block, n);
522
523 if (use_ldlv) {
524 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
525 instr->cat6.type = TYPE_U32;
526 instr->cat6.iim_val = 1;
527 } else {
528 instr = ir3_BARY_F(block, inloc, 0, ctx->frag_pos, 0);
529 instr->regs[2]->wrmask = 0x3;
530 }
531
532 return instr;
533 }
534
535 static struct ir3_instruction *
536 create_frag_coord(struct ir3_compile *ctx, unsigned comp)
537 {
538 struct ir3_block *block = ctx->block;
539 struct ir3_instruction *instr;
540
541 compile_assert(ctx, !ctx->frag_coord[comp]);
542
543 ctx->frag_coord[comp] = create_input(ctx->block, NULL, 0);
544
545 switch (comp) {
546 case 0: /* .x */
547 case 1: /* .y */
548 /* for frag_coord, we get unsigned values.. we need
549 * to subtract (integer) 8 and divide by 16 (right-
550 * shift by 4) then convert to float:
551 *
552 * add.s tmp, src, -8
553 * shr.b tmp, tmp, 4
554 * mov.u32f32 dst, tmp
555 *
556 */
557 instr = ir3_ADD_S(block, ctx->frag_coord[comp], 0,
558 create_immed(block, -8), 0);
559 instr = ir3_SHR_B(block, instr, 0,
560 create_immed(block, 4), 0);
561 instr = ir3_COV(block, instr, TYPE_U32, TYPE_F32);
562
563 return instr;
564 case 2: /* .z */
565 case 3: /* .w */
566 default:
567 /* seems that we can use these as-is: */
568 return ctx->frag_coord[comp];
569 }
570 }
571
572 static struct ir3_instruction *
573 create_frag_face(struct ir3_compile *ctx, unsigned comp)
574 {
575 struct ir3_block *block = ctx->block;
576 struct ir3_instruction *instr;
577
578 switch (comp) {
579 case 0: /* .x */
580 compile_assert(ctx, !ctx->frag_face);
581
582 ctx->frag_face = create_input(block, NULL, 0);
583
584 /* for faceness, we always get -1 or 0 (int).. but TGSI expects
585 * positive vs negative float.. and piglit further seems to
586 * expect -1.0 or 1.0:
587 *
588 * mul.s tmp, hr0.x, 2
589 * add.s tmp, tmp, 1
590 * mov.s32f32, dst, tmp
591 *
592 */
593 instr = ir3_MUL_S(block, ctx->frag_face, 0,
594 create_immed(block, 2), 0);
595 instr = ir3_ADD_S(block, instr, 0,
596 create_immed(block, 1), 0);
597 instr = ir3_COV(block, instr, TYPE_S32, TYPE_F32);
598
599 return instr;
600 case 1: /* .y */
601 case 2: /* .z */
602 return create_immed(block, fui(0.0));
603 default:
604 case 3: /* .w */
605 return create_immed(block, fui(1.0));
606 }
607 }
608
609 /* helper for instructions that produce multiple consecutive scalar
610 * outputs which need to have a split/fanout meta instruction inserted
611 */
612 static void
613 split_dest(struct ir3_block *block, struct ir3_instruction **dst,
614 struct ir3_instruction *src)
615 {
616 struct ir3_instruction *prev = NULL;
617 for (int i = 0, j = 0; i < 4; i++) {
618 struct ir3_instruction *split =
619 ir3_instr_create(block, -1, OPC_META_FO);
620 ir3_reg_create(split, 0, IR3_REG_SSA);
621 ir3_reg_create(split, 0, IR3_REG_SSA)->instr = src;
622 split->fo.off = i;
623
624 if (prev) {
625 split->cp.left = prev;
626 split->cp.left_cnt++;
627 prev->cp.right = split;
628 prev->cp.right_cnt++;
629 }
630 prev = split;
631
632 if (src->regs[0]->wrmask & (1 << i))
633 dst[j++] = split;
634 }
635 }
636
637 /*
638 * Adreno uses uint rather than having dedicated bool type,
639 * which (potentially) requires some conversion, in particular
640 * when using output of an bool instr to int input, or visa
641 * versa.
642 *
643 * | Adreno | NIR |
644 * -------+---------+-------+-
645 * true | 1 | ~0 |
646 * false | 0 | 0 |
647 *
648 * To convert from an adreno bool (uint) to nir, use:
649 *
650 * absneg.s dst, (neg)src
651 *
652 * To convert back in the other direction:
653 *
654 * absneg.s dst, (abs)arc
655 *
656 * The CP step can clean up the absneg.s that cancel each other
657 * out, and with a slight bit of extra cleverness (to recognize
658 * the instructions which produce either a 0 or 1) can eliminate
659 * the absneg.s's completely when an instruction that wants
660 * 0/1 consumes the result. For example, when a nir 'bcsel'
661 * consumes the result of 'feq'. So we should be able to get by
662 * without a boolean resolve step, and without incuring any
663 * extra penalty in instruction count.
664 */
665
666 /* NIR bool -> native (adreno): */
667 static struct ir3_instruction *
668 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
669 {
670 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
671 }
672
673 /* native (adreno) -> NIR bool: */
674 static struct ir3_instruction *
675 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
676 {
677 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
678 }
679
680 /*
681 * alu/sfu instructions:
682 */
683
684 static void
685 emit_alu(struct ir3_compile *ctx, nir_alu_instr *alu)
686 {
687 const nir_op_info *info = &nir_op_infos[alu->op];
688 struct ir3_instruction **dst, *src[info->num_inputs];
689 struct ir3_block *b = ctx->block;
690
691 dst = get_dst(ctx, &alu->dest.dest, MAX2(info->output_size, 1));
692
693 /* Vectors are special in that they have non-scalarized writemasks,
694 * and just take the first swizzle channel for each argument in
695 * order into each writemask channel.
696 */
697 if ((alu->op == nir_op_vec2) ||
698 (alu->op == nir_op_vec3) ||
699 (alu->op == nir_op_vec4)) {
700
701 for (int i = 0; i < info->num_inputs; i++) {
702 nir_alu_src *asrc = &alu->src[i];
703
704 compile_assert(ctx, !asrc->abs);
705 compile_assert(ctx, !asrc->negate);
706
707 src[i] = get_src(ctx, &asrc->src)[asrc->swizzle[0]];
708 if (!src[i])
709 src[i] = create_immed(ctx->block, 0);
710 dst[i] = ir3_MOV(b, src[i], TYPE_U32);
711 }
712
713 return;
714 }
715
716 /* General case: We can just grab the one used channel per src. */
717 for (int i = 0; i < info->num_inputs; i++) {
718 unsigned chan = ffs(alu->dest.write_mask) - 1;
719 nir_alu_src *asrc = &alu->src[i];
720
721 compile_assert(ctx, !asrc->abs);
722 compile_assert(ctx, !asrc->negate);
723
724 src[i] = get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
725 }
726
727 switch (alu->op) {
728 case nir_op_f2i:
729 dst[0] = ir3_COV(b, src[0], TYPE_F32, TYPE_S32);
730 break;
731 case nir_op_f2u:
732 dst[0] = ir3_COV(b, src[0], TYPE_F32, TYPE_U32);
733 break;
734 case nir_op_i2f:
735 dst[0] = ir3_COV(b, src[0], TYPE_S32, TYPE_F32);
736 break;
737 case nir_op_u2f:
738 dst[0] = ir3_COV(b, src[0], TYPE_U32, TYPE_F32);
739 break;
740 case nir_op_imov:
741 dst[0] = ir3_MOV(b, src[0], TYPE_S32);
742 break;
743 case nir_op_fmov:
744 dst[0] = ir3_MOV(b, src[0], TYPE_F32);
745 break;
746 case nir_op_f2b:
747 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
748 dst[0]->cat2.condition = IR3_COND_NE;
749 dst[0] = ir3_n2b(b, dst[0]);
750 break;
751 case nir_op_b2f:
752 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
753 break;
754 case nir_op_b2i:
755 dst[0] = ir3_b2n(b, src[0]);
756 break;
757 case nir_op_i2b:
758 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
759 dst[0]->cat2.condition = IR3_COND_NE;
760 dst[0] = ir3_n2b(b, dst[0]);
761 break;
762
763 case nir_op_fneg:
764 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
765 break;
766 case nir_op_fabs:
767 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
768 break;
769 case nir_op_fmax:
770 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
771 break;
772 case nir_op_fmin:
773 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
774 break;
775 case nir_op_fmul:
776 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
777 break;
778 case nir_op_fadd:
779 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
780 break;
781 case nir_op_fsub:
782 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
783 break;
784 case nir_op_ffma:
785 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
786 break;
787 case nir_op_fddx:
788 dst[0] = ir3_DSX(b, src[0], 0);
789 dst[0]->cat5.type = TYPE_F32;
790 break;
791 case nir_op_fddy:
792 dst[0] = ir3_DSY(b, src[0], 0);
793 dst[0]->cat5.type = TYPE_F32;
794 break;
795 break;
796 case nir_op_flt:
797 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
798 dst[0]->cat2.condition = IR3_COND_LT;
799 dst[0] = ir3_n2b(b, dst[0]);
800 break;
801 case nir_op_fge:
802 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
803 dst[0]->cat2.condition = IR3_COND_GE;
804 dst[0] = ir3_n2b(b, dst[0]);
805 break;
806 case nir_op_feq:
807 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
808 dst[0]->cat2.condition = IR3_COND_EQ;
809 dst[0] = ir3_n2b(b, dst[0]);
810 break;
811 case nir_op_fne:
812 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
813 dst[0]->cat2.condition = IR3_COND_NE;
814 dst[0] = ir3_n2b(b, dst[0]);
815 break;
816 case nir_op_fceil:
817 dst[0] = ir3_CEIL_F(b, src[0], 0);
818 break;
819 case nir_op_ffloor:
820 dst[0] = ir3_FLOOR_F(b, src[0], 0);
821 break;
822 case nir_op_ftrunc:
823 dst[0] = ir3_TRUNC_F(b, src[0], 0);
824 break;
825 case nir_op_fround_even:
826 dst[0] = ir3_RNDNE_F(b, src[0], 0);
827 break;
828 case nir_op_fsign:
829 dst[0] = ir3_SIGN_F(b, src[0], 0);
830 break;
831
832 case nir_op_fsin:
833 dst[0] = ir3_SIN(b, src[0], 0);
834 break;
835 case nir_op_fcos:
836 dst[0] = ir3_COS(b, src[0], 0);
837 break;
838 case nir_op_frsq:
839 dst[0] = ir3_RSQ(b, src[0], 0);
840 break;
841 case nir_op_frcp:
842 dst[0] = ir3_RCP(b, src[0], 0);
843 break;
844 case nir_op_flog2:
845 dst[0] = ir3_LOG2(b, src[0], 0);
846 break;
847 case nir_op_fexp2:
848 dst[0] = ir3_EXP2(b, src[0], 0);
849 break;
850 case nir_op_fsqrt:
851 dst[0] = ir3_SQRT(b, src[0], 0);
852 break;
853
854 case nir_op_iabs:
855 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
856 break;
857 case nir_op_iadd:
858 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
859 break;
860 case nir_op_iand:
861 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
862 break;
863 case nir_op_imax:
864 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
865 break;
866 case nir_op_imin:
867 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
868 break;
869 case nir_op_imul:
870 /*
871 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
872 * mull.u tmp0, a, b ; mul low, i.e. al * bl
873 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
874 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
875 */
876 dst[0] = ir3_MADSH_M16(b, src[1], 0, src[0], 0,
877 ir3_MADSH_M16(b, src[0], 0, src[1], 0,
878 ir3_MULL_U(b, src[0], 0, src[1], 0), 0), 0);
879 break;
880 case nir_op_ineg:
881 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
882 break;
883 case nir_op_inot:
884 dst[0] = ir3_NOT_B(b, src[0], 0);
885 break;
886 case nir_op_ior:
887 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
888 break;
889 case nir_op_ishl:
890 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
891 break;
892 case nir_op_ishr:
893 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
894 break;
895 case nir_op_isign: {
896 /* maybe this would be sane to lower in nir.. */
897 struct ir3_instruction *neg, *pos;
898
899 neg = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
900 neg->cat2.condition = IR3_COND_LT;
901
902 pos = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
903 pos->cat2.condition = IR3_COND_GT;
904
905 dst[0] = ir3_SUB_U(b, pos, 0, neg, 0);
906
907 break;
908 }
909 case nir_op_isub:
910 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
911 break;
912 case nir_op_ixor:
913 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
914 break;
915 case nir_op_ushr:
916 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
917 break;
918 case nir_op_ilt:
919 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
920 dst[0]->cat2.condition = IR3_COND_LT;
921 dst[0] = ir3_n2b(b, dst[0]);
922 break;
923 case nir_op_ige:
924 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
925 dst[0]->cat2.condition = IR3_COND_GE;
926 dst[0] = ir3_n2b(b, dst[0]);
927 break;
928 case nir_op_ieq:
929 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
930 dst[0]->cat2.condition = IR3_COND_EQ;
931 dst[0] = ir3_n2b(b, dst[0]);
932 break;
933 case nir_op_ine:
934 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
935 dst[0]->cat2.condition = IR3_COND_NE;
936 dst[0] = ir3_n2b(b, dst[0]);
937 break;
938 case nir_op_ult:
939 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
940 dst[0]->cat2.condition = IR3_COND_LT;
941 dst[0] = ir3_n2b(b, dst[0]);
942 break;
943 case nir_op_uge:
944 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
945 dst[0]->cat2.condition = IR3_COND_GE;
946 dst[0] = ir3_n2b(b, dst[0]);
947 break;
948
949 case nir_op_bcsel:
950 dst[0] = ir3_SEL_B32(b, src[1], 0, ir3_b2n(b, src[0]), 0, src[2], 0);
951 break;
952
953 default:
954 compile_error(ctx, "Unhandled ALU op: %s\n",
955 nir_op_infos[alu->op].name);
956 break;
957 }
958 }
959
960 /* handles array reads: */
961 static void
962 emit_intrinisic_load_var(struct ir3_compile *ctx, nir_intrinsic_instr *intr,
963 struct ir3_instruction **dst)
964 {
965 nir_deref_var *dvar = intr->variables[0];
966 nir_deref_array *darr = nir_deref_as_array(dvar->deref.child);
967 struct ir3_array *arr = get_var(ctx, dvar->var);
968
969 compile_assert(ctx, dvar->deref.child &&
970 (dvar->deref.child->deref_type == nir_deref_type_array));
971
972 switch (darr->deref_array_type) {
973 case nir_deref_array_type_direct:
974 /* direct access does not require anything special: */
975 for (int i = 0; i < intr->num_components; i++) {
976 unsigned n = darr->base_offset * 4 + i;
977 compile_assert(ctx, n < arr->length);
978 dst[i] = arr->arr[n];
979 }
980 break;
981 case nir_deref_array_type_indirect: {
982 /* for indirect, we need to collect all the array elements: */
983 struct ir3_instruction *collect =
984 create_collect(ctx->block, arr->arr, arr->length);
985 struct ir3_instruction *addr =
986 get_addr(ctx, get_src(ctx, &darr->indirect)[0]);
987 for (int i = 0; i < intr->num_components; i++) {
988 unsigned n = darr->base_offset * 4 + i;
989 compile_assert(ctx, n < arr->length);
990 dst[i] = create_indirect_load(ctx, arr->length, n, addr, collect);
991 }
992 break;
993 }
994 default:
995 compile_error(ctx, "Unhandled load deref type: %u\n",
996 darr->deref_array_type);
997 break;
998 }
999 }
1000
1001 /* handles array writes: */
1002 static void
1003 emit_intrinisic_store_var(struct ir3_compile *ctx, nir_intrinsic_instr *intr)
1004 {
1005 nir_deref_var *dvar = intr->variables[0];
1006 nir_deref_array *darr = nir_deref_as_array(dvar->deref.child);
1007 struct ir3_array *arr = get_var(ctx, dvar->var);
1008 struct ir3_instruction **src;
1009
1010 compile_assert(ctx, dvar->deref.child &&
1011 (dvar->deref.child->deref_type == nir_deref_type_array));
1012
1013 src = get_src(ctx, &intr->src[0]);
1014
1015 switch (darr->deref_array_type) {
1016 case nir_deref_array_type_direct:
1017 /* direct access does not require anything special: */
1018 for (int i = 0; i < intr->num_components; i++) {
1019 unsigned n = darr->base_offset * 4 + i;
1020 compile_assert(ctx, n < arr->length);
1021 arr->arr[n] = src[i];
1022 }
1023 break;
1024 case nir_deref_array_type_indirect: {
1025 /* for indirect, create indirect-store and fan that out: */
1026 struct ir3_instruction *collect =
1027 create_collect(ctx->block, arr->arr, arr->length);
1028 struct ir3_instruction *addr =
1029 get_addr(ctx, get_src(ctx, &darr->indirect)[0]);
1030 for (int i = 0; i < intr->num_components; i++) {
1031 struct ir3_instruction *store;
1032 unsigned n = darr->base_offset * 4 + i;
1033 compile_assert(ctx, n < arr->length);
1034
1035 store = create_indirect_store(ctx, arr->length,
1036 n, src[i], addr, collect);
1037
1038 store->fanin->fi.aid = arr->aid;
1039
1040 /* TODO: probably split this out to be used for
1041 * store_output_indirect? or move this into
1042 * create_indirect_store()?
1043 */
1044 for (int j = i; j < arr->length; j += 4) {
1045 struct ir3_instruction *split;
1046
1047 split = ir3_instr_create(ctx->block, -1, OPC_META_FO);
1048 split->fo.off = j;
1049 ir3_reg_create(split, 0, 0);
1050 ir3_reg_create(split, 0, IR3_REG_SSA)->instr = store;
1051
1052 arr->arr[j] = split;
1053 }
1054 }
1055 break;
1056 }
1057 default:
1058 compile_error(ctx, "Unhandled store deref type: %u\n",
1059 darr->deref_array_type);
1060 break;
1061 }
1062 }
1063
1064 static void
1065 emit_intrinisic(struct ir3_compile *ctx, nir_intrinsic_instr *intr)
1066 {
1067 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1068 struct ir3_instruction **dst, **src;
1069 struct ir3_block *b = ctx->block;
1070 unsigned idx = intr->const_index[0];
1071
1072 if (info->has_dest) {
1073 dst = get_dst(ctx, &intr->dest, intr->num_components);
1074 }
1075
1076 switch (intr->intrinsic) {
1077 case nir_intrinsic_load_uniform:
1078 compile_assert(ctx, intr->const_index[1] == 1);
1079 for (int i = 0; i < intr->num_components; i++) {
1080 unsigned n = idx * 4 + i;
1081 dst[i] = create_uniform(ctx, n);
1082 }
1083 break;
1084 case nir_intrinsic_load_uniform_indirect:
1085 compile_assert(ctx, intr->const_index[1] == 1);
1086 src = get_src(ctx, &intr->src[0]);
1087 for (int i = 0; i < intr->num_components; i++) {
1088 unsigned n = idx * 4 + i;
1089 dst[i] = create_uniform_indirect(ctx, n,
1090 get_addr(ctx, src[0]));
1091 }
1092 break;
1093 case nir_intrinsic_load_input:
1094 compile_assert(ctx, intr->const_index[1] == 1);
1095 for (int i = 0; i < intr->num_components; i++) {
1096 unsigned n = idx * 4 + i;
1097 dst[i] = b->inputs[n];
1098 }
1099 break;
1100 case nir_intrinsic_load_input_indirect:
1101 compile_assert(ctx, intr->const_index[1] == 1);
1102 src = get_src(ctx, &intr->src[0]);
1103 struct ir3_instruction *collect =
1104 create_collect(b, b->inputs, b->ninputs);
1105 struct ir3_instruction *addr = get_addr(ctx, src[0]);
1106 for (int i = 0; i < intr->num_components; i++) {
1107 unsigned n = idx * 4 + i;
1108 dst[i] = create_indirect_load(ctx, b->ninputs, n, addr, collect);
1109 }
1110 break;
1111 case nir_intrinsic_load_var:
1112 emit_intrinisic_load_var(ctx, intr, dst);
1113 break;
1114 case nir_intrinsic_store_var:
1115 emit_intrinisic_store_var(ctx, intr);
1116 break;
1117 case nir_intrinsic_store_output:
1118 compile_assert(ctx, intr->const_index[1] == 1);
1119 src = get_src(ctx, &intr->src[0]);
1120 for (int i = 0; i < intr->num_components; i++) {
1121 unsigned n = idx * 4 + i;
1122 b->outputs[n] = src[i];
1123 }
1124 break;
1125 case nir_intrinsic_discard_if:
1126 case nir_intrinsic_discard: {
1127 struct ir3_instruction *cond, *kill;
1128
1129 if (intr->intrinsic == nir_intrinsic_discard_if) {
1130 /* conditional discard: */
1131 src = get_src(ctx, &intr->src[0]);
1132 cond = ir3_b2n(b, src[0]);
1133 } else {
1134 /* unconditional discard: */
1135 cond = create_immed(b, 1);
1136 }
1137
1138 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1139 cond->cat2.condition = IR3_COND_NE;
1140
1141 /* condition always goes in predicate register: */
1142 cond->regs[0]->num = regid(REG_P0, 0);
1143
1144 kill = ir3_KILL(b, cond, 0);
1145
1146 ctx->kill[ctx->kill_count++] = kill;
1147 ctx->so->has_kill = true;
1148
1149 break;
1150 }
1151 default:
1152 compile_error(ctx, "Unhandled intrinsic type: %s\n",
1153 nir_intrinsic_infos[intr->intrinsic].name);
1154 break;
1155 }
1156 }
1157
1158 static void
1159 emit_load_const(struct ir3_compile *ctx, nir_load_const_instr *instr)
1160 {
1161 struct ir3_instruction **dst = get_dst_ssa(ctx, &instr->def,
1162 instr->def.num_components);
1163 for (int i = 0; i < instr->def.num_components; i++)
1164 dst[i] = create_immed(ctx->block, instr->value.u[i]);
1165 }
1166
1167 static void
1168 emit_undef(struct ir3_compile *ctx, nir_ssa_undef_instr *undef)
1169 {
1170 struct ir3_instruction **dst = get_dst_ssa(ctx, &undef->def,
1171 undef->def.num_components);
1172 /* backend doesn't want undefined instructions, so just plug
1173 * in 0.0..
1174 */
1175 for (int i = 0; i < undef->def.num_components; i++)
1176 dst[i] = create_immed(ctx->block, fui(0.0));
1177 }
1178
1179 /*
1180 * texture fetch/sample instructions:
1181 */
1182
1183 static void
1184 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1185 {
1186 unsigned coords, flags = 0;
1187
1188 /* note: would use tex->coord_components.. except txs.. also,
1189 * since array index goes after shadow ref, we don't want to
1190 * count it:
1191 */
1192 switch (tex->sampler_dim) {
1193 case GLSL_SAMPLER_DIM_1D:
1194 case GLSL_SAMPLER_DIM_BUF:
1195 coords = 1;
1196 break;
1197 case GLSL_SAMPLER_DIM_2D:
1198 case GLSL_SAMPLER_DIM_RECT:
1199 case GLSL_SAMPLER_DIM_EXTERNAL:
1200 case GLSL_SAMPLER_DIM_MS:
1201 coords = 2;
1202 break;
1203 case GLSL_SAMPLER_DIM_3D:
1204 case GLSL_SAMPLER_DIM_CUBE:
1205 coords = 3;
1206 flags |= IR3_INSTR_3D;
1207 break;
1208 }
1209
1210 if (tex->is_shadow)
1211 flags |= IR3_INSTR_S;
1212
1213 if (tex->is_array)
1214 flags |= IR3_INSTR_A;
1215
1216 *flagsp = flags;
1217 *coordsp = coords;
1218 }
1219
1220 static void
1221 emit_tex(struct ir3_compile *ctx, nir_tex_instr *tex)
1222 {
1223 struct ir3_block *b = ctx->block;
1224 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1225 struct ir3_instruction **coord, *lod, *compare, *proj, **off, **ddx, **ddy;
1226 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1227 unsigned i, coords, flags;
1228 unsigned nsrc0 = 0, nsrc1 = 0;
1229 type_t type;
1230 opc_t opc;
1231
1232 /* TODO: might just be one component for gathers? */
1233 dst = get_dst(ctx, &tex->dest, 4);
1234
1235 for (unsigned i = 0; i < tex->num_srcs; i++) {
1236 switch (tex->src[i].src_type) {
1237 case nir_tex_src_coord:
1238 coord = get_src(ctx, &tex->src[i].src);
1239 break;
1240 case nir_tex_src_bias:
1241 lod = get_src(ctx, &tex->src[i].src)[0];
1242 has_bias = true;
1243 break;
1244 case nir_tex_src_lod:
1245 lod = get_src(ctx, &tex->src[i].src)[0];
1246 has_lod = true;
1247 break;
1248 case nir_tex_src_comparitor: /* shadow comparator */
1249 compare = get_src(ctx, &tex->src[i].src)[0];
1250 break;
1251 case nir_tex_src_projector:
1252 proj = get_src(ctx, &tex->src[i].src)[0];
1253 has_proj = true;
1254 break;
1255 case nir_tex_src_offset:
1256 off = get_src(ctx, &tex->src[i].src);
1257 has_off = true;
1258 break;
1259 case nir_tex_src_ddx:
1260 ddx = get_src(ctx, &tex->src[i].src);
1261 break;
1262 case nir_tex_src_ddy:
1263 ddy = get_src(ctx, &tex->src[i].src);
1264 break;
1265 default:
1266 compile_error(ctx, "Unhandled NIR tex serc type: %d\n",
1267 tex->src[i].src_type);
1268 return;
1269 }
1270 }
1271
1272 /*
1273 * lay out the first argument in the proper order:
1274 * - actual coordinates first
1275 * - shadow reference
1276 * - array index
1277 * - projection w
1278 * - starting at offset 4, dpdx.xy, dpdy.xy
1279 *
1280 * bias/lod go into the second arg
1281 */
1282
1283 tex_info(tex, &flags, &coords);
1284
1285 /* insert tex coords: */
1286 for (i = 0; i < coords; i++)
1287 src0[nsrc0++] = coord[i];
1288
1289 if (coords == 1) {
1290 /* hw doesn't do 1d, so we treat it as 2d with
1291 * height of 1, and patch up the y coord.
1292 * TODO: y coord should be (int)0 in some cases..
1293 */
1294 src0[nsrc0++] = create_immed(b, fui(0.5));
1295 }
1296
1297 if (tex->is_shadow)
1298 src0[nsrc0++] = compare;
1299
1300 if (tex->is_array)
1301 src0[nsrc0++] = coord[coords];
1302
1303 if (has_proj) {
1304 src0[nsrc0++] = proj;
1305 flags |= IR3_INSTR_P;
1306 }
1307
1308 /* pad to 4, then ddx/ddy: */
1309 if (tex->op == nir_texop_txd) {
1310 while (nsrc0 < 4)
1311 src0[nsrc0++] = create_immed(b, fui(0.0));
1312 for (i = 0; i < coords; i++)
1313 src0[nsrc0++] = ddx[i];
1314 if (coords < 2)
1315 src0[nsrc0++] = create_immed(b, fui(0.0));
1316 for (i = 0; i < coords; i++)
1317 src0[nsrc0++] = ddy[i];
1318 if (coords < 2)
1319 src0[nsrc0++] = create_immed(b, fui(0.0));
1320 }
1321
1322 /*
1323 * second argument (if applicable):
1324 * - offsets
1325 * - lod
1326 * - bias
1327 */
1328 if (has_off | has_lod | has_bias) {
1329 if (has_off) {
1330 for (i = 0; i < coords; i++)
1331 src1[nsrc1++] = off[i];
1332 if (coords < 2)
1333 src1[nsrc1++] = create_immed(b, fui(0.0));
1334 flags |= IR3_INSTR_O;
1335 }
1336
1337 if (has_lod | has_bias)
1338 src1[nsrc1++] = lod;
1339 }
1340
1341 switch (tex->op) {
1342 case nir_texop_tex: opc = OPC_SAM; break;
1343 case nir_texop_txb: opc = OPC_SAMB; break;
1344 case nir_texop_txl: opc = OPC_SAML; break;
1345 case nir_texop_txd: opc = OPC_SAMGQ; break;
1346 case nir_texop_txf: opc = OPC_ISAML; break;
1347 case nir_texop_txf_ms:
1348 case nir_texop_txs:
1349 case nir_texop_lod:
1350 case nir_texop_tg4:
1351 case nir_texop_query_levels:
1352 compile_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
1353 return;
1354 }
1355
1356 switch (tex->dest_type) {
1357 case nir_type_invalid:
1358 case nir_type_float:
1359 type = TYPE_F32;
1360 break;
1361 case nir_type_int:
1362 type = TYPE_S32;
1363 break;
1364 case nir_type_unsigned:
1365 case nir_type_bool:
1366 type = TYPE_U32;
1367 break;
1368 }
1369
1370 sam = ir3_SAM(b, opc, type, TGSI_WRITEMASK_XYZW,
1371 flags, tex->sampler_index, tex->sampler_index,
1372 create_collect(b, src0, nsrc0),
1373 create_collect(b, src1, nsrc1));
1374
1375 split_dest(b, dst, sam);
1376 }
1377
1378
1379 static void
1380 emit_instr(struct ir3_compile *ctx, nir_instr *instr)
1381 {
1382 switch (instr->type) {
1383 case nir_instr_type_alu:
1384 emit_alu(ctx, nir_instr_as_alu(instr));
1385 break;
1386 case nir_instr_type_intrinsic:
1387 emit_intrinisic(ctx, nir_instr_as_intrinsic(instr));
1388 break;
1389 case nir_instr_type_load_const:
1390 emit_load_const(ctx, nir_instr_as_load_const(instr));
1391 break;
1392 case nir_instr_type_ssa_undef:
1393 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
1394 break;
1395 case nir_instr_type_tex:
1396 emit_tex(ctx, nir_instr_as_tex(instr));
1397 break;
1398
1399 case nir_instr_type_call:
1400 case nir_instr_type_jump:
1401 case nir_instr_type_phi:
1402 case nir_instr_type_parallel_copy:
1403 compile_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
1404 break;
1405 }
1406 }
1407
1408 static void
1409 emit_block(struct ir3_compile *ctx, nir_block *block)
1410 {
1411 nir_foreach_instr(block, instr) {
1412 emit_instr(ctx, instr);
1413 if (ctx->error)
1414 return;
1415 }
1416 }
1417
1418 static void
1419 emit_function(struct ir3_compile *ctx, nir_function_impl *impl)
1420 {
1421 foreach_list_typed(nir_cf_node, node, node, &impl->body) {
1422 switch (node->type) {
1423 case nir_cf_node_block:
1424 emit_block(ctx, nir_cf_node_as_block(node));
1425 break;
1426 case nir_cf_node_if:
1427 case nir_cf_node_loop:
1428 case nir_cf_node_function:
1429 compile_error(ctx, "TODO\n");
1430 break;
1431 }
1432 if (ctx->error)
1433 return;
1434 }
1435 }
1436
1437 static void
1438 setup_input(struct ir3_compile *ctx, nir_variable *in)
1439 {
1440 struct ir3_shader_variant *so = ctx->so;
1441 unsigned array_len = MAX2(glsl_get_length(in->type), 1);
1442 unsigned ncomp = glsl_get_components(in->type);
1443 /* XXX: map loc slots to semantics */
1444 unsigned semantic_name = in->data.location;
1445 unsigned semantic_index = in->data.index;
1446 unsigned n = in->data.driver_location;
1447
1448 DBG("; in: %u:%u, len=%ux%u, loc=%u\n",
1449 semantic_name, semantic_index, array_len,
1450 ncomp, n);
1451
1452 so->inputs[n].semantic =
1453 ir3_semantic_name(semantic_name, semantic_index);
1454 so->inputs[n].compmask = (1 << ncomp) - 1;
1455 so->inputs[n].inloc = ctx->next_inloc;
1456 so->inputs[n].interpolate = 0;
1457 so->inputs_count = MAX2(so->inputs_count, n + 1);
1458
1459 /* the fdN_program_emit() code expects tgsi consts here, so map
1460 * things back to tgsi for now:
1461 */
1462 switch (in->data.interpolation) {
1463 case INTERP_QUALIFIER_FLAT:
1464 so->inputs[n].interpolate = TGSI_INTERPOLATE_CONSTANT;
1465 break;
1466 case INTERP_QUALIFIER_NOPERSPECTIVE:
1467 so->inputs[n].interpolate = TGSI_INTERPOLATE_LINEAR;
1468 break;
1469 case INTERP_QUALIFIER_SMOOTH:
1470 so->inputs[n].interpolate = TGSI_INTERPOLATE_PERSPECTIVE;
1471 break;
1472 }
1473
1474 for (int i = 0; i < ncomp; i++) {
1475 struct ir3_instruction *instr = NULL;
1476 unsigned idx = (n * 4) + i;
1477
1478 if (ctx->so->type == SHADER_FRAGMENT) {
1479 if (semantic_name == TGSI_SEMANTIC_POSITION) {
1480 so->inputs[n].bary = false;
1481 so->frag_coord = true;
1482 instr = create_frag_coord(ctx, i);
1483 } else if (semantic_name == TGSI_SEMANTIC_FACE) {
1484 so->inputs[n].bary = false;
1485 so->frag_face = true;
1486 instr = create_frag_face(ctx, i);
1487 } else {
1488 bool use_ldlv = false;
1489
1490 /* with NIR, we need to infer TGSI_INTERPOLATE_COLOR
1491 * from the semantic name:
1492 */
1493 if (semantic_name == TGSI_SEMANTIC_COLOR)
1494 so->inputs[n].interpolate = TGSI_INTERPOLATE_COLOR;
1495
1496 if (ctx->flat_bypass) {
1497 /* with NIR, we need to infer TGSI_INTERPOLATE_COLOR
1498 * from the semantic name:
1499 */
1500 switch (so->inputs[n].interpolate) {
1501 case TGSI_INTERPOLATE_COLOR:
1502 if (!ctx->so->key.rasterflat)
1503 break;
1504 /* fallthrough */
1505 case TGSI_INTERPOLATE_CONSTANT:
1506 use_ldlv = true;
1507 break;
1508 }
1509 }
1510
1511 so->inputs[n].bary = true;
1512
1513 instr = create_frag_input(ctx, idx, use_ldlv);
1514 }
1515 } else {
1516 instr = create_input(ctx->block, NULL, idx);
1517 }
1518
1519 ctx->block->inputs[idx] = instr;
1520 }
1521
1522 if (so->inputs[n].bary || (ctx->so->type == SHADER_VERTEX)) {
1523 ctx->next_inloc += ncomp;
1524 so->total_in += ncomp;
1525 }
1526 }
1527
1528 static void
1529 setup_output(struct ir3_compile *ctx, nir_variable *out)
1530 {
1531 struct ir3_shader_variant *so = ctx->so;
1532 unsigned array_len = MAX2(glsl_get_length(out->type), 1);
1533 unsigned ncomp = glsl_get_components(out->type);
1534 /* XXX: map loc slots to semantics */
1535 unsigned semantic_name = out->data.location;
1536 unsigned semantic_index = out->data.index;
1537 unsigned n = out->data.driver_location;
1538 unsigned comp = 0;
1539
1540 DBG("; out: %u:%u, len=%ux%u, loc=%u\n",
1541 semantic_name, semantic_index, array_len,
1542 ncomp, n);
1543
1544 if (ctx->so->type == SHADER_VERTEX) {
1545 switch (semantic_name) {
1546 case TGSI_SEMANTIC_POSITION:
1547 so->writes_pos = true;
1548 break;
1549 case TGSI_SEMANTIC_PSIZE:
1550 so->writes_psize = true;
1551 break;
1552 case TGSI_SEMANTIC_COLOR:
1553 case TGSI_SEMANTIC_BCOLOR:
1554 case TGSI_SEMANTIC_GENERIC:
1555 case TGSI_SEMANTIC_FOG:
1556 case TGSI_SEMANTIC_TEXCOORD:
1557 break;
1558 default:
1559 compile_error(ctx, "unknown VS semantic name: %s\n",
1560 tgsi_semantic_names[semantic_name]);
1561 }
1562 } else {
1563 switch (semantic_name) {
1564 case TGSI_SEMANTIC_POSITION:
1565 comp = 2; /* tgsi will write to .z component */
1566 so->writes_pos = true;
1567 break;
1568 case TGSI_SEMANTIC_COLOR:
1569 break;
1570 default:
1571 compile_error(ctx, "unknown FS semantic name: %s\n",
1572 tgsi_semantic_names[semantic_name]);
1573 }
1574 }
1575
1576 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
1577
1578 so->outputs[n].semantic =
1579 ir3_semantic_name(semantic_name, semantic_index);
1580 so->outputs[n].regid = regid(n, comp);
1581 so->outputs_count = MAX2(so->outputs_count, n + 1);
1582
1583 for (int i = 0; i < ncomp; i++) {
1584 unsigned idx = (n * 4) + i;
1585
1586 ctx->block->outputs[idx] = create_immed(ctx->block, fui(0.0));
1587 }
1588 }
1589
1590 static void
1591 emit_instructions(struct ir3_compile *ctx)
1592 {
1593 unsigned ninputs = exec_list_length(&ctx->s->inputs) * 4;
1594 unsigned noutputs = exec_list_length(&ctx->s->outputs) * 4;
1595
1596 /* we need to allocate big enough outputs array so that
1597 * we can stuff the kill's at the end:
1598 */
1599 if (ctx->so->type == SHADER_FRAGMENT)
1600 noutputs += ARRAY_SIZE(ctx->kill);
1601
1602 ctx->block = ir3_block_create(ctx->ir, 0, ninputs, noutputs);
1603
1604 if (ctx->so->type == SHADER_FRAGMENT)
1605 ctx->block->noutputs -= ARRAY_SIZE(ctx->kill);
1606
1607
1608 /* for fragment shader, we have a single input register (usually
1609 * r0.xy) which is used as the base for bary.f varying fetch instrs:
1610 */
1611 if (ctx->so->type == SHADER_FRAGMENT) {
1612 // TODO maybe a helper for fi since we need it a few places..
1613 struct ir3_instruction *instr;
1614 instr = ir3_instr_create(ctx->block, -1, OPC_META_FI);
1615 ir3_reg_create(instr, 0, 0);
1616 ir3_reg_create(instr, 0, IR3_REG_SSA); /* r0.x */
1617 ir3_reg_create(instr, 0, IR3_REG_SSA); /* r0.y */
1618 ctx->frag_pos = instr;
1619 }
1620
1621 /* Setup inputs: */
1622 foreach_list_typed(nir_variable, var, node, &ctx->s->inputs) {
1623 setup_input(ctx, var);
1624 }
1625
1626 /* Setup outputs: */
1627 foreach_list_typed(nir_variable, var, node, &ctx->s->outputs) {
1628 setup_output(ctx, var);
1629 }
1630
1631 /* Setup variables (which should only be arrays): */
1632 foreach_list_typed(nir_variable, var, node, &ctx->s->globals) {
1633 declare_var(ctx, var);
1634 }
1635
1636 /* Find the main function and emit the body: */
1637 nir_foreach_overload(ctx->s, overload) {
1638 compile_assert(ctx, strcmp(overload->function->name, "main") == 0);
1639 compile_assert(ctx, overload->impl);
1640 emit_function(ctx, overload->impl);
1641 if (ctx->error)
1642 return;
1643 }
1644 }
1645
1646 /* from NIR perspective, we actually have inputs. But most of the "inputs"
1647 * for a fragment shader are just bary.f instructions. The *actual* inputs
1648 * from the hw perspective are the frag_pos and optionally frag_coord and
1649 * frag_face.
1650 */
1651 static void
1652 fixup_frag_inputs(struct ir3_compile *ctx)
1653 {
1654 struct ir3_shader_variant *so = ctx->so;
1655 struct ir3_block *block = ctx->block;
1656 struct ir3_instruction **inputs;
1657 struct ir3_instruction *instr;
1658 int n, regid = 0;
1659
1660 block->ninputs = 0;
1661
1662 n = 4; /* always have frag_pos */
1663 n += COND(so->frag_face, 4);
1664 n += COND(so->frag_coord, 4);
1665
1666 inputs = ir3_alloc(ctx->ir, n * (sizeof(struct ir3_instruction *)));
1667
1668 if (so->frag_face) {
1669 /* this ultimately gets assigned to hr0.x so doesn't conflict
1670 * with frag_coord/frag_pos..
1671 */
1672 inputs[block->ninputs++] = ctx->frag_face;
1673 ctx->frag_face->regs[0]->num = 0;
1674
1675 /* remaining channels not used, but let's avoid confusing
1676 * other parts that expect inputs to come in groups of vec4
1677 */
1678 inputs[block->ninputs++] = NULL;
1679 inputs[block->ninputs++] = NULL;
1680 inputs[block->ninputs++] = NULL;
1681 }
1682
1683 /* since we don't know where to set the regid for frag_coord,
1684 * we have to use r0.x for it. But we don't want to *always*
1685 * use r1.x for frag_pos as that could increase the register
1686 * footprint on simple shaders:
1687 */
1688 if (so->frag_coord) {
1689 ctx->frag_coord[0]->regs[0]->num = regid++;
1690 ctx->frag_coord[1]->regs[0]->num = regid++;
1691 ctx->frag_coord[2]->regs[0]->num = regid++;
1692 ctx->frag_coord[3]->regs[0]->num = regid++;
1693
1694 inputs[block->ninputs++] = ctx->frag_coord[0];
1695 inputs[block->ninputs++] = ctx->frag_coord[1];
1696 inputs[block->ninputs++] = ctx->frag_coord[2];
1697 inputs[block->ninputs++] = ctx->frag_coord[3];
1698 }
1699
1700 /* we always have frag_pos: */
1701 so->pos_regid = regid;
1702
1703 /* r0.x */
1704 instr = create_input(block, NULL, block->ninputs);
1705 instr->regs[0]->num = regid++;
1706 inputs[block->ninputs++] = instr;
1707 ctx->frag_pos->regs[1]->instr = instr;
1708
1709 /* r0.y */
1710 instr = create_input(block, NULL, block->ninputs);
1711 instr->regs[0]->num = regid++;
1712 inputs[block->ninputs++] = instr;
1713 ctx->frag_pos->regs[2]->instr = instr;
1714
1715 block->inputs = inputs;
1716 }
1717
1718 static void
1719 compile_dump(struct ir3_compile *ctx)
1720 {
1721 const char *name = (ctx->so->type == SHADER_VERTEX) ? "vert" : "frag";
1722 static unsigned n = 0;
1723 char fname[16];
1724 FILE *f;
1725 snprintf(fname, sizeof(fname), "%s-%04u.dot", name, n++);
1726 f = fopen(fname, "w");
1727 if (!f)
1728 return;
1729 ir3_block_depth(ctx->block);
1730 ir3_dump(ctx->ir, name, ctx->block, f);
1731 fclose(f);
1732 }
1733
1734 int
1735 ir3_compile_shader_nir(struct ir3_shader_variant *so,
1736 const struct tgsi_token *tokens, struct ir3_shader_key key)
1737 {
1738 struct ir3_compile *ctx;
1739 struct ir3_block *block;
1740 struct ir3_instruction **inputs;
1741 unsigned i, j, actual_in;
1742 int ret = 0, max_bary;
1743
1744 assert(!so->ir);
1745
1746 so->ir = ir3_create();
1747
1748 assert(so->ir);
1749
1750 ctx = compile_init(so, tokens);
1751 if (!ctx) {
1752 DBG("INIT failed!");
1753 ret = -1;
1754 goto out;
1755 }
1756
1757 emit_instructions(ctx);
1758
1759 if (ctx->error) {
1760 DBG("EMIT failed!");
1761 ret = -1;
1762 goto out;
1763 }
1764
1765 block = ctx->block;
1766 so->ir->block = block;
1767
1768 /* keep track of the inputs from TGSI perspective.. */
1769 inputs = block->inputs;
1770
1771 /* but fixup actual inputs for frag shader: */
1772 if (so->type == SHADER_FRAGMENT)
1773 fixup_frag_inputs(ctx);
1774
1775 /* at this point, for binning pass, throw away unneeded outputs: */
1776 if (key.binning_pass) {
1777 for (i = 0, j = 0; i < so->outputs_count; i++) {
1778 unsigned name = sem2name(so->outputs[i].semantic);
1779 unsigned idx = sem2idx(so->outputs[i].semantic);
1780
1781 /* throw away everything but first position/psize */
1782 if ((idx == 0) && ((name == TGSI_SEMANTIC_POSITION) ||
1783 (name == TGSI_SEMANTIC_PSIZE))) {
1784 if (i != j) {
1785 so->outputs[j] = so->outputs[i];
1786 block->outputs[(j*4)+0] = block->outputs[(i*4)+0];
1787 block->outputs[(j*4)+1] = block->outputs[(i*4)+1];
1788 block->outputs[(j*4)+2] = block->outputs[(i*4)+2];
1789 block->outputs[(j*4)+3] = block->outputs[(i*4)+3];
1790 }
1791 j++;
1792 }
1793 }
1794 so->outputs_count = j;
1795 block->noutputs = j * 4;
1796 }
1797
1798 /* if we want half-precision outputs, mark the output registers
1799 * as half:
1800 */
1801 if (key.half_precision) {
1802 for (i = 0; i < block->noutputs; i++) {
1803 if (!block->outputs[i])
1804 continue;
1805 block->outputs[i]->regs[0]->flags |= IR3_REG_HALF;
1806 }
1807 }
1808
1809 /* at this point, we want the kill's in the outputs array too,
1810 * so that they get scheduled (since they have no dst).. we've
1811 * already ensured that the array is big enough in push_block():
1812 */
1813 if (so->type == SHADER_FRAGMENT) {
1814 for (i = 0; i < ctx->kill_count; i++)
1815 block->outputs[block->noutputs++] = ctx->kill[i];
1816 }
1817
1818 if (fd_mesa_debug & FD_DBG_OPTDUMP)
1819 compile_dump(ctx);
1820
1821 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
1822 printf("BEFORE CP:\n");
1823 ir3_dump_instr_list(block->head);
1824 }
1825
1826 ir3_block_depth(block);
1827
1828 ir3_block_cp(block);
1829
1830 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
1831 printf("BEFORE GROUPING:\n");
1832 ir3_dump_instr_list(block->head);
1833 }
1834
1835 /* Group left/right neighbors, inserting mov's where needed to
1836 * solve conflicts:
1837 */
1838 ir3_block_group(block);
1839
1840 if (fd_mesa_debug & FD_DBG_OPTDUMP)
1841 compile_dump(ctx);
1842
1843 ir3_block_depth(block);
1844
1845 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
1846 printf("AFTER DEPTH:\n");
1847 ir3_dump_instr_list(block->head);
1848 }
1849
1850 ret = ir3_block_sched(block);
1851 if (ret) {
1852 DBG("SCHED failed!");
1853 goto out;
1854 }
1855
1856 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
1857 printf("AFTER SCHED:\n");
1858 ir3_dump_instr_list(block->head);
1859 }
1860
1861 ret = ir3_block_ra(block, so->type, so->frag_coord, so->frag_face);
1862 if (ret) {
1863 DBG("RA failed!");
1864 goto out;
1865 }
1866
1867 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
1868 printf("AFTER RA:\n");
1869 ir3_dump_instr_list(block->head);
1870 }
1871
1872 ir3_block_legalize(block, &so->has_samp, &max_bary);
1873
1874 /* fixup input/outputs: */
1875 for (i = 0; i < so->outputs_count; i++) {
1876 so->outputs[i].regid = block->outputs[i*4]->regs[0]->num;
1877 /* preserve hack for depth output.. tgsi writes depth to .z,
1878 * but what we give the hw is the scalar register:
1879 */
1880 if ((so->type == SHADER_FRAGMENT) &&
1881 (sem2name(so->outputs[i].semantic) == TGSI_SEMANTIC_POSITION))
1882 so->outputs[i].regid += 2;
1883 }
1884
1885 /* Note that some or all channels of an input may be unused: */
1886 actual_in = 0;
1887 for (i = 0; i < so->inputs_count; i++) {
1888 unsigned j, regid = ~0, compmask = 0;
1889 so->inputs[i].ncomp = 0;
1890 for (j = 0; j < 4; j++) {
1891 struct ir3_instruction *in = inputs[(i*4) + j];
1892 if (in) {
1893 compmask |= (1 << j);
1894 regid = in->regs[0]->num - j;
1895 actual_in++;
1896 so->inputs[i].ncomp++;
1897 }
1898 }
1899 so->inputs[i].regid = regid;
1900 so->inputs[i].compmask = compmask;
1901 }
1902
1903 /* fragment shader always gets full vec4's even if it doesn't
1904 * fetch all components, but vertex shader we need to update
1905 * with the actual number of components fetch, otherwise thing
1906 * will hang due to mismaptch between VFD_DECODE's and
1907 * TOTALATTRTOVS
1908 */
1909 if (so->type == SHADER_VERTEX)
1910 so->total_in = actual_in;
1911 else
1912 so->total_in = align(max_bary + 1, 4);
1913
1914 out:
1915 if (ret) {
1916 ir3_destroy(so->ir);
1917 so->ir = NULL;
1918 }
1919 compile_free(ctx);
1920
1921 return ret;
1922 }