1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
35 #include "tgsi/tgsi_lowering.h"
36 #include "tgsi/tgsi_strings.h"
38 #include "nir/tgsi_to_nir.h"
39 #include "glsl/shader_enums.h"
41 #include "freedreno_util.h"
43 #include "ir3_compiler.h"
44 #include "ir3_shader.h"
47 #include "instr-a3xx.h"
52 struct ir3_compiler
*compiler
;
54 const struct tgsi_token
*tokens
;
58 struct ir3_shader_variant
*so
;
60 struct ir3_block
*block
; /* the current block */
61 struct ir3_block
*in_block
; /* block created for shader inputs */
63 nir_function_impl
*impl
;
65 /* For fragment shaders, from the hw perspective the only
66 * actual input is r0.xy position register passed to bary.f.
67 * But TGSI doesn't know that, it still declares things as
68 * IN[] registers. So we do all the input tracking normally
69 * and fix things up after compile_instructions()
71 * NOTE that frag_pos is the hardware position (possibly it
72 * is actually an index or tag or some such.. it is *not*
73 * values that can be directly used for gl_FragCoord..)
75 struct ir3_instruction
*frag_pos
, *frag_face
, *frag_coord
[4];
77 /* For vertex shaders, keep track of the system values sources */
78 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
80 /* mapping from nir_register to defining instruction: */
81 struct hash_table
*def_ht
;
83 /* mapping from nir_variable to ir3_array: */
84 struct hash_table
*var_ht
;
87 /* a common pattern for indirect addressing is to request the
88 * same address register multiple times. To avoid generating
89 * duplicate instruction sequences (which our backend does not
90 * try to clean up, since that should be done as the NIR stage)
91 * we cache the address value generated for a given src value:
93 struct hash_table
*addr_ht
;
95 /* maps nir_block to ir3_block, mostly for the purposes of
96 * figuring out the blocks successors
98 struct hash_table
*block_ht
;
100 /* for calculating input/output positions/linkages: */
103 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
104 * so we need to use ldlv.u32 to load the varying directly:
108 /* on a3xx, we need to add one to # of array levels:
112 /* on a3xx, we need to scale up integer coords for isaml based
115 bool unminify_coords
;
117 /* for looking up which system value is which */
118 unsigned sysval_semantics
[8];
120 /* list of kill instructions: */
121 struct ir3_instruction
*kill
[16];
122 unsigned int kill_count
;
124 /* set if we encounter something we can't handle yet, so we
125 * can bail cleanly and fallback to TGSI compiler f/e
131 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
132 static struct ir3_block
* get_block(struct ir3_compile
*ctx
, nir_block
*nblock
);
134 static struct nir_shader
*to_nir(const struct tgsi_token
*tokens
)
136 struct nir_shader_compiler_options options
= {
141 .native_integers
= true,
145 struct nir_shader
*s
= tgsi_to_nir(tokens
, &options
);
147 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
148 debug_printf("----------------------\n");
149 nir_print_shader(s
, stdout
);
150 debug_printf("----------------------\n");
153 nir_opt_global_to_local(s
);
154 nir_convert_to_ssa(s
);
160 nir_lower_vars_to_ssa(s
);
161 nir_lower_alu_to_scalar(s
);
162 nir_lower_phis_to_scalar(s
);
164 progress
|= nir_copy_prop(s
);
165 progress
|= nir_opt_dce(s
);
166 progress
|= nir_opt_cse(s
);
167 progress
|= ir3_nir_lower_if_else(s
);
168 progress
|= nir_opt_algebraic(s
);
169 progress
|= nir_opt_constant_folding(s
);
173 nir_remove_dead_variables(s
);
174 nir_validate_shader(s
);
176 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
177 debug_printf("----------------------\n");
178 nir_print_shader(s
, stdout
);
179 debug_printf("----------------------\n");
185 /* TODO nir doesn't lower everything for us yet, but ideally it would: */
186 static const struct tgsi_token
*
187 lower_tgsi(struct ir3_compile
*ctx
, const struct tgsi_token
*tokens
,
188 struct ir3_shader_variant
*so
)
190 struct tgsi_shader_info info
;
191 struct tgsi_lowering_config lconfig
= {
192 .color_two_side
= so
->key
.color_two_side
,
197 case SHADER_FRAGMENT
:
199 lconfig
.saturate_s
= so
->key
.fsaturate_s
;
200 lconfig
.saturate_t
= so
->key
.fsaturate_t
;
201 lconfig
.saturate_r
= so
->key
.fsaturate_r
;
204 lconfig
.saturate_s
= so
->key
.vsaturate_s
;
205 lconfig
.saturate_t
= so
->key
.vsaturate_t
;
206 lconfig
.saturate_r
= so
->key
.vsaturate_r
;
210 if (ctx
->compiler
->gpu_id
>= 400) {
211 /* a4xx seems to have *no* sam.p */
212 lconfig
.lower_TXP
= ~0; /* lower all txp */
214 /* a3xx just needs to avoid sam.p for 3d tex */
215 lconfig
.lower_TXP
= (1 << TGSI_TEXTURE_3D
);
218 return tgsi_transform_lowering(&lconfig
, tokens
, &info
);
221 static struct ir3_compile
*
222 compile_init(struct ir3_compiler
*compiler
,
223 struct ir3_shader_variant
*so
,
224 const struct tgsi_token
*tokens
)
226 struct ir3_compile
*ctx
= rzalloc(NULL
, struct ir3_compile
);
227 const struct tgsi_token
*lowered_tokens
;
229 if (compiler
->gpu_id
>= 400) {
230 /* need special handling for "flat" */
231 ctx
->flat_bypass
= true;
232 ctx
->levels_add_one
= false;
233 ctx
->unminify_coords
= false;
235 /* no special handling for "flat" */
236 ctx
->flat_bypass
= false;
237 ctx
->levels_add_one
= true;
238 ctx
->unminify_coords
= true;
241 ctx
->compiler
= compiler
;
245 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
246 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
247 ctx
->var_ht
= _mesa_hash_table_create(ctx
,
248 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
249 ctx
->addr_ht
= _mesa_hash_table_create(ctx
,
250 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
251 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
252 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
254 lowered_tokens
= lower_tgsi(ctx
, tokens
, so
);
256 lowered_tokens
= tokens
;
257 ctx
->s
= to_nir(lowered_tokens
);
259 if (lowered_tokens
!= tokens
)
260 free((void *)lowered_tokens
);
262 so
->first_driver_param
= so
->first_immediate
= ctx
->s
->num_uniforms
;
264 /* one (vec4) slot for vertex id base: */
265 if (so
->type
== SHADER_VERTEX
)
266 so
->first_immediate
++;
268 /* reserve 4 (vec4) slots for ubo base addresses: */
269 so
->first_immediate
+= 4;
275 compile_error(struct ir3_compile
*ctx
, const char *format
, ...)
278 va_start(ap
, format
);
279 _debug_vprintf(format
, ap
);
281 nir_print_shader(ctx
->s
, stdout
);
286 #define compile_assert(ctx, cond) do { \
287 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
291 compile_free(struct ir3_compile
*ctx
)
296 /* global per-array information: */
298 unsigned length
, aid
;
301 /* per-block array state: */
302 struct ir3_array_value
{
303 /* TODO drop length/aid, and just have ptr back to ir3_array */
304 unsigned length
, aid
;
305 /* initial array element values are phi's, other than for the
306 * entry block. The phi src's get added later in a resolve step
307 * after we have visited all the blocks, to account for back
310 struct ir3_instruction
**phis
;
311 /* current array element values (as block is processed). When
312 * the array phi's are resolved, it will contain the array state
313 * at exit of block, so successor blocks can use it to add their
316 struct ir3_instruction
*arr
[];
319 /* track array assignments per basic block. When an array is read
320 * outside of the same basic block, we can use NIR's dominance-frontier
321 * information to figure out where phi nodes are needed.
323 struct ir3_nir_block_data
{
325 /* indexed by array-id (aid): */
326 struct ir3_array_value
*arrs
[];
329 static struct ir3_nir_block_data
*
330 get_block_data(struct ir3_compile
*ctx
, struct ir3_block
*block
)
333 struct ir3_nir_block_data
*bd
= ralloc_size(ctx
, sizeof(*bd
) +
334 ((ctx
->num_arrays
+ 1) * sizeof(bd
->arrs
[0])));
341 declare_var(struct ir3_compile
*ctx
, nir_variable
*var
)
343 unsigned length
= glsl_get_length(var
->type
) * 4; /* always vec4, at least with ttn */
344 struct ir3_array
*arr
= ralloc(ctx
, struct ir3_array
);
345 arr
->length
= length
;
346 arr
->aid
= ++ctx
->num_arrays
;
347 _mesa_hash_table_insert(ctx
->var_ht
, var
, arr
);
351 nir_block_pred(nir_block
*block
)
353 assert(block
->predecessors
->entries
< 2);
354 if (block
->predecessors
->entries
== 0)
356 return (nir_block
*)_mesa_set_next_entry(block
->predecessors
, NULL
)->key
;
359 static struct ir3_array_value
*
360 get_var(struct ir3_compile
*ctx
, nir_variable
*var
)
362 struct hash_entry
*entry
= _mesa_hash_table_search(ctx
->var_ht
, var
);
363 struct ir3_block
*block
= ctx
->block
;
364 struct ir3_nir_block_data
*bd
= get_block_data(ctx
, block
);
365 struct ir3_array
*arr
= entry
->data
;
367 if (!bd
->arrs
[arr
->aid
]) {
368 struct ir3_array_value
*av
= ralloc_size(bd
, sizeof(*av
) +
369 (arr
->length
* sizeof(av
->arr
[0])));
370 struct ir3_array_value
*defn
= NULL
;
371 nir_block
*pred_block
;
373 av
->length
= arr
->length
;
376 /* For loops, we have to consider that we have not visited some
377 * of the blocks who should feed into the phi (ie. back-edges in
378 * the cfg).. for example:
381 * block { load_var; ... }
382 * if then block {} else block {}
383 * block { store_var; ... }
384 * if then block {} else block {}
388 * We can skip the phi if we can chase the block predecessors
389 * until finding the block previously defining the array without
390 * crossing a block that has more than one predecessor.
392 * Otherwise create phi's and resolve them as a post-pass after
393 * all the blocks have been visited (to handle back-edges).
396 for (pred_block
= block
->nblock
;
397 pred_block
&& (pred_block
->predecessors
->entries
< 2) && !defn
;
398 pred_block
= nir_block_pred(pred_block
)) {
399 struct ir3_block
*pblock
= get_block(ctx
, pred_block
);
400 struct ir3_nir_block_data
*pbd
= pblock
->bd
;
403 defn
= pbd
->arrs
[arr
->aid
];
407 /* only one possible definer: */
408 for (unsigned i
= 0; i
< arr
->length
; i
++)
409 av
->arr
[i
] = defn
->arr
[i
];
410 } else if (pred_block
) {
411 /* not the first block, and multiple potential definers: */
412 av
->phis
= ralloc_size(av
, arr
->length
* sizeof(av
->phis
[0]));
414 for (unsigned i
= 0; i
< arr
->length
; i
++) {
415 struct ir3_instruction
*phi
;
417 phi
= ir3_instr_create2(block
, -1, OPC_META_PHI
,
418 1 + ctx
->impl
->num_blocks
);
419 ir3_reg_create(phi
, 0, 0); /* dst */
421 /* phi's should go at head of block: */
422 list_delinit(&phi
->node
);
423 list_add(&phi
->node
, &block
->instr_list
);
425 av
->phis
[i
] = av
->arr
[i
] = phi
;
428 /* Some shaders end up reading array elements without
429 * first writing.. so initialize things to prevent null
432 for (unsigned i
= 0; i
< arr
->length
; i
++)
433 av
->arr
[i
] = create_immed(block
, 0);
436 bd
->arrs
[arr
->aid
] = av
;
439 return bd
->arrs
[arr
->aid
];
443 add_array_phi_srcs(struct ir3_compile
*ctx
, nir_block
*nblock
,
444 struct ir3_array_value
*av
, BITSET_WORD
*visited
)
446 struct ir3_block
*block
;
447 struct ir3_nir_block_data
*bd
;
449 if (BITSET_TEST(visited
, nblock
->index
))
452 BITSET_SET(visited
, nblock
->index
);
454 block
= get_block(ctx
, nblock
);
457 if (bd
&& bd
->arrs
[av
->aid
]) {
458 struct ir3_array_value
*dav
= bd
->arrs
[av
->aid
];
459 for (unsigned i
= 0; i
< av
->length
; i
++) {
460 ir3_reg_create(av
->phis
[i
], 0, IR3_REG_SSA
)->instr
=
464 /* didn't find defn, recurse predecessors: */
465 struct set_entry
*entry
;
466 set_foreach(nblock
->predecessors
, entry
) {
467 add_array_phi_srcs(ctx
, (nir_block
*)entry
->key
, av
, visited
);
473 resolve_array_phis(struct ir3_compile
*ctx
, struct ir3_block
*block
)
475 struct ir3_nir_block_data
*bd
= block
->bd
;
476 unsigned bitset_words
= BITSET_WORDS(ctx
->impl
->num_blocks
);
481 /* TODO use nir dom_frontier to help us with this? */
483 for (unsigned i
= 1; i
<= ctx
->num_arrays
; i
++) {
484 struct ir3_array_value
*av
= bd
->arrs
[i
];
485 BITSET_WORD visited
[bitset_words
];
486 struct set_entry
*entry
;
488 if (!(av
&& av
->phis
))
491 memset(visited
, 0, sizeof(visited
));
492 set_foreach(block
->nblock
->predecessors
, entry
) {
493 add_array_phi_srcs(ctx
, (nir_block
*)entry
->key
, av
, visited
);
498 /* allocate a n element value array (to be populated by caller) and
501 static struct ir3_instruction
**
502 __get_dst(struct ir3_compile
*ctx
, void *key
, unsigned n
)
504 struct ir3_instruction
**value
=
505 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
506 _mesa_hash_table_insert(ctx
->def_ht
, key
, value
);
510 static struct ir3_instruction
**
511 get_dst(struct ir3_compile
*ctx
, nir_dest
*dst
, unsigned n
)
514 return __get_dst(ctx
, &dst
->ssa
, n
);
516 return __get_dst(ctx
, dst
->reg
.reg
, n
);
520 static struct ir3_instruction
**
521 get_dst_ssa(struct ir3_compile
*ctx
, nir_ssa_def
*dst
, unsigned n
)
523 return __get_dst(ctx
, dst
, n
);
526 static struct ir3_instruction
**
527 get_src(struct ir3_compile
*ctx
, nir_src
*src
)
529 struct hash_entry
*entry
;
531 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
533 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->reg
.reg
);
535 compile_assert(ctx
, entry
);
539 static struct ir3_instruction
*
540 create_immed(struct ir3_block
*block
, uint32_t val
)
542 struct ir3_instruction
*mov
;
544 mov
= ir3_instr_create(block
, 1, 0);
545 mov
->cat1
.src_type
= TYPE_U32
;
546 mov
->cat1
.dst_type
= TYPE_U32
;
547 ir3_reg_create(mov
, 0, 0);
548 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
553 static struct ir3_instruction
*
554 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
)
556 struct ir3_instruction
*instr
, *immed
;
558 /* TODO in at least some cases, the backend could probably be
559 * made clever enough to propagate IR3_REG_HALF..
561 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
562 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
564 immed
= create_immed(block
, 2);
565 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
567 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
568 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
569 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
571 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
572 instr
->regs
[0]->num
= regid(REG_A0
, 0);
573 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
574 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
579 /* caches addr values to avoid generating multiple cov/shl/mova
580 * sequences for each use of a given NIR level src as address
582 static struct ir3_instruction
*
583 get_addr(struct ir3_compile
*ctx
, struct ir3_instruction
*src
)
585 struct ir3_instruction
*addr
;
586 struct hash_entry
*entry
;
587 entry
= _mesa_hash_table_search(ctx
->addr_ht
, src
);
591 /* TODO do we need to cache per block? */
592 addr
= create_addr(ctx
->block
, src
);
593 _mesa_hash_table_insert(ctx
->addr_ht
, src
, addr
);
598 static struct ir3_instruction
*
599 get_predicate(struct ir3_compile
*ctx
, struct ir3_instruction
*src
)
601 struct ir3_block
*b
= ctx
->block
;
602 struct ir3_instruction
*cond
;
604 /* NOTE: only cmps.*.* can write p0.x: */
605 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
606 cond
->cat2
.condition
= IR3_COND_NE
;
608 /* condition always goes in predicate register: */
609 cond
->regs
[0]->num
= regid(REG_P0
, 0);
614 static struct ir3_instruction
*
615 create_uniform(struct ir3_compile
*ctx
, unsigned n
)
617 struct ir3_instruction
*mov
;
619 mov
= ir3_instr_create(ctx
->block
, 1, 0);
620 /* TODO get types right? */
621 mov
->cat1
.src_type
= TYPE_F32
;
622 mov
->cat1
.dst_type
= TYPE_F32
;
623 ir3_reg_create(mov
, 0, 0);
624 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
629 static struct ir3_instruction
*
630 create_uniform_indirect(struct ir3_compile
*ctx
, unsigned n
,
631 struct ir3_instruction
*address
)
633 struct ir3_instruction
*mov
;
635 mov
= ir3_instr_create(ctx
->block
, 1, 0);
636 mov
->cat1
.src_type
= TYPE_U32
;
637 mov
->cat1
.dst_type
= TYPE_U32
;
638 ir3_reg_create(mov
, 0, 0);
639 ir3_reg_create(mov
, n
, IR3_REG_CONST
| IR3_REG_RELATIV
);
640 mov
->address
= address
;
642 array_insert(ctx
->ir
->indirects
, mov
);
647 static struct ir3_instruction
*
648 create_collect(struct ir3_block
*block
, struct ir3_instruction
**arr
,
651 struct ir3_instruction
*collect
;
656 collect
= ir3_instr_create2(block
, -1, OPC_META_FI
, 1 + arrsz
);
657 ir3_reg_create(collect
, 0, 0); /* dst */
658 for (unsigned i
= 0; i
< arrsz
; i
++)
659 ir3_reg_create(collect
, 0, IR3_REG_SSA
)->instr
= arr
[i
];
664 static struct ir3_instruction
*
665 create_indirect_load(struct ir3_compile
*ctx
, unsigned arrsz
, unsigned n
,
666 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
668 struct ir3_block
*block
= ctx
->block
;
669 struct ir3_instruction
*mov
;
670 struct ir3_register
*src
;
672 mov
= ir3_instr_create(block
, 1, 0);
673 mov
->cat1
.src_type
= TYPE_U32
;
674 mov
->cat1
.dst_type
= TYPE_U32
;
675 ir3_reg_create(mov
, 0, 0);
676 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
677 src
->instr
= collect
;
680 mov
->address
= address
;
682 array_insert(ctx
->ir
->indirects
, mov
);
687 static struct ir3_instruction
*
688 create_indirect_store(struct ir3_compile
*ctx
, unsigned arrsz
, unsigned n
,
689 struct ir3_instruction
*src
, struct ir3_instruction
*address
,
690 struct ir3_instruction
*collect
)
692 struct ir3_block
*block
= ctx
->block
;
693 struct ir3_instruction
*mov
;
694 struct ir3_register
*dst
;
696 mov
= ir3_instr_create(block
, 1, 0);
697 mov
->cat1
.src_type
= TYPE_U32
;
698 mov
->cat1
.dst_type
= TYPE_U32
;
699 dst
= ir3_reg_create(mov
, 0, IR3_REG_RELATIV
);
702 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
703 mov
->address
= address
;
704 mov
->fanin
= collect
;
706 array_insert(ctx
->ir
->indirects
, mov
);
711 static struct ir3_instruction
*
712 create_input(struct ir3_block
*block
, struct ir3_instruction
*instr
,
715 struct ir3_instruction
*in
;
717 in
= ir3_instr_create(block
, -1, OPC_META_INPUT
);
718 in
->inout
.block
= block
;
719 ir3_reg_create(in
, n
, 0);
721 ir3_reg_create(in
, 0, IR3_REG_SSA
)->instr
= instr
;
726 static struct ir3_instruction
*
727 create_frag_input(struct ir3_compile
*ctx
, unsigned n
, bool use_ldlv
)
729 struct ir3_block
*block
= ctx
->block
;
730 struct ir3_instruction
*instr
;
731 struct ir3_instruction
*inloc
= create_immed(block
, n
);
734 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
735 instr
->cat6
.type
= TYPE_U32
;
736 instr
->cat6
.iim_val
= 1;
738 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_pos
, 0);
739 instr
->regs
[2]->wrmask
= 0x3;
745 static struct ir3_instruction
*
746 create_frag_coord(struct ir3_compile
*ctx
, unsigned comp
)
748 struct ir3_block
*block
= ctx
->block
;
749 struct ir3_instruction
*instr
;
751 compile_assert(ctx
, !ctx
->frag_coord
[comp
]);
753 ctx
->frag_coord
[comp
] = create_input(ctx
->block
, NULL
, 0);
758 /* for frag_coord, we get unsigned values.. we need
759 * to subtract (integer) 8 and divide by 16 (right-
760 * shift by 4) then convert to float:
764 * mov.u32f32 dst, tmp
767 instr
= ir3_SUB_S(block
, ctx
->frag_coord
[comp
], 0,
768 create_immed(block
, 8), 0);
769 instr
= ir3_SHR_B(block
, instr
, 0,
770 create_immed(block
, 4), 0);
771 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
777 /* seems that we can use these as-is: */
778 return ctx
->frag_coord
[comp
];
782 static struct ir3_instruction
*
783 create_frag_face(struct ir3_compile
*ctx
, unsigned comp
)
785 struct ir3_block
*block
= ctx
->block
;
786 struct ir3_instruction
*instr
;
790 compile_assert(ctx
, !ctx
->frag_face
);
792 ctx
->frag_face
= create_input(block
, NULL
, 0);
793 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
795 /* for faceness, we always get -1 or 0 (int).. but TGSI expects
796 * positive vs negative float.. and piglit further seems to
797 * expect -1.0 or 1.0:
799 * mul.s tmp, hr0.x, 2
801 * mov.s32f32, dst, tmp
804 instr
= ir3_MUL_S(block
, ctx
->frag_face
, 0,
805 create_immed(block
, 2), 0);
806 instr
= ir3_ADD_S(block
, instr
, 0,
807 create_immed(block
, 1), 0);
808 instr
= ir3_COV(block
, instr
, TYPE_S32
, TYPE_F32
);
813 return create_immed(block
, fui(0.0));
816 return create_immed(block
, fui(1.0));
820 /* helper for instructions that produce multiple consecutive scalar
821 * outputs which need to have a split/fanout meta instruction inserted
824 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
825 struct ir3_instruction
*src
, unsigned n
)
827 struct ir3_instruction
*prev
= NULL
;
828 for (int i
= 0, j
= 0; i
< n
; i
++) {
829 struct ir3_instruction
*split
=
830 ir3_instr_create(block
, -1, OPC_META_FO
);
831 ir3_reg_create(split
, 0, IR3_REG_SSA
);
832 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
836 split
->cp
.left
= prev
;
837 split
->cp
.left_cnt
++;
838 prev
->cp
.right
= split
;
839 prev
->cp
.right_cnt
++;
843 if (src
->regs
[0]->wrmask
& (1 << i
))
849 * Adreno uses uint rather than having dedicated bool type,
850 * which (potentially) requires some conversion, in particular
851 * when using output of an bool instr to int input, or visa
855 * -------+---------+-------+-
859 * To convert from an adreno bool (uint) to nir, use:
861 * absneg.s dst, (neg)src
863 * To convert back in the other direction:
865 * absneg.s dst, (abs)arc
867 * The CP step can clean up the absneg.s that cancel each other
868 * out, and with a slight bit of extra cleverness (to recognize
869 * the instructions which produce either a 0 or 1) can eliminate
870 * the absneg.s's completely when an instruction that wants
871 * 0/1 consumes the result. For example, when a nir 'bcsel'
872 * consumes the result of 'feq'. So we should be able to get by
873 * without a boolean resolve step, and without incuring any
874 * extra penalty in instruction count.
877 /* NIR bool -> native (adreno): */
878 static struct ir3_instruction
*
879 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
881 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
884 /* native (adreno) -> NIR bool: */
885 static struct ir3_instruction
*
886 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
888 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
892 * alu/sfu instructions:
896 emit_alu(struct ir3_compile
*ctx
, nir_alu_instr
*alu
)
898 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
899 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
900 struct ir3_block
*b
= ctx
->block
;
902 dst
= get_dst(ctx
, &alu
->dest
.dest
, MAX2(info
->output_size
, 1));
904 /* Vectors are special in that they have non-scalarized writemasks,
905 * and just take the first swizzle channel for each argument in
906 * order into each writemask channel.
908 if ((alu
->op
== nir_op_vec2
) ||
909 (alu
->op
== nir_op_vec3
) ||
910 (alu
->op
== nir_op_vec4
)) {
912 for (int i
= 0; i
< info
->num_inputs
; i
++) {
913 nir_alu_src
*asrc
= &alu
->src
[i
];
915 compile_assert(ctx
, !asrc
->abs
);
916 compile_assert(ctx
, !asrc
->negate
);
918 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
920 src
[i
] = create_immed(ctx
->block
, 0);
921 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
927 /* General case: We can just grab the one used channel per src. */
928 for (int i
= 0; i
< info
->num_inputs
; i
++) {
929 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
930 nir_alu_src
*asrc
= &alu
->src
[i
];
932 compile_assert(ctx
, !asrc
->abs
);
933 compile_assert(ctx
, !asrc
->negate
);
935 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
937 compile_assert(ctx
, src
[i
]);
942 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_S32
);
945 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_U32
);
948 dst
[0] = ir3_COV(b
, src
[0], TYPE_S32
, TYPE_F32
);
951 dst
[0] = ir3_COV(b
, src
[0], TYPE_U32
, TYPE_F32
);
954 dst
[0] = ir3_MOV(b
, src
[0], TYPE_S32
);
957 dst
[0] = ir3_MOV(b
, src
[0], TYPE_F32
);
960 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
961 dst
[0]->cat2
.condition
= IR3_COND_NE
;
962 dst
[0] = ir3_n2b(b
, dst
[0]);
965 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
968 dst
[0] = ir3_b2n(b
, src
[0]);
971 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
972 dst
[0]->cat2
.condition
= IR3_COND_NE
;
973 dst
[0] = ir3_n2b(b
, dst
[0]);
977 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
980 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
983 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
986 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
989 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
992 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
995 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
998 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
1001 dst
[0] = ir3_DSX(b
, src
[0], 0);
1002 dst
[0]->cat5
.type
= TYPE_F32
;
1005 dst
[0] = ir3_DSY(b
, src
[0], 0);
1006 dst
[0]->cat5
.type
= TYPE_F32
;
1010 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1011 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1012 dst
[0] = ir3_n2b(b
, dst
[0]);
1015 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1016 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1017 dst
[0] = ir3_n2b(b
, dst
[0]);
1020 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1021 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1022 dst
[0] = ir3_n2b(b
, dst
[0]);
1025 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1026 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1027 dst
[0] = ir3_n2b(b
, dst
[0]);
1030 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
1033 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
1036 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
1038 case nir_op_fround_even
:
1039 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
1042 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
1046 dst
[0] = ir3_SIN(b
, src
[0], 0);
1049 dst
[0] = ir3_COS(b
, src
[0], 0);
1052 dst
[0] = ir3_RSQ(b
, src
[0], 0);
1055 dst
[0] = ir3_RCP(b
, src
[0], 0);
1058 dst
[0] = ir3_LOG2(b
, src
[0], 0);
1061 dst
[0] = ir3_EXP2(b
, src
[0], 0);
1064 dst
[0] = ir3_SQRT(b
, src
[0], 0);
1068 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
1071 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
1074 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
1077 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
1080 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
1083 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
1086 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
1090 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
1091 * mull.u tmp0, a, b ; mul low, i.e. al * bl
1092 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
1093 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
1095 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
1096 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
1097 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
1100 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
1103 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
1106 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
1109 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
1112 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
1114 case nir_op_isign
: {
1115 /* maybe this would be sane to lower in nir.. */
1116 struct ir3_instruction
*neg
, *pos
;
1118 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1119 neg
->cat2
.condition
= IR3_COND_LT
;
1121 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1122 pos
->cat2
.condition
= IR3_COND_GT
;
1124 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
1129 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
1132 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
1135 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
1138 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1139 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1140 dst
[0] = ir3_n2b(b
, dst
[0]);
1143 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1144 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1145 dst
[0] = ir3_n2b(b
, dst
[0]);
1148 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1149 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1150 dst
[0] = ir3_n2b(b
, dst
[0]);
1153 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1154 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1155 dst
[0] = ir3_n2b(b
, dst
[0]);
1158 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1159 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1160 dst
[0] = ir3_n2b(b
, dst
[0]);
1163 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1164 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1165 dst
[0] = ir3_n2b(b
, dst
[0]);
1169 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, ir3_b2n(b
, src
[0]), 0, src
[2], 0);
1173 compile_error(ctx
, "Unhandled ALU op: %s\n",
1174 nir_op_infos
[alu
->op
].name
);
1179 /* handles direct/indirect UBO reads: */
1181 emit_intrinsic_load_ubo(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1182 struct ir3_instruction
**dst
)
1184 struct ir3_block
*b
= ctx
->block
;
1185 struct ir3_instruction
*addr
, *src0
, *src1
;
1186 /* UBO addresses are the first driver params: */
1187 unsigned ubo
= regid(ctx
->so
->first_driver_param
, 0);
1188 unsigned off
= intr
->const_index
[0];
1190 /* First src is ubo index, which could either be an immed or not: */
1191 src0
= get_src(ctx
, &intr
->src
[0])[0];
1192 if (is_same_type_mov(src0
) &&
1193 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1194 addr
= create_uniform(ctx
, ubo
+ src0
->regs
[1]->iim_val
);
1196 addr
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
));
1199 if (intr
->intrinsic
== nir_intrinsic_load_ubo_indirect
) {
1200 /* For load_ubo_indirect, second src is indirect offset: */
1201 src1
= get_src(ctx
, &intr
->src
[1])[0];
1203 /* and add offset to addr: */
1204 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1207 /* if offset is to large to encode in the ldg, split it out: */
1208 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1209 /* split out the minimal amount to improve the odds that
1210 * cp can fit the immediate in the add.s instruction:
1212 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1213 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1217 for (int i
= 0; i
< intr
->num_components
; i
++) {
1218 struct ir3_instruction
*load
=
1219 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1220 load
->cat6
.type
= TYPE_U32
;
1221 load
->cat6
.offset
= off
+ i
* 4; /* byte offset */
1226 /* handles array reads: */
1228 emit_intrinisic_load_var(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1229 struct ir3_instruction
**dst
)
1231 nir_deref_var
*dvar
= intr
->variables
[0];
1232 nir_deref_array
*darr
= nir_deref_as_array(dvar
->deref
.child
);
1233 struct ir3_array_value
*arr
= get_var(ctx
, dvar
->var
);
1235 compile_assert(ctx
, dvar
->deref
.child
&&
1236 (dvar
->deref
.child
->deref_type
== nir_deref_type_array
));
1238 switch (darr
->deref_array_type
) {
1239 case nir_deref_array_type_direct
:
1240 /* direct access does not require anything special: */
1241 for (int i
= 0; i
< intr
->num_components
; i
++) {
1242 unsigned n
= darr
->base_offset
* 4 + i
;
1243 compile_assert(ctx
, n
< arr
->length
);
1244 dst
[i
] = arr
->arr
[n
];
1247 case nir_deref_array_type_indirect
: {
1248 /* for indirect, we need to collect all the array elements: */
1249 struct ir3_instruction
*collect
=
1250 create_collect(ctx
->block
, arr
->arr
, arr
->length
);
1251 struct ir3_instruction
*addr
=
1252 get_addr(ctx
, get_src(ctx
, &darr
->indirect
)[0]);
1253 for (int i
= 0; i
< intr
->num_components
; i
++) {
1254 unsigned n
= darr
->base_offset
* 4 + i
;
1255 compile_assert(ctx
, n
< arr
->length
);
1256 dst
[i
] = create_indirect_load(ctx
, arr
->length
, n
, addr
, collect
);
1261 compile_error(ctx
, "Unhandled load deref type: %u\n",
1262 darr
->deref_array_type
);
1267 /* handles array writes: */
1269 emit_intrinisic_store_var(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1271 nir_deref_var
*dvar
= intr
->variables
[0];
1272 nir_deref_array
*darr
= nir_deref_as_array(dvar
->deref
.child
);
1273 struct ir3_array_value
*arr
= get_var(ctx
, dvar
->var
);
1274 struct ir3_instruction
**src
;
1276 compile_assert(ctx
, dvar
->deref
.child
&&
1277 (dvar
->deref
.child
->deref_type
== nir_deref_type_array
));
1279 src
= get_src(ctx
, &intr
->src
[0]);
1281 switch (darr
->deref_array_type
) {
1282 case nir_deref_array_type_direct
:
1283 /* direct access does not require anything special: */
1284 for (int i
= 0; i
< intr
->num_components
; i
++) {
1285 unsigned n
= darr
->base_offset
* 4 + i
;
1286 compile_assert(ctx
, n
< arr
->length
);
1287 arr
->arr
[n
] = src
[i
];
1290 case nir_deref_array_type_indirect
: {
1291 /* for indirect, create indirect-store and fan that out: */
1292 struct ir3_instruction
*collect
=
1293 create_collect(ctx
->block
, arr
->arr
, arr
->length
);
1294 struct ir3_instruction
*addr
=
1295 get_addr(ctx
, get_src(ctx
, &darr
->indirect
)[0]);
1296 for (int i
= 0; i
< intr
->num_components
; i
++) {
1297 struct ir3_instruction
*store
;
1298 unsigned n
= darr
->base_offset
* 4 + i
;
1299 compile_assert(ctx
, n
< arr
->length
);
1301 store
= create_indirect_store(ctx
, arr
->length
,
1302 n
, src
[i
], addr
, collect
);
1304 store
->fanin
->fi
.aid
= arr
->aid
;
1306 /* TODO: probably split this out to be used for
1307 * store_output_indirect? or move this into
1308 * create_indirect_store()?
1310 for (int j
= i
; j
< arr
->length
; j
+= intr
->num_components
) {
1311 struct ir3_instruction
*split
;
1313 split
= ir3_instr_create(ctx
->block
, -1, OPC_META_FO
);
1315 ir3_reg_create(split
, 0, 0);
1316 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= store
;
1318 arr
->arr
[j
] = split
;
1321 /* fixup fanout/split neighbors: */
1322 for (int i
= 0; i
< arr
->length
; i
++) {
1323 arr
->arr
[i
]->cp
.right
= (i
< (arr
->length
- 1)) ?
1324 arr
->arr
[i
+1] : NULL
;
1325 arr
->arr
[i
]->cp
.left
= (i
> 0) ?
1326 arr
->arr
[i
-1] : NULL
;
1331 compile_error(ctx
, "Unhandled store deref type: %u\n",
1332 darr
->deref_array_type
);
1337 static void add_sysval_input(struct ir3_compile
*ctx
, unsigned name
,
1338 struct ir3_instruction
*instr
)
1340 struct ir3_shader_variant
*so
= ctx
->so
;
1341 unsigned r
= regid(so
->inputs_count
, 0);
1342 unsigned n
= so
->inputs_count
++;
1344 so
->inputs
[n
].semantic
= ir3_semantic_name(name
, 0);
1345 so
->inputs
[n
].compmask
= 1;
1346 so
->inputs
[n
].regid
= r
;
1347 so
->inputs
[n
].interpolate
= TGSI_INTERPOLATE_CONSTANT
;
1350 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
1351 ctx
->ir
->inputs
[r
] = instr
;
1355 emit_intrinisic(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1357 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1358 struct ir3_instruction
**dst
, **src
;
1359 struct ir3_block
*b
= ctx
->block
;
1360 unsigned idx
= intr
->const_index
[0];
1362 if (info
->has_dest
) {
1363 dst
= get_dst(ctx
, &intr
->dest
, intr
->num_components
);
1368 switch (intr
->intrinsic
) {
1369 case nir_intrinsic_load_uniform
:
1370 for (int i
= 0; i
< intr
->num_components
; i
++) {
1371 unsigned n
= idx
* 4 + i
;
1372 dst
[i
] = create_uniform(ctx
, n
);
1375 case nir_intrinsic_load_uniform_indirect
:
1376 src
= get_src(ctx
, &intr
->src
[0]);
1377 for (int i
= 0; i
< intr
->num_components
; i
++) {
1378 unsigned n
= idx
* 4 + i
;
1379 dst
[i
] = create_uniform_indirect(ctx
, n
,
1380 get_addr(ctx
, src
[0]));
1382 /* NOTE: if relative addressing is used, we set constlen in
1383 * the compiler (to worst-case value) since we don't know in
1384 * the assembler what the max addr reg value can be:
1386 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
1388 case nir_intrinsic_load_ubo
:
1389 case nir_intrinsic_load_ubo_indirect
:
1390 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1392 case nir_intrinsic_load_input
:
1393 for (int i
= 0; i
< intr
->num_components
; i
++) {
1394 unsigned n
= idx
* 4 + i
;
1395 dst
[i
] = ctx
->ir
->inputs
[n
];
1398 case nir_intrinsic_load_input_indirect
:
1399 src
= get_src(ctx
, &intr
->src
[0]);
1400 struct ir3_instruction
*collect
=
1401 create_collect(b
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
1402 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0]);
1403 for (int i
= 0; i
< intr
->num_components
; i
++) {
1404 unsigned n
= idx
* 4 + i
;
1405 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
1409 case nir_intrinsic_load_var
:
1410 emit_intrinisic_load_var(ctx
, intr
, dst
);
1412 case nir_intrinsic_store_var
:
1413 emit_intrinisic_store_var(ctx
, intr
);
1415 case nir_intrinsic_store_output
:
1416 src
= get_src(ctx
, &intr
->src
[0]);
1417 for (int i
= 0; i
< intr
->num_components
; i
++) {
1418 unsigned n
= idx
* 4 + i
;
1419 ctx
->ir
->outputs
[n
] = src
[i
];
1422 case nir_intrinsic_load_base_vertex
:
1423 if (!ctx
->basevertex
) {
1424 /* first four vec4 sysval's reserved for UBOs: */
1425 unsigned r
= regid(ctx
->so
->first_driver_param
+ 4, 0);
1426 ctx
->basevertex
= create_uniform(ctx
, r
);
1427 add_sysval_input(ctx
, TGSI_SEMANTIC_BASEVERTEX
,
1430 dst
[0] = ctx
->basevertex
;
1432 case nir_intrinsic_load_vertex_id_zero_base
:
1433 if (!ctx
->vertex_id
) {
1434 ctx
->vertex_id
= create_input(ctx
->block
, NULL
, 0);
1435 add_sysval_input(ctx
, TGSI_SEMANTIC_VERTEXID_NOBASE
,
1438 dst
[0] = ctx
->vertex_id
;
1440 case nir_intrinsic_load_instance_id
:
1441 if (!ctx
->instance_id
) {
1442 ctx
->instance_id
= create_input(ctx
->block
, NULL
, 0);
1443 add_sysval_input(ctx
, TGSI_SEMANTIC_INSTANCEID
,
1446 dst
[0] = ctx
->instance_id
;
1448 case nir_intrinsic_discard_if
:
1449 case nir_intrinsic_discard
: {
1450 struct ir3_instruction
*cond
, *kill
;
1452 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
1453 /* conditional discard: */
1454 src
= get_src(ctx
, &intr
->src
[0]);
1455 cond
= ir3_b2n(b
, src
[0]);
1457 /* unconditional discard: */
1458 cond
= create_immed(b
, 1);
1461 /* NOTE: only cmps.*.* can write p0.x: */
1462 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1463 cond
->cat2
.condition
= IR3_COND_NE
;
1465 /* condition always goes in predicate register: */
1466 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1468 kill
= ir3_KILL(b
, cond
, 0);
1469 array_insert(ctx
->ir
->predicates
, kill
);
1471 ctx
->kill
[ctx
->kill_count
++] = kill
;
1472 ctx
->so
->has_kill
= true;
1477 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
1478 nir_intrinsic_infos
[intr
->intrinsic
].name
);
1484 emit_load_const(struct ir3_compile
*ctx
, nir_load_const_instr
*instr
)
1486 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
1487 instr
->def
.num_components
);
1488 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1489 dst
[i
] = create_immed(ctx
->block
, instr
->value
.u
[i
]);
1493 emit_undef(struct ir3_compile
*ctx
, nir_ssa_undef_instr
*undef
)
1495 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
1496 undef
->def
.num_components
);
1497 /* backend doesn't want undefined instructions, so just plug
1500 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
1501 dst
[i
] = create_immed(ctx
->block
, fui(0.0));
1505 * texture fetch/sample instructions:
1509 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
1511 unsigned coords
, flags
= 0;
1513 /* note: would use tex->coord_components.. except txs.. also,
1514 * since array index goes after shadow ref, we don't want to
1517 switch (tex
->sampler_dim
) {
1518 case GLSL_SAMPLER_DIM_1D
:
1519 case GLSL_SAMPLER_DIM_BUF
:
1522 case GLSL_SAMPLER_DIM_2D
:
1523 case GLSL_SAMPLER_DIM_RECT
:
1524 case GLSL_SAMPLER_DIM_EXTERNAL
:
1525 case GLSL_SAMPLER_DIM_MS
:
1528 case GLSL_SAMPLER_DIM_3D
:
1529 case GLSL_SAMPLER_DIM_CUBE
:
1531 flags
|= IR3_INSTR_3D
;
1534 unreachable("bad sampler_dim");
1538 flags
|= IR3_INSTR_S
;
1541 flags
|= IR3_INSTR_A
;
1548 emit_tex(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1550 struct ir3_block
*b
= ctx
->block
;
1551 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
1552 struct ir3_instruction
**coord
, *lod
, *compare
, *proj
, **off
, **ddx
, **ddy
;
1553 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
1554 unsigned i
, coords
, flags
;
1555 unsigned nsrc0
= 0, nsrc1
= 0;
1559 coord
= off
= ddx
= ddy
= NULL
;
1560 lod
= proj
= compare
= NULL
;
1562 /* TODO: might just be one component for gathers? */
1563 dst
= get_dst(ctx
, &tex
->dest
, 4);
1565 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
1566 switch (tex
->src
[i
].src_type
) {
1567 case nir_tex_src_coord
:
1568 coord
= get_src(ctx
, &tex
->src
[i
].src
);
1570 case nir_tex_src_bias
:
1571 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1574 case nir_tex_src_lod
:
1575 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1578 case nir_tex_src_comparitor
: /* shadow comparator */
1579 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1581 case nir_tex_src_projector
:
1582 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1585 case nir_tex_src_offset
:
1586 off
= get_src(ctx
, &tex
->src
[i
].src
);
1589 case nir_tex_src_ddx
:
1590 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
1592 case nir_tex_src_ddy
:
1593 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
1596 compile_error(ctx
, "Unhandled NIR tex serc type: %d\n",
1597 tex
->src
[i
].src_type
);
1603 case nir_texop_tex
: opc
= OPC_SAM
; break;
1604 case nir_texop_txb
: opc
= OPC_SAMB
; break;
1605 case nir_texop_txl
: opc
= OPC_SAML
; break;
1606 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
1607 case nir_texop_txf
: opc
= OPC_ISAML
; break;
1608 case nir_texop_txf_ms
:
1612 case nir_texop_query_levels
:
1613 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
1617 tex_info(tex
, &flags
, &coords
);
1619 /* scale up integer coords for TXF based on the LOD */
1620 if (ctx
->unminify_coords
&& (opc
== OPC_ISAML
)) {
1622 for (i
= 0; i
< coords
; i
++)
1623 coord
[i
] = ir3_SHL_B(b
, coord
[i
], 0, lod
, 0);
1627 * lay out the first argument in the proper order:
1628 * - actual coordinates first
1629 * - shadow reference
1632 * - starting at offset 4, dpdx.xy, dpdy.xy
1634 * bias/lod go into the second arg
1637 /* insert tex coords: */
1638 for (i
= 0; i
< coords
; i
++)
1639 src0
[nsrc0
++] = coord
[i
];
1642 /* hw doesn't do 1d, so we treat it as 2d with
1643 * height of 1, and patch up the y coord.
1644 * TODO: y coord should be (int)0 in some cases..
1646 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
1650 src0
[nsrc0
++] = compare
;
1653 src0
[nsrc0
++] = coord
[coords
];
1656 src0
[nsrc0
++] = proj
;
1657 flags
|= IR3_INSTR_P
;
1660 /* pad to 4, then ddx/ddy: */
1661 if (tex
->op
== nir_texop_txd
) {
1663 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1664 for (i
= 0; i
< coords
; i
++)
1665 src0
[nsrc0
++] = ddx
[i
];
1667 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1668 for (i
= 0; i
< coords
; i
++)
1669 src0
[nsrc0
++] = ddy
[i
];
1671 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1675 * second argument (if applicable):
1680 if (has_off
| has_lod
| has_bias
) {
1682 for (i
= 0; i
< coords
; i
++)
1683 src1
[nsrc1
++] = off
[i
];
1685 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
1686 flags
|= IR3_INSTR_O
;
1689 if (has_lod
| has_bias
)
1690 src1
[nsrc1
++] = lod
;
1693 switch (tex
->dest_type
) {
1694 case nir_type_invalid
:
1695 case nir_type_float
:
1701 case nir_type_unsigned
:
1706 unreachable("bad dest_type");
1709 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
,
1710 flags
, tex
->sampler_index
, tex
->sampler_index
,
1711 create_collect(b
, src0
, nsrc0
),
1712 create_collect(b
, src1
, nsrc1
));
1714 split_dest(b
, dst
, sam
, 4);
1718 emit_tex_query_levels(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1720 struct ir3_block
*b
= ctx
->block
;
1721 struct ir3_instruction
**dst
, *sam
;
1723 dst
= get_dst(ctx
, &tex
->dest
, 1);
1725 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
1726 tex
->sampler_index
, tex
->sampler_index
, NULL
, NULL
);
1728 /* even though there is only one component, since it ends
1729 * up in .z rather than .x, we need a split_dest()
1731 split_dest(b
, dst
, sam
, 3);
1733 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1734 * the value in TEX_CONST_0 is zero-based.
1736 if (ctx
->levels_add_one
)
1737 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
1741 emit_tex_txs(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1743 struct ir3_block
*b
= ctx
->block
;
1744 struct ir3_instruction
**dst
, *sam
, *lod
;
1745 unsigned flags
, coords
;
1747 tex_info(tex
, &flags
, &coords
);
1749 dst
= get_dst(ctx
, &tex
->dest
, 4);
1751 compile_assert(ctx
, tex
->num_srcs
== 1);
1752 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
1754 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
1756 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
1757 tex
->sampler_index
, tex
->sampler_index
, lod
, NULL
);
1759 split_dest(b
, dst
, sam
, 4);
1761 /* Array size actually ends up in .w rather than .z. This doesn't
1762 * matter for miplevel 0, but for higher mips the value in z is
1763 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1764 * returned, which means that we have to add 1 to it for arrays.
1766 if (tex
->is_array
) {
1767 if (ctx
->levels_add_one
) {
1768 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
1770 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
1776 emit_phi(struct ir3_compile
*ctx
, nir_phi_instr
*nphi
)
1778 struct ir3_instruction
*phi
, **dst
;
1780 /* NOTE: phi's should be lowered to scalar at this point */
1781 compile_assert(ctx
, nphi
->dest
.ssa
.num_components
== 1);
1783 dst
= get_dst(ctx
, &nphi
->dest
, 1);
1785 phi
= ir3_instr_create2(ctx
->block
, -1, OPC_META_PHI
,
1786 1 + exec_list_length(&nphi
->srcs
));
1787 ir3_reg_create(phi
, 0, 0); /* dst */
1788 phi
->phi
.nphi
= nphi
;
1793 /* phi instructions are left partially constructed. We don't resolve
1794 * their srcs until the end of the block, since (eg. loops) one of
1795 * the phi's srcs might be defined after the phi due to back edges in
1799 resolve_phis(struct ir3_compile
*ctx
, struct ir3_block
*block
)
1801 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
1802 nir_phi_instr
*nphi
;
1804 /* phi's only come at start of block: */
1805 if (!(is_meta(instr
) && (instr
->opc
== OPC_META_PHI
)))
1808 if (!instr
->phi
.nphi
)
1811 nphi
= instr
->phi
.nphi
;
1812 instr
->phi
.nphi
= NULL
;
1814 foreach_list_typed(nir_phi_src
, nsrc
, node
, &nphi
->srcs
) {
1815 struct ir3_instruction
*src
= get_src(ctx
, &nsrc
->src
)[0];
1816 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
1820 resolve_array_phis(ctx
, block
);
1824 emit_jump(struct ir3_compile
*ctx
, nir_jump_instr
*jump
)
1826 switch (jump
->type
) {
1827 case nir_jump_break
:
1828 case nir_jump_continue
:
1829 /* I *think* we can simply just ignore this, and use the
1830 * successor block link to figure out where we need to
1831 * jump to for break/continue
1835 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
1841 emit_instr(struct ir3_compile
*ctx
, nir_instr
*instr
)
1843 switch (instr
->type
) {
1844 case nir_instr_type_alu
:
1845 emit_alu(ctx
, nir_instr_as_alu(instr
));
1847 case nir_instr_type_intrinsic
:
1848 emit_intrinisic(ctx
, nir_instr_as_intrinsic(instr
));
1850 case nir_instr_type_load_const
:
1851 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1853 case nir_instr_type_ssa_undef
:
1854 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
1856 case nir_instr_type_tex
: {
1857 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
1858 /* couple tex instructions get special-cased:
1862 emit_tex_txs(ctx
, tex
);
1864 case nir_texop_query_levels
:
1865 emit_tex_query_levels(ctx
, tex
);
1873 case nir_instr_type_phi
:
1874 emit_phi(ctx
, nir_instr_as_phi(instr
));
1876 case nir_instr_type_jump
:
1877 emit_jump(ctx
, nir_instr_as_jump(instr
));
1879 case nir_instr_type_call
:
1880 case nir_instr_type_parallel_copy
:
1881 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
1886 static struct ir3_block
*
1887 get_block(struct ir3_compile
*ctx
, nir_block
*nblock
)
1889 struct ir3_block
*block
;
1890 struct hash_entry
*entry
;
1891 entry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
1895 block
= ir3_block_create(ctx
->ir
);
1896 block
->nblock
= nblock
;
1897 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
1903 emit_block(struct ir3_compile
*ctx
, nir_block
*nblock
)
1905 struct ir3_block
*block
= get_block(ctx
, nblock
);
1907 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
1908 if (nblock
->successors
[i
]) {
1909 block
->successors
[i
] =
1910 get_block(ctx
, nblock
->successors
[i
]);
1915 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
1917 nir_foreach_instr(nblock
, instr
) {
1918 emit_instr(ctx
, instr
);
1924 static void emit_cf_list(struct ir3_compile
*ctx
, struct exec_list
*list
);
1927 emit_if(struct ir3_compile
*ctx
, nir_if
*nif
)
1929 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
1931 ctx
->block
->condition
=
1932 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
1934 emit_cf_list(ctx
, &nif
->then_list
);
1935 emit_cf_list(ctx
, &nif
->else_list
);
1939 emit_loop(struct ir3_compile
*ctx
, nir_loop
*nloop
)
1941 emit_cf_list(ctx
, &nloop
->body
);
1945 emit_cf_list(struct ir3_compile
*ctx
, struct exec_list
*list
)
1947 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
1948 switch (node
->type
) {
1949 case nir_cf_node_block
:
1950 emit_block(ctx
, nir_cf_node_as_block(node
));
1952 case nir_cf_node_if
:
1953 emit_if(ctx
, nir_cf_node_as_if(node
));
1955 case nir_cf_node_loop
:
1956 emit_loop(ctx
, nir_cf_node_as_loop(node
));
1958 case nir_cf_node_function
:
1959 compile_error(ctx
, "TODO\n");
1966 emit_function(struct ir3_compile
*ctx
, nir_function_impl
*impl
)
1968 emit_cf_list(ctx
, &impl
->body
);
1969 emit_block(ctx
, impl
->end_block
);
1971 /* at this point, we should have a single empty block,
1972 * into which we emit the 'end' instruction.
1974 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
1975 ir3_END(ctx
->block
);
1979 setup_input(struct ir3_compile
*ctx
, nir_variable
*in
)
1981 struct ir3_shader_variant
*so
= ctx
->so
;
1982 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
1983 unsigned ncomp
= glsl_get_components(in
->type
);
1984 /* XXX: map loc slots to semantics */
1985 unsigned semantic_name
= in
->data
.location
;
1986 unsigned semantic_index
= in
->data
.index
;
1987 unsigned n
= in
->data
.driver_location
;
1989 DBG("; in: %u:%u, len=%ux%u, loc=%u\n",
1990 semantic_name
, semantic_index
, array_len
,
1993 so
->inputs
[n
].semantic
=
1994 ir3_semantic_name(semantic_name
, semantic_index
);
1995 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
1996 so
->inputs
[n
].inloc
= ctx
->next_inloc
;
1997 so
->inputs
[n
].interpolate
= 0;
1998 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2000 /* the fdN_program_emit() code expects tgsi consts here, so map
2001 * things back to tgsi for now:
2003 switch (in
->data
.interpolation
) {
2004 case INTERP_QUALIFIER_FLAT
:
2005 so
->inputs
[n
].interpolate
= TGSI_INTERPOLATE_CONSTANT
;
2007 case INTERP_QUALIFIER_NOPERSPECTIVE
:
2008 so
->inputs
[n
].interpolate
= TGSI_INTERPOLATE_LINEAR
;
2010 case INTERP_QUALIFIER_SMOOTH
:
2011 so
->inputs
[n
].interpolate
= TGSI_INTERPOLATE_PERSPECTIVE
;
2015 for (int i
= 0; i
< ncomp
; i
++) {
2016 struct ir3_instruction
*instr
= NULL
;
2017 unsigned idx
= (n
* 4) + i
;
2019 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2020 if (semantic_name
== TGSI_SEMANTIC_POSITION
) {
2021 so
->inputs
[n
].bary
= false;
2022 so
->frag_coord
= true;
2023 instr
= create_frag_coord(ctx
, i
);
2024 } else if (semantic_name
== TGSI_SEMANTIC_FACE
) {
2025 so
->inputs
[n
].bary
= false;
2026 so
->frag_face
= true;
2027 instr
= create_frag_face(ctx
, i
);
2029 bool use_ldlv
= false;
2031 /* with NIR, we need to infer TGSI_INTERPOLATE_COLOR
2032 * from the semantic name:
2034 if ((in
->data
.interpolation
== INTERP_QUALIFIER_NONE
) &&
2035 ((semantic_name
== TGSI_SEMANTIC_COLOR
) ||
2036 (semantic_name
== TGSI_SEMANTIC_BCOLOR
)))
2037 so
->inputs
[n
].interpolate
= TGSI_INTERPOLATE_COLOR
;
2039 if (ctx
->flat_bypass
) {
2040 /* with NIR, we need to infer TGSI_INTERPOLATE_COLOR
2041 * from the semantic name:
2043 switch (so
->inputs
[n
].interpolate
) {
2044 case TGSI_INTERPOLATE_COLOR
:
2045 if (!ctx
->so
->key
.rasterflat
)
2048 case TGSI_INTERPOLATE_CONSTANT
:
2054 so
->inputs
[n
].bary
= true;
2056 instr
= create_frag_input(ctx
,
2057 so
->inputs
[n
].inloc
+ i
- 8, use_ldlv
);
2060 instr
= create_input(ctx
->block
, NULL
, idx
);
2063 ctx
->ir
->inputs
[idx
] = instr
;
2066 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
2067 ctx
->next_inloc
+= ncomp
;
2068 so
->total_in
+= ncomp
;
2073 setup_output(struct ir3_compile
*ctx
, nir_variable
*out
)
2075 struct ir3_shader_variant
*so
= ctx
->so
;
2076 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
2077 unsigned ncomp
= glsl_get_components(out
->type
);
2078 /* XXX: map loc slots to semantics */
2079 unsigned semantic_name
= out
->data
.location
;
2080 unsigned semantic_index
= out
->data
.index
;
2081 unsigned n
= out
->data
.driver_location
;
2084 DBG("; out: %u:%u, len=%ux%u, loc=%u\n",
2085 semantic_name
, semantic_index
, array_len
,
2088 if (ctx
->so
->type
== SHADER_VERTEX
) {
2089 switch (semantic_name
) {
2090 case TGSI_SEMANTIC_POSITION
:
2091 so
->writes_pos
= true;
2093 case TGSI_SEMANTIC_PSIZE
:
2094 so
->writes_psize
= true;
2096 case TGSI_SEMANTIC_COLOR
:
2097 case TGSI_SEMANTIC_BCOLOR
:
2098 case TGSI_SEMANTIC_GENERIC
:
2099 case TGSI_SEMANTIC_FOG
:
2100 case TGSI_SEMANTIC_TEXCOORD
:
2103 compile_error(ctx
, "unknown VS semantic name: %s\n",
2104 tgsi_semantic_names
[semantic_name
]);
2107 switch (semantic_name
) {
2108 case TGSI_SEMANTIC_POSITION
:
2109 comp
= 2; /* tgsi will write to .z component */
2110 so
->writes_pos
= true;
2112 case TGSI_SEMANTIC_COLOR
:
2113 if (semantic_index
== -1) {
2119 compile_error(ctx
, "unknown FS semantic name: %s\n",
2120 tgsi_semantic_names
[semantic_name
]);
2124 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
2126 so
->outputs
[n
].semantic
=
2127 ir3_semantic_name(semantic_name
, semantic_index
);
2128 so
->outputs
[n
].regid
= regid(n
, comp
);
2129 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
2131 for (int i
= 0; i
< ncomp
; i
++) {
2132 unsigned idx
= (n
* 4) + i
;
2134 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
2139 emit_instructions(struct ir3_compile
*ctx
)
2141 unsigned ninputs
, noutputs
;
2142 nir_function_impl
*fxn
= NULL
;
2144 /* Find the main function: */
2145 nir_foreach_overload(ctx
->s
, overload
) {
2146 compile_assert(ctx
, strcmp(overload
->function
->name
, "main") == 0);
2147 compile_assert(ctx
, overload
->impl
);
2148 fxn
= overload
->impl
;
2152 ninputs
= exec_list_length(&ctx
->s
->inputs
) * 4;
2153 noutputs
= exec_list_length(&ctx
->s
->outputs
) * 4;
2155 /* we need to allocate big enough outputs array so that
2156 * we can stuff the kill's at the end. Likewise for vtx
2157 * shaders, we need to leave room for sysvals:
2159 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2160 noutputs
+= ARRAY_SIZE(ctx
->kill
);
2161 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2165 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
2167 /* Create inputs in first block: */
2168 ctx
->block
= get_block(ctx
, fxn
->start_block
);
2169 ctx
->in_block
= ctx
->block
;
2170 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
2172 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2173 ctx
->ir
->noutputs
-= ARRAY_SIZE(ctx
->kill
);
2174 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2175 ctx
->ir
->ninputs
-= 8;
2178 /* for fragment shader, we have a single input register (usually
2179 * r0.xy) which is used as the base for bary.f varying fetch instrs:
2181 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2182 // TODO maybe a helper for fi since we need it a few places..
2183 struct ir3_instruction
*instr
;
2184 instr
= ir3_instr_create(ctx
->block
, -1, OPC_META_FI
);
2185 ir3_reg_create(instr
, 0, 0);
2186 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.x */
2187 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.y */
2188 ctx
->frag_pos
= instr
;
2192 foreach_list_typed(nir_variable
, var
, node
, &ctx
->s
->inputs
) {
2193 setup_input(ctx
, var
);
2196 /* Setup outputs: */
2197 foreach_list_typed(nir_variable
, var
, node
, &ctx
->s
->outputs
) {
2198 setup_output(ctx
, var
);
2201 /* Setup variables (which should only be arrays): */
2202 foreach_list_typed(nir_variable
, var
, node
, &ctx
->s
->globals
) {
2203 declare_var(ctx
, var
);
2206 /* And emit the body: */
2208 emit_function(ctx
, fxn
);
2210 list_for_each_entry (struct ir3_block
, block
, &ctx
->ir
->block_list
, node
) {
2211 resolve_phis(ctx
, block
);
2215 /* from NIR perspective, we actually have inputs. But most of the "inputs"
2216 * for a fragment shader are just bary.f instructions. The *actual* inputs
2217 * from the hw perspective are the frag_pos and optionally frag_coord and
2221 fixup_frag_inputs(struct ir3_compile
*ctx
)
2223 struct ir3_shader_variant
*so
= ctx
->so
;
2224 struct ir3
*ir
= ctx
->ir
;
2225 struct ir3_instruction
**inputs
;
2226 struct ir3_instruction
*instr
;
2231 n
= 4; /* always have frag_pos */
2232 n
+= COND(so
->frag_face
, 4);
2233 n
+= COND(so
->frag_coord
, 4);
2235 inputs
= ir3_alloc(ctx
->ir
, n
* (sizeof(struct ir3_instruction
*)));
2237 if (so
->frag_face
) {
2238 /* this ultimately gets assigned to hr0.x so doesn't conflict
2239 * with frag_coord/frag_pos..
2241 inputs
[ir
->ninputs
++] = ctx
->frag_face
;
2242 ctx
->frag_face
->regs
[0]->num
= 0;
2244 /* remaining channels not used, but let's avoid confusing
2245 * other parts that expect inputs to come in groups of vec4
2247 inputs
[ir
->ninputs
++] = NULL
;
2248 inputs
[ir
->ninputs
++] = NULL
;
2249 inputs
[ir
->ninputs
++] = NULL
;
2252 /* since we don't know where to set the regid for frag_coord,
2253 * we have to use r0.x for it. But we don't want to *always*
2254 * use r1.x for frag_pos as that could increase the register
2255 * footprint on simple shaders:
2257 if (so
->frag_coord
) {
2258 ctx
->frag_coord
[0]->regs
[0]->num
= regid
++;
2259 ctx
->frag_coord
[1]->regs
[0]->num
= regid
++;
2260 ctx
->frag_coord
[2]->regs
[0]->num
= regid
++;
2261 ctx
->frag_coord
[3]->regs
[0]->num
= regid
++;
2263 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[0];
2264 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[1];
2265 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[2];
2266 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[3];
2269 /* we always have frag_pos: */
2270 so
->pos_regid
= regid
;
2273 instr
= create_input(ctx
->in_block
, NULL
, ir
->ninputs
);
2274 instr
->regs
[0]->num
= regid
++;
2275 inputs
[ir
->ninputs
++] = instr
;
2276 ctx
->frag_pos
->regs
[1]->instr
= instr
;
2279 instr
= create_input(ctx
->in_block
, NULL
, ir
->ninputs
);
2280 instr
->regs
[0]->num
= regid
++;
2281 inputs
[ir
->ninputs
++] = instr
;
2282 ctx
->frag_pos
->regs
[2]->instr
= instr
;
2284 ir
->inputs
= inputs
;
2288 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
2289 struct ir3_shader_variant
*so
,
2290 const struct tgsi_token
*tokens
,
2291 struct ir3_shader_key key
)
2293 struct ir3_compile
*ctx
;
2295 struct ir3_instruction
**inputs
;
2296 unsigned i
, j
, actual_in
;
2297 int ret
= 0, max_bary
;
2301 ctx
= compile_init(compiler
, so
, tokens
);
2303 DBG("INIT failed!");
2308 emit_instructions(ctx
);
2311 DBG("EMIT failed!");
2316 ir
= so
->ir
= ctx
->ir
;
2318 /* keep track of the inputs from TGSI perspective.. */
2319 inputs
= ir
->inputs
;
2321 /* but fixup actual inputs for frag shader: */
2322 if (so
->type
== SHADER_FRAGMENT
)
2323 fixup_frag_inputs(ctx
);
2325 /* at this point, for binning pass, throw away unneeded outputs: */
2326 if (key
.binning_pass
) {
2327 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
2328 unsigned name
= sem2name(so
->outputs
[i
].semantic
);
2329 unsigned idx
= sem2idx(so
->outputs
[i
].semantic
);
2331 /* throw away everything but first position/psize */
2332 if ((idx
== 0) && ((name
== TGSI_SEMANTIC_POSITION
) ||
2333 (name
== TGSI_SEMANTIC_PSIZE
))) {
2335 so
->outputs
[j
] = so
->outputs
[i
];
2336 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
2337 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
2338 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
2339 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
2344 so
->outputs_count
= j
;
2345 ir
->noutputs
= j
* 4;
2348 /* if we want half-precision outputs, mark the output registers
2351 if (key
.half_precision
) {
2352 for (i
= 0; i
< ir
->noutputs
; i
++) {
2353 struct ir3_instruction
*out
= ir
->outputs
[i
];
2356 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2357 /* output could be a fanout (ie. texture fetch output)
2358 * in which case we need to propagate the half-reg flag
2359 * up to the definer so that RA sees it:
2361 if (is_meta(out
) && (out
->opc
== OPC_META_FO
)) {
2362 out
= out
->regs
[1]->instr
;
2363 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2366 if (out
->category
== 1) {
2367 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
2372 /* at this point, we want the kill's in the outputs array too,
2373 * so that they get scheduled (since they have no dst).. we've
2374 * already ensured that the array is big enough in push_block():
2376 if (so
->type
== SHADER_FRAGMENT
) {
2377 for (i
= 0; i
< ctx
->kill_count
; i
++)
2378 ir
->outputs
[ir
->noutputs
++] = ctx
->kill
[i
];
2381 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2382 printf("BEFORE CP:\n");
2388 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2389 printf("BEFORE GROUPING:\n");
2393 /* Group left/right neighbors, inserting mov's where needed to
2400 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2401 printf("AFTER DEPTH:\n");
2405 ret
= ir3_sched(ir
);
2407 DBG("SCHED failed!");
2411 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2412 printf("AFTER SCHED:\n");
2416 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
2422 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2423 printf("AFTER RA:\n");
2427 ir3_legalize(ir
, &so
->has_samp
, &max_bary
);
2429 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2430 printf("AFTER LEGALIZE:\n");
2434 /* fixup input/outputs: */
2435 for (i
= 0; i
< so
->outputs_count
; i
++) {
2436 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
2437 /* preserve hack for depth output.. tgsi writes depth to .z,
2438 * but what we give the hw is the scalar register:
2440 if ((so
->type
== SHADER_FRAGMENT
) &&
2441 (sem2name(so
->outputs
[i
].semantic
) == TGSI_SEMANTIC_POSITION
))
2442 so
->outputs
[i
].regid
+= 2;
2445 /* Note that some or all channels of an input may be unused: */
2447 for (i
= 0; i
< so
->inputs_count
; i
++) {
2448 unsigned j
, regid
= ~0, compmask
= 0;
2449 so
->inputs
[i
].ncomp
= 0;
2450 for (j
= 0; j
< 4; j
++) {
2451 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
2453 compmask
|= (1 << j
);
2454 regid
= in
->regs
[0]->num
- j
;
2456 so
->inputs
[i
].ncomp
++;
2459 so
->inputs
[i
].regid
= regid
;
2460 so
->inputs
[i
].compmask
= compmask
;
2463 /* fragment shader always gets full vec4's even if it doesn't
2464 * fetch all components, but vertex shader we need to update
2465 * with the actual number of components fetch, otherwise thing
2466 * will hang due to mismaptch between VFD_DECODE's and
2469 if (so
->type
== SHADER_VERTEX
)
2470 so
->total_in
= actual_in
;
2472 so
->total_in
= align(max_bary
+ 1, 4);
2477 ir3_destroy(so
->ir
);