1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
36 #include "freedreno_util.h"
38 #include "ir3_compiler.h"
39 #include "ir3_shader.h"
42 #include "instr-a3xx.h"
47 struct ir3_compiler
*compiler
;
52 struct ir3_shader_variant
*so
;
54 struct ir3_block
*block
; /* the current block */
55 struct ir3_block
*in_block
; /* block created for shader inputs */
57 nir_function_impl
*impl
;
59 /* For fragment shaders, from the hw perspective the only
60 * actual input is r0.xy position register passed to bary.f.
61 * But TGSI doesn't know that, it still declares things as
62 * IN[] registers. So we do all the input tracking normally
63 * and fix things up after compile_instructions()
65 * NOTE that frag_pos is the hardware position (possibly it
66 * is actually an index or tag or some such.. it is *not*
67 * values that can be directly used for gl_FragCoord..)
69 struct ir3_instruction
*frag_pos
, *frag_face
, *frag_coord
[4];
71 /* For vertex shaders, keep track of the system values sources */
72 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
74 /* mapping from nir_register to defining instruction: */
75 struct hash_table
*def_ht
;
79 /* a common pattern for indirect addressing is to request the
80 * same address register multiple times. To avoid generating
81 * duplicate instruction sequences (which our backend does not
82 * try to clean up, since that should be done as the NIR stage)
83 * we cache the address value generated for a given src value:
85 struct hash_table
*addr_ht
;
87 /* maps nir_block to ir3_block, mostly for the purposes of
88 * figuring out the blocks successors
90 struct hash_table
*block_ht
;
92 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
93 * so we need to use ldlv.u32 to load the varying directly:
97 /* on a3xx, we need to add one to # of array levels:
101 /* on a3xx, we need to scale up integer coords for isaml based
104 bool unminify_coords
;
106 /* on a4xx, for array textures we need to add 0.5 to the array
109 bool array_index_add_half
;
111 /* for looking up which system value is which */
112 unsigned sysval_semantics
[8];
114 /* set if we encounter something we can't handle yet, so we
115 * can bail cleanly and fallback to TGSI compiler f/e
121 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
122 static struct ir3_block
* get_block(struct ir3_compile
*ctx
, nir_block
*nblock
);
125 static struct ir3_compile
*
126 compile_init(struct ir3_compiler
*compiler
,
127 struct ir3_shader_variant
*so
)
129 struct ir3_compile
*ctx
= rzalloc(NULL
, struct ir3_compile
);
131 if (compiler
->gpu_id
>= 400) {
132 /* need special handling for "flat" */
133 ctx
->flat_bypass
= true;
134 ctx
->levels_add_one
= false;
135 ctx
->unminify_coords
= false;
136 ctx
->array_index_add_half
= true;
138 /* no special handling for "flat" */
139 ctx
->flat_bypass
= false;
140 ctx
->levels_add_one
= true;
141 ctx
->unminify_coords
= true;
142 ctx
->array_index_add_half
= false;
145 ctx
->compiler
= compiler
;
148 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
149 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
150 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
151 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
153 /* TODO: maybe generate some sort of bitmask of what key
154 * lowers vs what shader has (ie. no need to lower
155 * texture clamp lowering if no texture sample instrs)..
156 * although should be done further up the stack to avoid
157 * creating duplicate variants..
160 if (ir3_key_lowers_nir(&so
->key
)) {
161 nir_shader
*s
= nir_shader_clone(ctx
, so
->shader
->nir
);
162 ctx
->s
= ir3_optimize_nir(so
->shader
, s
, &so
->key
);
164 /* fast-path for shader key that lowers nothing in NIR: */
165 ctx
->s
= so
->shader
->nir
;
168 if (fd_mesa_debug
& FD_DBG_DISASM
) {
169 DBG("dump nir%dv%d: type=%d, k={bp=%u,cts=%u,hp=%u}",
170 so
->shader
->id
, so
->id
, so
->type
,
171 so
->key
.binning_pass
, so
->key
.color_two_side
,
172 so
->key
.half_precision
);
173 nir_print_shader(ctx
->s
, stdout
);
176 so
->first_driver_param
= so
->first_immediate
= ctx
->s
->num_uniforms
;
178 /* Layout of constant registers:
180 * num_uniform * vec4 - user consts
181 * 4 * vec4 - UBO addresses
182 * if (vertex shader) {
183 * N * vec4 - driver params (IR3_DP_*)
184 * 1 * vec4 - stream-out addresses
187 * TODO this could be made more dynamic, to at least skip sections
188 * that we don't need..
191 /* reserve 4 (vec4) slots for ubo base addresses: */
192 so
->first_immediate
+= 4;
194 if (so
->type
== SHADER_VERTEX
) {
195 /* driver params (see ir3_driver_param): */
196 so
->first_immediate
+= IR3_DP_COUNT
/4; /* convert to vec4 */
197 /* one (vec4) slot for stream-output base addresses: */
198 so
->first_immediate
++;
205 compile_error(struct ir3_compile
*ctx
, const char *format
, ...)
208 va_start(ap
, format
);
209 _debug_vprintf(format
, ap
);
211 nir_print_shader(ctx
->s
, stdout
);
216 #define compile_assert(ctx, cond) do { \
217 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
221 compile_free(struct ir3_compile
*ctx
)
227 declare_var(struct ir3_compile
*ctx
, nir_variable
*var
)
229 unsigned length
= glsl_get_length(var
->type
) * 4; /* always vec4, at least with ttn */
230 struct ir3_array
*arr
= ralloc(ctx
, struct ir3_array
);
231 arr
->id
= ++ctx
->num_arrays
;
232 arr
->length
= length
;
234 list_addtail(&arr
->node
, &ctx
->ir
->array_list
);
237 static struct ir3_array
*
238 get_var(struct ir3_compile
*ctx
, nir_variable
*var
)
240 list_for_each_entry (struct ir3_array
, arr
, &ctx
->ir
->array_list
, node
) {
244 compile_error(ctx
, "bogus var: %s\n", var
->name
);
248 /* allocate a n element value array (to be populated by caller) and
251 static struct ir3_instruction
**
252 __get_dst(struct ir3_compile
*ctx
, void *key
, unsigned n
)
254 struct ir3_instruction
**value
=
255 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
256 _mesa_hash_table_insert(ctx
->def_ht
, key
, value
);
260 static struct ir3_instruction
**
261 get_dst(struct ir3_compile
*ctx
, nir_dest
*dst
, unsigned n
)
263 compile_assert(ctx
, dst
->is_ssa
);
265 return __get_dst(ctx
, &dst
->ssa
, n
);
267 return __get_dst(ctx
, dst
->reg
.reg
, n
);
271 static struct ir3_instruction
**
272 get_dst_ssa(struct ir3_compile
*ctx
, nir_ssa_def
*dst
, unsigned n
)
274 return __get_dst(ctx
, dst
, n
);
277 static struct ir3_instruction
**
278 get_src(struct ir3_compile
*ctx
, nir_src
*src
)
280 struct hash_entry
*entry
;
281 compile_assert(ctx
, src
->is_ssa
);
283 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
285 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->reg
.reg
);
287 compile_assert(ctx
, entry
);
291 static struct ir3_instruction
*
292 create_immed(struct ir3_block
*block
, uint32_t val
)
294 struct ir3_instruction
*mov
;
296 mov
= ir3_instr_create(block
, OPC_MOV
);
297 mov
->cat1
.src_type
= TYPE_U32
;
298 mov
->cat1
.dst_type
= TYPE_U32
;
299 ir3_reg_create(mov
, 0, 0);
300 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
305 static struct ir3_instruction
*
306 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
)
308 struct ir3_instruction
*instr
, *immed
;
310 /* TODO in at least some cases, the backend could probably be
311 * made clever enough to propagate IR3_REG_HALF..
313 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
314 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
316 immed
= create_immed(block
, 2);
317 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
319 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
320 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
321 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
323 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
324 instr
->regs
[0]->num
= regid(REG_A0
, 0);
325 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
326 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
331 /* caches addr values to avoid generating multiple cov/shl/mova
332 * sequences for each use of a given NIR level src as address
334 static struct ir3_instruction
*
335 get_addr(struct ir3_compile
*ctx
, struct ir3_instruction
*src
)
337 struct ir3_instruction
*addr
;
340 ctx
->addr_ht
= _mesa_hash_table_create(ctx
,
341 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
343 struct hash_entry
*entry
;
344 entry
= _mesa_hash_table_search(ctx
->addr_ht
, src
);
349 addr
= create_addr(ctx
->block
, src
);
350 _mesa_hash_table_insert(ctx
->addr_ht
, src
, addr
);
355 static struct ir3_instruction
*
356 get_predicate(struct ir3_compile
*ctx
, struct ir3_instruction
*src
)
358 struct ir3_block
*b
= ctx
->block
;
359 struct ir3_instruction
*cond
;
361 /* NOTE: only cmps.*.* can write p0.x: */
362 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
363 cond
->cat2
.condition
= IR3_COND_NE
;
365 /* condition always goes in predicate register: */
366 cond
->regs
[0]->num
= regid(REG_P0
, 0);
371 static struct ir3_instruction
*
372 create_uniform(struct ir3_compile
*ctx
, unsigned n
)
374 struct ir3_instruction
*mov
;
376 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
377 /* TODO get types right? */
378 mov
->cat1
.src_type
= TYPE_F32
;
379 mov
->cat1
.dst_type
= TYPE_F32
;
380 ir3_reg_create(mov
, 0, 0);
381 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
386 static struct ir3_instruction
*
387 create_uniform_indirect(struct ir3_compile
*ctx
, int n
,
388 struct ir3_instruction
*address
)
390 struct ir3_instruction
*mov
;
392 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
393 mov
->cat1
.src_type
= TYPE_U32
;
394 mov
->cat1
.dst_type
= TYPE_U32
;
395 ir3_reg_create(mov
, 0, 0);
396 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
398 ir3_instr_set_address(mov
, address
);
403 static struct ir3_instruction
*
404 create_collect(struct ir3_block
*block
, struct ir3_instruction
**arr
,
407 struct ir3_instruction
*collect
;
412 collect
= ir3_instr_create2(block
, OPC_META_FI
, 1 + arrsz
);
413 ir3_reg_create(collect
, 0, 0); /* dst */
414 for (unsigned i
= 0; i
< arrsz
; i
++)
415 ir3_reg_create(collect
, 0, IR3_REG_SSA
)->instr
= arr
[i
];
420 static struct ir3_instruction
*
421 create_indirect_load(struct ir3_compile
*ctx
, unsigned arrsz
, int n
,
422 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
424 struct ir3_block
*block
= ctx
->block
;
425 struct ir3_instruction
*mov
;
426 struct ir3_register
*src
;
428 mov
= ir3_instr_create(block
, OPC_MOV
);
429 mov
->cat1
.src_type
= TYPE_U32
;
430 mov
->cat1
.dst_type
= TYPE_U32
;
431 ir3_reg_create(mov
, 0, 0);
432 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
433 src
->instr
= collect
;
435 src
->array
.offset
= n
;
437 ir3_instr_set_address(mov
, address
);
442 /* relative (indirect) if address!=NULL */
443 static struct ir3_instruction
*
444 create_var_load(struct ir3_compile
*ctx
, struct ir3_array
*arr
, int n
,
445 struct ir3_instruction
*address
)
447 struct ir3_block
*block
= ctx
->block
;
448 struct ir3_instruction
*mov
;
449 struct ir3_register
*src
;
451 mov
= ir3_instr_create(block
, OPC_MOV
);
452 mov
->cat1
.src_type
= TYPE_U32
;
453 mov
->cat1
.dst_type
= TYPE_U32
;
454 ir3_reg_create(mov
, 0, 0);
455 src
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
456 COND(address
, IR3_REG_RELATIV
));
457 src
->instr
= arr
->last_write
;
458 src
->size
= arr
->length
;
459 src
->array
.id
= arr
->id
;
460 src
->array
.offset
= n
;
463 ir3_instr_set_address(mov
, address
);
465 arr
->last_access
= mov
;
470 /* relative (indirect) if address!=NULL */
471 static struct ir3_instruction
*
472 create_var_store(struct ir3_compile
*ctx
, struct ir3_array
*arr
, int n
,
473 struct ir3_instruction
*src
, struct ir3_instruction
*address
)
475 struct ir3_block
*block
= ctx
->block
;
476 struct ir3_instruction
*mov
;
477 struct ir3_register
*dst
;
479 mov
= ir3_instr_create(block
, OPC_MOV
);
480 mov
->cat1
.src_type
= TYPE_U32
;
481 mov
->cat1
.dst_type
= TYPE_U32
;
482 dst
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
483 COND(address
, IR3_REG_RELATIV
));
484 dst
->instr
= arr
->last_access
;
485 dst
->size
= arr
->length
;
486 dst
->array
.id
= arr
->id
;
487 dst
->array
.offset
= n
;
488 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
490 ir3_instr_set_address(mov
, address
);
492 arr
->last_write
= arr
->last_access
= mov
;
497 static struct ir3_instruction
*
498 create_input(struct ir3_block
*block
, unsigned n
)
500 struct ir3_instruction
*in
;
502 in
= ir3_instr_create(block
, OPC_META_INPUT
);
503 in
->inout
.block
= block
;
504 ir3_reg_create(in
, n
, 0);
509 static struct ir3_instruction
*
510 create_frag_input(struct ir3_compile
*ctx
, bool use_ldlv
)
512 struct ir3_block
*block
= ctx
->block
;
513 struct ir3_instruction
*instr
;
514 /* actual inloc is assigned and fixed up later: */
515 struct ir3_instruction
*inloc
= create_immed(block
, 0);
518 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
519 instr
->cat6
.type
= TYPE_U32
;
520 instr
->cat6
.iim_val
= 1;
522 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_pos
, 0);
523 instr
->regs
[2]->wrmask
= 0x3;
529 static struct ir3_instruction
*
530 create_frag_coord(struct ir3_compile
*ctx
, unsigned comp
)
532 struct ir3_block
*block
= ctx
->block
;
533 struct ir3_instruction
*instr
;
535 compile_assert(ctx
, !ctx
->frag_coord
[comp
]);
537 ctx
->frag_coord
[comp
] = create_input(ctx
->block
, 0);
542 /* for frag_coord, we get unsigned values.. we need
543 * to subtract (integer) 8 and divide by 16 (right-
544 * shift by 4) then convert to float:
548 * mov.u32f32 dst, tmp
551 instr
= ir3_SUB_S(block
, ctx
->frag_coord
[comp
], 0,
552 create_immed(block
, 8), 0);
553 instr
= ir3_SHR_B(block
, instr
, 0,
554 create_immed(block
, 4), 0);
555 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
561 /* seems that we can use these as-is: */
562 return ctx
->frag_coord
[comp
];
566 /* NOTE: this creates the "TGSI" style fragface (ie. input slot
567 * VARYING_SLOT_FACE). For NIR style nir_intrinsic_load_front_face
568 * we can just use the value from hw directly (since it is boolean)
570 static struct ir3_instruction
*
571 create_frag_face(struct ir3_compile
*ctx
, unsigned comp
)
573 struct ir3_block
*block
= ctx
->block
;
574 struct ir3_instruction
*instr
;
578 compile_assert(ctx
, !ctx
->frag_face
);
580 ctx
->frag_face
= create_input(block
, 0);
581 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
583 /* for faceness, we always get -1 or 0 (int).. but TGSI expects
584 * positive vs negative float.. and piglit further seems to
585 * expect -1.0 or 1.0:
587 * mul.s tmp, hr0.x, 2
589 * mov.s32f32, dst, tmp
592 instr
= ir3_MUL_S(block
, ctx
->frag_face
, 0,
593 create_immed(block
, 2), 0);
594 instr
= ir3_ADD_S(block
, instr
, 0,
595 create_immed(block
, 1), 0);
596 instr
= ir3_COV(block
, instr
, TYPE_S32
, TYPE_F32
);
601 return create_immed(block
, fui(0.0));
604 return create_immed(block
, fui(1.0));
608 static struct ir3_instruction
*
609 create_driver_param(struct ir3_compile
*ctx
, enum ir3_driver_param dp
)
611 /* first four vec4 sysval's reserved for UBOs: */
612 /* NOTE: dp is in scalar, but there can be >4 dp components: */
613 unsigned n
= ctx
->so
->first_driver_param
+ IR3_DRIVER_PARAM_OFF
;
614 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
615 return create_uniform(ctx
, r
);
618 /* helper for instructions that produce multiple consecutive scalar
619 * outputs which need to have a split/fanout meta instruction inserted
622 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
623 struct ir3_instruction
*src
, unsigned n
)
625 struct ir3_instruction
*prev
= NULL
;
626 for (int i
= 0, j
= 0; i
< n
; i
++) {
627 struct ir3_instruction
*split
= ir3_instr_create(block
, OPC_META_FO
);
628 ir3_reg_create(split
, 0, IR3_REG_SSA
);
629 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
633 split
->cp
.left
= prev
;
634 split
->cp
.left_cnt
++;
635 prev
->cp
.right
= split
;
636 prev
->cp
.right_cnt
++;
640 if (src
->regs
[0]->wrmask
& (1 << i
))
646 * Adreno uses uint rather than having dedicated bool type,
647 * which (potentially) requires some conversion, in particular
648 * when using output of an bool instr to int input, or visa
652 * -------+---------+-------+-
656 * To convert from an adreno bool (uint) to nir, use:
658 * absneg.s dst, (neg)src
660 * To convert back in the other direction:
662 * absneg.s dst, (abs)arc
664 * The CP step can clean up the absneg.s that cancel each other
665 * out, and with a slight bit of extra cleverness (to recognize
666 * the instructions which produce either a 0 or 1) can eliminate
667 * the absneg.s's completely when an instruction that wants
668 * 0/1 consumes the result. For example, when a nir 'bcsel'
669 * consumes the result of 'feq'. So we should be able to get by
670 * without a boolean resolve step, and without incuring any
671 * extra penalty in instruction count.
674 /* NIR bool -> native (adreno): */
675 static struct ir3_instruction
*
676 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
678 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
681 /* native (adreno) -> NIR bool: */
682 static struct ir3_instruction
*
683 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
685 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
689 * alu/sfu instructions:
693 emit_alu(struct ir3_compile
*ctx
, nir_alu_instr
*alu
)
695 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
696 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
697 struct ir3_block
*b
= ctx
->block
;
699 dst
= get_dst(ctx
, &alu
->dest
.dest
, MAX2(info
->output_size
, 1));
701 /* Vectors are special in that they have non-scalarized writemasks,
702 * and just take the first swizzle channel for each argument in
703 * order into each writemask channel.
705 if ((alu
->op
== nir_op_vec2
) ||
706 (alu
->op
== nir_op_vec3
) ||
707 (alu
->op
== nir_op_vec4
)) {
709 for (int i
= 0; i
< info
->num_inputs
; i
++) {
710 nir_alu_src
*asrc
= &alu
->src
[i
];
712 compile_assert(ctx
, !asrc
->abs
);
713 compile_assert(ctx
, !asrc
->negate
);
715 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
717 src
[i
] = create_immed(ctx
->block
, 0);
718 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
724 /* General case: We can just grab the one used channel per src. */
725 for (int i
= 0; i
< info
->num_inputs
; i
++) {
726 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
727 nir_alu_src
*asrc
= &alu
->src
[i
];
729 compile_assert(ctx
, !asrc
->abs
);
730 compile_assert(ctx
, !asrc
->negate
);
732 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
734 compile_assert(ctx
, src
[i
]);
739 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_S32
);
742 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_U32
);
745 dst
[0] = ir3_COV(b
, src
[0], TYPE_S32
, TYPE_F32
);
748 dst
[0] = ir3_COV(b
, src
[0], TYPE_U32
, TYPE_F32
);
751 dst
[0] = ir3_MOV(b
, src
[0], TYPE_S32
);
754 dst
[0] = ir3_MOV(b
, src
[0], TYPE_F32
);
757 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
758 dst
[0]->cat2
.condition
= IR3_COND_NE
;
759 dst
[0] = ir3_n2b(b
, dst
[0]);
762 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
765 dst
[0] = ir3_b2n(b
, src
[0]);
768 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
769 dst
[0]->cat2
.condition
= IR3_COND_NE
;
770 dst
[0] = ir3_n2b(b
, dst
[0]);
774 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
777 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
780 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
783 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
786 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
789 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
792 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
795 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
798 dst
[0] = ir3_DSX(b
, src
[0], 0);
799 dst
[0]->cat5
.type
= TYPE_F32
;
802 dst
[0] = ir3_DSY(b
, src
[0], 0);
803 dst
[0]->cat5
.type
= TYPE_F32
;
807 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
808 dst
[0]->cat2
.condition
= IR3_COND_LT
;
809 dst
[0] = ir3_n2b(b
, dst
[0]);
812 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
813 dst
[0]->cat2
.condition
= IR3_COND_GE
;
814 dst
[0] = ir3_n2b(b
, dst
[0]);
817 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
818 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
819 dst
[0] = ir3_n2b(b
, dst
[0]);
822 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
823 dst
[0]->cat2
.condition
= IR3_COND_NE
;
824 dst
[0] = ir3_n2b(b
, dst
[0]);
827 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
830 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
833 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
835 case nir_op_fround_even
:
836 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
839 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
843 dst
[0] = ir3_SIN(b
, src
[0], 0);
846 dst
[0] = ir3_COS(b
, src
[0], 0);
849 dst
[0] = ir3_RSQ(b
, src
[0], 0);
852 dst
[0] = ir3_RCP(b
, src
[0], 0);
855 dst
[0] = ir3_LOG2(b
, src
[0], 0);
858 dst
[0] = ir3_EXP2(b
, src
[0], 0);
861 dst
[0] = ir3_SQRT(b
, src
[0], 0);
865 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
868 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
871 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
874 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
877 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
880 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
883 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
887 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
888 * mull.u tmp0, a, b ; mul low, i.e. al * bl
889 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
890 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
892 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
893 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
894 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
897 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
900 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
903 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
906 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
909 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
912 /* maybe this would be sane to lower in nir.. */
913 struct ir3_instruction
*neg
, *pos
;
915 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
916 neg
->cat2
.condition
= IR3_COND_LT
;
918 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
919 pos
->cat2
.condition
= IR3_COND_GT
;
921 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
926 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
929 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
932 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
935 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
936 dst
[0]->cat2
.condition
= IR3_COND_LT
;
937 dst
[0] = ir3_n2b(b
, dst
[0]);
940 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
941 dst
[0]->cat2
.condition
= IR3_COND_GE
;
942 dst
[0] = ir3_n2b(b
, dst
[0]);
945 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
946 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
947 dst
[0] = ir3_n2b(b
, dst
[0]);
950 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
951 dst
[0]->cat2
.condition
= IR3_COND_NE
;
952 dst
[0] = ir3_n2b(b
, dst
[0]);
955 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
956 dst
[0]->cat2
.condition
= IR3_COND_LT
;
957 dst
[0] = ir3_n2b(b
, dst
[0]);
960 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
961 dst
[0]->cat2
.condition
= IR3_COND_GE
;
962 dst
[0] = ir3_n2b(b
, dst
[0]);
966 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, ir3_b2n(b
, src
[0]), 0, src
[2], 0);
969 case nir_op_bit_count
:
970 dst
[0] = ir3_CBITS_B(b
, src
[0], 0);
972 case nir_op_ifind_msb
: {
973 struct ir3_instruction
*cmp
;
974 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
975 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
976 cmp
->cat2
.condition
= IR3_COND_GE
;
977 dst
[0] = ir3_SEL_B32(b
,
978 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
982 case nir_op_ufind_msb
:
983 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
984 dst
[0] = ir3_SEL_B32(b
,
985 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
986 src
[0], 0, dst
[0], 0);
988 case nir_op_find_lsb
:
989 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
990 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
992 case nir_op_bitfield_reverse
:
993 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
997 compile_error(ctx
, "Unhandled ALU op: %s\n",
998 nir_op_infos
[alu
->op
].name
);
1003 /* handles direct/indirect UBO reads: */
1005 emit_intrinsic_load_ubo(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1006 struct ir3_instruction
**dst
)
1008 struct ir3_block
*b
= ctx
->block
;
1009 struct ir3_instruction
*addr
, *src0
, *src1
;
1010 nir_const_value
*const_offset
;
1011 /* UBO addresses are the first driver params: */
1012 unsigned ubo
= regid(ctx
->so
->first_driver_param
+ IR3_UBOS_OFF
, 0);
1015 /* First src is ubo index, which could either be an immed or not: */
1016 src0
= get_src(ctx
, &intr
->src
[0])[0];
1017 if (is_same_type_mov(src0
) &&
1018 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1019 addr
= create_uniform(ctx
, ubo
+ src0
->regs
[1]->iim_val
);
1021 addr
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
));
1024 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1026 off
+= const_offset
->u32
[0];
1028 /* For load_ubo_indirect, second src is indirect offset: */
1029 src1
= get_src(ctx
, &intr
->src
[1])[0];
1031 /* and add offset to addr: */
1032 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1035 /* if offset is to large to encode in the ldg, split it out: */
1036 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1037 /* split out the minimal amount to improve the odds that
1038 * cp can fit the immediate in the add.s instruction:
1040 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1041 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1045 for (int i
= 0; i
< intr
->num_components
; i
++) {
1046 struct ir3_instruction
*load
=
1047 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1048 load
->cat6
.type
= TYPE_U32
;
1049 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
1054 /* handles array reads: */
1056 emit_intrinsic_load_var(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1057 struct ir3_instruction
**dst
)
1059 nir_deref_var
*dvar
= intr
->variables
[0];
1060 nir_deref_array
*darr
= nir_deref_as_array(dvar
->deref
.child
);
1061 struct ir3_array
*arr
= get_var(ctx
, dvar
->var
);
1063 compile_assert(ctx
, dvar
->deref
.child
&&
1064 (dvar
->deref
.child
->deref_type
== nir_deref_type_array
));
1066 switch (darr
->deref_array_type
) {
1067 case nir_deref_array_type_direct
:
1068 /* direct access does not require anything special: */
1069 for (int i
= 0; i
< intr
->num_components
; i
++) {
1070 unsigned n
= darr
->base_offset
* 4 + i
;
1071 compile_assert(ctx
, n
< arr
->length
);
1072 dst
[i
] = create_var_load(ctx
, arr
, n
, NULL
);
1075 case nir_deref_array_type_indirect
: {
1076 /* for indirect, we need to collect all the array elements: */
1077 struct ir3_instruction
*addr
=
1078 get_addr(ctx
, get_src(ctx
, &darr
->indirect
)[0]);
1079 for (int i
= 0; i
< intr
->num_components
; i
++) {
1080 unsigned n
= darr
->base_offset
* 4 + i
;
1081 compile_assert(ctx
, n
< arr
->length
);
1082 dst
[i
] = create_var_load(ctx
, arr
, n
, addr
);
1087 compile_error(ctx
, "Unhandled load deref type: %u\n",
1088 darr
->deref_array_type
);
1093 /* handles array writes: */
1095 emit_intrinsic_store_var(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1097 nir_deref_var
*dvar
= intr
->variables
[0];
1098 nir_deref_array
*darr
= nir_deref_as_array(dvar
->deref
.child
);
1099 struct ir3_array
*arr
= get_var(ctx
, dvar
->var
);
1100 struct ir3_instruction
*addr
, **src
;
1101 unsigned wrmask
= nir_intrinsic_write_mask(intr
);
1103 compile_assert(ctx
, dvar
->deref
.child
&&
1104 (dvar
->deref
.child
->deref_type
== nir_deref_type_array
));
1106 src
= get_src(ctx
, &intr
->src
[0]);
1108 switch (darr
->deref_array_type
) {
1109 case nir_deref_array_type_direct
:
1112 case nir_deref_array_type_indirect
:
1113 addr
= get_addr(ctx
, get_src(ctx
, &darr
->indirect
)[0]);
1116 compile_error(ctx
, "Unhandled store deref type: %u\n",
1117 darr
->deref_array_type
);
1121 for (int i
= 0; i
< intr
->num_components
; i
++) {
1122 if (!(wrmask
& (1 << i
)))
1124 unsigned n
= darr
->base_offset
* 4 + i
;
1125 compile_assert(ctx
, n
< arr
->length
);
1126 create_var_store(ctx
, arr
, n
, src
[i
], addr
);
1130 static void add_sysval_input(struct ir3_compile
*ctx
, gl_system_value slot
,
1131 struct ir3_instruction
*instr
)
1133 struct ir3_shader_variant
*so
= ctx
->so
;
1134 unsigned r
= regid(so
->inputs_count
, 0);
1135 unsigned n
= so
->inputs_count
++;
1137 so
->inputs
[n
].sysval
= true;
1138 so
->inputs
[n
].slot
= slot
;
1139 so
->inputs
[n
].compmask
= 1;
1140 so
->inputs
[n
].regid
= r
;
1141 so
->inputs
[n
].interpolate
= INTERP_QUALIFIER_FLAT
;
1144 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
1145 ctx
->ir
->inputs
[r
] = instr
;
1149 emit_intrinsic(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1151 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1152 struct ir3_instruction
**dst
, **src
;
1153 struct ir3_block
*b
= ctx
->block
;
1154 nir_const_value
*const_offset
;
1157 if (info
->has_dest
) {
1158 dst
= get_dst(ctx
, &intr
->dest
, intr
->num_components
);
1163 switch (intr
->intrinsic
) {
1164 case nir_intrinsic_load_uniform
:
1165 idx
= nir_intrinsic_base(intr
);
1166 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1168 idx
+= const_offset
->u32
[0];
1169 for (int i
= 0; i
< intr
->num_components
; i
++) {
1170 unsigned n
= idx
* 4 + i
;
1171 dst
[i
] = create_uniform(ctx
, n
);
1174 src
= get_src(ctx
, &intr
->src
[0]);
1175 for (int i
= 0; i
< intr
->num_components
; i
++) {
1176 int n
= idx
* 4 + i
;
1177 dst
[i
] = create_uniform_indirect(ctx
, n
,
1178 get_addr(ctx
, src
[0]));
1180 /* NOTE: if relative addressing is used, we set
1181 * constlen in the compiler (to worst-case value)
1182 * since we don't know in the assembler what the max
1183 * addr reg value can be:
1185 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
1188 case nir_intrinsic_load_ubo
:
1189 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1191 case nir_intrinsic_load_input
:
1192 idx
= nir_intrinsic_base(intr
);
1193 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1195 idx
+= const_offset
->u32
[0];
1196 for (int i
= 0; i
< intr
->num_components
; i
++) {
1197 unsigned n
= idx
* 4 + i
;
1198 dst
[i
] = ctx
->ir
->inputs
[n
];
1201 src
= get_src(ctx
, &intr
->src
[0]);
1202 struct ir3_instruction
*collect
=
1203 create_collect(b
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
1204 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0]);
1205 for (int i
= 0; i
< intr
->num_components
; i
++) {
1206 unsigned n
= idx
* 4 + i
;
1207 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
1212 case nir_intrinsic_load_var
:
1213 emit_intrinsic_load_var(ctx
, intr
, dst
);
1215 case nir_intrinsic_store_var
:
1216 emit_intrinsic_store_var(ctx
, intr
);
1218 case nir_intrinsic_store_output
:
1219 idx
= nir_intrinsic_base(intr
);
1220 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1221 compile_assert(ctx
, const_offset
!= NULL
);
1222 idx
+= const_offset
->u32
[0];
1224 src
= get_src(ctx
, &intr
->src
[0]);
1225 for (int i
= 0; i
< intr
->num_components
; i
++) {
1226 unsigned n
= idx
* 4 + i
;
1227 ctx
->ir
->outputs
[n
] = src
[i
];
1230 case nir_intrinsic_load_base_vertex
:
1231 if (!ctx
->basevertex
) {
1232 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
1233 add_sysval_input(ctx
, SYSTEM_VALUE_BASE_VERTEX
,
1236 dst
[0] = ctx
->basevertex
;
1238 case nir_intrinsic_load_vertex_id_zero_base
:
1239 if (!ctx
->vertex_id
) {
1240 ctx
->vertex_id
= create_input(b
, 0);
1241 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
,
1244 dst
[0] = ctx
->vertex_id
;
1246 case nir_intrinsic_load_instance_id
:
1247 if (!ctx
->instance_id
) {
1248 ctx
->instance_id
= create_input(b
, 0);
1249 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
1252 dst
[0] = ctx
->instance_id
;
1254 case nir_intrinsic_load_user_clip_plane
:
1255 idx
= nir_intrinsic_ucp_id(intr
);
1256 for (int i
= 0; i
< intr
->num_components
; i
++) {
1257 unsigned n
= idx
* 4 + i
;
1258 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
1261 case nir_intrinsic_load_front_face
:
1262 if (!ctx
->frag_face
) {
1263 ctx
->so
->frag_face
= true;
1264 ctx
->frag_face
= create_input(b
, 0);
1265 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
1267 /* for fragface, we always get -1 or 0, but that is inverse
1268 * of what nir expects (where ~0 is true). Unfortunately
1269 * trying to widen from half to full in add.s seems to do a
1270 * non-sign-extending widen (resulting in something that
1271 * gets interpreted as float Inf??)
1273 dst
[0] = ir3_COV(b
, ctx
->frag_face
, TYPE_S16
, TYPE_S32
);
1274 dst
[0] = ir3_ADD_S(b
, dst
[0], 0, create_immed(b
, 1), 0);
1276 case nir_intrinsic_discard_if
:
1277 case nir_intrinsic_discard
: {
1278 struct ir3_instruction
*cond
, *kill
;
1280 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
1281 /* conditional discard: */
1282 src
= get_src(ctx
, &intr
->src
[0]);
1283 cond
= ir3_b2n(b
, src
[0]);
1285 /* unconditional discard: */
1286 cond
= create_immed(b
, 1);
1289 /* NOTE: only cmps.*.* can write p0.x: */
1290 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1291 cond
->cat2
.condition
= IR3_COND_NE
;
1293 /* condition always goes in predicate register: */
1294 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1296 kill
= ir3_KILL(b
, cond
, 0);
1297 array_insert(ctx
->ir
->predicates
, kill
);
1299 array_insert(ctx
->ir
->keeps
, kill
);
1300 ctx
->so
->has_kill
= true;
1305 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
1306 nir_intrinsic_infos
[intr
->intrinsic
].name
);
1312 emit_load_const(struct ir3_compile
*ctx
, nir_load_const_instr
*instr
)
1314 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
1315 instr
->def
.num_components
);
1316 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1317 dst
[i
] = create_immed(ctx
->block
, instr
->value
.u32
[i
]);
1321 emit_undef(struct ir3_compile
*ctx
, nir_ssa_undef_instr
*undef
)
1323 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
1324 undef
->def
.num_components
);
1325 /* backend doesn't want undefined instructions, so just plug
1328 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
1329 dst
[i
] = create_immed(ctx
->block
, fui(0.0));
1333 * texture fetch/sample instructions:
1337 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
1339 unsigned coords
, flags
= 0;
1341 /* note: would use tex->coord_components.. except txs.. also,
1342 * since array index goes after shadow ref, we don't want to
1345 switch (tex
->sampler_dim
) {
1346 case GLSL_SAMPLER_DIM_1D
:
1347 case GLSL_SAMPLER_DIM_BUF
:
1350 case GLSL_SAMPLER_DIM_2D
:
1351 case GLSL_SAMPLER_DIM_RECT
:
1352 case GLSL_SAMPLER_DIM_EXTERNAL
:
1353 case GLSL_SAMPLER_DIM_MS
:
1356 case GLSL_SAMPLER_DIM_3D
:
1357 case GLSL_SAMPLER_DIM_CUBE
:
1359 flags
|= IR3_INSTR_3D
;
1362 unreachable("bad sampler_dim");
1365 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1366 flags
|= IR3_INSTR_S
;
1368 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
1369 flags
|= IR3_INSTR_A
;
1376 emit_tex(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1378 struct ir3_block
*b
= ctx
->block
;
1379 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
1380 struct ir3_instruction
**coord
, *lod
, *compare
, *proj
, **off
, **ddx
, **ddy
;
1381 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
1382 unsigned i
, coords
, flags
;
1383 unsigned nsrc0
= 0, nsrc1
= 0;
1387 coord
= off
= ddx
= ddy
= NULL
;
1388 lod
= proj
= compare
= NULL
;
1390 /* TODO: might just be one component for gathers? */
1391 dst
= get_dst(ctx
, &tex
->dest
, 4);
1393 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
1394 switch (tex
->src
[i
].src_type
) {
1395 case nir_tex_src_coord
:
1396 coord
= get_src(ctx
, &tex
->src
[i
].src
);
1398 case nir_tex_src_bias
:
1399 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1402 case nir_tex_src_lod
:
1403 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1406 case nir_tex_src_comparitor
: /* shadow comparator */
1407 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1409 case nir_tex_src_projector
:
1410 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1413 case nir_tex_src_offset
:
1414 off
= get_src(ctx
, &tex
->src
[i
].src
);
1417 case nir_tex_src_ddx
:
1418 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
1420 case nir_tex_src_ddy
:
1421 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
1424 compile_error(ctx
, "Unhandled NIR tex src type: %d\n",
1425 tex
->src
[i
].src_type
);
1431 case nir_texop_tex
: opc
= OPC_SAM
; break;
1432 case nir_texop_txb
: opc
= OPC_SAMB
; break;
1433 case nir_texop_txl
: opc
= OPC_SAML
; break;
1434 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
1435 case nir_texop_txf
: opc
= OPC_ISAML
; break;
1436 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
1437 case nir_texop_txf_ms
:
1440 case nir_texop_query_levels
:
1441 case nir_texop_texture_samples
:
1442 case nir_texop_samples_identical
:
1443 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
1447 tex_info(tex
, &flags
, &coords
);
1449 /* scale up integer coords for TXF based on the LOD */
1450 if (ctx
->unminify_coords
&& (opc
== OPC_ISAML
)) {
1452 for (i
= 0; i
< coords
; i
++)
1453 coord
[i
] = ir3_SHL_B(b
, coord
[i
], 0, lod
, 0);
1456 /* the array coord for cube arrays needs 0.5 added to it */
1457 if (ctx
->array_index_add_half
&& tex
->is_array
&& (opc
!= OPC_ISAML
))
1458 coord
[coords
] = ir3_ADD_F(b
, coord
[coords
], 0, create_immed(b
, fui(0.5)), 0);
1461 * lay out the first argument in the proper order:
1462 * - actual coordinates first
1463 * - shadow reference
1466 * - starting at offset 4, dpdx.xy, dpdy.xy
1468 * bias/lod go into the second arg
1471 /* insert tex coords: */
1472 for (i
= 0; i
< coords
; i
++)
1473 src0
[nsrc0
++] = coord
[i
];
1476 /* hw doesn't do 1d, so we treat it as 2d with
1477 * height of 1, and patch up the y coord.
1478 * TODO: y coord should be (int)0 in some cases..
1480 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
1483 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1484 src0
[nsrc0
++] = compare
;
1486 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
1487 src0
[nsrc0
++] = coord
[coords
];
1490 src0
[nsrc0
++] = proj
;
1491 flags
|= IR3_INSTR_P
;
1494 /* pad to 4, then ddx/ddy: */
1495 if (tex
->op
== nir_texop_txd
) {
1497 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1498 for (i
= 0; i
< coords
; i
++)
1499 src0
[nsrc0
++] = ddx
[i
];
1501 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1502 for (i
= 0; i
< coords
; i
++)
1503 src0
[nsrc0
++] = ddy
[i
];
1505 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1509 * second argument (if applicable):
1514 if (has_off
| has_lod
| has_bias
) {
1516 for (i
= 0; i
< coords
; i
++)
1517 src1
[nsrc1
++] = off
[i
];
1519 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
1520 flags
|= IR3_INSTR_O
;
1523 if (has_lod
| has_bias
)
1524 src1
[nsrc1
++] = lod
;
1527 switch (tex
->dest_type
) {
1528 case nir_type_invalid
:
1529 case nir_type_float
:
1540 unreachable("bad dest_type");
1543 if (opc
== OPC_GETLOD
)
1546 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
,
1547 flags
, tex
->texture_index
, tex
->texture_index
,
1548 create_collect(b
, src0
, nsrc0
),
1549 create_collect(b
, src1
, nsrc1
));
1551 split_dest(b
, dst
, sam
, 4);
1553 /* GETLOD returns results in 4.8 fixed point */
1554 if (opc
== OPC_GETLOD
) {
1555 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
1557 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
1558 for (i
= 0; i
< 2; i
++) {
1559 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_U32
, TYPE_F32
), 0,
1566 emit_tex_query_levels(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1568 struct ir3_block
*b
= ctx
->block
;
1569 struct ir3_instruction
**dst
, *sam
;
1571 dst
= get_dst(ctx
, &tex
->dest
, 1);
1573 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
1574 tex
->texture_index
, tex
->texture_index
, NULL
, NULL
);
1576 /* even though there is only one component, since it ends
1577 * up in .z rather than .x, we need a split_dest()
1579 split_dest(b
, dst
, sam
, 3);
1581 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1582 * the value in TEX_CONST_0 is zero-based.
1584 if (ctx
->levels_add_one
)
1585 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
1589 emit_tex_txs(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1591 struct ir3_block
*b
= ctx
->block
;
1592 struct ir3_instruction
**dst
, *sam
, *lod
;
1593 unsigned flags
, coords
;
1595 tex_info(tex
, &flags
, &coords
);
1597 /* Actually we want the number of dimensions, not coordinates. This
1598 * distinction only matters for cubes.
1600 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
1603 dst
= get_dst(ctx
, &tex
->dest
, 4);
1605 compile_assert(ctx
, tex
->num_srcs
== 1);
1606 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
1608 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
1610 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
1611 tex
->texture_index
, tex
->texture_index
, lod
, NULL
);
1613 split_dest(b
, dst
, sam
, 4);
1615 /* Array size actually ends up in .w rather than .z. This doesn't
1616 * matter for miplevel 0, but for higher mips the value in z is
1617 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1618 * returned, which means that we have to add 1 to it for arrays.
1620 if (tex
->is_array
) {
1621 if (ctx
->levels_add_one
) {
1622 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
1624 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
1630 emit_phi(struct ir3_compile
*ctx
, nir_phi_instr
*nphi
)
1632 struct ir3_instruction
*phi
, **dst
;
1634 /* NOTE: phi's should be lowered to scalar at this point */
1635 compile_assert(ctx
, nphi
->dest
.ssa
.num_components
== 1);
1637 dst
= get_dst(ctx
, &nphi
->dest
, 1);
1639 phi
= ir3_instr_create2(ctx
->block
, OPC_META_PHI
,
1640 1 + exec_list_length(&nphi
->srcs
));
1641 ir3_reg_create(phi
, 0, 0); /* dst */
1642 phi
->phi
.nphi
= nphi
;
1647 /* phi instructions are left partially constructed. We don't resolve
1648 * their srcs until the end of the block, since (eg. loops) one of
1649 * the phi's srcs might be defined after the phi due to back edges in
1653 resolve_phis(struct ir3_compile
*ctx
, struct ir3_block
*block
)
1655 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
1656 nir_phi_instr
*nphi
;
1658 /* phi's only come at start of block: */
1659 if (instr
->opc
!= OPC_META_PHI
)
1662 if (!instr
->phi
.nphi
)
1665 nphi
= instr
->phi
.nphi
;
1666 instr
->phi
.nphi
= NULL
;
1668 foreach_list_typed(nir_phi_src
, nsrc
, node
, &nphi
->srcs
) {
1669 struct ir3_instruction
*src
= get_src(ctx
, &nsrc
->src
)[0];
1671 /* NOTE: src might not be in the same block as it comes from
1672 * according to the phi.. but in the end the backend assumes
1673 * it will be able to assign the same register to each (which
1674 * only works if it is assigned in the src block), so insert
1675 * an extra mov to make sure the phi src is assigned in the
1676 * block it comes from:
1678 src
= ir3_MOV(get_block(ctx
, nsrc
->pred
), src
, TYPE_U32
);
1680 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
1686 emit_jump(struct ir3_compile
*ctx
, nir_jump_instr
*jump
)
1688 switch (jump
->type
) {
1689 case nir_jump_break
:
1690 case nir_jump_continue
:
1691 /* I *think* we can simply just ignore this, and use the
1692 * successor block link to figure out where we need to
1693 * jump to for break/continue
1697 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
1703 emit_instr(struct ir3_compile
*ctx
, nir_instr
*instr
)
1705 switch (instr
->type
) {
1706 case nir_instr_type_alu
:
1707 emit_alu(ctx
, nir_instr_as_alu(instr
));
1709 case nir_instr_type_intrinsic
:
1710 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1712 case nir_instr_type_load_const
:
1713 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1715 case nir_instr_type_ssa_undef
:
1716 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
1718 case nir_instr_type_tex
: {
1719 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
1720 /* couple tex instructions get special-cased:
1724 emit_tex_txs(ctx
, tex
);
1726 case nir_texop_query_levels
:
1727 emit_tex_query_levels(ctx
, tex
);
1735 case nir_instr_type_phi
:
1736 emit_phi(ctx
, nir_instr_as_phi(instr
));
1738 case nir_instr_type_jump
:
1739 emit_jump(ctx
, nir_instr_as_jump(instr
));
1741 case nir_instr_type_call
:
1742 case nir_instr_type_parallel_copy
:
1743 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
1748 static struct ir3_block
*
1749 get_block(struct ir3_compile
*ctx
, nir_block
*nblock
)
1751 struct ir3_block
*block
;
1752 struct hash_entry
*entry
;
1753 entry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
1757 block
= ir3_block_create(ctx
->ir
);
1758 block
->nblock
= nblock
;
1759 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
1765 emit_block(struct ir3_compile
*ctx
, nir_block
*nblock
)
1767 struct ir3_block
*block
= get_block(ctx
, nblock
);
1769 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
1770 if (nblock
->successors
[i
]) {
1771 block
->successors
[i
] =
1772 get_block(ctx
, nblock
->successors
[i
]);
1777 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
1779 /* re-emit addr register in each block if needed: */
1780 _mesa_hash_table_destroy(ctx
->addr_ht
, NULL
);
1781 ctx
->addr_ht
= NULL
;
1783 nir_foreach_instr(nblock
, instr
) {
1784 emit_instr(ctx
, instr
);
1790 static void emit_cf_list(struct ir3_compile
*ctx
, struct exec_list
*list
);
1793 emit_if(struct ir3_compile
*ctx
, nir_if
*nif
)
1795 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
1797 ctx
->block
->condition
=
1798 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
1800 emit_cf_list(ctx
, &nif
->then_list
);
1801 emit_cf_list(ctx
, &nif
->else_list
);
1805 emit_loop(struct ir3_compile
*ctx
, nir_loop
*nloop
)
1807 emit_cf_list(ctx
, &nloop
->body
);
1811 emit_cf_list(struct ir3_compile
*ctx
, struct exec_list
*list
)
1813 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
1814 switch (node
->type
) {
1815 case nir_cf_node_block
:
1816 emit_block(ctx
, nir_cf_node_as_block(node
));
1818 case nir_cf_node_if
:
1819 emit_if(ctx
, nir_cf_node_as_if(node
));
1821 case nir_cf_node_loop
:
1822 emit_loop(ctx
, nir_cf_node_as_loop(node
));
1824 case nir_cf_node_function
:
1825 compile_error(ctx
, "TODO\n");
1831 /* emit stream-out code. At this point, the current block is the original
1832 * (nir) end block, and nir ensures that all flow control paths terminate
1833 * into the end block. We re-purpose the original end block to generate
1834 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
1835 * block holding stream-out write instructions, followed by the new end
1839 * p0.x = (vtxcnt < maxvtxcnt)
1840 * // succs: blockStreamOut, blockNewEnd
1843 * ... stream-out instructions ...
1844 * // succs: blockNewEnd
1850 emit_stream_out(struct ir3_compile
*ctx
)
1852 struct ir3_shader_variant
*v
= ctx
->so
;
1853 struct ir3
*ir
= ctx
->ir
;
1854 struct pipe_stream_output_info
*strmout
=
1855 &ctx
->so
->shader
->stream_output
;
1856 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
1857 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
1858 struct ir3_instruction
*bases
[PIPE_MAX_SO_BUFFERS
];
1860 /* create vtxcnt input in input block at top of shader,
1861 * so that it is seen as live over the entire duration
1864 vtxcnt
= create_input(ctx
->in_block
, 0);
1865 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
1867 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
1869 /* at this point, we are at the original 'end' block,
1870 * re-purpose this block to stream-out condition, then
1871 * append stream-out block and new-end block
1873 orig_end_block
= ctx
->block
;
1875 stream_out_block
= ir3_block_create(ir
);
1876 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
1878 new_end_block
= ir3_block_create(ir
);
1879 list_addtail(&new_end_block
->node
, &ir
->block_list
);
1881 orig_end_block
->successors
[0] = stream_out_block
;
1882 orig_end_block
->successors
[1] = new_end_block
;
1883 stream_out_block
->successors
[0] = new_end_block
;
1885 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
1886 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
1887 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1888 cond
->cat2
.condition
= IR3_COND_LT
;
1890 /* condition goes on previous block to the conditional,
1891 * since it is used to pick which of the two successor
1894 orig_end_block
->condition
= cond
;
1896 /* switch to stream_out_block to generate the stream-out
1899 ctx
->block
= stream_out_block
;
1901 /* Calculate base addresses based on vtxcnt. Instructions
1902 * generated for bases not used in following loop will be
1903 * stripped out in the backend.
1905 for (unsigned i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
1906 unsigned stride
= strmout
->stride
[i
];
1907 struct ir3_instruction
*base
, *off
;
1909 base
= create_uniform(ctx
, regid(v
->first_driver_param
+ IR3_TFBOS_OFF
, i
));
1911 /* 24-bit should be enough: */
1912 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
1913 create_immed(ctx
->block
, stride
* 4), 0);
1915 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
1918 /* Generate the per-output store instructions: */
1919 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
1920 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
1921 unsigned c
= j
+ strmout
->output
[i
].start_component
;
1922 struct ir3_instruction
*base
, *out
, *stg
;
1924 base
= bases
[strmout
->output
[i
].output_buffer
];
1925 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
1927 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
1928 create_immed(ctx
->block
, 1), 0);
1929 stg
->cat6
.type
= TYPE_U32
;
1930 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
1932 array_insert(ctx
->ir
->keeps
, stg
);
1936 /* and finally switch to the new_end_block: */
1937 ctx
->block
= new_end_block
;
1941 emit_function(struct ir3_compile
*ctx
, nir_function_impl
*impl
)
1943 nir_metadata_require(impl
, nir_metadata_block_index
);
1945 emit_cf_list(ctx
, &impl
->body
);
1946 emit_block(ctx
, impl
->end_block
);
1948 /* at this point, we should have a single empty block,
1949 * into which we emit the 'end' instruction.
1951 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
1953 /* If stream-out (aka transform-feedback) enabled, emit the
1954 * stream-out instructions, followed by a new empty block (into
1955 * which the 'end' instruction lands).
1957 * NOTE: it is done in this order, rather than inserting before
1958 * we emit end_block, because NIR guarantees that all blocks
1959 * flow into end_block, and that end_block has no successors.
1960 * So by re-purposing end_block as the first block of stream-
1961 * out, we guarantee that all exit paths flow into the stream-
1964 if ((ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
1965 !ctx
->so
->key
.binning_pass
) {
1966 debug_assert(ctx
->so
->type
== SHADER_VERTEX
);
1967 emit_stream_out(ctx
);
1970 ir3_END(ctx
->block
);
1974 setup_input(struct ir3_compile
*ctx
, nir_variable
*in
)
1976 struct ir3_shader_variant
*so
= ctx
->so
;
1977 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
1978 unsigned ncomp
= glsl_get_components(in
->type
);
1979 unsigned n
= in
->data
.driver_location
;
1980 unsigned slot
= in
->data
.location
;
1982 DBG("; in: slot=%u, len=%ux%u, drvloc=%u",
1983 slot
, array_len
, ncomp
, n
);
1985 so
->inputs
[n
].slot
= slot
;
1986 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
1987 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
1988 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
1990 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
1991 for (int i
= 0; i
< ncomp
; i
++) {
1992 struct ir3_instruction
*instr
= NULL
;
1993 unsigned idx
= (n
* 4) + i
;
1995 if (slot
== VARYING_SLOT_POS
) {
1996 so
->inputs
[n
].bary
= false;
1997 so
->frag_coord
= true;
1998 instr
= create_frag_coord(ctx
, i
);
1999 } else if (slot
== VARYING_SLOT_FACE
) {
2000 so
->inputs
[n
].bary
= false;
2001 so
->frag_face
= true;
2002 instr
= create_frag_face(ctx
, i
);
2004 bool use_ldlv
= false;
2006 /* detect the special case for front/back colors where
2007 * we need to do flat vs smooth shading depending on
2010 if (in
->data
.interpolation
== INTERP_QUALIFIER_NONE
) {
2012 case VARYING_SLOT_COL0
:
2013 case VARYING_SLOT_COL1
:
2014 case VARYING_SLOT_BFC0
:
2015 case VARYING_SLOT_BFC1
:
2016 so
->inputs
[n
].rasterflat
= true;
2023 if (ctx
->flat_bypass
) {
2024 if ((so
->inputs
[n
].interpolate
== INTERP_QUALIFIER_FLAT
) ||
2025 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
2029 so
->inputs
[n
].bary
= true;
2031 instr
= create_frag_input(ctx
, use_ldlv
);
2034 ctx
->ir
->inputs
[idx
] = instr
;
2036 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2037 for (int i
= 0; i
< ncomp
; i
++) {
2038 unsigned idx
= (n
* 4) + i
;
2039 ctx
->ir
->inputs
[idx
] = create_input(ctx
->block
, idx
);
2042 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2045 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
2046 so
->total_in
+= ncomp
;
2051 setup_output(struct ir3_compile
*ctx
, nir_variable
*out
)
2053 struct ir3_shader_variant
*so
= ctx
->so
;
2054 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
2055 unsigned ncomp
= glsl_get_components(out
->type
);
2056 unsigned n
= out
->data
.driver_location
;
2057 unsigned slot
= out
->data
.location
;
2060 DBG("; out: slot=%u, len=%ux%u, drvloc=%u",
2061 slot
, array_len
, ncomp
, n
);
2063 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2065 case FRAG_RESULT_DEPTH
:
2066 comp
= 2; /* tgsi will write to .z component */
2067 so
->writes_pos
= true;
2069 case FRAG_RESULT_COLOR
:
2073 if (slot
>= FRAG_RESULT_DATA0
)
2075 compile_error(ctx
, "unknown FS output name: %s\n",
2076 gl_frag_result_name(slot
));
2078 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2080 case VARYING_SLOT_POS
:
2081 so
->writes_pos
= true;
2083 case VARYING_SLOT_PSIZ
:
2084 so
->writes_psize
= true;
2086 case VARYING_SLOT_COL0
:
2087 case VARYING_SLOT_COL1
:
2088 case VARYING_SLOT_BFC0
:
2089 case VARYING_SLOT_BFC1
:
2090 case VARYING_SLOT_FOGC
:
2091 case VARYING_SLOT_CLIP_DIST0
:
2092 case VARYING_SLOT_CLIP_DIST1
:
2094 case VARYING_SLOT_CLIP_VERTEX
:
2095 /* handled entirely in nir_lower_clip: */
2098 if (slot
>= VARYING_SLOT_VAR0
)
2100 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
2102 compile_error(ctx
, "unknown VS output name: %s\n",
2103 gl_varying_slot_name(slot
));
2106 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2109 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
2111 so
->outputs
[n
].slot
= slot
;
2112 so
->outputs
[n
].regid
= regid(n
, comp
);
2113 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
2115 for (int i
= 0; i
< ncomp
; i
++) {
2116 unsigned idx
= (n
* 4) + i
;
2118 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
2123 emit_instructions(struct ir3_compile
*ctx
)
2125 unsigned ninputs
, noutputs
;
2126 nir_function_impl
*fxn
= NULL
;
2128 /* Find the main function: */
2129 nir_foreach_function(ctx
->s
, function
) {
2130 compile_assert(ctx
, strcmp(function
->name
, "main") == 0);
2131 compile_assert(ctx
, function
->impl
);
2132 fxn
= function
->impl
;
2136 ninputs
= exec_list_length(&ctx
->s
->inputs
) * 4;
2137 noutputs
= exec_list_length(&ctx
->s
->outputs
) * 4;
2139 /* or vtx shaders, we need to leave room for sysvals:
2141 if (ctx
->so
->type
== SHADER_VERTEX
) {
2145 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
2147 /* Create inputs in first block: */
2148 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
2149 ctx
->in_block
= ctx
->block
;
2150 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
2152 if (ctx
->so
->type
== SHADER_VERTEX
) {
2153 ctx
->ir
->ninputs
-= 8;
2156 /* for fragment shader, we have a single input register (usually
2157 * r0.xy) which is used as the base for bary.f varying fetch instrs:
2159 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2160 // TODO maybe a helper for fi since we need it a few places..
2161 struct ir3_instruction
*instr
;
2162 instr
= ir3_instr_create(ctx
->block
, OPC_META_FI
);
2163 ir3_reg_create(instr
, 0, 0);
2164 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.x */
2165 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.y */
2166 ctx
->frag_pos
= instr
;
2170 nir_foreach_variable(var
, &ctx
->s
->inputs
) {
2171 setup_input(ctx
, var
);
2174 /* Setup outputs: */
2175 nir_foreach_variable(var
, &ctx
->s
->outputs
) {
2176 setup_output(ctx
, var
);
2179 /* Setup global variables (which should only be arrays): */
2180 nir_foreach_variable(var
, &ctx
->s
->globals
) {
2181 declare_var(ctx
, var
);
2184 /* Setup local variables (which should only be arrays): */
2185 /* NOTE: need to do something more clever when we support >1 fxn */
2186 nir_foreach_variable(var
, &fxn
->locals
) {
2187 declare_var(ctx
, var
);
2190 /* And emit the body: */
2192 emit_function(ctx
, fxn
);
2194 list_for_each_entry (struct ir3_block
, block
, &ctx
->ir
->block_list
, node
) {
2195 resolve_phis(ctx
, block
);
2199 /* from NIR perspective, we actually have inputs. But most of the "inputs"
2200 * for a fragment shader are just bary.f instructions. The *actual* inputs
2201 * from the hw perspective are the frag_pos and optionally frag_coord and
2205 fixup_frag_inputs(struct ir3_compile
*ctx
)
2207 struct ir3_shader_variant
*so
= ctx
->so
;
2208 struct ir3
*ir
= ctx
->ir
;
2209 struct ir3_instruction
**inputs
;
2210 struct ir3_instruction
*instr
;
2215 n
= 4; /* always have frag_pos */
2216 n
+= COND(so
->frag_face
, 4);
2217 n
+= COND(so
->frag_coord
, 4);
2219 inputs
= ir3_alloc(ctx
->ir
, n
* (sizeof(struct ir3_instruction
*)));
2221 if (so
->frag_face
) {
2222 /* this ultimately gets assigned to hr0.x so doesn't conflict
2223 * with frag_coord/frag_pos..
2225 inputs
[ir
->ninputs
++] = ctx
->frag_face
;
2226 ctx
->frag_face
->regs
[0]->num
= 0;
2228 /* remaining channels not used, but let's avoid confusing
2229 * other parts that expect inputs to come in groups of vec4
2231 inputs
[ir
->ninputs
++] = NULL
;
2232 inputs
[ir
->ninputs
++] = NULL
;
2233 inputs
[ir
->ninputs
++] = NULL
;
2236 /* since we don't know where to set the regid for frag_coord,
2237 * we have to use r0.x for it. But we don't want to *always*
2238 * use r1.x for frag_pos as that could increase the register
2239 * footprint on simple shaders:
2241 if (so
->frag_coord
) {
2242 ctx
->frag_coord
[0]->regs
[0]->num
= regid
++;
2243 ctx
->frag_coord
[1]->regs
[0]->num
= regid
++;
2244 ctx
->frag_coord
[2]->regs
[0]->num
= regid
++;
2245 ctx
->frag_coord
[3]->regs
[0]->num
= regid
++;
2247 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[0];
2248 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[1];
2249 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[2];
2250 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[3];
2253 /* we always have frag_pos: */
2254 so
->pos_regid
= regid
;
2257 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2258 instr
->regs
[0]->num
= regid
++;
2259 inputs
[ir
->ninputs
++] = instr
;
2260 ctx
->frag_pos
->regs
[1]->instr
= instr
;
2263 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2264 instr
->regs
[0]->num
= regid
++;
2265 inputs
[ir
->ninputs
++] = instr
;
2266 ctx
->frag_pos
->regs
[2]->instr
= instr
;
2268 ir
->inputs
= inputs
;
2272 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
2273 struct ir3_shader_variant
*so
)
2275 struct ir3_compile
*ctx
;
2277 struct ir3_instruction
**inputs
;
2278 unsigned i
, j
, actual_in
, inloc
;
2279 int ret
= 0, max_bary
;
2283 ctx
= compile_init(compiler
, so
);
2285 DBG("INIT failed!");
2290 emit_instructions(ctx
);
2293 DBG("EMIT failed!");
2298 ir
= so
->ir
= ctx
->ir
;
2300 /* keep track of the inputs from TGSI perspective.. */
2301 inputs
= ir
->inputs
;
2303 /* but fixup actual inputs for frag shader: */
2304 if (so
->type
== SHADER_FRAGMENT
)
2305 fixup_frag_inputs(ctx
);
2307 /* at this point, for binning pass, throw away unneeded outputs: */
2308 if (so
->key
.binning_pass
) {
2309 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
2310 unsigned slot
= so
->outputs
[i
].slot
;
2312 /* throw away everything but first position/psize */
2313 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
2315 so
->outputs
[j
] = so
->outputs
[i
];
2316 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
2317 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
2318 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
2319 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
2324 so
->outputs_count
= j
;
2325 ir
->noutputs
= j
* 4;
2328 /* if we want half-precision outputs, mark the output registers
2331 if (so
->key
.half_precision
) {
2332 for (i
= 0; i
< ir
->noutputs
; i
++) {
2333 struct ir3_instruction
*out
= ir
->outputs
[i
];
2336 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2337 /* output could be a fanout (ie. texture fetch output)
2338 * in which case we need to propagate the half-reg flag
2339 * up to the definer so that RA sees it:
2341 if (out
->opc
== OPC_META_FO
) {
2342 out
= out
->regs
[1]->instr
;
2343 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2346 if (out
->opc
== OPC_MOV
) {
2347 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
2352 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2353 printf("BEFORE CP:\n");
2359 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2360 printf("BEFORE GROUPING:\n");
2364 /* Group left/right neighbors, inserting mov's where needed to
2371 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2372 printf("AFTER DEPTH:\n");
2376 ret
= ir3_sched(ir
);
2378 DBG("SCHED failed!");
2382 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2383 printf("AFTER SCHED:\n");
2387 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
2393 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2394 printf("AFTER RA:\n");
2398 /* fixup input/outputs: */
2399 for (i
= 0; i
< so
->outputs_count
; i
++) {
2400 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
2401 /* preserve hack for depth output.. tgsi writes depth to .z,
2402 * but what we give the hw is the scalar register:
2404 if ((so
->type
== SHADER_FRAGMENT
) &&
2405 (so
->outputs
[i
].slot
== FRAG_RESULT_DEPTH
))
2406 so
->outputs
[i
].regid
+= 2;
2409 /* Note that some or all channels of an input may be unused: */
2412 for (i
= 0; i
< so
->inputs_count
; i
++) {
2413 unsigned j
, regid
= ~0, compmask
= 0;
2414 so
->inputs
[i
].ncomp
= 0;
2415 so
->inputs
[i
].inloc
= inloc
+ 8;
2416 for (j
= 0; j
< 4; j
++) {
2417 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
2418 if (in
&& !(in
->flags
& IR3_INSTR_UNUSED
)) {
2419 compmask
|= (1 << j
);
2420 regid
= in
->regs
[0]->num
- j
;
2422 so
->inputs
[i
].ncomp
++;
2423 if ((so
->type
== SHADER_FRAGMENT
) && so
->inputs
[i
].bary
) {
2425 assert(in
->regs
[1]->flags
& IR3_REG_IMMED
);
2426 in
->regs
[1]->iim_val
= inloc
++;
2430 if ((so
->type
== SHADER_FRAGMENT
) && compmask
&& so
->inputs
[i
].bary
)
2432 so
->inputs
[i
].regid
= regid
;
2433 so
->inputs
[i
].compmask
= compmask
;
2436 /* We need to do legalize after (for frag shader's) the "bary.f"
2437 * offsets (inloc) have been assigned.
2439 ir3_legalize(ir
, &so
->has_samp
, &max_bary
);
2441 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2442 printf("AFTER LEGALIZE:\n");
2446 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
2447 if (so
->type
== SHADER_VERTEX
)
2448 so
->total_in
= actual_in
;
2450 so
->total_in
= max_bary
+ 1;
2455 ir3_destroy(so
->ir
);