1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
35 #include "tgsi/tgsi_lowering.h"
36 #include "tgsi/tgsi_strings.h"
38 #include "nir/tgsi_to_nir.h"
40 #include "freedreno_util.h"
42 #include "ir3_compiler.h"
43 #include "ir3_shader.h"
46 #include "instr-a3xx.h"
51 struct ir3_compiler
*compiler
;
53 const struct tgsi_token
*tokens
;
57 struct ir3_shader_variant
*so
;
59 struct ir3_block
*block
; /* the current block */
60 struct ir3_block
*in_block
; /* block created for shader inputs */
62 nir_function_impl
*impl
;
64 /* For fragment shaders, from the hw perspective the only
65 * actual input is r0.xy position register passed to bary.f.
66 * But TGSI doesn't know that, it still declares things as
67 * IN[] registers. So we do all the input tracking normally
68 * and fix things up after compile_instructions()
70 * NOTE that frag_pos is the hardware position (possibly it
71 * is actually an index or tag or some such.. it is *not*
72 * values that can be directly used for gl_FragCoord..)
74 struct ir3_instruction
*frag_pos
, *frag_face
, *frag_coord
[4];
76 /* For vertex shaders, keep track of the system values sources */
77 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
79 /* mapping from nir_register to defining instruction: */
80 struct hash_table
*def_ht
;
82 /* mapping from nir_variable to ir3_array: */
83 struct hash_table
*var_ht
;
86 /* a common pattern for indirect addressing is to request the
87 * same address register multiple times. To avoid generating
88 * duplicate instruction sequences (which our backend does not
89 * try to clean up, since that should be done as the NIR stage)
90 * we cache the address value generated for a given src value:
92 struct hash_table
*addr_ht
;
94 /* maps nir_block to ir3_block, mostly for the purposes of
95 * figuring out the blocks successors
97 struct hash_table
*block_ht
;
99 /* for calculating input/output positions/linkages: */
102 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
103 * so we need to use ldlv.u32 to load the varying directly:
107 /* on a3xx, we need to add one to # of array levels:
111 /* on a3xx, we need to scale up integer coords for isaml based
114 bool unminify_coords
;
116 /* for looking up which system value is which */
117 unsigned sysval_semantics
[8];
119 /* set if we encounter something we can't handle yet, so we
120 * can bail cleanly and fallback to TGSI compiler f/e
126 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
127 static struct ir3_block
* get_block(struct ir3_compile
*ctx
, nir_block
*nblock
);
129 static struct nir_shader
*to_nir(struct ir3_compile
*ctx
,
130 const struct tgsi_token
*tokens
, struct ir3_shader_variant
*so
)
132 static const nir_shader_compiler_options options
= {
137 .lower_ffract
= true,
138 .native_integers
= true,
140 struct nir_lower_tex_options tex_options
= {
146 case SHADER_FRAGMENT
:
148 tex_options
.saturate_s
= so
->key
.fsaturate_s
;
149 tex_options
.saturate_t
= so
->key
.fsaturate_t
;
150 tex_options
.saturate_r
= so
->key
.fsaturate_r
;
153 tex_options
.saturate_s
= so
->key
.vsaturate_s
;
154 tex_options
.saturate_t
= so
->key
.vsaturate_t
;
155 tex_options
.saturate_r
= so
->key
.vsaturate_r
;
159 if (ctx
->compiler
->gpu_id
>= 400) {
160 /* a4xx seems to have *no* sam.p */
161 tex_options
.lower_txp
= ~0; /* lower all txp */
163 /* a3xx just needs to avoid sam.p for 3d tex */
164 tex_options
.lower_txp
= (1 << GLSL_SAMPLER_DIM_3D
);
167 struct nir_shader
*s
= tgsi_to_nir(tokens
, &options
);
169 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
170 debug_printf("----------------------\n");
171 nir_print_shader(s
, stdout
);
172 debug_printf("----------------------\n");
175 nir_opt_global_to_local(s
);
176 nir_convert_to_ssa(s
);
177 if (s
->stage
== MESA_SHADER_VERTEX
) {
178 nir_lower_clip_vs(s
, so
->key
.ucp_enables
);
179 } else if (s
->stage
== MESA_SHADER_FRAGMENT
) {
180 nir_lower_clip_fs(s
, so
->key
.ucp_enables
);
182 nir_lower_tex(s
, &tex_options
);
183 if (so
->key
.color_two_side
)
184 nir_lower_two_sided_color(s
);
186 nir_lower_load_const_to_scalar(s
);
191 nir_lower_vars_to_ssa(s
);
192 nir_lower_alu_to_scalar(s
);
193 nir_lower_phis_to_scalar(s
);
195 progress
|= nir_copy_prop(s
);
196 progress
|= nir_opt_dce(s
);
197 progress
|= nir_opt_cse(s
);
198 progress
|= ir3_nir_lower_if_else(s
);
199 progress
|= nir_opt_algebraic(s
);
200 progress
|= nir_opt_constant_folding(s
);
204 nir_remove_dead_variables(s
);
205 nir_validate_shader(s
);
207 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
208 debug_printf("----------------------\n");
209 nir_print_shader(s
, stdout
);
210 debug_printf("----------------------\n");
216 static struct ir3_compile
*
217 compile_init(struct ir3_compiler
*compiler
,
218 struct ir3_shader_variant
*so
,
219 const struct tgsi_token
*tokens
)
221 struct ir3_compile
*ctx
= rzalloc(NULL
, struct ir3_compile
);
223 if (compiler
->gpu_id
>= 400) {
224 /* need special handling for "flat" */
225 ctx
->flat_bypass
= true;
226 ctx
->levels_add_one
= false;
227 ctx
->unminify_coords
= false;
229 /* no special handling for "flat" */
230 ctx
->flat_bypass
= false;
231 ctx
->levels_add_one
= true;
232 ctx
->unminify_coords
= true;
235 ctx
->compiler
= compiler
;
239 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
240 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
241 ctx
->var_ht
= _mesa_hash_table_create(ctx
,
242 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
243 ctx
->addr_ht
= _mesa_hash_table_create(ctx
,
244 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
245 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
246 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
248 ctx
->s
= to_nir(ctx
, tokens
, so
);
250 so
->first_driver_param
= so
->first_immediate
= ctx
->s
->num_uniforms
;
252 /* Layout of constant registers:
254 * num_uniform * vec4 - user consts
255 * 4 * vec4 - UBO addresses
256 * if (vertex shader) {
257 * N * vec4 - driver params (IR3_DP_*)
258 * 1 * vec4 - stream-out addresses
261 * TODO this could be made more dynamic, to at least skip sections
262 * that we don't need..
265 /* reserve 4 (vec4) slots for ubo base addresses: */
266 so
->first_immediate
+= 4;
268 if (so
->type
== SHADER_VERTEX
) {
269 /* driver params (see ir3_driver_param): */
270 so
->first_immediate
+= IR3_DP_COUNT
/4; /* convert to vec4 */
271 /* one (vec4) slot for stream-output base addresses: */
272 so
->first_immediate
++;
279 compile_error(struct ir3_compile
*ctx
, const char *format
, ...)
282 va_start(ap
, format
);
283 _debug_vprintf(format
, ap
);
285 nir_print_shader(ctx
->s
, stdout
);
290 #define compile_assert(ctx, cond) do { \
291 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
295 compile_free(struct ir3_compile
*ctx
)
300 /* global per-array information: */
302 unsigned length
, aid
;
305 /* per-block array state: */
306 struct ir3_array_value
{
307 /* TODO drop length/aid, and just have ptr back to ir3_array */
308 unsigned length
, aid
;
309 /* initial array element values are phi's, other than for the
310 * entry block. The phi src's get added later in a resolve step
311 * after we have visited all the blocks, to account for back
314 struct ir3_instruction
**phis
;
315 /* current array element values (as block is processed). When
316 * the array phi's are resolved, it will contain the array state
317 * at exit of block, so successor blocks can use it to add their
320 struct ir3_instruction
*arr
[];
323 /* track array assignments per basic block. When an array is read
324 * outside of the same basic block, we can use NIR's dominance-frontier
325 * information to figure out where phi nodes are needed.
327 struct ir3_nir_block_data
{
329 /* indexed by array-id (aid): */
330 struct ir3_array_value
*arrs
[];
333 static struct ir3_nir_block_data
*
334 get_block_data(struct ir3_compile
*ctx
, struct ir3_block
*block
)
337 struct ir3_nir_block_data
*bd
= ralloc_size(ctx
, sizeof(*bd
) +
338 ((ctx
->num_arrays
+ 1) * sizeof(bd
->arrs
[0])));
345 declare_var(struct ir3_compile
*ctx
, nir_variable
*var
)
347 unsigned length
= glsl_get_length(var
->type
) * 4; /* always vec4, at least with ttn */
348 struct ir3_array
*arr
= ralloc(ctx
, struct ir3_array
);
349 arr
->length
= length
;
350 arr
->aid
= ++ctx
->num_arrays
;
351 _mesa_hash_table_insert(ctx
->var_ht
, var
, arr
);
355 nir_block_pred(nir_block
*block
)
357 assert(block
->predecessors
->entries
< 2);
358 if (block
->predecessors
->entries
== 0)
360 return (nir_block
*)_mesa_set_next_entry(block
->predecessors
, NULL
)->key
;
363 static struct ir3_array_value
*
364 get_var(struct ir3_compile
*ctx
, nir_variable
*var
)
366 struct hash_entry
*entry
= _mesa_hash_table_search(ctx
->var_ht
, var
);
367 struct ir3_block
*block
= ctx
->block
;
368 struct ir3_nir_block_data
*bd
= get_block_data(ctx
, block
);
369 struct ir3_array
*arr
= entry
->data
;
371 if (!bd
->arrs
[arr
->aid
]) {
372 struct ir3_array_value
*av
= ralloc_size(bd
, sizeof(*av
) +
373 (arr
->length
* sizeof(av
->arr
[0])));
374 struct ir3_array_value
*defn
= NULL
;
375 nir_block
*pred_block
;
377 av
->length
= arr
->length
;
380 /* For loops, we have to consider that we have not visited some
381 * of the blocks who should feed into the phi (ie. back-edges in
382 * the cfg).. for example:
385 * block { load_var; ... }
386 * if then block {} else block {}
387 * block { store_var; ... }
388 * if then block {} else block {}
392 * We can skip the phi if we can chase the block predecessors
393 * until finding the block previously defining the array without
394 * crossing a block that has more than one predecessor.
396 * Otherwise create phi's and resolve them as a post-pass after
397 * all the blocks have been visited (to handle back-edges).
400 for (pred_block
= block
->nblock
;
401 pred_block
&& (pred_block
->predecessors
->entries
< 2) && !defn
;
402 pred_block
= nir_block_pred(pred_block
)) {
403 struct ir3_block
*pblock
= get_block(ctx
, pred_block
);
404 struct ir3_nir_block_data
*pbd
= pblock
->bd
;
407 defn
= pbd
->arrs
[arr
->aid
];
411 /* only one possible definer: */
412 for (unsigned i
= 0; i
< arr
->length
; i
++)
413 av
->arr
[i
] = defn
->arr
[i
];
414 } else if (pred_block
) {
415 /* not the first block, and multiple potential definers: */
416 av
->phis
= ralloc_size(av
, arr
->length
* sizeof(av
->phis
[0]));
418 for (unsigned i
= 0; i
< arr
->length
; i
++) {
419 struct ir3_instruction
*phi
;
421 phi
= ir3_instr_create2(block
, -1, OPC_META_PHI
,
422 1 + ctx
->impl
->num_blocks
);
423 ir3_reg_create(phi
, 0, 0); /* dst */
425 /* phi's should go at head of block: */
426 list_delinit(&phi
->node
);
427 list_add(&phi
->node
, &block
->instr_list
);
429 av
->phis
[i
] = av
->arr
[i
] = phi
;
432 /* Some shaders end up reading array elements without
433 * first writing.. so initialize things to prevent null
436 for (unsigned i
= 0; i
< arr
->length
; i
++)
437 av
->arr
[i
] = create_immed(block
, 0);
440 bd
->arrs
[arr
->aid
] = av
;
443 return bd
->arrs
[arr
->aid
];
447 add_array_phi_srcs(struct ir3_compile
*ctx
, nir_block
*nblock
,
448 struct ir3_array_value
*av
, BITSET_WORD
*visited
)
450 struct ir3_block
*block
;
451 struct ir3_nir_block_data
*bd
;
453 if (BITSET_TEST(visited
, nblock
->index
))
456 BITSET_SET(visited
, nblock
->index
);
458 block
= get_block(ctx
, nblock
);
461 if (bd
&& bd
->arrs
[av
->aid
]) {
462 struct ir3_array_value
*dav
= bd
->arrs
[av
->aid
];
463 for (unsigned i
= 0; i
< av
->length
; i
++) {
464 ir3_reg_create(av
->phis
[i
], 0, IR3_REG_SSA
)->instr
=
468 /* didn't find defn, recurse predecessors: */
469 struct set_entry
*entry
;
470 set_foreach(nblock
->predecessors
, entry
) {
471 add_array_phi_srcs(ctx
, (nir_block
*)entry
->key
, av
, visited
);
477 resolve_array_phis(struct ir3_compile
*ctx
, struct ir3_block
*block
)
479 struct ir3_nir_block_data
*bd
= block
->bd
;
480 unsigned bitset_words
= BITSET_WORDS(ctx
->impl
->num_blocks
);
485 /* TODO use nir dom_frontier to help us with this? */
487 for (unsigned i
= 1; i
<= ctx
->num_arrays
; i
++) {
488 struct ir3_array_value
*av
= bd
->arrs
[i
];
489 BITSET_WORD visited
[bitset_words
];
490 struct set_entry
*entry
;
492 if (!(av
&& av
->phis
))
495 memset(visited
, 0, sizeof(visited
));
496 set_foreach(block
->nblock
->predecessors
, entry
) {
497 add_array_phi_srcs(ctx
, (nir_block
*)entry
->key
, av
, visited
);
502 /* allocate a n element value array (to be populated by caller) and
505 static struct ir3_instruction
**
506 __get_dst(struct ir3_compile
*ctx
, void *key
, unsigned n
)
508 struct ir3_instruction
**value
=
509 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
510 _mesa_hash_table_insert(ctx
->def_ht
, key
, value
);
514 static struct ir3_instruction
**
515 get_dst(struct ir3_compile
*ctx
, nir_dest
*dst
, unsigned n
)
518 return __get_dst(ctx
, &dst
->ssa
, n
);
520 return __get_dst(ctx
, dst
->reg
.reg
, n
);
524 static struct ir3_instruction
**
525 get_dst_ssa(struct ir3_compile
*ctx
, nir_ssa_def
*dst
, unsigned n
)
527 return __get_dst(ctx
, dst
, n
);
530 static struct ir3_instruction
**
531 get_src(struct ir3_compile
*ctx
, nir_src
*src
)
533 struct hash_entry
*entry
;
535 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
537 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->reg
.reg
);
539 compile_assert(ctx
, entry
);
543 static struct ir3_instruction
*
544 create_immed(struct ir3_block
*block
, uint32_t val
)
546 struct ir3_instruction
*mov
;
548 mov
= ir3_instr_create(block
, 1, 0);
549 mov
->cat1
.src_type
= TYPE_U32
;
550 mov
->cat1
.dst_type
= TYPE_U32
;
551 ir3_reg_create(mov
, 0, 0);
552 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
557 static struct ir3_instruction
*
558 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
)
560 struct ir3_instruction
*instr
, *immed
;
562 /* TODO in at least some cases, the backend could probably be
563 * made clever enough to propagate IR3_REG_HALF..
565 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
566 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
568 immed
= create_immed(block
, 2);
569 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
571 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
572 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
573 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
575 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
576 instr
->regs
[0]->num
= regid(REG_A0
, 0);
577 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
578 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
583 /* caches addr values to avoid generating multiple cov/shl/mova
584 * sequences for each use of a given NIR level src as address
586 static struct ir3_instruction
*
587 get_addr(struct ir3_compile
*ctx
, struct ir3_instruction
*src
)
589 struct ir3_instruction
*addr
;
590 struct hash_entry
*entry
;
591 entry
= _mesa_hash_table_search(ctx
->addr_ht
, src
);
595 /* TODO do we need to cache per block? */
596 addr
= create_addr(ctx
->block
, src
);
597 _mesa_hash_table_insert(ctx
->addr_ht
, src
, addr
);
602 static struct ir3_instruction
*
603 get_predicate(struct ir3_compile
*ctx
, struct ir3_instruction
*src
)
605 struct ir3_block
*b
= ctx
->block
;
606 struct ir3_instruction
*cond
;
608 /* NOTE: only cmps.*.* can write p0.x: */
609 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
610 cond
->cat2
.condition
= IR3_COND_NE
;
612 /* condition always goes in predicate register: */
613 cond
->regs
[0]->num
= regid(REG_P0
, 0);
618 static struct ir3_instruction
*
619 create_uniform(struct ir3_compile
*ctx
, unsigned n
)
621 struct ir3_instruction
*mov
;
623 mov
= ir3_instr_create(ctx
->block
, 1, 0);
624 /* TODO get types right? */
625 mov
->cat1
.src_type
= TYPE_F32
;
626 mov
->cat1
.dst_type
= TYPE_F32
;
627 ir3_reg_create(mov
, 0, 0);
628 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
633 static struct ir3_instruction
*
634 create_uniform_indirect(struct ir3_compile
*ctx
, unsigned n
,
635 struct ir3_instruction
*address
)
637 struct ir3_instruction
*mov
;
639 mov
= ir3_instr_create(ctx
->block
, 1, 0);
640 mov
->cat1
.src_type
= TYPE_U32
;
641 mov
->cat1
.dst_type
= TYPE_U32
;
642 ir3_reg_create(mov
, 0, 0);
643 ir3_reg_create(mov
, n
, IR3_REG_CONST
| IR3_REG_RELATIV
);
645 ir3_instr_set_address(mov
, address
);
650 static struct ir3_instruction
*
651 create_collect(struct ir3_block
*block
, struct ir3_instruction
**arr
,
654 struct ir3_instruction
*collect
;
659 collect
= ir3_instr_create2(block
, -1, OPC_META_FI
, 1 + arrsz
);
660 ir3_reg_create(collect
, 0, 0); /* dst */
661 for (unsigned i
= 0; i
< arrsz
; i
++)
662 ir3_reg_create(collect
, 0, IR3_REG_SSA
)->instr
= arr
[i
];
667 static struct ir3_instruction
*
668 create_indirect_load(struct ir3_compile
*ctx
, unsigned arrsz
, unsigned n
,
669 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
671 struct ir3_block
*block
= ctx
->block
;
672 struct ir3_instruction
*mov
;
673 struct ir3_register
*src
;
675 mov
= ir3_instr_create(block
, 1, 0);
676 mov
->cat1
.src_type
= TYPE_U32
;
677 mov
->cat1
.dst_type
= TYPE_U32
;
678 ir3_reg_create(mov
, 0, 0);
679 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
680 src
->instr
= collect
;
684 ir3_instr_set_address(mov
, address
);
689 static struct ir3_instruction
*
690 create_indirect_store(struct ir3_compile
*ctx
, unsigned arrsz
, unsigned n
,
691 struct ir3_instruction
*src
, struct ir3_instruction
*address
,
692 struct ir3_instruction
*collect
)
694 struct ir3_block
*block
= ctx
->block
;
695 struct ir3_instruction
*mov
;
696 struct ir3_register
*dst
;
698 mov
= ir3_instr_create(block
, 1, 0);
699 mov
->cat1
.src_type
= TYPE_U32
;
700 mov
->cat1
.dst_type
= TYPE_U32
;
701 dst
= ir3_reg_create(mov
, 0, IR3_REG_RELATIV
);
704 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
705 mov
->fanin
= collect
;
707 ir3_instr_set_address(mov
, address
);
712 static struct ir3_instruction
*
713 create_input(struct ir3_block
*block
, unsigned n
)
715 struct ir3_instruction
*in
;
717 in
= ir3_instr_create(block
, -1, OPC_META_INPUT
);
718 in
->inout
.block
= block
;
719 ir3_reg_create(in
, n
, 0);
724 static struct ir3_instruction
*
725 create_frag_input(struct ir3_compile
*ctx
, unsigned n
, bool use_ldlv
)
727 struct ir3_block
*block
= ctx
->block
;
728 struct ir3_instruction
*instr
;
729 struct ir3_instruction
*inloc
= create_immed(block
, n
);
732 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
733 instr
->cat6
.type
= TYPE_U32
;
734 instr
->cat6
.iim_val
= 1;
736 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_pos
, 0);
737 instr
->regs
[2]->wrmask
= 0x3;
743 static struct ir3_instruction
*
744 create_frag_coord(struct ir3_compile
*ctx
, unsigned comp
)
746 struct ir3_block
*block
= ctx
->block
;
747 struct ir3_instruction
*instr
;
749 compile_assert(ctx
, !ctx
->frag_coord
[comp
]);
751 ctx
->frag_coord
[comp
] = create_input(ctx
->block
, 0);
756 /* for frag_coord, we get unsigned values.. we need
757 * to subtract (integer) 8 and divide by 16 (right-
758 * shift by 4) then convert to float:
762 * mov.u32f32 dst, tmp
765 instr
= ir3_SUB_S(block
, ctx
->frag_coord
[comp
], 0,
766 create_immed(block
, 8), 0);
767 instr
= ir3_SHR_B(block
, instr
, 0,
768 create_immed(block
, 4), 0);
769 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
775 /* seems that we can use these as-is: */
776 return ctx
->frag_coord
[comp
];
780 static struct ir3_instruction
*
781 create_frag_face(struct ir3_compile
*ctx
, unsigned comp
)
783 struct ir3_block
*block
= ctx
->block
;
784 struct ir3_instruction
*instr
;
788 compile_assert(ctx
, !ctx
->frag_face
);
790 ctx
->frag_face
= create_input(block
, 0);
791 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
793 /* for faceness, we always get -1 or 0 (int).. but TGSI expects
794 * positive vs negative float.. and piglit further seems to
795 * expect -1.0 or 1.0:
797 * mul.s tmp, hr0.x, 2
799 * mov.s32f32, dst, tmp
802 instr
= ir3_MUL_S(block
, ctx
->frag_face
, 0,
803 create_immed(block
, 2), 0);
804 instr
= ir3_ADD_S(block
, instr
, 0,
805 create_immed(block
, 1), 0);
806 instr
= ir3_COV(block
, instr
, TYPE_S32
, TYPE_F32
);
811 return create_immed(block
, fui(0.0));
814 return create_immed(block
, fui(1.0));
818 static struct ir3_instruction
*
819 create_driver_param(struct ir3_compile
*ctx
, enum ir3_driver_param dp
)
821 /* first four vec4 sysval's reserved for UBOs: */
822 /* NOTE: dp is in scalar, but there can be >4 dp components: */
823 unsigned n
= ctx
->so
->first_driver_param
+ IR3_DRIVER_PARAM_OFF
;
824 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
825 return create_uniform(ctx
, r
);
828 /* helper for instructions that produce multiple consecutive scalar
829 * outputs which need to have a split/fanout meta instruction inserted
832 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
833 struct ir3_instruction
*src
, unsigned n
)
835 struct ir3_instruction
*prev
= NULL
;
836 for (int i
= 0, j
= 0; i
< n
; i
++) {
837 struct ir3_instruction
*split
=
838 ir3_instr_create(block
, -1, OPC_META_FO
);
839 ir3_reg_create(split
, 0, IR3_REG_SSA
);
840 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
844 split
->cp
.left
= prev
;
845 split
->cp
.left_cnt
++;
846 prev
->cp
.right
= split
;
847 prev
->cp
.right_cnt
++;
851 if (src
->regs
[0]->wrmask
& (1 << i
))
857 * Adreno uses uint rather than having dedicated bool type,
858 * which (potentially) requires some conversion, in particular
859 * when using output of an bool instr to int input, or visa
863 * -------+---------+-------+-
867 * To convert from an adreno bool (uint) to nir, use:
869 * absneg.s dst, (neg)src
871 * To convert back in the other direction:
873 * absneg.s dst, (abs)arc
875 * The CP step can clean up the absneg.s that cancel each other
876 * out, and with a slight bit of extra cleverness (to recognize
877 * the instructions which produce either a 0 or 1) can eliminate
878 * the absneg.s's completely when an instruction that wants
879 * 0/1 consumes the result. For example, when a nir 'bcsel'
880 * consumes the result of 'feq'. So we should be able to get by
881 * without a boolean resolve step, and without incuring any
882 * extra penalty in instruction count.
885 /* NIR bool -> native (adreno): */
886 static struct ir3_instruction
*
887 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
889 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
892 /* native (adreno) -> NIR bool: */
893 static struct ir3_instruction
*
894 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
896 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
900 * alu/sfu instructions:
904 emit_alu(struct ir3_compile
*ctx
, nir_alu_instr
*alu
)
906 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
907 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
908 struct ir3_block
*b
= ctx
->block
;
910 dst
= get_dst(ctx
, &alu
->dest
.dest
, MAX2(info
->output_size
, 1));
912 /* Vectors are special in that they have non-scalarized writemasks,
913 * and just take the first swizzle channel for each argument in
914 * order into each writemask channel.
916 if ((alu
->op
== nir_op_vec2
) ||
917 (alu
->op
== nir_op_vec3
) ||
918 (alu
->op
== nir_op_vec4
)) {
920 for (int i
= 0; i
< info
->num_inputs
; i
++) {
921 nir_alu_src
*asrc
= &alu
->src
[i
];
923 compile_assert(ctx
, !asrc
->abs
);
924 compile_assert(ctx
, !asrc
->negate
);
926 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
928 src
[i
] = create_immed(ctx
->block
, 0);
929 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
935 /* General case: We can just grab the one used channel per src. */
936 for (int i
= 0; i
< info
->num_inputs
; i
++) {
937 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
938 nir_alu_src
*asrc
= &alu
->src
[i
];
940 compile_assert(ctx
, !asrc
->abs
);
941 compile_assert(ctx
, !asrc
->negate
);
943 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
945 compile_assert(ctx
, src
[i
]);
950 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_S32
);
953 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_U32
);
956 dst
[0] = ir3_COV(b
, src
[0], TYPE_S32
, TYPE_F32
);
959 dst
[0] = ir3_COV(b
, src
[0], TYPE_U32
, TYPE_F32
);
962 dst
[0] = ir3_MOV(b
, src
[0], TYPE_S32
);
965 dst
[0] = ir3_MOV(b
, src
[0], TYPE_F32
);
968 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
969 dst
[0]->cat2
.condition
= IR3_COND_NE
;
970 dst
[0] = ir3_n2b(b
, dst
[0]);
973 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
976 dst
[0] = ir3_b2n(b
, src
[0]);
979 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
980 dst
[0]->cat2
.condition
= IR3_COND_NE
;
981 dst
[0] = ir3_n2b(b
, dst
[0]);
985 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
988 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
991 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
994 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
997 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
1000 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
1003 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
1006 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
1009 dst
[0] = ir3_DSX(b
, src
[0], 0);
1010 dst
[0]->cat5
.type
= TYPE_F32
;
1013 dst
[0] = ir3_DSY(b
, src
[0], 0);
1014 dst
[0]->cat5
.type
= TYPE_F32
;
1018 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1019 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1020 dst
[0] = ir3_n2b(b
, dst
[0]);
1023 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1024 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1025 dst
[0] = ir3_n2b(b
, dst
[0]);
1028 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1029 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1030 dst
[0] = ir3_n2b(b
, dst
[0]);
1033 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1034 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1035 dst
[0] = ir3_n2b(b
, dst
[0]);
1038 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
1041 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
1044 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
1046 case nir_op_fround_even
:
1047 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
1050 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
1054 dst
[0] = ir3_SIN(b
, src
[0], 0);
1057 dst
[0] = ir3_COS(b
, src
[0], 0);
1060 dst
[0] = ir3_RSQ(b
, src
[0], 0);
1063 dst
[0] = ir3_RCP(b
, src
[0], 0);
1066 dst
[0] = ir3_LOG2(b
, src
[0], 0);
1069 dst
[0] = ir3_EXP2(b
, src
[0], 0);
1072 dst
[0] = ir3_SQRT(b
, src
[0], 0);
1076 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
1079 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
1082 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
1085 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
1088 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
1091 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
1094 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
1098 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
1099 * mull.u tmp0, a, b ; mul low, i.e. al * bl
1100 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
1101 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
1103 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
1104 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
1105 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
1108 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
1111 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
1114 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
1117 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
1120 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
1122 case nir_op_isign
: {
1123 /* maybe this would be sane to lower in nir.. */
1124 struct ir3_instruction
*neg
, *pos
;
1126 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1127 neg
->cat2
.condition
= IR3_COND_LT
;
1129 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1130 pos
->cat2
.condition
= IR3_COND_GT
;
1132 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
1137 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
1140 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
1143 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
1146 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1147 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1148 dst
[0] = ir3_n2b(b
, dst
[0]);
1151 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1152 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1153 dst
[0] = ir3_n2b(b
, dst
[0]);
1156 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1157 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1158 dst
[0] = ir3_n2b(b
, dst
[0]);
1161 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1162 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1163 dst
[0] = ir3_n2b(b
, dst
[0]);
1166 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1167 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1168 dst
[0] = ir3_n2b(b
, dst
[0]);
1171 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1172 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1173 dst
[0] = ir3_n2b(b
, dst
[0]);
1177 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, ir3_b2n(b
, src
[0]), 0, src
[2], 0);
1180 case nir_op_bit_count
:
1181 dst
[0] = ir3_CBITS_B(b
, src
[0], 0);
1183 case nir_op_ifind_msb
: {
1184 struct ir3_instruction
*cmp
;
1185 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
1186 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
1187 cmp
->cat2
.condition
= IR3_COND_GE
;
1188 dst
[0] = ir3_SEL_B32(b
,
1189 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1193 case nir_op_ufind_msb
:
1194 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
1195 dst
[0] = ir3_SEL_B32(b
,
1196 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1197 src
[0], 0, dst
[0], 0);
1199 case nir_op_find_lsb
:
1200 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1201 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
1203 case nir_op_bitfield_reverse
:
1204 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1208 compile_error(ctx
, "Unhandled ALU op: %s\n",
1209 nir_op_infos
[alu
->op
].name
);
1214 /* handles direct/indirect UBO reads: */
1216 emit_intrinsic_load_ubo(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1217 struct ir3_instruction
**dst
)
1219 struct ir3_block
*b
= ctx
->block
;
1220 struct ir3_instruction
*addr
, *src0
, *src1
;
1221 /* UBO addresses are the first driver params: */
1222 unsigned ubo
= regid(ctx
->so
->first_driver_param
+ IR3_UBOS_OFF
, 0);
1223 unsigned off
= intr
->const_index
[0];
1225 /* First src is ubo index, which could either be an immed or not: */
1226 src0
= get_src(ctx
, &intr
->src
[0])[0];
1227 if (is_same_type_mov(src0
) &&
1228 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1229 addr
= create_uniform(ctx
, ubo
+ src0
->regs
[1]->iim_val
);
1231 addr
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
));
1234 if (intr
->intrinsic
== nir_intrinsic_load_ubo_indirect
) {
1235 /* For load_ubo_indirect, second src is indirect offset: */
1236 src1
= get_src(ctx
, &intr
->src
[1])[0];
1238 /* and add offset to addr: */
1239 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1242 /* if offset is to large to encode in the ldg, split it out: */
1243 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1244 /* split out the minimal amount to improve the odds that
1245 * cp can fit the immediate in the add.s instruction:
1247 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1248 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1252 for (int i
= 0; i
< intr
->num_components
; i
++) {
1253 struct ir3_instruction
*load
=
1254 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1255 load
->cat6
.type
= TYPE_U32
;
1256 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
1261 /* handles array reads: */
1263 emit_intrinisic_load_var(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1264 struct ir3_instruction
**dst
)
1266 nir_deref_var
*dvar
= intr
->variables
[0];
1267 nir_deref_array
*darr
= nir_deref_as_array(dvar
->deref
.child
);
1268 struct ir3_array_value
*arr
= get_var(ctx
, dvar
->var
);
1270 compile_assert(ctx
, dvar
->deref
.child
&&
1271 (dvar
->deref
.child
->deref_type
== nir_deref_type_array
));
1273 switch (darr
->deref_array_type
) {
1274 case nir_deref_array_type_direct
:
1275 /* direct access does not require anything special: */
1276 for (int i
= 0; i
< intr
->num_components
; i
++) {
1277 unsigned n
= darr
->base_offset
* 4 + i
;
1278 compile_assert(ctx
, n
< arr
->length
);
1279 dst
[i
] = arr
->arr
[n
];
1282 case nir_deref_array_type_indirect
: {
1283 /* for indirect, we need to collect all the array elements: */
1284 struct ir3_instruction
*collect
=
1285 create_collect(ctx
->block
, arr
->arr
, arr
->length
);
1286 struct ir3_instruction
*addr
=
1287 get_addr(ctx
, get_src(ctx
, &darr
->indirect
)[0]);
1288 for (int i
= 0; i
< intr
->num_components
; i
++) {
1289 unsigned n
= darr
->base_offset
* 4 + i
;
1290 compile_assert(ctx
, n
< arr
->length
);
1291 dst
[i
] = create_indirect_load(ctx
, arr
->length
, n
, addr
, collect
);
1296 compile_error(ctx
, "Unhandled load deref type: %u\n",
1297 darr
->deref_array_type
);
1302 /* handles array writes: */
1304 emit_intrinisic_store_var(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1306 nir_deref_var
*dvar
= intr
->variables
[0];
1307 nir_deref_array
*darr
= nir_deref_as_array(dvar
->deref
.child
);
1308 struct ir3_array_value
*arr
= get_var(ctx
, dvar
->var
);
1309 struct ir3_instruction
**src
;
1311 compile_assert(ctx
, dvar
->deref
.child
&&
1312 (dvar
->deref
.child
->deref_type
== nir_deref_type_array
));
1314 src
= get_src(ctx
, &intr
->src
[0]);
1316 switch (darr
->deref_array_type
) {
1317 case nir_deref_array_type_direct
:
1318 /* direct access does not require anything special: */
1319 for (int i
= 0; i
< intr
->num_components
; i
++) {
1320 unsigned n
= darr
->base_offset
* 4 + i
;
1321 compile_assert(ctx
, n
< arr
->length
);
1322 arr
->arr
[n
] = src
[i
];
1325 case nir_deref_array_type_indirect
: {
1326 /* for indirect, create indirect-store and fan that out: */
1327 struct ir3_instruction
*collect
=
1328 create_collect(ctx
->block
, arr
->arr
, arr
->length
);
1329 struct ir3_instruction
*addr
=
1330 get_addr(ctx
, get_src(ctx
, &darr
->indirect
)[0]);
1331 for (int i
= 0; i
< intr
->num_components
; i
++) {
1332 struct ir3_instruction
*store
;
1333 unsigned n
= darr
->base_offset
* 4 + i
;
1334 compile_assert(ctx
, n
< arr
->length
);
1336 store
= create_indirect_store(ctx
, arr
->length
,
1337 n
, src
[i
], addr
, collect
);
1339 store
->fanin
->fi
.aid
= arr
->aid
;
1341 /* TODO: probably split this out to be used for
1342 * store_output_indirect? or move this into
1343 * create_indirect_store()?
1345 for (int j
= i
; j
< arr
->length
; j
+= intr
->num_components
) {
1346 struct ir3_instruction
*split
;
1348 split
= ir3_instr_create(ctx
->block
, -1, OPC_META_FO
);
1350 ir3_reg_create(split
, 0, 0);
1351 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= store
;
1353 arr
->arr
[j
] = split
;
1356 /* fixup fanout/split neighbors: */
1357 for (int i
= 0; i
< arr
->length
; i
++) {
1358 arr
->arr
[i
]->cp
.right
= (i
< (arr
->length
- 1)) ?
1359 arr
->arr
[i
+1] : NULL
;
1360 arr
->arr
[i
]->cp
.left
= (i
> 0) ?
1361 arr
->arr
[i
-1] : NULL
;
1366 compile_error(ctx
, "Unhandled store deref type: %u\n",
1367 darr
->deref_array_type
);
1372 static void add_sysval_input(struct ir3_compile
*ctx
, gl_system_value slot
,
1373 struct ir3_instruction
*instr
)
1375 struct ir3_shader_variant
*so
= ctx
->so
;
1376 unsigned r
= regid(so
->inputs_count
, 0);
1377 unsigned n
= so
->inputs_count
++;
1379 so
->inputs
[n
].sysval
= true;
1380 so
->inputs
[n
].slot
= slot
;
1381 so
->inputs
[n
].compmask
= 1;
1382 so
->inputs
[n
].regid
= r
;
1383 so
->inputs
[n
].interpolate
= INTERP_QUALIFIER_FLAT
;
1386 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
1387 ctx
->ir
->inputs
[r
] = instr
;
1391 emit_intrinisic(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1393 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1394 struct ir3_instruction
**dst
, **src
;
1395 struct ir3_block
*b
= ctx
->block
;
1396 unsigned idx
= intr
->const_index
[0];
1398 if (info
->has_dest
) {
1399 dst
= get_dst(ctx
, &intr
->dest
, intr
->num_components
);
1404 switch (intr
->intrinsic
) {
1405 case nir_intrinsic_load_uniform
:
1406 for (int i
= 0; i
< intr
->num_components
; i
++) {
1407 unsigned n
= idx
* 4 + i
;
1408 dst
[i
] = create_uniform(ctx
, n
);
1411 case nir_intrinsic_load_uniform_indirect
:
1412 src
= get_src(ctx
, &intr
->src
[0]);
1413 for (int i
= 0; i
< intr
->num_components
; i
++) {
1414 unsigned n
= idx
* 4 + i
;
1415 dst
[i
] = create_uniform_indirect(ctx
, n
,
1416 get_addr(ctx
, src
[0]));
1418 /* NOTE: if relative addressing is used, we set constlen in
1419 * the compiler (to worst-case value) since we don't know in
1420 * the assembler what the max addr reg value can be:
1422 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
1424 case nir_intrinsic_load_ubo
:
1425 case nir_intrinsic_load_ubo_indirect
:
1426 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1428 case nir_intrinsic_load_input
:
1429 for (int i
= 0; i
< intr
->num_components
; i
++) {
1430 unsigned n
= idx
* 4 + i
;
1431 dst
[i
] = ctx
->ir
->inputs
[n
];
1434 case nir_intrinsic_load_input_indirect
:
1435 src
= get_src(ctx
, &intr
->src
[0]);
1436 struct ir3_instruction
*collect
=
1437 create_collect(b
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
1438 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0]);
1439 for (int i
= 0; i
< intr
->num_components
; i
++) {
1440 unsigned n
= idx
* 4 + i
;
1441 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
1445 case nir_intrinsic_load_var
:
1446 emit_intrinisic_load_var(ctx
, intr
, dst
);
1448 case nir_intrinsic_store_var
:
1449 emit_intrinisic_store_var(ctx
, intr
);
1451 case nir_intrinsic_store_output
:
1452 src
= get_src(ctx
, &intr
->src
[0]);
1453 for (int i
= 0; i
< intr
->num_components
; i
++) {
1454 unsigned n
= idx
* 4 + i
;
1455 ctx
->ir
->outputs
[n
] = src
[i
];
1458 case nir_intrinsic_load_base_vertex
:
1459 if (!ctx
->basevertex
) {
1460 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
1461 add_sysval_input(ctx
, SYSTEM_VALUE_BASE_VERTEX
,
1464 dst
[0] = ctx
->basevertex
;
1466 case nir_intrinsic_load_vertex_id_zero_base
:
1467 if (!ctx
->vertex_id
) {
1468 ctx
->vertex_id
= create_input(ctx
->block
, 0);
1469 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
,
1472 dst
[0] = ctx
->vertex_id
;
1474 case nir_intrinsic_load_instance_id
:
1475 if (!ctx
->instance_id
) {
1476 ctx
->instance_id
= create_input(ctx
->block
, 0);
1477 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
1480 dst
[0] = ctx
->instance_id
;
1482 case nir_intrinsic_load_user_clip_plane
:
1483 for (int i
= 0; i
< intr
->num_components
; i
++) {
1484 unsigned n
= idx
* 4 + i
;
1485 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
1488 case nir_intrinsic_discard_if
:
1489 case nir_intrinsic_discard
: {
1490 struct ir3_instruction
*cond
, *kill
;
1492 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
1493 /* conditional discard: */
1494 src
= get_src(ctx
, &intr
->src
[0]);
1495 cond
= ir3_b2n(b
, src
[0]);
1497 /* unconditional discard: */
1498 cond
= create_immed(b
, 1);
1501 /* NOTE: only cmps.*.* can write p0.x: */
1502 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1503 cond
->cat2
.condition
= IR3_COND_NE
;
1505 /* condition always goes in predicate register: */
1506 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1508 kill
= ir3_KILL(b
, cond
, 0);
1509 array_insert(ctx
->ir
->predicates
, kill
);
1511 array_insert(ctx
->ir
->keeps
, kill
);
1512 ctx
->so
->has_kill
= true;
1517 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
1518 nir_intrinsic_infos
[intr
->intrinsic
].name
);
1524 emit_load_const(struct ir3_compile
*ctx
, nir_load_const_instr
*instr
)
1526 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
1527 instr
->def
.num_components
);
1528 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1529 dst
[i
] = create_immed(ctx
->block
, instr
->value
.u
[i
]);
1533 emit_undef(struct ir3_compile
*ctx
, nir_ssa_undef_instr
*undef
)
1535 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
1536 undef
->def
.num_components
);
1537 /* backend doesn't want undefined instructions, so just plug
1540 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
1541 dst
[i
] = create_immed(ctx
->block
, fui(0.0));
1545 * texture fetch/sample instructions:
1549 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
1551 unsigned coords
, flags
= 0;
1553 /* note: would use tex->coord_components.. except txs.. also,
1554 * since array index goes after shadow ref, we don't want to
1557 switch (tex
->sampler_dim
) {
1558 case GLSL_SAMPLER_DIM_1D
:
1559 case GLSL_SAMPLER_DIM_BUF
:
1562 case GLSL_SAMPLER_DIM_2D
:
1563 case GLSL_SAMPLER_DIM_RECT
:
1564 case GLSL_SAMPLER_DIM_EXTERNAL
:
1565 case GLSL_SAMPLER_DIM_MS
:
1568 case GLSL_SAMPLER_DIM_3D
:
1569 case GLSL_SAMPLER_DIM_CUBE
:
1571 flags
|= IR3_INSTR_3D
;
1574 unreachable("bad sampler_dim");
1577 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1578 flags
|= IR3_INSTR_S
;
1580 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
1581 flags
|= IR3_INSTR_A
;
1588 emit_tex(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1590 struct ir3_block
*b
= ctx
->block
;
1591 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
1592 struct ir3_instruction
**coord
, *lod
, *compare
, *proj
, **off
, **ddx
, **ddy
;
1593 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
1594 unsigned i
, coords
, flags
;
1595 unsigned nsrc0
= 0, nsrc1
= 0;
1599 coord
= off
= ddx
= ddy
= NULL
;
1600 lod
= proj
= compare
= NULL
;
1602 /* TODO: might just be one component for gathers? */
1603 dst
= get_dst(ctx
, &tex
->dest
, 4);
1605 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
1606 switch (tex
->src
[i
].src_type
) {
1607 case nir_tex_src_coord
:
1608 coord
= get_src(ctx
, &tex
->src
[i
].src
);
1610 case nir_tex_src_bias
:
1611 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1614 case nir_tex_src_lod
:
1615 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1618 case nir_tex_src_comparitor
: /* shadow comparator */
1619 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1621 case nir_tex_src_projector
:
1622 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1625 case nir_tex_src_offset
:
1626 off
= get_src(ctx
, &tex
->src
[i
].src
);
1629 case nir_tex_src_ddx
:
1630 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
1632 case nir_tex_src_ddy
:
1633 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
1636 compile_error(ctx
, "Unhandled NIR tex serc type: %d\n",
1637 tex
->src
[i
].src_type
);
1643 case nir_texop_tex
: opc
= OPC_SAM
; break;
1644 case nir_texop_txb
: opc
= OPC_SAMB
; break;
1645 case nir_texop_txl
: opc
= OPC_SAML
; break;
1646 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
1647 case nir_texop_txf
: opc
= OPC_ISAML
; break;
1648 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
1649 case nir_texop_txf_ms
:
1652 case nir_texop_query_levels
:
1653 case nir_texop_texture_samples
:
1654 case nir_texop_samples_identical
:
1655 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
1659 tex_info(tex
, &flags
, &coords
);
1661 /* scale up integer coords for TXF based on the LOD */
1662 if (ctx
->unminify_coords
&& (opc
== OPC_ISAML
)) {
1664 for (i
= 0; i
< coords
; i
++)
1665 coord
[i
] = ir3_SHL_B(b
, coord
[i
], 0, lod
, 0);
1668 /* the array coord for cube arrays needs 0.5 added to it */
1669 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& tex
->is_array
&&
1671 coord
[3] = ir3_ADD_F(b
, coord
[3], 0, create_immed(b
, fui(0.5)), 0);
1674 * lay out the first argument in the proper order:
1675 * - actual coordinates first
1676 * - shadow reference
1679 * - starting at offset 4, dpdx.xy, dpdy.xy
1681 * bias/lod go into the second arg
1684 /* insert tex coords: */
1685 for (i
= 0; i
< coords
; i
++)
1686 src0
[nsrc0
++] = coord
[i
];
1689 /* hw doesn't do 1d, so we treat it as 2d with
1690 * height of 1, and patch up the y coord.
1691 * TODO: y coord should be (int)0 in some cases..
1693 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
1696 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1697 src0
[nsrc0
++] = compare
;
1699 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
1700 src0
[nsrc0
++] = coord
[coords
];
1703 src0
[nsrc0
++] = proj
;
1704 flags
|= IR3_INSTR_P
;
1707 /* pad to 4, then ddx/ddy: */
1708 if (tex
->op
== nir_texop_txd
) {
1710 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1711 for (i
= 0; i
< coords
; i
++)
1712 src0
[nsrc0
++] = ddx
[i
];
1714 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1715 for (i
= 0; i
< coords
; i
++)
1716 src0
[nsrc0
++] = ddy
[i
];
1718 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1722 * second argument (if applicable):
1727 if (has_off
| has_lod
| has_bias
) {
1729 for (i
= 0; i
< coords
; i
++)
1730 src1
[nsrc1
++] = off
[i
];
1732 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
1733 flags
|= IR3_INSTR_O
;
1736 if (has_lod
| has_bias
)
1737 src1
[nsrc1
++] = lod
;
1740 switch (tex
->dest_type
) {
1741 case nir_type_invalid
:
1742 case nir_type_float
:
1753 unreachable("bad dest_type");
1756 if (opc
== OPC_GETLOD
)
1759 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
,
1760 flags
, tex
->sampler_index
, tex
->sampler_index
,
1761 create_collect(b
, src0
, nsrc0
),
1762 create_collect(b
, src1
, nsrc1
));
1764 split_dest(b
, dst
, sam
, 4);
1766 /* GETLOD returns results in 4.8 fixed point */
1767 if (opc
== OPC_GETLOD
) {
1768 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
1770 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
1771 for (i
= 0; i
< 2; i
++) {
1772 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_U32
, TYPE_F32
), 0,
1779 emit_tex_query_levels(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1781 struct ir3_block
*b
= ctx
->block
;
1782 struct ir3_instruction
**dst
, *sam
;
1784 dst
= get_dst(ctx
, &tex
->dest
, 1);
1786 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
1787 tex
->sampler_index
, tex
->sampler_index
, NULL
, NULL
);
1789 /* even though there is only one component, since it ends
1790 * up in .z rather than .x, we need a split_dest()
1792 split_dest(b
, dst
, sam
, 3);
1794 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1795 * the value in TEX_CONST_0 is zero-based.
1797 if (ctx
->levels_add_one
)
1798 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
1802 emit_tex_txs(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1804 struct ir3_block
*b
= ctx
->block
;
1805 struct ir3_instruction
**dst
, *sam
, *lod
;
1806 unsigned flags
, coords
;
1808 tex_info(tex
, &flags
, &coords
);
1810 /* Actually we want the number of dimensions, not coordinates. This
1811 * distinction only matters for cubes.
1813 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
1816 dst
= get_dst(ctx
, &tex
->dest
, 4);
1818 compile_assert(ctx
, tex
->num_srcs
== 1);
1819 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
1821 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
1823 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
1824 tex
->sampler_index
, tex
->sampler_index
, lod
, NULL
);
1826 split_dest(b
, dst
, sam
, 4);
1828 /* Array size actually ends up in .w rather than .z. This doesn't
1829 * matter for miplevel 0, but for higher mips the value in z is
1830 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1831 * returned, which means that we have to add 1 to it for arrays.
1833 if (tex
->is_array
) {
1834 if (ctx
->levels_add_one
) {
1835 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
1837 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
1843 emit_phi(struct ir3_compile
*ctx
, nir_phi_instr
*nphi
)
1845 struct ir3_instruction
*phi
, **dst
;
1847 /* NOTE: phi's should be lowered to scalar at this point */
1848 compile_assert(ctx
, nphi
->dest
.ssa
.num_components
== 1);
1850 dst
= get_dst(ctx
, &nphi
->dest
, 1);
1852 phi
= ir3_instr_create2(ctx
->block
, -1, OPC_META_PHI
,
1853 1 + exec_list_length(&nphi
->srcs
));
1854 ir3_reg_create(phi
, 0, 0); /* dst */
1855 phi
->phi
.nphi
= nphi
;
1860 /* phi instructions are left partially constructed. We don't resolve
1861 * their srcs until the end of the block, since (eg. loops) one of
1862 * the phi's srcs might be defined after the phi due to back edges in
1866 resolve_phis(struct ir3_compile
*ctx
, struct ir3_block
*block
)
1868 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
1869 nir_phi_instr
*nphi
;
1871 /* phi's only come at start of block: */
1872 if (!(is_meta(instr
) && (instr
->opc
== OPC_META_PHI
)))
1875 if (!instr
->phi
.nphi
)
1878 nphi
= instr
->phi
.nphi
;
1879 instr
->phi
.nphi
= NULL
;
1881 foreach_list_typed(nir_phi_src
, nsrc
, node
, &nphi
->srcs
) {
1882 struct ir3_instruction
*src
= get_src(ctx
, &nsrc
->src
)[0];
1883 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
1887 resolve_array_phis(ctx
, block
);
1891 emit_jump(struct ir3_compile
*ctx
, nir_jump_instr
*jump
)
1893 switch (jump
->type
) {
1894 case nir_jump_break
:
1895 case nir_jump_continue
:
1896 /* I *think* we can simply just ignore this, and use the
1897 * successor block link to figure out where we need to
1898 * jump to for break/continue
1902 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
1908 emit_instr(struct ir3_compile
*ctx
, nir_instr
*instr
)
1910 switch (instr
->type
) {
1911 case nir_instr_type_alu
:
1912 emit_alu(ctx
, nir_instr_as_alu(instr
));
1914 case nir_instr_type_intrinsic
:
1915 emit_intrinisic(ctx
, nir_instr_as_intrinsic(instr
));
1917 case nir_instr_type_load_const
:
1918 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1920 case nir_instr_type_ssa_undef
:
1921 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
1923 case nir_instr_type_tex
: {
1924 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
1925 /* couple tex instructions get special-cased:
1929 emit_tex_txs(ctx
, tex
);
1931 case nir_texop_query_levels
:
1932 emit_tex_query_levels(ctx
, tex
);
1934 case nir_texop_samples_identical
:
1935 unreachable("nir_texop_samples_identical");
1942 case nir_instr_type_phi
:
1943 emit_phi(ctx
, nir_instr_as_phi(instr
));
1945 case nir_instr_type_jump
:
1946 emit_jump(ctx
, nir_instr_as_jump(instr
));
1948 case nir_instr_type_call
:
1949 case nir_instr_type_parallel_copy
:
1950 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
1955 static struct ir3_block
*
1956 get_block(struct ir3_compile
*ctx
, nir_block
*nblock
)
1958 struct ir3_block
*block
;
1959 struct hash_entry
*entry
;
1960 entry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
1964 block
= ir3_block_create(ctx
->ir
);
1965 block
->nblock
= nblock
;
1966 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
1972 emit_block(struct ir3_compile
*ctx
, nir_block
*nblock
)
1974 struct ir3_block
*block
= get_block(ctx
, nblock
);
1976 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
1977 if (nblock
->successors
[i
]) {
1978 block
->successors
[i
] =
1979 get_block(ctx
, nblock
->successors
[i
]);
1984 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
1986 nir_foreach_instr(nblock
, instr
) {
1987 emit_instr(ctx
, instr
);
1993 static void emit_cf_list(struct ir3_compile
*ctx
, struct exec_list
*list
);
1996 emit_if(struct ir3_compile
*ctx
, nir_if
*nif
)
1998 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
2000 ctx
->block
->condition
=
2001 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
2003 emit_cf_list(ctx
, &nif
->then_list
);
2004 emit_cf_list(ctx
, &nif
->else_list
);
2008 emit_loop(struct ir3_compile
*ctx
, nir_loop
*nloop
)
2010 emit_cf_list(ctx
, &nloop
->body
);
2014 emit_cf_list(struct ir3_compile
*ctx
, struct exec_list
*list
)
2016 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2017 switch (node
->type
) {
2018 case nir_cf_node_block
:
2019 emit_block(ctx
, nir_cf_node_as_block(node
));
2021 case nir_cf_node_if
:
2022 emit_if(ctx
, nir_cf_node_as_if(node
));
2024 case nir_cf_node_loop
:
2025 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2027 case nir_cf_node_function
:
2028 compile_error(ctx
, "TODO\n");
2034 /* emit stream-out code. At this point, the current block is the original
2035 * (nir) end block, and nir ensures that all flow control paths terminate
2036 * into the end block. We re-purpose the original end block to generate
2037 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2038 * block holding stream-out write instructions, followed by the new end
2042 * p0.x = (vtxcnt < maxvtxcnt)
2043 * // succs: blockStreamOut, blockNewEnd
2046 * ... stream-out instructions ...
2047 * // succs: blockNewEnd
2053 emit_stream_out(struct ir3_compile
*ctx
)
2055 struct ir3_shader_variant
*v
= ctx
->so
;
2056 struct ir3
*ir
= ctx
->ir
;
2057 struct pipe_stream_output_info
*strmout
=
2058 &ctx
->so
->shader
->stream_output
;
2059 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
2060 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
2061 struct ir3_instruction
*bases
[PIPE_MAX_SO_BUFFERS
];
2063 /* create vtxcnt input in input block at top of shader,
2064 * so that it is seen as live over the entire duration
2067 vtxcnt
= create_input(ctx
->in_block
, 0);
2068 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
2070 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
2072 /* at this point, we are at the original 'end' block,
2073 * re-purpose this block to stream-out condition, then
2074 * append stream-out block and new-end block
2076 orig_end_block
= ctx
->block
;
2078 stream_out_block
= ir3_block_create(ir
);
2079 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
2081 new_end_block
= ir3_block_create(ir
);
2082 list_addtail(&new_end_block
->node
, &ir
->block_list
);
2084 orig_end_block
->successors
[0] = stream_out_block
;
2085 orig_end_block
->successors
[1] = new_end_block
;
2086 stream_out_block
->successors
[0] = new_end_block
;
2088 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2089 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
2090 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2091 cond
->cat2
.condition
= IR3_COND_LT
;
2093 /* condition goes on previous block to the conditional,
2094 * since it is used to pick which of the two successor
2097 orig_end_block
->condition
= cond
;
2099 /* switch to stream_out_block to generate the stream-out
2102 ctx
->block
= stream_out_block
;
2104 /* Calculate base addresses based on vtxcnt. Instructions
2105 * generated for bases not used in following loop will be
2106 * stripped out in the backend.
2108 for (unsigned i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
2109 unsigned stride
= strmout
->stride
[i
];
2110 struct ir3_instruction
*base
, *off
;
2112 base
= create_uniform(ctx
, regid(v
->first_driver_param
+ IR3_TFBOS_OFF
, i
));
2114 /* 24-bit should be enough: */
2115 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
2116 create_immed(ctx
->block
, stride
* 4), 0);
2118 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
2121 /* Generate the per-output store instructions: */
2122 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
2123 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
2124 unsigned c
= j
+ strmout
->output
[i
].start_component
;
2125 struct ir3_instruction
*base
, *out
, *stg
;
2127 base
= bases
[strmout
->output
[i
].output_buffer
];
2128 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
2130 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
2131 create_immed(ctx
->block
, 1), 0);
2132 stg
->cat6
.type
= TYPE_U32
;
2133 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
2135 array_insert(ctx
->ir
->keeps
, stg
);
2139 /* and finally switch to the new_end_block: */
2140 ctx
->block
= new_end_block
;
2144 emit_function(struct ir3_compile
*ctx
, nir_function_impl
*impl
)
2146 emit_cf_list(ctx
, &impl
->body
);
2147 emit_block(ctx
, impl
->end_block
);
2149 /* at this point, we should have a single empty block,
2150 * into which we emit the 'end' instruction.
2152 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
2154 /* If stream-out (aka transform-feedback) enabled, emit the
2155 * stream-out instructions, followed by a new empty block (into
2156 * which the 'end' instruction lands).
2158 * NOTE: it is done in this order, rather than inserting before
2159 * we emit end_block, because NIR guarantees that all blocks
2160 * flow into end_block, and that end_block has no successors.
2161 * So by re-purposing end_block as the first block of stream-
2162 * out, we guarantee that all exit paths flow into the stream-
2165 if ((ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
2166 !ctx
->so
->key
.binning_pass
) {
2167 debug_assert(ctx
->so
->type
== SHADER_VERTEX
);
2168 emit_stream_out(ctx
);
2171 ir3_END(ctx
->block
);
2175 setup_input(struct ir3_compile
*ctx
, nir_variable
*in
)
2177 struct ir3_shader_variant
*so
= ctx
->so
;
2178 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
2179 unsigned ncomp
= glsl_get_components(in
->type
);
2180 unsigned n
= in
->data
.driver_location
;
2181 unsigned slot
= in
->data
.location
;
2183 DBG("; in: slot=%u, len=%ux%u, drvloc=%u",
2184 slot
, array_len
, ncomp
, n
);
2186 so
->inputs
[n
].slot
= slot
;
2187 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
2188 so
->inputs
[n
].inloc
= ctx
->next_inloc
;
2189 so
->inputs
[n
].interpolate
= INTERP_QUALIFIER_NONE
;
2190 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2191 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
2193 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2194 for (int i
= 0; i
< ncomp
; i
++) {
2195 struct ir3_instruction
*instr
= NULL
;
2196 unsigned idx
= (n
* 4) + i
;
2198 if (slot
== VARYING_SLOT_POS
) {
2199 so
->inputs
[n
].bary
= false;
2200 so
->frag_coord
= true;
2201 instr
= create_frag_coord(ctx
, i
);
2202 } else if (slot
== VARYING_SLOT_FACE
) {
2203 so
->inputs
[n
].bary
= false;
2204 so
->frag_face
= true;
2205 instr
= create_frag_face(ctx
, i
);
2207 bool use_ldlv
= false;
2209 /* detect the special case for front/back colors where
2210 * we need to do flat vs smooth shading depending on
2213 if (in
->data
.interpolation
== INTERP_QUALIFIER_NONE
) {
2215 case VARYING_SLOT_COL0
:
2216 case VARYING_SLOT_COL1
:
2217 case VARYING_SLOT_BFC0
:
2218 case VARYING_SLOT_BFC1
:
2219 so
->inputs
[n
].rasterflat
= true;
2226 if (ctx
->flat_bypass
) {
2227 if ((so
->inputs
[n
].interpolate
== INTERP_QUALIFIER_FLAT
) ||
2228 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
2232 so
->inputs
[n
].bary
= true;
2234 instr
= create_frag_input(ctx
,
2235 so
->inputs
[n
].inloc
+ i
- 8, use_ldlv
);
2238 ctx
->ir
->inputs
[idx
] = instr
;
2240 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2241 for (int i
= 0; i
< ncomp
; i
++) {
2242 unsigned idx
= (n
* 4) + i
;
2243 ctx
->ir
->inputs
[idx
] = create_input(ctx
->block
, idx
);
2246 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2249 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
2250 ctx
->next_inloc
+= ncomp
;
2251 so
->total_in
+= ncomp
;
2256 setup_output(struct ir3_compile
*ctx
, nir_variable
*out
)
2258 struct ir3_shader_variant
*so
= ctx
->so
;
2259 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
2260 unsigned ncomp
= glsl_get_components(out
->type
);
2261 unsigned n
= out
->data
.driver_location
;
2262 unsigned slot
= out
->data
.location
;
2265 DBG("; out: slot=%u, len=%ux%u, drvloc=%u",
2266 slot
, array_len
, ncomp
, n
);
2268 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2270 case FRAG_RESULT_DEPTH
:
2271 comp
= 2; /* tgsi will write to .z component */
2272 so
->writes_pos
= true;
2274 case FRAG_RESULT_COLOR
:
2278 if (slot
>= FRAG_RESULT_DATA0
)
2280 compile_error(ctx
, "unknown FS output name: %s\n",
2281 gl_frag_result_name(slot
));
2283 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2285 case VARYING_SLOT_POS
:
2286 so
->writes_pos
= true;
2288 case VARYING_SLOT_PSIZ
:
2289 so
->writes_psize
= true;
2291 case VARYING_SLOT_COL0
:
2292 case VARYING_SLOT_COL1
:
2293 case VARYING_SLOT_BFC0
:
2294 case VARYING_SLOT_BFC1
:
2295 case VARYING_SLOT_FOGC
:
2296 case VARYING_SLOT_CLIP_DIST0
:
2297 case VARYING_SLOT_CLIP_DIST1
:
2300 if (slot
>= VARYING_SLOT_VAR0
)
2302 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
2304 compile_error(ctx
, "unknown VS output name: %s\n",
2305 gl_varying_slot_name(slot
));
2308 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2311 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
2313 so
->outputs
[n
].slot
= slot
;
2314 so
->outputs
[n
].regid
= regid(n
, comp
);
2315 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
2317 for (int i
= 0; i
< ncomp
; i
++) {
2318 unsigned idx
= (n
* 4) + i
;
2320 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
2325 emit_instructions(struct ir3_compile
*ctx
)
2327 unsigned ninputs
, noutputs
;
2328 nir_function_impl
*fxn
= NULL
;
2330 /* Find the main function: */
2331 nir_foreach_overload(ctx
->s
, overload
) {
2332 compile_assert(ctx
, strcmp(overload
->function
->name
, "main") == 0);
2333 compile_assert(ctx
, overload
->impl
);
2334 fxn
= overload
->impl
;
2338 ninputs
= exec_list_length(&ctx
->s
->inputs
) * 4;
2339 noutputs
= exec_list_length(&ctx
->s
->outputs
) * 4;
2341 /* or vtx shaders, we need to leave room for sysvals:
2343 if (ctx
->so
->type
== SHADER_VERTEX
) {
2347 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
2349 /* Create inputs in first block: */
2350 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
2351 ctx
->in_block
= ctx
->block
;
2352 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
2354 if (ctx
->so
->type
== SHADER_VERTEX
) {
2355 ctx
->ir
->ninputs
-= 8;
2358 /* for fragment shader, we have a single input register (usually
2359 * r0.xy) which is used as the base for bary.f varying fetch instrs:
2361 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2362 // TODO maybe a helper for fi since we need it a few places..
2363 struct ir3_instruction
*instr
;
2364 instr
= ir3_instr_create(ctx
->block
, -1, OPC_META_FI
);
2365 ir3_reg_create(instr
, 0, 0);
2366 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.x */
2367 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.y */
2368 ctx
->frag_pos
= instr
;
2372 nir_foreach_variable(var
, &ctx
->s
->inputs
) {
2373 setup_input(ctx
, var
);
2376 /* Setup outputs: */
2377 nir_foreach_variable(var
, &ctx
->s
->outputs
) {
2378 setup_output(ctx
, var
);
2381 /* Setup variables (which should only be arrays): */
2382 nir_foreach_variable(var
, &ctx
->s
->globals
) {
2383 declare_var(ctx
, var
);
2386 /* And emit the body: */
2388 emit_function(ctx
, fxn
);
2390 list_for_each_entry (struct ir3_block
, block
, &ctx
->ir
->block_list
, node
) {
2391 resolve_phis(ctx
, block
);
2395 /* from NIR perspective, we actually have inputs. But most of the "inputs"
2396 * for a fragment shader are just bary.f instructions. The *actual* inputs
2397 * from the hw perspective are the frag_pos and optionally frag_coord and
2401 fixup_frag_inputs(struct ir3_compile
*ctx
)
2403 struct ir3_shader_variant
*so
= ctx
->so
;
2404 struct ir3
*ir
= ctx
->ir
;
2405 struct ir3_instruction
**inputs
;
2406 struct ir3_instruction
*instr
;
2411 n
= 4; /* always have frag_pos */
2412 n
+= COND(so
->frag_face
, 4);
2413 n
+= COND(so
->frag_coord
, 4);
2415 inputs
= ir3_alloc(ctx
->ir
, n
* (sizeof(struct ir3_instruction
*)));
2417 if (so
->frag_face
) {
2418 /* this ultimately gets assigned to hr0.x so doesn't conflict
2419 * with frag_coord/frag_pos..
2421 inputs
[ir
->ninputs
++] = ctx
->frag_face
;
2422 ctx
->frag_face
->regs
[0]->num
= 0;
2424 /* remaining channels not used, but let's avoid confusing
2425 * other parts that expect inputs to come in groups of vec4
2427 inputs
[ir
->ninputs
++] = NULL
;
2428 inputs
[ir
->ninputs
++] = NULL
;
2429 inputs
[ir
->ninputs
++] = NULL
;
2432 /* since we don't know where to set the regid for frag_coord,
2433 * we have to use r0.x for it. But we don't want to *always*
2434 * use r1.x for frag_pos as that could increase the register
2435 * footprint on simple shaders:
2437 if (so
->frag_coord
) {
2438 ctx
->frag_coord
[0]->regs
[0]->num
= regid
++;
2439 ctx
->frag_coord
[1]->regs
[0]->num
= regid
++;
2440 ctx
->frag_coord
[2]->regs
[0]->num
= regid
++;
2441 ctx
->frag_coord
[3]->regs
[0]->num
= regid
++;
2443 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[0];
2444 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[1];
2445 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[2];
2446 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[3];
2449 /* we always have frag_pos: */
2450 so
->pos_regid
= regid
;
2453 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2454 instr
->regs
[0]->num
= regid
++;
2455 inputs
[ir
->ninputs
++] = instr
;
2456 ctx
->frag_pos
->regs
[1]->instr
= instr
;
2459 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2460 instr
->regs
[0]->num
= regid
++;
2461 inputs
[ir
->ninputs
++] = instr
;
2462 ctx
->frag_pos
->regs
[2]->instr
= instr
;
2464 ir
->inputs
= inputs
;
2468 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
2469 struct ir3_shader_variant
*so
)
2471 struct ir3_compile
*ctx
;
2473 struct ir3_instruction
**inputs
;
2474 unsigned i
, j
, actual_in
;
2475 int ret
= 0, max_bary
;
2479 ctx
= compile_init(compiler
, so
, so
->shader
->tokens
);
2481 DBG("INIT failed!");
2486 emit_instructions(ctx
);
2489 DBG("EMIT failed!");
2494 ir
= so
->ir
= ctx
->ir
;
2496 /* keep track of the inputs from TGSI perspective.. */
2497 inputs
= ir
->inputs
;
2499 /* but fixup actual inputs for frag shader: */
2500 if (so
->type
== SHADER_FRAGMENT
)
2501 fixup_frag_inputs(ctx
);
2503 /* at this point, for binning pass, throw away unneeded outputs: */
2504 if (so
->key
.binning_pass
) {
2505 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
2506 unsigned slot
= so
->outputs
[i
].slot
;
2508 /* throw away everything but first position/psize */
2509 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
2511 so
->outputs
[j
] = so
->outputs
[i
];
2512 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
2513 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
2514 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
2515 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
2520 so
->outputs_count
= j
;
2521 ir
->noutputs
= j
* 4;
2524 /* if we want half-precision outputs, mark the output registers
2527 if (so
->key
.half_precision
) {
2528 for (i
= 0; i
< ir
->noutputs
; i
++) {
2529 struct ir3_instruction
*out
= ir
->outputs
[i
];
2532 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2533 /* output could be a fanout (ie. texture fetch output)
2534 * in which case we need to propagate the half-reg flag
2535 * up to the definer so that RA sees it:
2537 if (is_meta(out
) && (out
->opc
== OPC_META_FO
)) {
2538 out
= out
->regs
[1]->instr
;
2539 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2542 if (out
->category
== 1) {
2543 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
2548 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2549 printf("BEFORE CP:\n");
2555 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2556 printf("BEFORE GROUPING:\n");
2560 /* Group left/right neighbors, inserting mov's where needed to
2567 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2568 printf("AFTER DEPTH:\n");
2572 ret
= ir3_sched(ir
);
2574 DBG("SCHED failed!");
2578 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2579 printf("AFTER SCHED:\n");
2583 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
2589 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2590 printf("AFTER RA:\n");
2594 ir3_legalize(ir
, &so
->has_samp
, &max_bary
);
2596 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2597 printf("AFTER LEGALIZE:\n");
2601 /* fixup input/outputs: */
2602 for (i
= 0; i
< so
->outputs_count
; i
++) {
2603 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
2604 /* preserve hack for depth output.. tgsi writes depth to .z,
2605 * but what we give the hw is the scalar register:
2607 if ((so
->type
== SHADER_FRAGMENT
) &&
2608 (so
->outputs
[i
].slot
== FRAG_RESULT_DEPTH
))
2609 so
->outputs
[i
].regid
+= 2;
2612 /* Note that some or all channels of an input may be unused: */
2614 for (i
= 0; i
< so
->inputs_count
; i
++) {
2615 unsigned j
, regid
= ~0, compmask
= 0;
2616 so
->inputs
[i
].ncomp
= 0;
2617 for (j
= 0; j
< 4; j
++) {
2618 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
2620 compmask
|= (1 << j
);
2621 regid
= in
->regs
[0]->num
- j
;
2623 so
->inputs
[i
].ncomp
++;
2626 so
->inputs
[i
].regid
= regid
;
2627 so
->inputs
[i
].compmask
= compmask
;
2630 /* fragment shader always gets full vec4's even if it doesn't
2631 * fetch all components, but vertex shader we need to update
2632 * with the actual number of components fetch, otherwise thing
2633 * will hang due to mismaptch between VFD_DECODE's and
2636 if (so
->type
== SHADER_VERTEX
)
2637 so
->total_in
= actual_in
;
2639 so
->total_in
= align(max_bary
+ 1, 4);
2644 ir3_destroy(so
->ir
);