1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
36 #include "freedreno_util.h"
38 #include "ir3_compiler.h"
39 #include "ir3_shader.h"
42 #include "instr-a3xx.h"
47 struct ir3_compiler
*compiler
;
52 struct ir3_shader_variant
*so
;
54 struct ir3_block
*block
; /* the current block */
55 struct ir3_block
*in_block
; /* block created for shader inputs */
57 nir_function_impl
*impl
;
59 /* For fragment shaders, from the hw perspective the only
60 * actual input is r0.xy position register passed to bary.f.
61 * But TGSI doesn't know that, it still declares things as
62 * IN[] registers. So we do all the input tracking normally
63 * and fix things up after compile_instructions()
65 * NOTE that frag_pos is the hardware position (possibly it
66 * is actually an index or tag or some such.. it is *not*
67 * values that can be directly used for gl_FragCoord..)
69 struct ir3_instruction
*frag_pos
, *frag_face
, *frag_coord
[4];
71 /* For vertex shaders, keep track of the system values sources */
72 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
74 /* mapping from nir_register to defining instruction: */
75 struct hash_table
*def_ht
;
77 /* mapping from nir_variable to ir3_array: */
78 struct hash_table
*var_ht
;
81 /* a common pattern for indirect addressing is to request the
82 * same address register multiple times. To avoid generating
83 * duplicate instruction sequences (which our backend does not
84 * try to clean up, since that should be done as the NIR stage)
85 * we cache the address value generated for a given src value:
87 struct hash_table
*addr_ht
;
89 /* maps nir_block to ir3_block, mostly for the purposes of
90 * figuring out the blocks successors
92 struct hash_table
*block_ht
;
94 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
95 * so we need to use ldlv.u32 to load the varying directly:
99 /* on a3xx, we need to add one to # of array levels:
103 /* on a3xx, we need to scale up integer coords for isaml based
106 bool unminify_coords
;
108 /* for looking up which system value is which */
109 unsigned sysval_semantics
[8];
111 /* set if we encounter something we can't handle yet, so we
112 * can bail cleanly and fallback to TGSI compiler f/e
118 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
119 static struct ir3_block
* get_block(struct ir3_compile
*ctx
, nir_block
*nblock
);
122 static struct ir3_compile
*
123 compile_init(struct ir3_compiler
*compiler
,
124 struct ir3_shader_variant
*so
)
126 struct ir3_compile
*ctx
= rzalloc(NULL
, struct ir3_compile
);
128 if (compiler
->gpu_id
>= 400) {
129 /* need special handling for "flat" */
130 ctx
->flat_bypass
= true;
131 ctx
->levels_add_one
= false;
132 ctx
->unminify_coords
= false;
134 /* no special handling for "flat" */
135 ctx
->flat_bypass
= false;
136 ctx
->levels_add_one
= true;
137 ctx
->unminify_coords
= true;
140 ctx
->compiler
= compiler
;
143 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
144 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
145 ctx
->var_ht
= _mesa_hash_table_create(ctx
,
146 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
147 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
148 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
150 /* TODO: maybe generate some sort of bitmask of what key
151 * lowers vs what shader has (ie. no need to lower
152 * texture clamp lowering if no texture sample instrs)..
153 * although should be done further up the stack to avoid
154 * creating duplicate variants..
157 if (ir3_key_lowers_nir(&so
->key
)) {
158 nir_shader
*s
= nir_shader_clone(ctx
, so
->shader
->nir
);
159 ctx
->s
= ir3_optimize_nir(so
->shader
, s
, &so
->key
);
161 /* fast-path for shader key that lowers nothing in NIR: */
162 ctx
->s
= so
->shader
->nir
;
165 if (fd_mesa_debug
& FD_DBG_DISASM
) {
166 DBG("dump nir%dv%d: type=%d, k={bp=%u,cts=%u,hp=%u}",
167 so
->shader
->id
, so
->id
, so
->type
,
168 so
->key
.binning_pass
, so
->key
.color_two_side
,
169 so
->key
.half_precision
);
170 nir_print_shader(ctx
->s
, stdout
);
173 so
->first_driver_param
= so
->first_immediate
= ctx
->s
->num_uniforms
;
175 /* Layout of constant registers:
177 * num_uniform * vec4 - user consts
178 * 4 * vec4 - UBO addresses
179 * if (vertex shader) {
180 * N * vec4 - driver params (IR3_DP_*)
181 * 1 * vec4 - stream-out addresses
184 * TODO this could be made more dynamic, to at least skip sections
185 * that we don't need..
188 /* reserve 4 (vec4) slots for ubo base addresses: */
189 so
->first_immediate
+= 4;
191 if (so
->type
== SHADER_VERTEX
) {
192 /* driver params (see ir3_driver_param): */
193 so
->first_immediate
+= IR3_DP_COUNT
/4; /* convert to vec4 */
194 /* one (vec4) slot for stream-output base addresses: */
195 so
->first_immediate
++;
202 compile_error(struct ir3_compile
*ctx
, const char *format
, ...)
205 va_start(ap
, format
);
206 _debug_vprintf(format
, ap
);
208 nir_print_shader(ctx
->s
, stdout
);
213 #define compile_assert(ctx, cond) do { \
214 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
218 compile_free(struct ir3_compile
*ctx
)
223 /* global per-array information: */
225 unsigned length
, aid
;
228 /* per-block array state: */
229 struct ir3_array_value
{
230 /* TODO drop length/aid, and just have ptr back to ir3_array */
231 unsigned length
, aid
;
232 /* initial array element values are phi's, other than for the
233 * entry block. The phi src's get added later in a resolve step
234 * after we have visited all the blocks, to account for back
237 struct ir3_instruction
**phis
;
238 /* current array element values (as block is processed). When
239 * the array phi's are resolved, it will contain the array state
240 * at exit of block, so successor blocks can use it to add their
243 struct ir3_instruction
*arr
[];
246 /* track array assignments per basic block. When an array is read
247 * outside of the same basic block, we can use NIR's dominance-frontier
248 * information to figure out where phi nodes are needed.
250 struct ir3_nir_block_data
{
252 /* indexed by array-id (aid): */
253 struct ir3_array_value
*arrs
[];
256 static struct ir3_nir_block_data
*
257 get_block_data(struct ir3_compile
*ctx
, struct ir3_block
*block
)
260 struct ir3_nir_block_data
*bd
= ralloc_size(ctx
, sizeof(*bd
) +
261 ((ctx
->num_arrays
+ 1) * sizeof(bd
->arrs
[0])));
268 declare_var(struct ir3_compile
*ctx
, nir_variable
*var
)
270 unsigned length
= glsl_get_length(var
->type
) * 4; /* always vec4, at least with ttn */
271 struct ir3_array
*arr
= ralloc(ctx
, struct ir3_array
);
272 arr
->length
= length
;
273 arr
->aid
= ++ctx
->num_arrays
;
274 _mesa_hash_table_insert(ctx
->var_ht
, var
, arr
);
278 nir_block_pred(nir_block
*block
)
280 assert(block
->predecessors
->entries
< 2);
281 if (block
->predecessors
->entries
== 0)
283 return (nir_block
*)_mesa_set_next_entry(block
->predecessors
, NULL
)->key
;
286 static struct ir3_array_value
*
287 get_var(struct ir3_compile
*ctx
, nir_variable
*var
)
289 struct hash_entry
*entry
= _mesa_hash_table_search(ctx
->var_ht
, var
);
290 struct ir3_block
*block
= ctx
->block
;
291 struct ir3_nir_block_data
*bd
= get_block_data(ctx
, block
);
292 struct ir3_array
*arr
= entry
->data
;
294 if (!bd
->arrs
[arr
->aid
]) {
295 struct ir3_array_value
*av
= ralloc_size(bd
, sizeof(*av
) +
296 (arr
->length
* sizeof(av
->arr
[0])));
297 struct ir3_array_value
*defn
= NULL
;
298 nir_block
*pred_block
;
300 av
->length
= arr
->length
;
303 /* For loops, we have to consider that we have not visited some
304 * of the blocks who should feed into the phi (ie. back-edges in
305 * the cfg).. for example:
308 * block { load_var; ... }
309 * if then block {} else block {}
310 * block { store_var; ... }
311 * if then block {} else block {}
315 * We can skip the phi if we can chase the block predecessors
316 * until finding the block previously defining the array without
317 * crossing a block that has more than one predecessor.
319 * Otherwise create phi's and resolve them as a post-pass after
320 * all the blocks have been visited (to handle back-edges).
323 for (pred_block
= block
->nblock
;
324 pred_block
&& (pred_block
->predecessors
->entries
< 2) && !defn
;
325 pred_block
= nir_block_pred(pred_block
)) {
326 struct ir3_block
*pblock
= get_block(ctx
, pred_block
);
327 struct ir3_nir_block_data
*pbd
= pblock
->data
;
330 defn
= pbd
->arrs
[arr
->aid
];
334 /* only one possible definer: */
335 for (unsigned i
= 0; i
< arr
->length
; i
++)
336 av
->arr
[i
] = defn
->arr
[i
];
337 } else if (pred_block
) {
338 /* not the first block, and multiple potential definers: */
339 av
->phis
= ralloc_size(av
, arr
->length
* sizeof(av
->phis
[0]));
341 for (unsigned i
= 0; i
< arr
->length
; i
++) {
342 struct ir3_instruction
*phi
;
344 phi
= ir3_instr_create2(block
, -1, OPC_META_PHI
,
345 1 + ctx
->impl
->num_blocks
);
346 ir3_reg_create(phi
, 0, 0); /* dst */
348 /* phi's should go at head of block: */
349 list_delinit(&phi
->node
);
350 list_add(&phi
->node
, &block
->instr_list
);
352 av
->phis
[i
] = av
->arr
[i
] = phi
;
355 /* Some shaders end up reading array elements without
356 * first writing.. so initialize things to prevent null
359 for (unsigned i
= 0; i
< arr
->length
; i
++)
360 av
->arr
[i
] = create_immed(block
, 0);
363 bd
->arrs
[arr
->aid
] = av
;
366 return bd
->arrs
[arr
->aid
];
370 add_array_phi_srcs(struct ir3_compile
*ctx
, nir_block
*nblock
,
371 struct ir3_array_value
*av
, BITSET_WORD
*visited
)
373 struct ir3_block
*block
;
374 struct ir3_nir_block_data
*bd
;
376 if (BITSET_TEST(visited
, nblock
->index
))
379 BITSET_SET(visited
, nblock
->index
);
381 block
= get_block(ctx
, nblock
);
384 if (bd
&& bd
->arrs
[av
->aid
]) {
385 struct ir3_array_value
*dav
= bd
->arrs
[av
->aid
];
386 for (unsigned i
= 0; i
< av
->length
; i
++) {
387 ir3_reg_create(av
->phis
[i
], 0, IR3_REG_SSA
)->instr
=
391 /* didn't find defn, recurse predecessors: */
392 struct set_entry
*entry
;
393 set_foreach(nblock
->predecessors
, entry
) {
394 add_array_phi_srcs(ctx
, (nir_block
*)entry
->key
, av
, visited
);
400 resolve_array_phis(struct ir3_compile
*ctx
, struct ir3_block
*block
)
402 struct ir3_nir_block_data
*bd
= block
->data
;
403 unsigned bitset_words
= BITSET_WORDS(ctx
->impl
->num_blocks
);
408 /* TODO use nir dom_frontier to help us with this? */
410 for (unsigned i
= 1; i
<= ctx
->num_arrays
; i
++) {
411 struct ir3_array_value
*av
= bd
->arrs
[i
];
412 BITSET_WORD visited
[bitset_words
];
413 struct set_entry
*entry
;
415 if (!(av
&& av
->phis
))
418 memset(visited
, 0, sizeof(visited
));
419 set_foreach(block
->nblock
->predecessors
, entry
) {
420 add_array_phi_srcs(ctx
, (nir_block
*)entry
->key
, av
, visited
);
425 /* allocate a n element value array (to be populated by caller) and
428 static struct ir3_instruction
**
429 __get_dst(struct ir3_compile
*ctx
, void *key
, unsigned n
)
431 struct ir3_instruction
**value
=
432 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
433 _mesa_hash_table_insert(ctx
->def_ht
, key
, value
);
437 static struct ir3_instruction
**
438 get_dst(struct ir3_compile
*ctx
, nir_dest
*dst
, unsigned n
)
441 return __get_dst(ctx
, &dst
->ssa
, n
);
443 return __get_dst(ctx
, dst
->reg
.reg
, n
);
447 static struct ir3_instruction
**
448 get_dst_ssa(struct ir3_compile
*ctx
, nir_ssa_def
*dst
, unsigned n
)
450 return __get_dst(ctx
, dst
, n
);
453 static struct ir3_instruction
**
454 get_src(struct ir3_compile
*ctx
, nir_src
*src
)
456 struct hash_entry
*entry
;
458 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
460 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->reg
.reg
);
462 compile_assert(ctx
, entry
);
466 static struct ir3_instruction
*
467 create_immed(struct ir3_block
*block
, uint32_t val
)
469 struct ir3_instruction
*mov
;
471 mov
= ir3_instr_create(block
, 1, 0);
472 mov
->cat1
.src_type
= TYPE_U32
;
473 mov
->cat1
.dst_type
= TYPE_U32
;
474 ir3_reg_create(mov
, 0, 0);
475 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
480 static struct ir3_instruction
*
481 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
)
483 struct ir3_instruction
*instr
, *immed
;
485 /* TODO in at least some cases, the backend could probably be
486 * made clever enough to propagate IR3_REG_HALF..
488 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
489 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
491 immed
= create_immed(block
, 2);
492 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
494 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
495 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
496 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
498 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
499 instr
->regs
[0]->num
= regid(REG_A0
, 0);
500 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
501 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
506 /* caches addr values to avoid generating multiple cov/shl/mova
507 * sequences for each use of a given NIR level src as address
509 static struct ir3_instruction
*
510 get_addr(struct ir3_compile
*ctx
, struct ir3_instruction
*src
)
512 struct ir3_instruction
*addr
;
515 ctx
->addr_ht
= _mesa_hash_table_create(ctx
,
516 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
518 struct hash_entry
*entry
;
519 entry
= _mesa_hash_table_search(ctx
->addr_ht
, src
);
524 addr
= create_addr(ctx
->block
, src
);
525 _mesa_hash_table_insert(ctx
->addr_ht
, src
, addr
);
530 static struct ir3_instruction
*
531 get_predicate(struct ir3_compile
*ctx
, struct ir3_instruction
*src
)
533 struct ir3_block
*b
= ctx
->block
;
534 struct ir3_instruction
*cond
;
536 /* NOTE: only cmps.*.* can write p0.x: */
537 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
538 cond
->cat2
.condition
= IR3_COND_NE
;
540 /* condition always goes in predicate register: */
541 cond
->regs
[0]->num
= regid(REG_P0
, 0);
546 static struct ir3_instruction
*
547 create_uniform(struct ir3_compile
*ctx
, unsigned n
)
549 struct ir3_instruction
*mov
;
551 mov
= ir3_instr_create(ctx
->block
, 1, 0);
552 /* TODO get types right? */
553 mov
->cat1
.src_type
= TYPE_F32
;
554 mov
->cat1
.dst_type
= TYPE_F32
;
555 ir3_reg_create(mov
, 0, 0);
556 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
561 static struct ir3_instruction
*
562 create_uniform_indirect(struct ir3_compile
*ctx
, unsigned n
,
563 struct ir3_instruction
*address
)
565 struct ir3_instruction
*mov
;
567 mov
= ir3_instr_create(ctx
->block
, 1, 0);
568 mov
->cat1
.src_type
= TYPE_U32
;
569 mov
->cat1
.dst_type
= TYPE_U32
;
570 ir3_reg_create(mov
, 0, 0);
571 ir3_reg_create(mov
, n
, IR3_REG_CONST
| IR3_REG_RELATIV
);
573 ir3_instr_set_address(mov
, address
);
578 static struct ir3_instruction
*
579 create_collect(struct ir3_block
*block
, struct ir3_instruction
**arr
,
582 struct ir3_instruction
*collect
;
587 collect
= ir3_instr_create2(block
, -1, OPC_META_FI
, 1 + arrsz
);
588 ir3_reg_create(collect
, 0, 0); /* dst */
589 for (unsigned i
= 0; i
< arrsz
; i
++)
590 ir3_reg_create(collect
, 0, IR3_REG_SSA
)->instr
= arr
[i
];
595 static struct ir3_instruction
*
596 create_indirect_load(struct ir3_compile
*ctx
, unsigned arrsz
, unsigned n
,
597 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
599 struct ir3_block
*block
= ctx
->block
;
600 struct ir3_instruction
*mov
;
601 struct ir3_register
*src
;
603 mov
= ir3_instr_create(block
, 1, 0);
604 mov
->cat1
.src_type
= TYPE_U32
;
605 mov
->cat1
.dst_type
= TYPE_U32
;
606 ir3_reg_create(mov
, 0, 0);
607 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
608 src
->instr
= collect
;
612 ir3_instr_set_address(mov
, address
);
617 static struct ir3_instruction
*
618 create_indirect_store(struct ir3_compile
*ctx
, unsigned arrsz
, unsigned n
,
619 struct ir3_instruction
*src
, struct ir3_instruction
*address
,
620 struct ir3_instruction
*collect
)
622 struct ir3_block
*block
= ctx
->block
;
623 struct ir3_instruction
*mov
;
624 struct ir3_register
*dst
;
626 mov
= ir3_instr_create(block
, 1, 0);
627 mov
->cat1
.src_type
= TYPE_U32
;
628 mov
->cat1
.dst_type
= TYPE_U32
;
629 dst
= ir3_reg_create(mov
, 0, IR3_REG_RELATIV
);
632 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
633 mov
->fanin
= collect
;
635 ir3_instr_set_address(mov
, address
);
640 static struct ir3_instruction
*
641 create_input(struct ir3_block
*block
, unsigned n
)
643 struct ir3_instruction
*in
;
645 in
= ir3_instr_create(block
, -1, OPC_META_INPUT
);
646 in
->inout
.block
= block
;
647 ir3_reg_create(in
, n
, 0);
652 static struct ir3_instruction
*
653 create_frag_input(struct ir3_compile
*ctx
, bool use_ldlv
)
655 struct ir3_block
*block
= ctx
->block
;
656 struct ir3_instruction
*instr
;
657 /* actual inloc is assigned and fixed up later: */
658 struct ir3_instruction
*inloc
= create_immed(block
, 0);
661 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
662 instr
->cat6
.type
= TYPE_U32
;
663 instr
->cat6
.iim_val
= 1;
665 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_pos
, 0);
666 instr
->regs
[2]->wrmask
= 0x3;
672 static struct ir3_instruction
*
673 create_frag_coord(struct ir3_compile
*ctx
, unsigned comp
)
675 struct ir3_block
*block
= ctx
->block
;
676 struct ir3_instruction
*instr
;
678 compile_assert(ctx
, !ctx
->frag_coord
[comp
]);
680 ctx
->frag_coord
[comp
] = create_input(ctx
->block
, 0);
685 /* for frag_coord, we get unsigned values.. we need
686 * to subtract (integer) 8 and divide by 16 (right-
687 * shift by 4) then convert to float:
691 * mov.u32f32 dst, tmp
694 instr
= ir3_SUB_S(block
, ctx
->frag_coord
[comp
], 0,
695 create_immed(block
, 8), 0);
696 instr
= ir3_SHR_B(block
, instr
, 0,
697 create_immed(block
, 4), 0);
698 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
704 /* seems that we can use these as-is: */
705 return ctx
->frag_coord
[comp
];
709 static struct ir3_instruction
*
710 create_frag_face(struct ir3_compile
*ctx
, unsigned comp
)
712 struct ir3_block
*block
= ctx
->block
;
713 struct ir3_instruction
*instr
;
717 compile_assert(ctx
, !ctx
->frag_face
);
719 ctx
->frag_face
= create_input(block
, 0);
720 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
722 /* for faceness, we always get -1 or 0 (int).. but TGSI expects
723 * positive vs negative float.. and piglit further seems to
724 * expect -1.0 or 1.0:
726 * mul.s tmp, hr0.x, 2
728 * mov.s32f32, dst, tmp
731 instr
= ir3_MUL_S(block
, ctx
->frag_face
, 0,
732 create_immed(block
, 2), 0);
733 instr
= ir3_ADD_S(block
, instr
, 0,
734 create_immed(block
, 1), 0);
735 instr
= ir3_COV(block
, instr
, TYPE_S32
, TYPE_F32
);
740 return create_immed(block
, fui(0.0));
743 return create_immed(block
, fui(1.0));
747 static struct ir3_instruction
*
748 create_driver_param(struct ir3_compile
*ctx
, enum ir3_driver_param dp
)
750 /* first four vec4 sysval's reserved for UBOs: */
751 /* NOTE: dp is in scalar, but there can be >4 dp components: */
752 unsigned n
= ctx
->so
->first_driver_param
+ IR3_DRIVER_PARAM_OFF
;
753 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
754 return create_uniform(ctx
, r
);
757 /* helper for instructions that produce multiple consecutive scalar
758 * outputs which need to have a split/fanout meta instruction inserted
761 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
762 struct ir3_instruction
*src
, unsigned n
)
764 struct ir3_instruction
*prev
= NULL
;
765 for (int i
= 0, j
= 0; i
< n
; i
++) {
766 struct ir3_instruction
*split
=
767 ir3_instr_create(block
, -1, OPC_META_FO
);
768 ir3_reg_create(split
, 0, IR3_REG_SSA
);
769 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
773 split
->cp
.left
= prev
;
774 split
->cp
.left_cnt
++;
775 prev
->cp
.right
= split
;
776 prev
->cp
.right_cnt
++;
780 if (src
->regs
[0]->wrmask
& (1 << i
))
786 * Adreno uses uint rather than having dedicated bool type,
787 * which (potentially) requires some conversion, in particular
788 * when using output of an bool instr to int input, or visa
792 * -------+---------+-------+-
796 * To convert from an adreno bool (uint) to nir, use:
798 * absneg.s dst, (neg)src
800 * To convert back in the other direction:
802 * absneg.s dst, (abs)arc
804 * The CP step can clean up the absneg.s that cancel each other
805 * out, and with a slight bit of extra cleverness (to recognize
806 * the instructions which produce either a 0 or 1) can eliminate
807 * the absneg.s's completely when an instruction that wants
808 * 0/1 consumes the result. For example, when a nir 'bcsel'
809 * consumes the result of 'feq'. So we should be able to get by
810 * without a boolean resolve step, and without incuring any
811 * extra penalty in instruction count.
814 /* NIR bool -> native (adreno): */
815 static struct ir3_instruction
*
816 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
818 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
821 /* native (adreno) -> NIR bool: */
822 static struct ir3_instruction
*
823 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
825 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
829 * alu/sfu instructions:
833 emit_alu(struct ir3_compile
*ctx
, nir_alu_instr
*alu
)
835 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
836 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
837 struct ir3_block
*b
= ctx
->block
;
839 dst
= get_dst(ctx
, &alu
->dest
.dest
, MAX2(info
->output_size
, 1));
841 /* Vectors are special in that they have non-scalarized writemasks,
842 * and just take the first swizzle channel for each argument in
843 * order into each writemask channel.
845 if ((alu
->op
== nir_op_vec2
) ||
846 (alu
->op
== nir_op_vec3
) ||
847 (alu
->op
== nir_op_vec4
)) {
849 for (int i
= 0; i
< info
->num_inputs
; i
++) {
850 nir_alu_src
*asrc
= &alu
->src
[i
];
852 compile_assert(ctx
, !asrc
->abs
);
853 compile_assert(ctx
, !asrc
->negate
);
855 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
857 src
[i
] = create_immed(ctx
->block
, 0);
858 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
864 /* General case: We can just grab the one used channel per src. */
865 for (int i
= 0; i
< info
->num_inputs
; i
++) {
866 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
867 nir_alu_src
*asrc
= &alu
->src
[i
];
869 compile_assert(ctx
, !asrc
->abs
);
870 compile_assert(ctx
, !asrc
->negate
);
872 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
874 compile_assert(ctx
, src
[i
]);
879 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_S32
);
882 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_U32
);
885 dst
[0] = ir3_COV(b
, src
[0], TYPE_S32
, TYPE_F32
);
888 dst
[0] = ir3_COV(b
, src
[0], TYPE_U32
, TYPE_F32
);
891 dst
[0] = ir3_MOV(b
, src
[0], TYPE_S32
);
894 dst
[0] = ir3_MOV(b
, src
[0], TYPE_F32
);
897 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
898 dst
[0]->cat2
.condition
= IR3_COND_NE
;
899 dst
[0] = ir3_n2b(b
, dst
[0]);
902 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
905 dst
[0] = ir3_b2n(b
, src
[0]);
908 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
909 dst
[0]->cat2
.condition
= IR3_COND_NE
;
910 dst
[0] = ir3_n2b(b
, dst
[0]);
914 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
917 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
920 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
923 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
926 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
929 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
932 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
935 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
938 dst
[0] = ir3_DSX(b
, src
[0], 0);
939 dst
[0]->cat5
.type
= TYPE_F32
;
942 dst
[0] = ir3_DSY(b
, src
[0], 0);
943 dst
[0]->cat5
.type
= TYPE_F32
;
947 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
948 dst
[0]->cat2
.condition
= IR3_COND_LT
;
949 dst
[0] = ir3_n2b(b
, dst
[0]);
952 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
953 dst
[0]->cat2
.condition
= IR3_COND_GE
;
954 dst
[0] = ir3_n2b(b
, dst
[0]);
957 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
958 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
959 dst
[0] = ir3_n2b(b
, dst
[0]);
962 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
963 dst
[0]->cat2
.condition
= IR3_COND_NE
;
964 dst
[0] = ir3_n2b(b
, dst
[0]);
967 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
970 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
973 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
975 case nir_op_fround_even
:
976 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
979 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
983 dst
[0] = ir3_SIN(b
, src
[0], 0);
986 dst
[0] = ir3_COS(b
, src
[0], 0);
989 dst
[0] = ir3_RSQ(b
, src
[0], 0);
992 dst
[0] = ir3_RCP(b
, src
[0], 0);
995 dst
[0] = ir3_LOG2(b
, src
[0], 0);
998 dst
[0] = ir3_EXP2(b
, src
[0], 0);
1001 dst
[0] = ir3_SQRT(b
, src
[0], 0);
1005 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
1008 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
1011 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
1014 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
1017 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
1020 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
1023 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
1027 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
1028 * mull.u tmp0, a, b ; mul low, i.e. al * bl
1029 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
1030 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
1032 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
1033 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
1034 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
1037 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
1040 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
1043 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
1046 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
1049 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
1051 case nir_op_isign
: {
1052 /* maybe this would be sane to lower in nir.. */
1053 struct ir3_instruction
*neg
, *pos
;
1055 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1056 neg
->cat2
.condition
= IR3_COND_LT
;
1058 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1059 pos
->cat2
.condition
= IR3_COND_GT
;
1061 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
1066 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
1069 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
1072 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
1075 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1076 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1077 dst
[0] = ir3_n2b(b
, dst
[0]);
1080 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1081 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1082 dst
[0] = ir3_n2b(b
, dst
[0]);
1085 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1086 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1087 dst
[0] = ir3_n2b(b
, dst
[0]);
1090 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1091 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1092 dst
[0] = ir3_n2b(b
, dst
[0]);
1095 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1096 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1097 dst
[0] = ir3_n2b(b
, dst
[0]);
1100 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1101 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1102 dst
[0] = ir3_n2b(b
, dst
[0]);
1106 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, ir3_b2n(b
, src
[0]), 0, src
[2], 0);
1109 case nir_op_bit_count
:
1110 dst
[0] = ir3_CBITS_B(b
, src
[0], 0);
1112 case nir_op_ifind_msb
: {
1113 struct ir3_instruction
*cmp
;
1114 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
1115 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
1116 cmp
->cat2
.condition
= IR3_COND_GE
;
1117 dst
[0] = ir3_SEL_B32(b
,
1118 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1122 case nir_op_ufind_msb
:
1123 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
1124 dst
[0] = ir3_SEL_B32(b
,
1125 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1126 src
[0], 0, dst
[0], 0);
1128 case nir_op_find_lsb
:
1129 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1130 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
1132 case nir_op_bitfield_reverse
:
1133 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1137 compile_error(ctx
, "Unhandled ALU op: %s\n",
1138 nir_op_infos
[alu
->op
].name
);
1143 /* handles direct/indirect UBO reads: */
1145 emit_intrinsic_load_ubo(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1146 struct ir3_instruction
**dst
)
1148 struct ir3_block
*b
= ctx
->block
;
1149 struct ir3_instruction
*addr
, *src0
, *src1
;
1150 nir_const_value
*const_offset
;
1151 /* UBO addresses are the first driver params: */
1152 unsigned ubo
= regid(ctx
->so
->first_driver_param
+ IR3_UBOS_OFF
, 0);
1153 unsigned off
= intr
->const_index
[0];
1155 /* First src is ubo index, which could either be an immed or not: */
1156 src0
= get_src(ctx
, &intr
->src
[0])[0];
1157 if (is_same_type_mov(src0
) &&
1158 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1159 addr
= create_uniform(ctx
, ubo
+ src0
->regs
[1]->iim_val
);
1161 addr
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
));
1164 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1166 off
+= const_offset
->u
[0];
1168 /* For load_ubo_indirect, second src is indirect offset: */
1169 src1
= get_src(ctx
, &intr
->src
[1])[0];
1171 /* and add offset to addr: */
1172 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1175 /* if offset is to large to encode in the ldg, split it out: */
1176 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1177 /* split out the minimal amount to improve the odds that
1178 * cp can fit the immediate in the add.s instruction:
1180 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1181 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1185 for (int i
= 0; i
< intr
->num_components
; i
++) {
1186 struct ir3_instruction
*load
=
1187 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1188 load
->cat6
.type
= TYPE_U32
;
1189 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
1194 /* handles array reads: */
1196 emit_intrinsic_load_var(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1197 struct ir3_instruction
**dst
)
1199 nir_deref_var
*dvar
= intr
->variables
[0];
1200 nir_deref_array
*darr
= nir_deref_as_array(dvar
->deref
.child
);
1201 struct ir3_array_value
*arr
= get_var(ctx
, dvar
->var
);
1203 compile_assert(ctx
, dvar
->deref
.child
&&
1204 (dvar
->deref
.child
->deref_type
== nir_deref_type_array
));
1206 switch (darr
->deref_array_type
) {
1207 case nir_deref_array_type_direct
:
1208 /* direct access does not require anything special: */
1209 for (int i
= 0; i
< intr
->num_components
; i
++) {
1210 unsigned n
= darr
->base_offset
* 4 + i
;
1211 compile_assert(ctx
, n
< arr
->length
);
1212 dst
[i
] = arr
->arr
[n
];
1215 case nir_deref_array_type_indirect
: {
1216 /* for indirect, we need to collect all the array elements: */
1217 struct ir3_instruction
*collect
=
1218 create_collect(ctx
->block
, arr
->arr
, arr
->length
);
1219 struct ir3_instruction
*addr
=
1220 get_addr(ctx
, get_src(ctx
, &darr
->indirect
)[0]);
1221 for (int i
= 0; i
< intr
->num_components
; i
++) {
1222 unsigned n
= darr
->base_offset
* 4 + i
;
1223 compile_assert(ctx
, n
< arr
->length
);
1224 dst
[i
] = create_indirect_load(ctx
, arr
->length
, n
, addr
, collect
);
1229 compile_error(ctx
, "Unhandled load deref type: %u\n",
1230 darr
->deref_array_type
);
1235 /* handles array writes: */
1237 emit_intrinsic_store_var(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1239 nir_deref_var
*dvar
= intr
->variables
[0];
1240 nir_deref_array
*darr
= nir_deref_as_array(dvar
->deref
.child
);
1241 struct ir3_array_value
*arr
= get_var(ctx
, dvar
->var
);
1242 struct ir3_instruction
**src
;
1244 compile_assert(ctx
, dvar
->deref
.child
&&
1245 (dvar
->deref
.child
->deref_type
== nir_deref_type_array
));
1247 src
= get_src(ctx
, &intr
->src
[0]);
1249 switch (darr
->deref_array_type
) {
1250 case nir_deref_array_type_direct
:
1251 /* direct access does not require anything special: */
1252 for (int i
= 0; i
< intr
->num_components
; i
++) {
1253 /* ttn doesn't generate partial writemasks */
1254 assert(intr
->const_index
[0] ==
1255 (1 << intr
->num_components
) - 1);
1257 unsigned n
= darr
->base_offset
* 4 + i
;
1258 compile_assert(ctx
, n
< arr
->length
);
1259 arr
->arr
[n
] = src
[i
];
1262 case nir_deref_array_type_indirect
: {
1263 /* for indirect, create indirect-store and fan that out: */
1264 struct ir3_instruction
*collect
=
1265 create_collect(ctx
->block
, arr
->arr
, arr
->length
);
1266 struct ir3_instruction
*addr
=
1267 get_addr(ctx
, get_src(ctx
, &darr
->indirect
)[0]);
1268 for (int i
= 0; i
< intr
->num_components
; i
++) {
1269 /* ttn doesn't generate partial writemasks */
1270 assert(intr
->const_index
[0] ==
1271 (1 << intr
->num_components
) - 1);
1273 struct ir3_instruction
*store
;
1274 unsigned n
= darr
->base_offset
* 4 + i
;
1275 compile_assert(ctx
, n
< arr
->length
);
1277 store
= create_indirect_store(ctx
, arr
->length
,
1278 n
, src
[i
], addr
, collect
);
1280 store
->fanin
->fi
.aid
= arr
->aid
;
1282 /* TODO: probably split this out to be used for
1283 * store_output_indirect? or move this into
1284 * create_indirect_store()?
1286 for (int j
= i
; j
< arr
->length
; j
+= intr
->num_components
) {
1287 struct ir3_instruction
*split
;
1289 split
= ir3_instr_create(ctx
->block
, -1, OPC_META_FO
);
1291 ir3_reg_create(split
, 0, 0);
1292 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= store
;
1294 arr
->arr
[j
] = split
;
1297 /* fixup fanout/split neighbors: */
1298 for (int i
= 0; i
< arr
->length
; i
++) {
1299 arr
->arr
[i
]->cp
.right
= (i
< (arr
->length
- 1)) ?
1300 arr
->arr
[i
+1] : NULL
;
1301 arr
->arr
[i
]->cp
.left
= (i
> 0) ?
1302 arr
->arr
[i
-1] : NULL
;
1307 compile_error(ctx
, "Unhandled store deref type: %u\n",
1308 darr
->deref_array_type
);
1313 static void add_sysval_input(struct ir3_compile
*ctx
, gl_system_value slot
,
1314 struct ir3_instruction
*instr
)
1316 struct ir3_shader_variant
*so
= ctx
->so
;
1317 unsigned r
= regid(so
->inputs_count
, 0);
1318 unsigned n
= so
->inputs_count
++;
1320 so
->inputs
[n
].sysval
= true;
1321 so
->inputs
[n
].slot
= slot
;
1322 so
->inputs
[n
].compmask
= 1;
1323 so
->inputs
[n
].regid
= r
;
1324 so
->inputs
[n
].interpolate
= INTERP_QUALIFIER_FLAT
;
1327 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
1328 ctx
->ir
->inputs
[r
] = instr
;
1332 emit_intrinsic(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1334 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1335 struct ir3_instruction
**dst
, **src
;
1336 struct ir3_block
*b
= ctx
->block
;
1337 unsigned idx
= intr
->const_index
[0];
1338 nir_const_value
*const_offset
;
1340 if (info
->has_dest
) {
1341 dst
= get_dst(ctx
, &intr
->dest
, intr
->num_components
);
1346 switch (intr
->intrinsic
) {
1347 case nir_intrinsic_load_uniform
:
1348 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1350 idx
+= const_offset
->u
[0];
1351 for (int i
= 0; i
< intr
->num_components
; i
++) {
1352 unsigned n
= idx
* 4 + i
;
1353 dst
[i
] = create_uniform(ctx
, n
);
1356 src
= get_src(ctx
, &intr
->src
[0]);
1357 for (int i
= 0; i
< intr
->num_components
; i
++) {
1358 unsigned n
= idx
* 4 + i
;
1359 dst
[i
] = create_uniform_indirect(ctx
, n
,
1360 get_addr(ctx
, src
[0]));
1362 /* NOTE: if relative addressing is used, we set
1363 * constlen in the compiler (to worst-case value)
1364 * since we don't know in the assembler what the max
1365 * addr reg value can be:
1367 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
1370 case nir_intrinsic_load_ubo
:
1371 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1373 case nir_intrinsic_load_input
:
1374 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1376 idx
+= const_offset
->u
[0];
1377 for (int i
= 0; i
< intr
->num_components
; i
++) {
1378 unsigned n
= idx
* 4 + i
;
1379 dst
[i
] = ctx
->ir
->inputs
[n
];
1382 src
= get_src(ctx
, &intr
->src
[0]);
1383 struct ir3_instruction
*collect
=
1384 create_collect(b
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
1385 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0]);
1386 for (int i
= 0; i
< intr
->num_components
; i
++) {
1387 unsigned n
= idx
* 4 + i
;
1388 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
1393 case nir_intrinsic_load_var
:
1394 emit_intrinsic_load_var(ctx
, intr
, dst
);
1396 case nir_intrinsic_store_var
:
1397 emit_intrinsic_store_var(ctx
, intr
);
1399 case nir_intrinsic_store_output
:
1400 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1401 compile_assert(ctx
, const_offset
!= NULL
);
1402 idx
+= const_offset
->u
[0];
1404 src
= get_src(ctx
, &intr
->src
[0]);
1405 for (int i
= 0; i
< intr
->num_components
; i
++) {
1406 unsigned n
= idx
* 4 + i
;
1407 ctx
->ir
->outputs
[n
] = src
[i
];
1410 case nir_intrinsic_load_base_vertex
:
1411 if (!ctx
->basevertex
) {
1412 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
1413 add_sysval_input(ctx
, SYSTEM_VALUE_BASE_VERTEX
,
1416 dst
[0] = ctx
->basevertex
;
1418 case nir_intrinsic_load_vertex_id_zero_base
:
1419 if (!ctx
->vertex_id
) {
1420 ctx
->vertex_id
= create_input(ctx
->block
, 0);
1421 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
,
1424 dst
[0] = ctx
->vertex_id
;
1426 case nir_intrinsic_load_instance_id
:
1427 if (!ctx
->instance_id
) {
1428 ctx
->instance_id
= create_input(ctx
->block
, 0);
1429 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
1432 dst
[0] = ctx
->instance_id
;
1434 case nir_intrinsic_load_user_clip_plane
:
1435 for (int i
= 0; i
< intr
->num_components
; i
++) {
1436 unsigned n
= idx
* 4 + i
;
1437 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
1440 case nir_intrinsic_discard_if
:
1441 case nir_intrinsic_discard
: {
1442 struct ir3_instruction
*cond
, *kill
;
1444 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
1445 /* conditional discard: */
1446 src
= get_src(ctx
, &intr
->src
[0]);
1447 cond
= ir3_b2n(b
, src
[0]);
1449 /* unconditional discard: */
1450 cond
= create_immed(b
, 1);
1453 /* NOTE: only cmps.*.* can write p0.x: */
1454 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1455 cond
->cat2
.condition
= IR3_COND_NE
;
1457 /* condition always goes in predicate register: */
1458 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1460 kill
= ir3_KILL(b
, cond
, 0);
1461 array_insert(ctx
->ir
->predicates
, kill
);
1463 array_insert(ctx
->ir
->keeps
, kill
);
1464 ctx
->so
->has_kill
= true;
1469 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
1470 nir_intrinsic_infos
[intr
->intrinsic
].name
);
1476 emit_load_const(struct ir3_compile
*ctx
, nir_load_const_instr
*instr
)
1478 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
1479 instr
->def
.num_components
);
1480 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1481 dst
[i
] = create_immed(ctx
->block
, instr
->value
.u
[i
]);
1485 emit_undef(struct ir3_compile
*ctx
, nir_ssa_undef_instr
*undef
)
1487 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
1488 undef
->def
.num_components
);
1489 /* backend doesn't want undefined instructions, so just plug
1492 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
1493 dst
[i
] = create_immed(ctx
->block
, fui(0.0));
1497 * texture fetch/sample instructions:
1501 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
1503 unsigned coords
, flags
= 0;
1505 /* note: would use tex->coord_components.. except txs.. also,
1506 * since array index goes after shadow ref, we don't want to
1509 switch (tex
->sampler_dim
) {
1510 case GLSL_SAMPLER_DIM_1D
:
1511 case GLSL_SAMPLER_DIM_BUF
:
1514 case GLSL_SAMPLER_DIM_2D
:
1515 case GLSL_SAMPLER_DIM_RECT
:
1516 case GLSL_SAMPLER_DIM_EXTERNAL
:
1517 case GLSL_SAMPLER_DIM_MS
:
1520 case GLSL_SAMPLER_DIM_3D
:
1521 case GLSL_SAMPLER_DIM_CUBE
:
1523 flags
|= IR3_INSTR_3D
;
1526 unreachable("bad sampler_dim");
1529 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1530 flags
|= IR3_INSTR_S
;
1532 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
1533 flags
|= IR3_INSTR_A
;
1540 emit_tex(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1542 struct ir3_block
*b
= ctx
->block
;
1543 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
1544 struct ir3_instruction
**coord
, *lod
, *compare
, *proj
, **off
, **ddx
, **ddy
;
1545 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
1546 unsigned i
, coords
, flags
;
1547 unsigned nsrc0
= 0, nsrc1
= 0;
1551 coord
= off
= ddx
= ddy
= NULL
;
1552 lod
= proj
= compare
= NULL
;
1554 /* TODO: might just be one component for gathers? */
1555 dst
= get_dst(ctx
, &tex
->dest
, 4);
1557 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
1558 switch (tex
->src
[i
].src_type
) {
1559 case nir_tex_src_coord
:
1560 coord
= get_src(ctx
, &tex
->src
[i
].src
);
1562 case nir_tex_src_bias
:
1563 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1566 case nir_tex_src_lod
:
1567 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1570 case nir_tex_src_comparitor
: /* shadow comparator */
1571 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1573 case nir_tex_src_projector
:
1574 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1577 case nir_tex_src_offset
:
1578 off
= get_src(ctx
, &tex
->src
[i
].src
);
1581 case nir_tex_src_ddx
:
1582 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
1584 case nir_tex_src_ddy
:
1585 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
1588 compile_error(ctx
, "Unhandled NIR tex serc type: %d\n",
1589 tex
->src
[i
].src_type
);
1595 case nir_texop_tex
: opc
= OPC_SAM
; break;
1596 case nir_texop_txb
: opc
= OPC_SAMB
; break;
1597 case nir_texop_txl
: opc
= OPC_SAML
; break;
1598 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
1599 case nir_texop_txf
: opc
= OPC_ISAML
; break;
1600 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
1601 case nir_texop_txf_ms
:
1604 case nir_texop_query_levels
:
1605 case nir_texop_texture_samples
:
1606 case nir_texop_samples_identical
:
1607 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
1611 tex_info(tex
, &flags
, &coords
);
1613 /* scale up integer coords for TXF based on the LOD */
1614 if (ctx
->unminify_coords
&& (opc
== OPC_ISAML
)) {
1616 for (i
= 0; i
< coords
; i
++)
1617 coord
[i
] = ir3_SHL_B(b
, coord
[i
], 0, lod
, 0);
1620 /* the array coord for cube arrays needs 0.5 added to it */
1621 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& tex
->is_array
&&
1623 coord
[3] = ir3_ADD_F(b
, coord
[3], 0, create_immed(b
, fui(0.5)), 0);
1626 * lay out the first argument in the proper order:
1627 * - actual coordinates first
1628 * - shadow reference
1631 * - starting at offset 4, dpdx.xy, dpdy.xy
1633 * bias/lod go into the second arg
1636 /* insert tex coords: */
1637 for (i
= 0; i
< coords
; i
++)
1638 src0
[nsrc0
++] = coord
[i
];
1641 /* hw doesn't do 1d, so we treat it as 2d with
1642 * height of 1, and patch up the y coord.
1643 * TODO: y coord should be (int)0 in some cases..
1645 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
1648 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1649 src0
[nsrc0
++] = compare
;
1651 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
1652 src0
[nsrc0
++] = coord
[coords
];
1655 src0
[nsrc0
++] = proj
;
1656 flags
|= IR3_INSTR_P
;
1659 /* pad to 4, then ddx/ddy: */
1660 if (tex
->op
== nir_texop_txd
) {
1662 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1663 for (i
= 0; i
< coords
; i
++)
1664 src0
[nsrc0
++] = ddx
[i
];
1666 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1667 for (i
= 0; i
< coords
; i
++)
1668 src0
[nsrc0
++] = ddy
[i
];
1670 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1674 * second argument (if applicable):
1679 if (has_off
| has_lod
| has_bias
) {
1681 for (i
= 0; i
< coords
; i
++)
1682 src1
[nsrc1
++] = off
[i
];
1684 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
1685 flags
|= IR3_INSTR_O
;
1688 if (has_lod
| has_bias
)
1689 src1
[nsrc1
++] = lod
;
1692 switch (tex
->dest_type
) {
1693 case nir_type_invalid
:
1694 case nir_type_float
:
1705 unreachable("bad dest_type");
1708 if (opc
== OPC_GETLOD
)
1711 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
,
1712 flags
, tex
->sampler_index
, tex
->sampler_index
,
1713 create_collect(b
, src0
, nsrc0
),
1714 create_collect(b
, src1
, nsrc1
));
1716 split_dest(b
, dst
, sam
, 4);
1718 /* GETLOD returns results in 4.8 fixed point */
1719 if (opc
== OPC_GETLOD
) {
1720 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
1722 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
1723 for (i
= 0; i
< 2; i
++) {
1724 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_U32
, TYPE_F32
), 0,
1731 emit_tex_query_levels(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1733 struct ir3_block
*b
= ctx
->block
;
1734 struct ir3_instruction
**dst
, *sam
;
1736 dst
= get_dst(ctx
, &tex
->dest
, 1);
1738 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
1739 tex
->sampler_index
, tex
->sampler_index
, NULL
, NULL
);
1741 /* even though there is only one component, since it ends
1742 * up in .z rather than .x, we need a split_dest()
1744 split_dest(b
, dst
, sam
, 3);
1746 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1747 * the value in TEX_CONST_0 is zero-based.
1749 if (ctx
->levels_add_one
)
1750 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
1754 emit_tex_txs(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1756 struct ir3_block
*b
= ctx
->block
;
1757 struct ir3_instruction
**dst
, *sam
, *lod
;
1758 unsigned flags
, coords
;
1760 tex_info(tex
, &flags
, &coords
);
1762 /* Actually we want the number of dimensions, not coordinates. This
1763 * distinction only matters for cubes.
1765 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
1768 dst
= get_dst(ctx
, &tex
->dest
, 4);
1770 compile_assert(ctx
, tex
->num_srcs
== 1);
1771 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
1773 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
1775 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
1776 tex
->sampler_index
, tex
->sampler_index
, lod
, NULL
);
1778 split_dest(b
, dst
, sam
, 4);
1780 /* Array size actually ends up in .w rather than .z. This doesn't
1781 * matter for miplevel 0, but for higher mips the value in z is
1782 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1783 * returned, which means that we have to add 1 to it for arrays.
1785 if (tex
->is_array
) {
1786 if (ctx
->levels_add_one
) {
1787 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
1789 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
1795 emit_phi(struct ir3_compile
*ctx
, nir_phi_instr
*nphi
)
1797 struct ir3_instruction
*phi
, **dst
;
1799 /* NOTE: phi's should be lowered to scalar at this point */
1800 compile_assert(ctx
, nphi
->dest
.ssa
.num_components
== 1);
1802 dst
= get_dst(ctx
, &nphi
->dest
, 1);
1804 phi
= ir3_instr_create2(ctx
->block
, -1, OPC_META_PHI
,
1805 1 + exec_list_length(&nphi
->srcs
));
1806 ir3_reg_create(phi
, 0, 0); /* dst */
1807 phi
->phi
.nphi
= nphi
;
1812 /* phi instructions are left partially constructed. We don't resolve
1813 * their srcs until the end of the block, since (eg. loops) one of
1814 * the phi's srcs might be defined after the phi due to back edges in
1818 resolve_phis(struct ir3_compile
*ctx
, struct ir3_block
*block
)
1820 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
1821 nir_phi_instr
*nphi
;
1823 /* phi's only come at start of block: */
1824 if (!(is_meta(instr
) && (instr
->opc
== OPC_META_PHI
)))
1827 if (!instr
->phi
.nphi
)
1830 nphi
= instr
->phi
.nphi
;
1831 instr
->phi
.nphi
= NULL
;
1833 foreach_list_typed(nir_phi_src
, nsrc
, node
, &nphi
->srcs
) {
1834 struct ir3_instruction
*src
= get_src(ctx
, &nsrc
->src
)[0];
1835 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
1839 resolve_array_phis(ctx
, block
);
1843 emit_jump(struct ir3_compile
*ctx
, nir_jump_instr
*jump
)
1845 switch (jump
->type
) {
1846 case nir_jump_break
:
1847 case nir_jump_continue
:
1848 /* I *think* we can simply just ignore this, and use the
1849 * successor block link to figure out where we need to
1850 * jump to for break/continue
1854 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
1860 emit_instr(struct ir3_compile
*ctx
, nir_instr
*instr
)
1862 switch (instr
->type
) {
1863 case nir_instr_type_alu
:
1864 emit_alu(ctx
, nir_instr_as_alu(instr
));
1866 case nir_instr_type_intrinsic
:
1867 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1869 case nir_instr_type_load_const
:
1870 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1872 case nir_instr_type_ssa_undef
:
1873 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
1875 case nir_instr_type_tex
: {
1876 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
1877 /* couple tex instructions get special-cased:
1881 emit_tex_txs(ctx
, tex
);
1883 case nir_texop_query_levels
:
1884 emit_tex_query_levels(ctx
, tex
);
1892 case nir_instr_type_phi
:
1893 emit_phi(ctx
, nir_instr_as_phi(instr
));
1895 case nir_instr_type_jump
:
1896 emit_jump(ctx
, nir_instr_as_jump(instr
));
1898 case nir_instr_type_call
:
1899 case nir_instr_type_parallel_copy
:
1900 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
1905 static struct ir3_block
*
1906 get_block(struct ir3_compile
*ctx
, nir_block
*nblock
)
1908 struct ir3_block
*block
;
1909 struct hash_entry
*entry
;
1910 entry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
1914 block
= ir3_block_create(ctx
->ir
);
1915 block
->nblock
= nblock
;
1916 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
1922 emit_block(struct ir3_compile
*ctx
, nir_block
*nblock
)
1924 struct ir3_block
*block
= get_block(ctx
, nblock
);
1926 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
1927 if (nblock
->successors
[i
]) {
1928 block
->successors
[i
] =
1929 get_block(ctx
, nblock
->successors
[i
]);
1934 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
1936 /* re-emit addr register in each block if needed: */
1937 _mesa_hash_table_destroy(ctx
->addr_ht
, NULL
);
1938 ctx
->addr_ht
= NULL
;
1940 nir_foreach_instr(nblock
, instr
) {
1941 emit_instr(ctx
, instr
);
1947 static void emit_cf_list(struct ir3_compile
*ctx
, struct exec_list
*list
);
1950 emit_if(struct ir3_compile
*ctx
, nir_if
*nif
)
1952 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
1954 ctx
->block
->condition
=
1955 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
1957 emit_cf_list(ctx
, &nif
->then_list
);
1958 emit_cf_list(ctx
, &nif
->else_list
);
1962 emit_loop(struct ir3_compile
*ctx
, nir_loop
*nloop
)
1964 emit_cf_list(ctx
, &nloop
->body
);
1968 emit_cf_list(struct ir3_compile
*ctx
, struct exec_list
*list
)
1970 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
1971 switch (node
->type
) {
1972 case nir_cf_node_block
:
1973 emit_block(ctx
, nir_cf_node_as_block(node
));
1975 case nir_cf_node_if
:
1976 emit_if(ctx
, nir_cf_node_as_if(node
));
1978 case nir_cf_node_loop
:
1979 emit_loop(ctx
, nir_cf_node_as_loop(node
));
1981 case nir_cf_node_function
:
1982 compile_error(ctx
, "TODO\n");
1988 /* emit stream-out code. At this point, the current block is the original
1989 * (nir) end block, and nir ensures that all flow control paths terminate
1990 * into the end block. We re-purpose the original end block to generate
1991 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
1992 * block holding stream-out write instructions, followed by the new end
1996 * p0.x = (vtxcnt < maxvtxcnt)
1997 * // succs: blockStreamOut, blockNewEnd
2000 * ... stream-out instructions ...
2001 * // succs: blockNewEnd
2007 emit_stream_out(struct ir3_compile
*ctx
)
2009 struct ir3_shader_variant
*v
= ctx
->so
;
2010 struct ir3
*ir
= ctx
->ir
;
2011 struct pipe_stream_output_info
*strmout
=
2012 &ctx
->so
->shader
->stream_output
;
2013 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
2014 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
2015 struct ir3_instruction
*bases
[PIPE_MAX_SO_BUFFERS
];
2017 /* create vtxcnt input in input block at top of shader,
2018 * so that it is seen as live over the entire duration
2021 vtxcnt
= create_input(ctx
->in_block
, 0);
2022 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
2024 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
2026 /* at this point, we are at the original 'end' block,
2027 * re-purpose this block to stream-out condition, then
2028 * append stream-out block and new-end block
2030 orig_end_block
= ctx
->block
;
2032 stream_out_block
= ir3_block_create(ir
);
2033 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
2035 new_end_block
= ir3_block_create(ir
);
2036 list_addtail(&new_end_block
->node
, &ir
->block_list
);
2038 orig_end_block
->successors
[0] = stream_out_block
;
2039 orig_end_block
->successors
[1] = new_end_block
;
2040 stream_out_block
->successors
[0] = new_end_block
;
2042 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2043 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
2044 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2045 cond
->cat2
.condition
= IR3_COND_LT
;
2047 /* condition goes on previous block to the conditional,
2048 * since it is used to pick which of the two successor
2051 orig_end_block
->condition
= cond
;
2053 /* switch to stream_out_block to generate the stream-out
2056 ctx
->block
= stream_out_block
;
2058 /* Calculate base addresses based on vtxcnt. Instructions
2059 * generated for bases not used in following loop will be
2060 * stripped out in the backend.
2062 for (unsigned i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
2063 unsigned stride
= strmout
->stride
[i
];
2064 struct ir3_instruction
*base
, *off
;
2066 base
= create_uniform(ctx
, regid(v
->first_driver_param
+ IR3_TFBOS_OFF
, i
));
2068 /* 24-bit should be enough: */
2069 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
2070 create_immed(ctx
->block
, stride
* 4), 0);
2072 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
2075 /* Generate the per-output store instructions: */
2076 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
2077 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
2078 unsigned c
= j
+ strmout
->output
[i
].start_component
;
2079 struct ir3_instruction
*base
, *out
, *stg
;
2081 base
= bases
[strmout
->output
[i
].output_buffer
];
2082 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
2084 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
2085 create_immed(ctx
->block
, 1), 0);
2086 stg
->cat6
.type
= TYPE_U32
;
2087 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
2089 array_insert(ctx
->ir
->keeps
, stg
);
2093 /* and finally switch to the new_end_block: */
2094 ctx
->block
= new_end_block
;
2098 emit_function(struct ir3_compile
*ctx
, nir_function_impl
*impl
)
2100 nir_metadata_require(impl
, nir_metadata_block_index
);
2102 emit_cf_list(ctx
, &impl
->body
);
2103 emit_block(ctx
, impl
->end_block
);
2105 /* at this point, we should have a single empty block,
2106 * into which we emit the 'end' instruction.
2108 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
2110 /* If stream-out (aka transform-feedback) enabled, emit the
2111 * stream-out instructions, followed by a new empty block (into
2112 * which the 'end' instruction lands).
2114 * NOTE: it is done in this order, rather than inserting before
2115 * we emit end_block, because NIR guarantees that all blocks
2116 * flow into end_block, and that end_block has no successors.
2117 * So by re-purposing end_block as the first block of stream-
2118 * out, we guarantee that all exit paths flow into the stream-
2121 if ((ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
2122 !ctx
->so
->key
.binning_pass
) {
2123 debug_assert(ctx
->so
->type
== SHADER_VERTEX
);
2124 emit_stream_out(ctx
);
2127 ir3_END(ctx
->block
);
2131 setup_input(struct ir3_compile
*ctx
, nir_variable
*in
)
2133 struct ir3_shader_variant
*so
= ctx
->so
;
2134 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
2135 unsigned ncomp
= glsl_get_components(in
->type
);
2136 unsigned n
= in
->data
.driver_location
;
2137 unsigned slot
= in
->data
.location
;
2139 DBG("; in: slot=%u, len=%ux%u, drvloc=%u",
2140 slot
, array_len
, ncomp
, n
);
2142 so
->inputs
[n
].slot
= slot
;
2143 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
2144 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2145 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
2147 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2148 for (int i
= 0; i
< ncomp
; i
++) {
2149 struct ir3_instruction
*instr
= NULL
;
2150 unsigned idx
= (n
* 4) + i
;
2152 if (slot
== VARYING_SLOT_POS
) {
2153 so
->inputs
[n
].bary
= false;
2154 so
->frag_coord
= true;
2155 instr
= create_frag_coord(ctx
, i
);
2156 } else if (slot
== VARYING_SLOT_FACE
) {
2157 so
->inputs
[n
].bary
= false;
2158 so
->frag_face
= true;
2159 instr
= create_frag_face(ctx
, i
);
2161 bool use_ldlv
= false;
2163 /* detect the special case for front/back colors where
2164 * we need to do flat vs smooth shading depending on
2167 if (in
->data
.interpolation
== INTERP_QUALIFIER_NONE
) {
2169 case VARYING_SLOT_COL0
:
2170 case VARYING_SLOT_COL1
:
2171 case VARYING_SLOT_BFC0
:
2172 case VARYING_SLOT_BFC1
:
2173 so
->inputs
[n
].rasterflat
= true;
2180 if (ctx
->flat_bypass
) {
2181 if ((so
->inputs
[n
].interpolate
== INTERP_QUALIFIER_FLAT
) ||
2182 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
2186 so
->inputs
[n
].bary
= true;
2188 instr
= create_frag_input(ctx
, use_ldlv
);
2191 ctx
->ir
->inputs
[idx
] = instr
;
2193 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2194 for (int i
= 0; i
< ncomp
; i
++) {
2195 unsigned idx
= (n
* 4) + i
;
2196 ctx
->ir
->inputs
[idx
] = create_input(ctx
->block
, idx
);
2199 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2202 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
2203 so
->total_in
+= ncomp
;
2208 setup_output(struct ir3_compile
*ctx
, nir_variable
*out
)
2210 struct ir3_shader_variant
*so
= ctx
->so
;
2211 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
2212 unsigned ncomp
= glsl_get_components(out
->type
);
2213 unsigned n
= out
->data
.driver_location
;
2214 unsigned slot
= out
->data
.location
;
2217 DBG("; out: slot=%u, len=%ux%u, drvloc=%u",
2218 slot
, array_len
, ncomp
, n
);
2220 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2222 case FRAG_RESULT_DEPTH
:
2223 comp
= 2; /* tgsi will write to .z component */
2224 so
->writes_pos
= true;
2226 case FRAG_RESULT_COLOR
:
2230 if (slot
>= FRAG_RESULT_DATA0
)
2232 compile_error(ctx
, "unknown FS output name: %s\n",
2233 gl_frag_result_name(slot
));
2235 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2237 case VARYING_SLOT_POS
:
2238 so
->writes_pos
= true;
2240 case VARYING_SLOT_PSIZ
:
2241 so
->writes_psize
= true;
2243 case VARYING_SLOT_COL0
:
2244 case VARYING_SLOT_COL1
:
2245 case VARYING_SLOT_BFC0
:
2246 case VARYING_SLOT_BFC1
:
2247 case VARYING_SLOT_FOGC
:
2248 case VARYING_SLOT_CLIP_DIST0
:
2249 case VARYING_SLOT_CLIP_DIST1
:
2252 if (slot
>= VARYING_SLOT_VAR0
)
2254 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
2256 compile_error(ctx
, "unknown VS output name: %s\n",
2257 gl_varying_slot_name(slot
));
2260 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2263 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
2265 so
->outputs
[n
].slot
= slot
;
2266 so
->outputs
[n
].regid
= regid(n
, comp
);
2267 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
2269 for (int i
= 0; i
< ncomp
; i
++) {
2270 unsigned idx
= (n
* 4) + i
;
2272 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
2277 emit_instructions(struct ir3_compile
*ctx
)
2279 unsigned ninputs
, noutputs
;
2280 nir_function_impl
*fxn
= NULL
;
2282 /* Find the main function: */
2283 nir_foreach_function(ctx
->s
, function
) {
2284 compile_assert(ctx
, strcmp(function
->name
, "main") == 0);
2285 compile_assert(ctx
, function
->impl
);
2286 fxn
= function
->impl
;
2290 ninputs
= exec_list_length(&ctx
->s
->inputs
) * 4;
2291 noutputs
= exec_list_length(&ctx
->s
->outputs
) * 4;
2293 /* or vtx shaders, we need to leave room for sysvals:
2295 if (ctx
->so
->type
== SHADER_VERTEX
) {
2299 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
2301 /* Create inputs in first block: */
2302 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
2303 ctx
->in_block
= ctx
->block
;
2304 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
2306 if (ctx
->so
->type
== SHADER_VERTEX
) {
2307 ctx
->ir
->ninputs
-= 8;
2310 /* for fragment shader, we have a single input register (usually
2311 * r0.xy) which is used as the base for bary.f varying fetch instrs:
2313 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2314 // TODO maybe a helper for fi since we need it a few places..
2315 struct ir3_instruction
*instr
;
2316 instr
= ir3_instr_create(ctx
->block
, -1, OPC_META_FI
);
2317 ir3_reg_create(instr
, 0, 0);
2318 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.x */
2319 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.y */
2320 ctx
->frag_pos
= instr
;
2324 nir_foreach_variable(var
, &ctx
->s
->inputs
) {
2325 setup_input(ctx
, var
);
2328 /* Setup outputs: */
2329 nir_foreach_variable(var
, &ctx
->s
->outputs
) {
2330 setup_output(ctx
, var
);
2333 /* Setup variables (which should only be arrays): */
2334 nir_foreach_variable(var
, &ctx
->s
->globals
) {
2335 declare_var(ctx
, var
);
2338 /* And emit the body: */
2340 emit_function(ctx
, fxn
);
2342 list_for_each_entry (struct ir3_block
, block
, &ctx
->ir
->block_list
, node
) {
2343 resolve_phis(ctx
, block
);
2347 /* from NIR perspective, we actually have inputs. But most of the "inputs"
2348 * for a fragment shader are just bary.f instructions. The *actual* inputs
2349 * from the hw perspective are the frag_pos and optionally frag_coord and
2353 fixup_frag_inputs(struct ir3_compile
*ctx
)
2355 struct ir3_shader_variant
*so
= ctx
->so
;
2356 struct ir3
*ir
= ctx
->ir
;
2357 struct ir3_instruction
**inputs
;
2358 struct ir3_instruction
*instr
;
2363 n
= 4; /* always have frag_pos */
2364 n
+= COND(so
->frag_face
, 4);
2365 n
+= COND(so
->frag_coord
, 4);
2367 inputs
= ir3_alloc(ctx
->ir
, n
* (sizeof(struct ir3_instruction
*)));
2369 if (so
->frag_face
) {
2370 /* this ultimately gets assigned to hr0.x so doesn't conflict
2371 * with frag_coord/frag_pos..
2373 inputs
[ir
->ninputs
++] = ctx
->frag_face
;
2374 ctx
->frag_face
->regs
[0]->num
= 0;
2376 /* remaining channels not used, but let's avoid confusing
2377 * other parts that expect inputs to come in groups of vec4
2379 inputs
[ir
->ninputs
++] = NULL
;
2380 inputs
[ir
->ninputs
++] = NULL
;
2381 inputs
[ir
->ninputs
++] = NULL
;
2384 /* since we don't know where to set the regid for frag_coord,
2385 * we have to use r0.x for it. But we don't want to *always*
2386 * use r1.x for frag_pos as that could increase the register
2387 * footprint on simple shaders:
2389 if (so
->frag_coord
) {
2390 ctx
->frag_coord
[0]->regs
[0]->num
= regid
++;
2391 ctx
->frag_coord
[1]->regs
[0]->num
= regid
++;
2392 ctx
->frag_coord
[2]->regs
[0]->num
= regid
++;
2393 ctx
->frag_coord
[3]->regs
[0]->num
= regid
++;
2395 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[0];
2396 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[1];
2397 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[2];
2398 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[3];
2401 /* we always have frag_pos: */
2402 so
->pos_regid
= regid
;
2405 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2406 instr
->regs
[0]->num
= regid
++;
2407 inputs
[ir
->ninputs
++] = instr
;
2408 ctx
->frag_pos
->regs
[1]->instr
= instr
;
2411 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2412 instr
->regs
[0]->num
= regid
++;
2413 inputs
[ir
->ninputs
++] = instr
;
2414 ctx
->frag_pos
->regs
[2]->instr
= instr
;
2416 ir
->inputs
= inputs
;
2420 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
2421 struct ir3_shader_variant
*so
)
2423 struct ir3_compile
*ctx
;
2425 struct ir3_instruction
**inputs
;
2426 unsigned i
, j
, actual_in
, inloc
;
2427 int ret
= 0, max_bary
;
2431 ctx
= compile_init(compiler
, so
);
2433 DBG("INIT failed!");
2438 emit_instructions(ctx
);
2441 DBG("EMIT failed!");
2446 ir
= so
->ir
= ctx
->ir
;
2448 /* keep track of the inputs from TGSI perspective.. */
2449 inputs
= ir
->inputs
;
2451 /* but fixup actual inputs for frag shader: */
2452 if (so
->type
== SHADER_FRAGMENT
)
2453 fixup_frag_inputs(ctx
);
2455 /* at this point, for binning pass, throw away unneeded outputs: */
2456 if (so
->key
.binning_pass
) {
2457 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
2458 unsigned slot
= so
->outputs
[i
].slot
;
2460 /* throw away everything but first position/psize */
2461 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
2463 so
->outputs
[j
] = so
->outputs
[i
];
2464 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
2465 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
2466 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
2467 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
2472 so
->outputs_count
= j
;
2473 ir
->noutputs
= j
* 4;
2476 /* if we want half-precision outputs, mark the output registers
2479 if (so
->key
.half_precision
) {
2480 for (i
= 0; i
< ir
->noutputs
; i
++) {
2481 struct ir3_instruction
*out
= ir
->outputs
[i
];
2484 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2485 /* output could be a fanout (ie. texture fetch output)
2486 * in which case we need to propagate the half-reg flag
2487 * up to the definer so that RA sees it:
2489 if (is_meta(out
) && (out
->opc
== OPC_META_FO
)) {
2490 out
= out
->regs
[1]->instr
;
2491 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2494 if (out
->category
== 1) {
2495 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
2500 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2501 printf("BEFORE CP:\n");
2507 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2508 printf("BEFORE GROUPING:\n");
2512 /* Group left/right neighbors, inserting mov's where needed to
2519 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2520 printf("AFTER DEPTH:\n");
2524 ret
= ir3_sched(ir
);
2526 DBG("SCHED failed!");
2530 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2531 printf("AFTER SCHED:\n");
2535 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
2541 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2542 printf("AFTER RA:\n");
2546 /* fixup input/outputs: */
2547 for (i
= 0; i
< so
->outputs_count
; i
++) {
2548 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
2549 /* preserve hack for depth output.. tgsi writes depth to .z,
2550 * but what we give the hw is the scalar register:
2552 if ((so
->type
== SHADER_FRAGMENT
) &&
2553 (so
->outputs
[i
].slot
== FRAG_RESULT_DEPTH
))
2554 so
->outputs
[i
].regid
+= 2;
2557 /* Note that some or all channels of an input may be unused: */
2560 for (i
= 0; i
< so
->inputs_count
; i
++) {
2561 unsigned j
, regid
= ~0, compmask
= 0;
2562 so
->inputs
[i
].ncomp
= 0;
2563 so
->inputs
[i
].inloc
= inloc
+ 8;
2564 for (j
= 0; j
< 4; j
++) {
2565 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
2566 if (in
&& !(in
->flags
& IR3_INSTR_UNUSED
)) {
2567 compmask
|= (1 << j
);
2568 regid
= in
->regs
[0]->num
- j
;
2570 so
->inputs
[i
].ncomp
++;
2571 if ((so
->type
== SHADER_FRAGMENT
) && so
->inputs
[i
].bary
) {
2573 assert(in
->regs
[1]->flags
& IR3_REG_IMMED
);
2574 in
->regs
[1]->iim_val
= inloc
++;
2578 if ((so
->type
== SHADER_FRAGMENT
) && compmask
&& so
->inputs
[i
].bary
)
2580 so
->inputs
[i
].regid
= regid
;
2581 so
->inputs
[i
].compmask
= compmask
;
2584 /* We need to do legalize after (for frag shader's) the "bary.f"
2585 * offsets (inloc) have been assigned.
2587 ir3_legalize(ir
, &so
->has_samp
, &max_bary
);
2589 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2590 printf("AFTER LEGALIZE:\n");
2594 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
2595 if (so
->type
== SHADER_VERTEX
)
2596 so
->total_in
= actual_in
;
2598 so
->total_in
= max_bary
+ 1;
2603 ir3_destroy(so
->ir
);