1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
36 #include "freedreno_util.h"
38 #include "ir3_compiler.h"
39 #include "ir3_shader.h"
42 #include "instr-a3xx.h"
47 struct ir3_compiler
*compiler
;
52 struct ir3_shader_variant
*so
;
54 struct ir3_block
*block
; /* the current block */
55 struct ir3_block
*in_block
; /* block created for shader inputs */
57 nir_function_impl
*impl
;
59 /* For fragment shaders, from the hw perspective the only
60 * actual input is r0.xy position register passed to bary.f.
61 * But TGSI doesn't know that, it still declares things as
62 * IN[] registers. So we do all the input tracking normally
63 * and fix things up after compile_instructions()
65 * NOTE that frag_pos is the hardware position (possibly it
66 * is actually an index or tag or some such.. it is *not*
67 * values that can be directly used for gl_FragCoord..)
69 struct ir3_instruction
*frag_pos
, *frag_face
, *frag_coord
[4];
71 /* For vertex shaders, keep track of the system values sources */
72 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
74 /* Compute shader inputs: */
75 struct ir3_instruction
*local_invocation_id
, *work_group_id
;
77 /* For SSBO's and atomics, we need to preserve order, such
78 * that reads don't overtake writes, and the order of writes
79 * is preserved. Atomics are considered as a write.
81 * To do this, we track last write and last access, in a
82 * similar way to ir3_array. But since we don't know whether
83 * the same SSBO is bound to multiple slots, so we simply
84 * track this globally rather than per-SSBO.
86 * TODO should we track this per block instead? I guess it
87 * shouldn't matter much?
89 struct ir3_instruction
*last_write
, *last_access
;
91 /* mapping from nir_register to defining instruction: */
92 struct hash_table
*def_ht
;
96 /* a common pattern for indirect addressing is to request the
97 * same address register multiple times. To avoid generating
98 * duplicate instruction sequences (which our backend does not
99 * try to clean up, since that should be done as the NIR stage)
100 * we cache the address value generated for a given src value:
102 struct hash_table
*addr_ht
;
104 /* maps nir_block to ir3_block, mostly for the purposes of
105 * figuring out the blocks successors
107 struct hash_table
*block_ht
;
109 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
110 * so we need to use ldlv.u32 to load the varying directly:
114 /* on a3xx, we need to add one to # of array levels:
118 /* on a3xx, we need to scale up integer coords for isaml based
121 bool unminify_coords
;
123 /* on a4xx, for array textures we need to add 0.5 to the array
126 bool array_index_add_half
;
128 /* on a4xx, bitmask of samplers which need astc+srgb workaround: */
131 unsigned max_texture_index
;
133 /* set if we encounter something we can't handle yet, so we
134 * can bail cleanly and fallback to TGSI compiler f/e
139 /* gpu pointer size in units of 32bit registers/slots */
140 static unsigned pointer_size(struct ir3_compile
*ctx
)
142 return (ctx
->compiler
->gpu_id
>= 500) ? 2 : 1;
145 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
146 static struct ir3_block
* get_block(struct ir3_compile
*ctx
, nir_block
*nblock
);
149 static struct ir3_compile
*
150 compile_init(struct ir3_compiler
*compiler
,
151 struct ir3_shader_variant
*so
)
153 struct ir3_compile
*ctx
= rzalloc(NULL
, struct ir3_compile
);
155 if (compiler
->gpu_id
>= 400) {
156 /* need special handling for "flat" */
157 ctx
->flat_bypass
= true;
158 ctx
->levels_add_one
= false;
159 ctx
->unminify_coords
= false;
160 ctx
->array_index_add_half
= true;
162 if (so
->type
== SHADER_VERTEX
)
163 ctx
->astc_srgb
= so
->key
.vastc_srgb
;
164 else if (so
->type
== SHADER_FRAGMENT
)
165 ctx
->astc_srgb
= so
->key
.fastc_srgb
;
168 /* no special handling for "flat" */
169 ctx
->flat_bypass
= false;
170 ctx
->levels_add_one
= true;
171 ctx
->unminify_coords
= true;
172 ctx
->array_index_add_half
= false;
175 ctx
->compiler
= compiler
;
178 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
179 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
180 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
181 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
183 /* TODO: maybe generate some sort of bitmask of what key
184 * lowers vs what shader has (ie. no need to lower
185 * texture clamp lowering if no texture sample instrs)..
186 * although should be done further up the stack to avoid
187 * creating duplicate variants..
190 if (ir3_key_lowers_nir(&so
->key
)) {
191 nir_shader
*s
= nir_shader_clone(ctx
, so
->shader
->nir
);
192 ctx
->s
= ir3_optimize_nir(so
->shader
, s
, &so
->key
);
194 /* fast-path for shader key that lowers nothing in NIR: */
195 ctx
->s
= so
->shader
->nir
;
198 if (fd_mesa_debug
& FD_DBG_DISASM
) {
199 DBG("dump nir%dv%d: type=%d, k={bp=%u,cts=%u,hp=%u}",
200 so
->shader
->id
, so
->id
, so
->type
,
201 so
->key
.binning_pass
, so
->key
.color_two_side
,
202 so
->key
.half_precision
);
203 nir_print_shader(ctx
->s
, stdout
);
206 so
->num_uniforms
= ctx
->s
->num_uniforms
;
207 so
->num_ubos
= ctx
->s
->info
->num_ubos
;
209 /* Layout of constant registers, each section aligned to vec4. Note
210 * that pointer size (ubo, etc) changes depending on generation.
214 * if (vertex shader) {
215 * driver params (IR3_DP_*)
216 * if (stream_output.num_outputs > 0)
217 * stream-out addresses
221 * Immediates go last mostly because they are inserted in the CP pass
222 * after the nir -> ir3 frontend.
224 unsigned constoff
= align(ctx
->s
->num_uniforms
, 4);
225 unsigned ptrsz
= pointer_size(ctx
);
227 memset(&so
->constbase
, ~0, sizeof(so
->constbase
));
229 if (so
->num_ubos
> 0) {
230 so
->constbase
.ubo
= constoff
;
231 constoff
+= align(ctx
->s
->info
->num_ubos
* ptrsz
, 4) / 4;
234 unsigned num_driver_params
= 0;
235 if (so
->type
== SHADER_VERTEX
) {
236 num_driver_params
= IR3_DP_VS_COUNT
;
237 } else if (so
->type
== SHADER_COMPUTE
) {
238 num_driver_params
= IR3_DP_CS_COUNT
;
241 so
->constbase
.driver_param
= constoff
;
242 constoff
+= align(num_driver_params
, 4) / 4;
244 if ((so
->type
== SHADER_VERTEX
) &&
245 (compiler
->gpu_id
< 500) &&
246 so
->shader
->stream_output
.num_outputs
> 0) {
247 so
->constbase
.tfbo
= constoff
;
248 constoff
+= align(PIPE_MAX_SO_BUFFERS
* ptrsz
, 4) / 4;
251 so
->constbase
.immediate
= constoff
;
257 compile_error(struct ir3_compile
*ctx
, const char *format
, ...)
260 va_start(ap
, format
);
261 _debug_vprintf(format
, ap
);
263 nir_print_shader(ctx
->s
, stdout
);
268 #define compile_assert(ctx, cond) do { \
269 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
273 compile_free(struct ir3_compile
*ctx
)
279 declare_var(struct ir3_compile
*ctx
, nir_variable
*var
)
281 unsigned length
= glsl_get_length(var
->type
) * 4; /* always vec4, at least with ttn */
282 struct ir3_array
*arr
= rzalloc(ctx
, struct ir3_array
);
283 arr
->id
= ++ctx
->num_arrays
;
284 arr
->length
= length
;
286 list_addtail(&arr
->node
, &ctx
->ir
->array_list
);
289 static struct ir3_array
*
290 get_var(struct ir3_compile
*ctx
, nir_variable
*var
)
292 list_for_each_entry (struct ir3_array
, arr
, &ctx
->ir
->array_list
, node
) {
296 compile_error(ctx
, "bogus var: %s\n", var
->name
);
300 /* allocate a n element value array (to be populated by caller) and
303 static struct ir3_instruction
**
304 __get_dst(struct ir3_compile
*ctx
, void *key
, unsigned n
)
306 struct ir3_instruction
**value
=
307 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
308 _mesa_hash_table_insert(ctx
->def_ht
, key
, value
);
312 static struct ir3_instruction
**
313 get_dst(struct ir3_compile
*ctx
, nir_dest
*dst
, unsigned n
)
315 compile_assert(ctx
, dst
->is_ssa
);
317 return __get_dst(ctx
, &dst
->ssa
, n
);
319 return __get_dst(ctx
, dst
->reg
.reg
, n
);
323 static struct ir3_instruction
**
324 get_dst_ssa(struct ir3_compile
*ctx
, nir_ssa_def
*dst
, unsigned n
)
326 return __get_dst(ctx
, dst
, n
);
329 static struct ir3_instruction
* const *
330 get_src(struct ir3_compile
*ctx
, nir_src
*src
)
332 struct hash_entry
*entry
;
333 compile_assert(ctx
, src
->is_ssa
);
335 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
337 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->reg
.reg
);
339 compile_assert(ctx
, entry
);
343 static struct ir3_instruction
*
344 create_immed(struct ir3_block
*block
, uint32_t val
)
346 struct ir3_instruction
*mov
;
348 mov
= ir3_instr_create(block
, OPC_MOV
);
349 mov
->cat1
.src_type
= TYPE_U32
;
350 mov
->cat1
.dst_type
= TYPE_U32
;
351 ir3_reg_create(mov
, 0, 0);
352 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
357 static struct ir3_instruction
*
358 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
)
360 struct ir3_instruction
*instr
, *immed
;
362 /* TODO in at least some cases, the backend could probably be
363 * made clever enough to propagate IR3_REG_HALF..
365 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
366 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
368 immed
= create_immed(block
, 2);
369 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
371 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
372 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
373 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
375 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
376 instr
->regs
[0]->num
= regid(REG_A0
, 0);
377 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
378 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
383 /* caches addr values to avoid generating multiple cov/shl/mova
384 * sequences for each use of a given NIR level src as address
386 static struct ir3_instruction
*
387 get_addr(struct ir3_compile
*ctx
, struct ir3_instruction
*src
)
389 struct ir3_instruction
*addr
;
392 ctx
->addr_ht
= _mesa_hash_table_create(ctx
,
393 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
395 struct hash_entry
*entry
;
396 entry
= _mesa_hash_table_search(ctx
->addr_ht
, src
);
401 addr
= create_addr(ctx
->block
, src
);
402 _mesa_hash_table_insert(ctx
->addr_ht
, src
, addr
);
407 static struct ir3_instruction
*
408 get_predicate(struct ir3_compile
*ctx
, struct ir3_instruction
*src
)
410 struct ir3_block
*b
= ctx
->block
;
411 struct ir3_instruction
*cond
;
413 /* NOTE: only cmps.*.* can write p0.x: */
414 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
415 cond
->cat2
.condition
= IR3_COND_NE
;
417 /* condition always goes in predicate register: */
418 cond
->regs
[0]->num
= regid(REG_P0
, 0);
423 static struct ir3_instruction
*
424 create_uniform(struct ir3_compile
*ctx
, unsigned n
)
426 struct ir3_instruction
*mov
;
428 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
429 /* TODO get types right? */
430 mov
->cat1
.src_type
= TYPE_F32
;
431 mov
->cat1
.dst_type
= TYPE_F32
;
432 ir3_reg_create(mov
, 0, 0);
433 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
438 static struct ir3_instruction
*
439 create_uniform_indirect(struct ir3_compile
*ctx
, int n
,
440 struct ir3_instruction
*address
)
442 struct ir3_instruction
*mov
;
444 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
445 mov
->cat1
.src_type
= TYPE_U32
;
446 mov
->cat1
.dst_type
= TYPE_U32
;
447 ir3_reg_create(mov
, 0, 0);
448 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
450 ir3_instr_set_address(mov
, address
);
455 static struct ir3_instruction
*
456 create_collect(struct ir3_block
*block
, struct ir3_instruction
*const *arr
,
459 struct ir3_instruction
*collect
;
464 collect
= ir3_instr_create2(block
, OPC_META_FI
, 1 + arrsz
);
465 ir3_reg_create(collect
, 0, 0); /* dst */
466 for (unsigned i
= 0; i
< arrsz
; i
++)
467 ir3_reg_create(collect
, 0, IR3_REG_SSA
)->instr
= arr
[i
];
472 static struct ir3_instruction
*
473 create_indirect_load(struct ir3_compile
*ctx
, unsigned arrsz
, int n
,
474 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
476 struct ir3_block
*block
= ctx
->block
;
477 struct ir3_instruction
*mov
;
478 struct ir3_register
*src
;
480 mov
= ir3_instr_create(block
, OPC_MOV
);
481 mov
->cat1
.src_type
= TYPE_U32
;
482 mov
->cat1
.dst_type
= TYPE_U32
;
483 ir3_reg_create(mov
, 0, 0);
484 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
485 src
->instr
= collect
;
487 src
->array
.offset
= n
;
489 ir3_instr_set_address(mov
, address
);
494 /* relative (indirect) if address!=NULL */
495 static struct ir3_instruction
*
496 create_var_load(struct ir3_compile
*ctx
, struct ir3_array
*arr
, int n
,
497 struct ir3_instruction
*address
)
499 struct ir3_block
*block
= ctx
->block
;
500 struct ir3_instruction
*mov
;
501 struct ir3_register
*src
;
503 mov
= ir3_instr_create(block
, OPC_MOV
);
504 mov
->cat1
.src_type
= TYPE_U32
;
505 mov
->cat1
.dst_type
= TYPE_U32
;
506 ir3_reg_create(mov
, 0, 0);
507 src
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
508 COND(address
, IR3_REG_RELATIV
));
509 src
->instr
= arr
->last_write
;
510 src
->size
= arr
->length
;
511 src
->array
.id
= arr
->id
;
512 src
->array
.offset
= n
;
515 ir3_instr_set_address(mov
, address
);
517 arr
->last_access
= mov
;
522 /* relative (indirect) if address!=NULL */
523 static struct ir3_instruction
*
524 create_var_store(struct ir3_compile
*ctx
, struct ir3_array
*arr
, int n
,
525 struct ir3_instruction
*src
, struct ir3_instruction
*address
)
527 struct ir3_block
*block
= ctx
->block
;
528 struct ir3_instruction
*mov
;
529 struct ir3_register
*dst
;
531 mov
= ir3_instr_create(block
, OPC_MOV
);
532 mov
->cat1
.src_type
= TYPE_U32
;
533 mov
->cat1
.dst_type
= TYPE_U32
;
534 dst
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
535 COND(address
, IR3_REG_RELATIV
));
536 dst
->instr
= arr
->last_access
;
537 dst
->size
= arr
->length
;
538 dst
->array
.id
= arr
->id
;
539 dst
->array
.offset
= n
;
540 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
542 ir3_instr_set_address(mov
, address
);
544 arr
->last_write
= arr
->last_access
= mov
;
549 static struct ir3_instruction
*
550 create_input_compmask(struct ir3_block
*block
, unsigned n
, unsigned compmask
)
552 struct ir3_instruction
*in
;
554 in
= ir3_instr_create(block
, OPC_META_INPUT
);
555 in
->inout
.block
= block
;
556 ir3_reg_create(in
, n
, 0);
558 in
->regs
[0]->wrmask
= compmask
;
563 static struct ir3_instruction
*
564 create_input(struct ir3_block
*block
, unsigned n
)
566 return create_input_compmask(block
, n
, 0x1);
569 static struct ir3_instruction
*
570 create_frag_input(struct ir3_compile
*ctx
, bool use_ldlv
)
572 struct ir3_block
*block
= ctx
->block
;
573 struct ir3_instruction
*instr
;
574 /* actual inloc is assigned and fixed up later: */
575 struct ir3_instruction
*inloc
= create_immed(block
, 0);
578 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
579 instr
->cat6
.type
= TYPE_U32
;
580 instr
->cat6
.iim_val
= 1;
582 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_pos
, 0);
583 instr
->regs
[2]->wrmask
= 0x3;
589 static struct ir3_instruction
*
590 create_frag_coord(struct ir3_compile
*ctx
, unsigned comp
)
592 struct ir3_block
*block
= ctx
->block
;
593 struct ir3_instruction
*instr
;
595 compile_assert(ctx
, !ctx
->frag_coord
[comp
]);
597 ctx
->frag_coord
[comp
] = create_input(ctx
->block
, 0);
602 /* for frag_coord, we get unsigned values.. we need
603 * to subtract (integer) 8 and divide by 16 (right-
604 * shift by 4) then convert to float:
608 * mov.u32f32 dst, tmp
611 instr
= ir3_SUB_S(block
, ctx
->frag_coord
[comp
], 0,
612 create_immed(block
, 8), 0);
613 instr
= ir3_SHR_B(block
, instr
, 0,
614 create_immed(block
, 4), 0);
615 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
621 /* seems that we can use these as-is: */
622 return ctx
->frag_coord
[comp
];
626 static struct ir3_instruction
*
627 create_driver_param(struct ir3_compile
*ctx
, enum ir3_driver_param dp
)
629 /* first four vec4 sysval's reserved for UBOs: */
630 /* NOTE: dp is in scalar, but there can be >4 dp components: */
631 unsigned n
= ctx
->so
->constbase
.driver_param
;
632 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
633 return create_uniform(ctx
, r
);
636 /* helper for instructions that produce multiple consecutive scalar
637 * outputs which need to have a split/fanout meta instruction inserted
640 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
641 struct ir3_instruction
*src
, unsigned base
, unsigned n
)
643 struct ir3_instruction
*prev
= NULL
;
644 for (int i
= 0, j
= 0; i
< n
; i
++) {
645 struct ir3_instruction
*split
= ir3_instr_create(block
, OPC_META_FO
);
646 ir3_reg_create(split
, 0, IR3_REG_SSA
);
647 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
648 split
->fo
.off
= i
+ base
;
651 split
->cp
.left
= prev
;
652 split
->cp
.left_cnt
++;
653 prev
->cp
.right
= split
;
654 prev
->cp
.right_cnt
++;
658 if (src
->regs
[0]->wrmask
& (1 << (i
+ base
)))
664 * Adreno uses uint rather than having dedicated bool type,
665 * which (potentially) requires some conversion, in particular
666 * when using output of an bool instr to int input, or visa
670 * -------+---------+-------+-
674 * To convert from an adreno bool (uint) to nir, use:
676 * absneg.s dst, (neg)src
678 * To convert back in the other direction:
680 * absneg.s dst, (abs)arc
682 * The CP step can clean up the absneg.s that cancel each other
683 * out, and with a slight bit of extra cleverness (to recognize
684 * the instructions which produce either a 0 or 1) can eliminate
685 * the absneg.s's completely when an instruction that wants
686 * 0/1 consumes the result. For example, when a nir 'bcsel'
687 * consumes the result of 'feq'. So we should be able to get by
688 * without a boolean resolve step, and without incuring any
689 * extra penalty in instruction count.
692 /* NIR bool -> native (adreno): */
693 static struct ir3_instruction
*
694 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
696 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
699 /* native (adreno) -> NIR bool: */
700 static struct ir3_instruction
*
701 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
703 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
707 * alu/sfu instructions:
711 emit_alu(struct ir3_compile
*ctx
, nir_alu_instr
*alu
)
713 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
714 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
715 struct ir3_block
*b
= ctx
->block
;
717 dst
= get_dst(ctx
, &alu
->dest
.dest
, MAX2(info
->output_size
, 1));
719 /* Vectors are special in that they have non-scalarized writemasks,
720 * and just take the first swizzle channel for each argument in
721 * order into each writemask channel.
723 if ((alu
->op
== nir_op_vec2
) ||
724 (alu
->op
== nir_op_vec3
) ||
725 (alu
->op
== nir_op_vec4
)) {
727 for (int i
= 0; i
< info
->num_inputs
; i
++) {
728 nir_alu_src
*asrc
= &alu
->src
[i
];
730 compile_assert(ctx
, !asrc
->abs
);
731 compile_assert(ctx
, !asrc
->negate
);
733 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
735 src
[i
] = create_immed(ctx
->block
, 0);
736 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
742 /* General case: We can just grab the one used channel per src. */
743 for (int i
= 0; i
< info
->num_inputs
; i
++) {
744 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
745 nir_alu_src
*asrc
= &alu
->src
[i
];
747 compile_assert(ctx
, !asrc
->abs
);
748 compile_assert(ctx
, !asrc
->negate
);
750 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
752 compile_assert(ctx
, src
[i
]);
757 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_S32
);
760 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_U32
);
763 dst
[0] = ir3_COV(b
, src
[0], TYPE_S32
, TYPE_F32
);
766 dst
[0] = ir3_COV(b
, src
[0], TYPE_U32
, TYPE_F32
);
769 dst
[0] = ir3_MOV(b
, src
[0], TYPE_S32
);
772 dst
[0] = ir3_MOV(b
, src
[0], TYPE_F32
);
775 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
776 dst
[0]->cat2
.condition
= IR3_COND_NE
;
777 dst
[0] = ir3_n2b(b
, dst
[0]);
780 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
783 dst
[0] = ir3_b2n(b
, src
[0]);
786 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
787 dst
[0]->cat2
.condition
= IR3_COND_NE
;
788 dst
[0] = ir3_n2b(b
, dst
[0]);
792 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
795 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
798 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
801 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
804 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
807 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
810 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
813 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
816 dst
[0] = ir3_DSX(b
, src
[0], 0);
817 dst
[0]->cat5
.type
= TYPE_F32
;
820 dst
[0] = ir3_DSY(b
, src
[0], 0);
821 dst
[0]->cat5
.type
= TYPE_F32
;
825 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
826 dst
[0]->cat2
.condition
= IR3_COND_LT
;
827 dst
[0] = ir3_n2b(b
, dst
[0]);
830 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
831 dst
[0]->cat2
.condition
= IR3_COND_GE
;
832 dst
[0] = ir3_n2b(b
, dst
[0]);
835 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
836 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
837 dst
[0] = ir3_n2b(b
, dst
[0]);
840 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
841 dst
[0]->cat2
.condition
= IR3_COND_NE
;
842 dst
[0] = ir3_n2b(b
, dst
[0]);
845 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
848 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
851 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
853 case nir_op_fround_even
:
854 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
857 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
861 dst
[0] = ir3_SIN(b
, src
[0], 0);
864 dst
[0] = ir3_COS(b
, src
[0], 0);
867 dst
[0] = ir3_RSQ(b
, src
[0], 0);
870 dst
[0] = ir3_RCP(b
, src
[0], 0);
873 dst
[0] = ir3_LOG2(b
, src
[0], 0);
876 dst
[0] = ir3_EXP2(b
, src
[0], 0);
879 dst
[0] = ir3_SQRT(b
, src
[0], 0);
883 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
886 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
889 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
892 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
895 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
898 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
901 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
905 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
906 * mull.u tmp0, a, b ; mul low, i.e. al * bl
907 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
908 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
910 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
911 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
912 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
915 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
918 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
921 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
924 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
927 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
930 /* maybe this would be sane to lower in nir.. */
931 struct ir3_instruction
*neg
, *pos
;
933 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
934 neg
->cat2
.condition
= IR3_COND_LT
;
936 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
937 pos
->cat2
.condition
= IR3_COND_GT
;
939 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
944 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
947 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
950 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
953 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
954 dst
[0]->cat2
.condition
= IR3_COND_LT
;
955 dst
[0] = ir3_n2b(b
, dst
[0]);
958 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
959 dst
[0]->cat2
.condition
= IR3_COND_GE
;
960 dst
[0] = ir3_n2b(b
, dst
[0]);
963 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
964 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
965 dst
[0] = ir3_n2b(b
, dst
[0]);
968 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
969 dst
[0]->cat2
.condition
= IR3_COND_NE
;
970 dst
[0] = ir3_n2b(b
, dst
[0]);
973 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
974 dst
[0]->cat2
.condition
= IR3_COND_LT
;
975 dst
[0] = ir3_n2b(b
, dst
[0]);
978 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
979 dst
[0]->cat2
.condition
= IR3_COND_GE
;
980 dst
[0] = ir3_n2b(b
, dst
[0]);
984 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, ir3_b2n(b
, src
[0]), 0, src
[2], 0);
987 case nir_op_bit_count
:
988 dst
[0] = ir3_CBITS_B(b
, src
[0], 0);
990 case nir_op_ifind_msb
: {
991 struct ir3_instruction
*cmp
;
992 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
993 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
994 cmp
->cat2
.condition
= IR3_COND_GE
;
995 dst
[0] = ir3_SEL_B32(b
,
996 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1000 case nir_op_ufind_msb
:
1001 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
1002 dst
[0] = ir3_SEL_B32(b
,
1003 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1004 src
[0], 0, dst
[0], 0);
1006 case nir_op_find_lsb
:
1007 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1008 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
1010 case nir_op_bitfield_reverse
:
1011 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1015 compile_error(ctx
, "Unhandled ALU op: %s\n",
1016 nir_op_infos
[alu
->op
].name
);
1021 /* handles direct/indirect UBO reads: */
1023 emit_intrinsic_load_ubo(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1024 struct ir3_instruction
**dst
)
1026 struct ir3_block
*b
= ctx
->block
;
1027 struct ir3_instruction
*base_lo
, *base_hi
, *addr
, *src0
, *src1
;
1028 nir_const_value
*const_offset
;
1029 /* UBO addresses are the first driver params: */
1030 unsigned ubo
= regid(ctx
->so
->constbase
.ubo
, 0);
1031 const unsigned ptrsz
= pointer_size(ctx
);
1035 /* First src is ubo index, which could either be an immed or not: */
1036 src0
= get_src(ctx
, &intr
->src
[0])[0];
1037 if (is_same_type_mov(src0
) &&
1038 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1039 base_lo
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
));
1040 base_hi
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
) + 1);
1042 base_lo
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
));
1043 base_hi
= create_uniform_indirect(ctx
, ubo
+ 1, get_addr(ctx
, src0
));
1046 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
1049 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1051 off
+= const_offset
->u32
[0];
1053 /* For load_ubo_indirect, second src is indirect offset: */
1054 src1
= get_src(ctx
, &intr
->src
[1])[0];
1056 /* and add offset to addr: */
1057 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1060 /* if offset is to large to encode in the ldg, split it out: */
1061 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1062 /* split out the minimal amount to improve the odds that
1063 * cp can fit the immediate in the add.s instruction:
1065 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1066 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1071 struct ir3_instruction
*carry
;
1073 /* handle 32b rollover, ie:
1074 * if (addr < base_lo)
1077 carry
= ir3_CMPS_U(b
, addr
, 0, base_lo
, 0);
1078 carry
->cat2
.condition
= IR3_COND_LT
;
1079 base_hi
= ir3_ADD_S(b
, base_hi
, 0, carry
, 0);
1081 addr
= create_collect(b
, (struct ir3_instruction
*[]){ addr
, base_hi
}, 2);
1084 for (int i
= 0; i
< intr
->num_components
; i
++) {
1085 struct ir3_instruction
*load
=
1086 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1087 load
->cat6
.type
= TYPE_U32
;
1088 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
1093 /* handles array reads: */
1095 emit_intrinsic_load_var(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1096 struct ir3_instruction
**dst
)
1098 nir_deref_var
*dvar
= intr
->variables
[0];
1099 nir_deref_array
*darr
= nir_deref_as_array(dvar
->deref
.child
);
1100 struct ir3_array
*arr
= get_var(ctx
, dvar
->var
);
1102 compile_assert(ctx
, dvar
->deref
.child
&&
1103 (dvar
->deref
.child
->deref_type
== nir_deref_type_array
));
1105 switch (darr
->deref_array_type
) {
1106 case nir_deref_array_type_direct
:
1107 /* direct access does not require anything special: */
1108 for (int i
= 0; i
< intr
->num_components
; i
++) {
1109 unsigned n
= darr
->base_offset
* 4 + i
;
1110 compile_assert(ctx
, n
< arr
->length
);
1111 dst
[i
] = create_var_load(ctx
, arr
, n
, NULL
);
1114 case nir_deref_array_type_indirect
: {
1115 /* for indirect, we need to collect all the array elements: */
1116 struct ir3_instruction
*addr
=
1117 get_addr(ctx
, get_src(ctx
, &darr
->indirect
)[0]);
1118 for (int i
= 0; i
< intr
->num_components
; i
++) {
1119 unsigned n
= darr
->base_offset
* 4 + i
;
1120 compile_assert(ctx
, n
< arr
->length
);
1121 dst
[i
] = create_var_load(ctx
, arr
, n
, addr
);
1126 compile_error(ctx
, "Unhandled load deref type: %u\n",
1127 darr
->deref_array_type
);
1132 /* handles array writes: */
1134 emit_intrinsic_store_var(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1136 nir_deref_var
*dvar
= intr
->variables
[0];
1137 nir_deref_array
*darr
= nir_deref_as_array(dvar
->deref
.child
);
1138 struct ir3_array
*arr
= get_var(ctx
, dvar
->var
);
1139 struct ir3_instruction
*addr
;
1140 struct ir3_instruction
* const *src
;
1141 unsigned wrmask
= nir_intrinsic_write_mask(intr
);
1143 compile_assert(ctx
, dvar
->deref
.child
&&
1144 (dvar
->deref
.child
->deref_type
== nir_deref_type_array
));
1146 src
= get_src(ctx
, &intr
->src
[0]);
1148 switch (darr
->deref_array_type
) {
1149 case nir_deref_array_type_direct
:
1152 case nir_deref_array_type_indirect
:
1153 addr
= get_addr(ctx
, get_src(ctx
, &darr
->indirect
)[0]);
1156 compile_error(ctx
, "Unhandled store deref type: %u\n",
1157 darr
->deref_array_type
);
1161 for (int i
= 0; i
< intr
->num_components
; i
++) {
1162 if (!(wrmask
& (1 << i
)))
1164 unsigned n
= darr
->base_offset
* 4 + i
;
1165 compile_assert(ctx
, n
< arr
->length
);
1166 create_var_store(ctx
, arr
, n
, src
[i
], addr
);
1171 mark_ssbo_read(struct ir3_compile
*ctx
, struct ir3_instruction
*instr
)
1173 instr
->regs
[0]->instr
= ctx
->last_write
;
1174 instr
->regs
[0]->flags
|= IR3_REG_SSA
;
1175 ctx
->last_access
= instr
;
1179 mark_ssbo_write(struct ir3_compile
*ctx
, struct ir3_instruction
*instr
)
1181 instr
->regs
[0]->instr
= ctx
->last_access
;
1182 instr
->regs
[0]->flags
|= IR3_REG_SSA
;
1183 ctx
->last_write
= ctx
->last_access
= instr
;
1187 emit_intrinsic_load_ssbo(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1188 struct ir3_instruction
**dst
)
1190 struct ir3_block
*b
= ctx
->block
;
1191 struct ir3_instruction
*ldgb
, *src0
, *src1
, *offset
;
1192 nir_const_value
*const_offset
;
1194 /* can this be non-const buffer_index? how do we handle that? */
1195 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1196 compile_assert(ctx
, const_offset
);
1198 offset
= get_src(ctx
, &intr
->src
[1])[0];
1200 /* src0 is uvec2(offset*4, 0), src1 is offset.. nir already *= 4: */
1201 src0
= create_collect(b
, (struct ir3_instruction
*[]){
1205 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1207 ldgb
= ir3_LDGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1209 ldgb
->regs
[0]->wrmask
= (1 << intr
->num_components
) - 1;
1210 ldgb
->cat6
.iim_val
= intr
->num_components
;
1211 ldgb
->cat6
.type
= TYPE_U32
;
1212 mark_ssbo_read(ctx
, ldgb
);
1214 split_dest(b
, dst
, ldgb
, 0, intr
->num_components
);
1217 /* src[] = { value, block_index, offset }. const_index[] = { write_mask } */
1219 emit_intrinsic_store_ssbo(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1221 struct ir3_block
*b
= ctx
->block
;
1222 struct ir3_instruction
*stgb
, *src0
, *src1
, *src2
, *offset
;
1223 nir_const_value
*const_offset
;
1224 unsigned ncomp
= ffs(~intr
->const_index
[0]) - 1;
1226 /* can this be non-const buffer_index? how do we handle that? */
1227 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1228 compile_assert(ctx
, const_offset
);
1230 offset
= get_src(ctx
, &intr
->src
[2])[0];
1232 /* src0 is value, src1 is offset, src2 is uvec2(offset*4, 0)..
1235 src0
= create_collect(b
, get_src(ctx
, &intr
->src
[0]), ncomp
);
1236 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1237 src2
= create_collect(b
, (struct ir3_instruction
*[]){
1242 stgb
= ir3_STGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1243 src0
, 0, src1
, 0, src2
, 0);
1244 stgb
->cat6
.iim_val
= ncomp
;
1245 stgb
->cat6
.type
= TYPE_U32
;
1246 mark_ssbo_write(ctx
, stgb
);
1248 array_insert(b
, b
->keeps
, stgb
);
1252 emit_intrinsic_atomic(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1254 struct ir3_block
*b
= ctx
->block
;
1255 struct ir3_instruction
*atomic
, *ssbo
, *src0
, *src1
, *src2
, *offset
;
1256 nir_const_value
*const_offset
;
1257 type_t type
= TYPE_U32
;
1259 /* can this be non-const buffer_index? how do we handle that? */
1260 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1261 compile_assert(ctx
, const_offset
);
1262 ssbo
= create_immed(b
, const_offset
->u32
[0]);
1264 offset
= get_src(ctx
, &intr
->src
[1])[0];
1266 /* src0 is data (or uvec2(data, compare)
1268 * src2 is uvec2(offset*4, 0)
1270 * Note that nir already multiplies the offset by four
1272 src0
= get_src(ctx
, &intr
->src
[2])[0];
1273 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1274 src2
= create_collect(b
, (struct ir3_instruction
*[]){
1279 switch (intr
->intrinsic
) {
1280 case nir_intrinsic_ssbo_atomic_add
:
1281 atomic
= ir3_ATOMIC_ADD(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1283 case nir_intrinsic_ssbo_atomic_imin
:
1284 atomic
= ir3_ATOMIC_MIN(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1287 case nir_intrinsic_ssbo_atomic_umin
:
1288 atomic
= ir3_ATOMIC_MIN(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1290 case nir_intrinsic_ssbo_atomic_imax
:
1291 atomic
= ir3_ATOMIC_MAX(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1294 case nir_intrinsic_ssbo_atomic_umax
:
1295 atomic
= ir3_ATOMIC_MAX(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1297 case nir_intrinsic_ssbo_atomic_and
:
1298 atomic
= ir3_ATOMIC_AND(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1300 case nir_intrinsic_ssbo_atomic_or
:
1301 atomic
= ir3_ATOMIC_OR(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1303 case nir_intrinsic_ssbo_atomic_xor
:
1304 atomic
= ir3_ATOMIC_XOR(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1306 case nir_intrinsic_ssbo_atomic_exchange
:
1307 atomic
= ir3_ATOMIC_XCHG(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1309 case nir_intrinsic_ssbo_atomic_comp_swap
:
1310 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
1311 src0
= create_collect(b
, (struct ir3_instruction
*[]){
1313 get_src(ctx
, &intr
->src
[3])[0],
1315 atomic
= ir3_ATOMIC_CMPXCHG(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1321 atomic
->cat6
.iim_val
= 1;
1322 atomic
->cat6
.type
= type
;
1323 mark_ssbo_write(ctx
, atomic
);
1325 /* even if nothing consume the result, we can't DCE the instruction: */
1326 array_insert(b
, b
->keeps
, atomic
);
1329 static void add_sysval_input_compmask(struct ir3_compile
*ctx
,
1330 gl_system_value slot
, unsigned compmask
,
1331 struct ir3_instruction
*instr
)
1333 struct ir3_shader_variant
*so
= ctx
->so
;
1334 unsigned r
= regid(so
->inputs_count
, 0);
1335 unsigned n
= so
->inputs_count
++;
1337 so
->inputs
[n
].sysval
= true;
1338 so
->inputs
[n
].slot
= slot
;
1339 so
->inputs
[n
].compmask
= compmask
;
1340 so
->inputs
[n
].regid
= r
;
1341 so
->inputs
[n
].interpolate
= INTERP_MODE_FLAT
;
1344 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
1345 ctx
->ir
->inputs
[r
] = instr
;
1348 static void add_sysval_input(struct ir3_compile
*ctx
, gl_system_value slot
,
1349 struct ir3_instruction
*instr
)
1351 add_sysval_input_compmask(ctx
, slot
, 0x1, instr
);
1355 emit_intrinsic(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1357 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1358 struct ir3_instruction
**dst
;
1359 struct ir3_instruction
* const *src
;
1360 struct ir3_block
*b
= ctx
->block
;
1361 nir_const_value
*const_offset
;
1364 if (info
->has_dest
) {
1365 dst
= get_dst(ctx
, &intr
->dest
, intr
->num_components
);
1370 switch (intr
->intrinsic
) {
1371 case nir_intrinsic_load_uniform
:
1372 idx
= nir_intrinsic_base(intr
);
1373 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1375 idx
+= const_offset
->u32
[0];
1376 for (int i
= 0; i
< intr
->num_components
; i
++) {
1377 unsigned n
= idx
* 4 + i
;
1378 dst
[i
] = create_uniform(ctx
, n
);
1381 src
= get_src(ctx
, &intr
->src
[0]);
1382 for (int i
= 0; i
< intr
->num_components
; i
++) {
1383 int n
= idx
* 4 + i
;
1384 dst
[i
] = create_uniform_indirect(ctx
, n
,
1385 get_addr(ctx
, src
[0]));
1387 /* NOTE: if relative addressing is used, we set
1388 * constlen in the compiler (to worst-case value)
1389 * since we don't know in the assembler what the max
1390 * addr reg value can be:
1392 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
1395 case nir_intrinsic_load_ubo
:
1396 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1398 case nir_intrinsic_load_input
:
1399 idx
= nir_intrinsic_base(intr
);
1400 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1402 idx
+= const_offset
->u32
[0];
1403 for (int i
= 0; i
< intr
->num_components
; i
++) {
1404 unsigned n
= idx
* 4 + i
;
1405 dst
[i
] = ctx
->ir
->inputs
[n
];
1408 src
= get_src(ctx
, &intr
->src
[0]);
1409 struct ir3_instruction
*collect
=
1410 create_collect(b
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
1411 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0]);
1412 for (int i
= 0; i
< intr
->num_components
; i
++) {
1413 unsigned n
= idx
* 4 + i
;
1414 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
1419 case nir_intrinsic_load_var
:
1420 emit_intrinsic_load_var(ctx
, intr
, dst
);
1422 case nir_intrinsic_store_var
:
1423 emit_intrinsic_store_var(ctx
, intr
);
1425 case nir_intrinsic_load_ssbo
:
1426 emit_intrinsic_load_ssbo(ctx
, intr
, dst
);
1428 case nir_intrinsic_store_ssbo
:
1429 emit_intrinsic_store_ssbo(ctx
, intr
);
1431 case nir_intrinsic_ssbo_atomic_add
:
1432 case nir_intrinsic_ssbo_atomic_imin
:
1433 case nir_intrinsic_ssbo_atomic_umin
:
1434 case nir_intrinsic_ssbo_atomic_imax
:
1435 case nir_intrinsic_ssbo_atomic_umax
:
1436 case nir_intrinsic_ssbo_atomic_and
:
1437 case nir_intrinsic_ssbo_atomic_or
:
1438 case nir_intrinsic_ssbo_atomic_xor
:
1439 case nir_intrinsic_ssbo_atomic_exchange
:
1440 case nir_intrinsic_ssbo_atomic_comp_swap
:
1441 emit_intrinsic_atomic(ctx
, intr
);
1443 case nir_intrinsic_store_output
:
1444 idx
= nir_intrinsic_base(intr
);
1445 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1446 compile_assert(ctx
, const_offset
!= NULL
);
1447 idx
+= const_offset
->u32
[0];
1449 src
= get_src(ctx
, &intr
->src
[0]);
1450 for (int i
= 0; i
< intr
->num_components
; i
++) {
1451 unsigned n
= idx
* 4 + i
;
1452 ctx
->ir
->outputs
[n
] = src
[i
];
1455 case nir_intrinsic_load_base_vertex
:
1456 if (!ctx
->basevertex
) {
1457 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
1458 add_sysval_input(ctx
, SYSTEM_VALUE_BASE_VERTEX
,
1461 dst
[0] = ctx
->basevertex
;
1463 case nir_intrinsic_load_vertex_id_zero_base
:
1464 case nir_intrinsic_load_vertex_id
:
1465 if (!ctx
->vertex_id
) {
1466 gl_system_value sv
= (intr
->intrinsic
== nir_intrinsic_load_vertex_id
) ?
1467 SYSTEM_VALUE_VERTEX_ID
: SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
;
1468 ctx
->vertex_id
= create_input(b
, 0);
1469 add_sysval_input(ctx
, sv
, ctx
->vertex_id
);
1471 dst
[0] = ctx
->vertex_id
;
1473 case nir_intrinsic_load_instance_id
:
1474 if (!ctx
->instance_id
) {
1475 ctx
->instance_id
= create_input(b
, 0);
1476 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
1479 dst
[0] = ctx
->instance_id
;
1481 case nir_intrinsic_load_user_clip_plane
:
1482 idx
= nir_intrinsic_ucp_id(intr
);
1483 for (int i
= 0; i
< intr
->num_components
; i
++) {
1484 unsigned n
= idx
* 4 + i
;
1485 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
1488 case nir_intrinsic_load_front_face
:
1489 if (!ctx
->frag_face
) {
1490 ctx
->so
->frag_face
= true;
1491 ctx
->frag_face
= create_input(b
, 0);
1492 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
1494 /* for fragface, we always get -1 or 0, but that is inverse
1495 * of what nir expects (where ~0 is true). Unfortunately
1496 * trying to widen from half to full in add.s seems to do a
1497 * non-sign-extending widen (resulting in something that
1498 * gets interpreted as float Inf??)
1500 dst
[0] = ir3_COV(b
, ctx
->frag_face
, TYPE_S16
, TYPE_S32
);
1501 dst
[0] = ir3_ADD_S(b
, dst
[0], 0, create_immed(b
, 1), 0);
1503 case nir_intrinsic_load_local_invocation_id
:
1504 if (!ctx
->local_invocation_id
) {
1505 ctx
->local_invocation_id
= create_input_compmask(b
, 0, 0x7);
1506 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
,
1507 0x7, ctx
->local_invocation_id
);
1509 split_dest(b
, dst
, ctx
->local_invocation_id
, 0, 3);
1511 case nir_intrinsic_load_work_group_id
:
1512 if (!ctx
->work_group_id
) {
1513 ctx
->work_group_id
= create_input_compmask(b
, 0, 0x7);
1514 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_WORK_GROUP_ID
,
1515 0x7, ctx
->work_group_id
);
1516 ctx
->work_group_id
->regs
[0]->flags
|= IR3_REG_HIGH
;
1518 split_dest(b
, dst
, ctx
->work_group_id
, 0, 3);
1520 case nir_intrinsic_load_num_work_groups
:
1521 for (int i
= 0; i
< intr
->num_components
; i
++) {
1522 dst
[i
] = create_driver_param(ctx
, IR3_DP_NUM_WORK_GROUPS_X
+ i
);
1525 case nir_intrinsic_discard_if
:
1526 case nir_intrinsic_discard
: {
1527 struct ir3_instruction
*cond
, *kill
;
1529 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
1530 /* conditional discard: */
1531 src
= get_src(ctx
, &intr
->src
[0]);
1532 cond
= ir3_b2n(b
, src
[0]);
1534 /* unconditional discard: */
1535 cond
= create_immed(b
, 1);
1538 /* NOTE: only cmps.*.* can write p0.x: */
1539 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1540 cond
->cat2
.condition
= IR3_COND_NE
;
1542 /* condition always goes in predicate register: */
1543 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1545 kill
= ir3_KILL(b
, cond
, 0);
1546 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
1548 array_insert(b
, b
->keeps
, kill
);
1549 ctx
->so
->has_kill
= true;
1554 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
1555 nir_intrinsic_infos
[intr
->intrinsic
].name
);
1561 emit_load_const(struct ir3_compile
*ctx
, nir_load_const_instr
*instr
)
1563 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
1564 instr
->def
.num_components
);
1565 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1566 dst
[i
] = create_immed(ctx
->block
, instr
->value
.u32
[i
]);
1570 emit_undef(struct ir3_compile
*ctx
, nir_ssa_undef_instr
*undef
)
1572 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
1573 undef
->def
.num_components
);
1574 /* backend doesn't want undefined instructions, so just plug
1577 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
1578 dst
[i
] = create_immed(ctx
->block
, fui(0.0));
1582 * texture fetch/sample instructions:
1586 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
1588 unsigned coords
, flags
= 0;
1590 /* note: would use tex->coord_components.. except txs.. also,
1591 * since array index goes after shadow ref, we don't want to
1594 switch (tex
->sampler_dim
) {
1595 case GLSL_SAMPLER_DIM_1D
:
1596 case GLSL_SAMPLER_DIM_BUF
:
1599 case GLSL_SAMPLER_DIM_2D
:
1600 case GLSL_SAMPLER_DIM_RECT
:
1601 case GLSL_SAMPLER_DIM_EXTERNAL
:
1602 case GLSL_SAMPLER_DIM_MS
:
1605 case GLSL_SAMPLER_DIM_3D
:
1606 case GLSL_SAMPLER_DIM_CUBE
:
1608 flags
|= IR3_INSTR_3D
;
1611 unreachable("bad sampler_dim");
1614 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1615 flags
|= IR3_INSTR_S
;
1617 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
1618 flags
|= IR3_INSTR_A
;
1625 emit_tex(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1627 struct ir3_block
*b
= ctx
->block
;
1628 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
1629 struct ir3_instruction
* const *coord
, * const *off
, * const *ddx
, * const *ddy
;
1630 struct ir3_instruction
*lod
, *compare
, *proj
;
1631 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
1632 unsigned i
, coords
, flags
;
1633 unsigned nsrc0
= 0, nsrc1
= 0;
1637 coord
= off
= ddx
= ddy
= NULL
;
1638 lod
= proj
= compare
= NULL
;
1640 /* TODO: might just be one component for gathers? */
1641 dst
= get_dst(ctx
, &tex
->dest
, 4);
1643 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
1644 switch (tex
->src
[i
].src_type
) {
1645 case nir_tex_src_coord
:
1646 coord
= get_src(ctx
, &tex
->src
[i
].src
);
1648 case nir_tex_src_bias
:
1649 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1652 case nir_tex_src_lod
:
1653 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1656 case nir_tex_src_comparator
: /* shadow comparator */
1657 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1659 case nir_tex_src_projector
:
1660 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1663 case nir_tex_src_offset
:
1664 off
= get_src(ctx
, &tex
->src
[i
].src
);
1667 case nir_tex_src_ddx
:
1668 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
1670 case nir_tex_src_ddy
:
1671 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
1674 compile_error(ctx
, "Unhandled NIR tex src type: %d\n",
1675 tex
->src
[i
].src_type
);
1681 case nir_texop_tex
: opc
= OPC_SAM
; break;
1682 case nir_texop_txb
: opc
= OPC_SAMB
; break;
1683 case nir_texop_txl
: opc
= OPC_SAML
; break;
1684 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
1685 case nir_texop_txf
: opc
= OPC_ISAML
; break;
1686 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
1687 case nir_texop_txf_ms
:
1690 case nir_texop_query_levels
:
1691 case nir_texop_texture_samples
:
1692 case nir_texop_samples_identical
:
1693 case nir_texop_txf_ms_mcs
:
1694 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
1698 tex_info(tex
, &flags
, &coords
);
1701 * lay out the first argument in the proper order:
1702 * - actual coordinates first
1703 * - shadow reference
1706 * - starting at offset 4, dpdx.xy, dpdy.xy
1708 * bias/lod go into the second arg
1711 /* insert tex coords: */
1712 for (i
= 0; i
< coords
; i
++)
1717 /* scale up integer coords for TXF based on the LOD */
1718 if (ctx
->unminify_coords
&& (opc
== OPC_ISAML
)) {
1720 for (i
= 0; i
< coords
; i
++)
1721 src0
[i
] = ir3_SHL_B(b
, src0
[i
], 0, lod
, 0);
1725 /* hw doesn't do 1d, so we treat it as 2d with
1726 * height of 1, and patch up the y coord.
1727 * TODO: y coord should be (int)0 in some cases..
1729 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
1732 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1733 src0
[nsrc0
++] = compare
;
1735 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
) {
1736 struct ir3_instruction
*idx
= coord
[coords
];
1738 /* the array coord for cube arrays needs 0.5 added to it */
1739 if (ctx
->array_index_add_half
&& (opc
!= OPC_ISAML
))
1740 idx
= ir3_ADD_F(b
, idx
, 0, create_immed(b
, fui(0.5)), 0);
1742 src0
[nsrc0
++] = idx
;
1746 src0
[nsrc0
++] = proj
;
1747 flags
|= IR3_INSTR_P
;
1750 /* pad to 4, then ddx/ddy: */
1751 if (tex
->op
== nir_texop_txd
) {
1753 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1754 for (i
= 0; i
< coords
; i
++)
1755 src0
[nsrc0
++] = ddx
[i
];
1757 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1758 for (i
= 0; i
< coords
; i
++)
1759 src0
[nsrc0
++] = ddy
[i
];
1761 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1765 * second argument (if applicable):
1770 if (has_off
| has_lod
| has_bias
) {
1772 for (i
= 0; i
< coords
; i
++)
1773 src1
[nsrc1
++] = off
[i
];
1775 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
1776 flags
|= IR3_INSTR_O
;
1779 if (has_lod
| has_bias
)
1780 src1
[nsrc1
++] = lod
;
1783 switch (tex
->dest_type
) {
1784 case nir_type_invalid
:
1785 case nir_type_float
:
1796 unreachable("bad dest_type");
1799 if (opc
== OPC_GETLOD
)
1802 unsigned tex_idx
= tex
->texture_index
;
1804 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex_idx
);
1806 struct ir3_instruction
*col0
= create_collect(b
, src0
, nsrc0
);
1807 struct ir3_instruction
*col1
= create_collect(b
, src1
, nsrc1
);
1809 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
, flags
,
1810 tex_idx
, tex_idx
, col0
, col1
);
1812 if ((ctx
->astc_srgb
& (1 << tex_idx
)) && !nir_tex_instr_is_query(tex
)) {
1813 /* only need first 3 components: */
1814 sam
->regs
[0]->wrmask
= 0x7;
1815 split_dest(b
, dst
, sam
, 0, 3);
1817 /* we need to sample the alpha separately with a non-ASTC
1820 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_W
, flags
,
1821 tex_idx
, tex_idx
, col0
, col1
);
1823 array_insert(ctx
->ir
, ctx
->ir
->astc_srgb
, sam
);
1825 /* fixup .w component: */
1826 split_dest(b
, &dst
[3], sam
, 3, 1);
1828 /* normal (non-workaround) case: */
1829 split_dest(b
, dst
, sam
, 0, 4);
1832 /* GETLOD returns results in 4.8 fixed point */
1833 if (opc
== OPC_GETLOD
) {
1834 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
1836 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
1837 for (i
= 0; i
< 2; i
++) {
1838 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_U32
, TYPE_F32
), 0,
1845 emit_tex_query_levels(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1847 struct ir3_block
*b
= ctx
->block
;
1848 struct ir3_instruction
**dst
, *sam
;
1850 dst
= get_dst(ctx
, &tex
->dest
, 1);
1852 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
1853 tex
->texture_index
, tex
->texture_index
, NULL
, NULL
);
1855 /* even though there is only one component, since it ends
1856 * up in .z rather than .x, we need a split_dest()
1858 split_dest(b
, dst
, sam
, 0, 3);
1860 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1861 * the value in TEX_CONST_0 is zero-based.
1863 if (ctx
->levels_add_one
)
1864 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
1868 emit_tex_txs(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1870 struct ir3_block
*b
= ctx
->block
;
1871 struct ir3_instruction
**dst
, *sam
;
1872 struct ir3_instruction
*lod
;
1873 unsigned flags
, coords
;
1875 tex_info(tex
, &flags
, &coords
);
1877 /* Actually we want the number of dimensions, not coordinates. This
1878 * distinction only matters for cubes.
1880 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
1883 dst
= get_dst(ctx
, &tex
->dest
, 4);
1885 compile_assert(ctx
, tex
->num_srcs
== 1);
1886 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
1888 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
1890 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
1891 tex
->texture_index
, tex
->texture_index
, lod
, NULL
);
1893 split_dest(b
, dst
, sam
, 0, 4);
1895 /* Array size actually ends up in .w rather than .z. This doesn't
1896 * matter for miplevel 0, but for higher mips the value in z is
1897 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1898 * returned, which means that we have to add 1 to it for arrays.
1900 if (tex
->is_array
) {
1901 if (ctx
->levels_add_one
) {
1902 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
1904 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
1910 emit_phi(struct ir3_compile
*ctx
, nir_phi_instr
*nphi
)
1912 struct ir3_instruction
*phi
, **dst
;
1914 /* NOTE: phi's should be lowered to scalar at this point */
1915 compile_assert(ctx
, nphi
->dest
.ssa
.num_components
== 1);
1917 dst
= get_dst(ctx
, &nphi
->dest
, 1);
1919 phi
= ir3_instr_create2(ctx
->block
, OPC_META_PHI
,
1920 1 + exec_list_length(&nphi
->srcs
));
1921 ir3_reg_create(phi
, 0, 0); /* dst */
1922 phi
->phi
.nphi
= nphi
;
1927 /* phi instructions are left partially constructed. We don't resolve
1928 * their srcs until the end of the block, since (eg. loops) one of
1929 * the phi's srcs might be defined after the phi due to back edges in
1933 resolve_phis(struct ir3_compile
*ctx
, struct ir3_block
*block
)
1935 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
1936 nir_phi_instr
*nphi
;
1938 /* phi's only come at start of block: */
1939 if (instr
->opc
!= OPC_META_PHI
)
1942 if (!instr
->phi
.nphi
)
1945 nphi
= instr
->phi
.nphi
;
1946 instr
->phi
.nphi
= NULL
;
1948 foreach_list_typed(nir_phi_src
, nsrc
, node
, &nphi
->srcs
) {
1949 struct ir3_instruction
*src
= get_src(ctx
, &nsrc
->src
)[0];
1951 /* NOTE: src might not be in the same block as it comes from
1952 * according to the phi.. but in the end the backend assumes
1953 * it will be able to assign the same register to each (which
1954 * only works if it is assigned in the src block), so insert
1955 * an extra mov to make sure the phi src is assigned in the
1956 * block it comes from:
1958 src
= ir3_MOV(get_block(ctx
, nsrc
->pred
), src
, TYPE_U32
);
1960 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
1966 emit_jump(struct ir3_compile
*ctx
, nir_jump_instr
*jump
)
1968 switch (jump
->type
) {
1969 case nir_jump_break
:
1970 case nir_jump_continue
:
1971 /* I *think* we can simply just ignore this, and use the
1972 * successor block link to figure out where we need to
1973 * jump to for break/continue
1977 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
1983 emit_instr(struct ir3_compile
*ctx
, nir_instr
*instr
)
1985 switch (instr
->type
) {
1986 case nir_instr_type_alu
:
1987 emit_alu(ctx
, nir_instr_as_alu(instr
));
1989 case nir_instr_type_intrinsic
:
1990 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1992 case nir_instr_type_load_const
:
1993 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1995 case nir_instr_type_ssa_undef
:
1996 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
1998 case nir_instr_type_tex
: {
1999 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
2000 /* couple tex instructions get special-cased:
2004 emit_tex_txs(ctx
, tex
);
2006 case nir_texop_query_levels
:
2007 emit_tex_query_levels(ctx
, tex
);
2015 case nir_instr_type_phi
:
2016 emit_phi(ctx
, nir_instr_as_phi(instr
));
2018 case nir_instr_type_jump
:
2019 emit_jump(ctx
, nir_instr_as_jump(instr
));
2021 case nir_instr_type_call
:
2022 case nir_instr_type_parallel_copy
:
2023 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
2028 static struct ir3_block
*
2029 get_block(struct ir3_compile
*ctx
, nir_block
*nblock
)
2031 struct ir3_block
*block
;
2032 struct hash_entry
*entry
;
2033 entry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
2037 block
= ir3_block_create(ctx
->ir
);
2038 block
->nblock
= nblock
;
2039 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
2045 emit_block(struct ir3_compile
*ctx
, nir_block
*nblock
)
2047 struct ir3_block
*block
= get_block(ctx
, nblock
);
2049 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
2050 if (nblock
->successors
[i
]) {
2051 block
->successors
[i
] =
2052 get_block(ctx
, nblock
->successors
[i
]);
2057 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
2059 /* re-emit addr register in each block if needed: */
2060 _mesa_hash_table_destroy(ctx
->addr_ht
, NULL
);
2061 ctx
->addr_ht
= NULL
;
2063 nir_foreach_instr(instr
, nblock
) {
2064 emit_instr(ctx
, instr
);
2070 static void emit_cf_list(struct ir3_compile
*ctx
, struct exec_list
*list
);
2073 emit_if(struct ir3_compile
*ctx
, nir_if
*nif
)
2075 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
2077 ctx
->block
->condition
=
2078 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
2080 emit_cf_list(ctx
, &nif
->then_list
);
2081 emit_cf_list(ctx
, &nif
->else_list
);
2085 emit_loop(struct ir3_compile
*ctx
, nir_loop
*nloop
)
2087 emit_cf_list(ctx
, &nloop
->body
);
2091 emit_cf_list(struct ir3_compile
*ctx
, struct exec_list
*list
)
2093 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2094 switch (node
->type
) {
2095 case nir_cf_node_block
:
2096 emit_block(ctx
, nir_cf_node_as_block(node
));
2098 case nir_cf_node_if
:
2099 emit_if(ctx
, nir_cf_node_as_if(node
));
2101 case nir_cf_node_loop
:
2102 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2104 case nir_cf_node_function
:
2105 compile_error(ctx
, "TODO\n");
2111 /* emit stream-out code. At this point, the current block is the original
2112 * (nir) end block, and nir ensures that all flow control paths terminate
2113 * into the end block. We re-purpose the original end block to generate
2114 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2115 * block holding stream-out write instructions, followed by the new end
2119 * p0.x = (vtxcnt < maxvtxcnt)
2120 * // succs: blockStreamOut, blockNewEnd
2123 * ... stream-out instructions ...
2124 * // succs: blockNewEnd
2130 emit_stream_out(struct ir3_compile
*ctx
)
2132 struct ir3_shader_variant
*v
= ctx
->so
;
2133 struct ir3
*ir
= ctx
->ir
;
2134 struct pipe_stream_output_info
*strmout
=
2135 &ctx
->so
->shader
->stream_output
;
2136 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
2137 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
2138 struct ir3_instruction
*bases
[PIPE_MAX_SO_BUFFERS
];
2140 /* create vtxcnt input in input block at top of shader,
2141 * so that it is seen as live over the entire duration
2144 vtxcnt
= create_input(ctx
->in_block
, 0);
2145 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
2147 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
2149 /* at this point, we are at the original 'end' block,
2150 * re-purpose this block to stream-out condition, then
2151 * append stream-out block and new-end block
2153 orig_end_block
= ctx
->block
;
2155 stream_out_block
= ir3_block_create(ir
);
2156 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
2158 new_end_block
= ir3_block_create(ir
);
2159 list_addtail(&new_end_block
->node
, &ir
->block_list
);
2161 orig_end_block
->successors
[0] = stream_out_block
;
2162 orig_end_block
->successors
[1] = new_end_block
;
2163 stream_out_block
->successors
[0] = new_end_block
;
2165 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2166 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
2167 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2168 cond
->cat2
.condition
= IR3_COND_LT
;
2170 /* condition goes on previous block to the conditional,
2171 * since it is used to pick which of the two successor
2174 orig_end_block
->condition
= cond
;
2176 /* switch to stream_out_block to generate the stream-out
2179 ctx
->block
= stream_out_block
;
2181 /* Calculate base addresses based on vtxcnt. Instructions
2182 * generated for bases not used in following loop will be
2183 * stripped out in the backend.
2185 for (unsigned i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
2186 unsigned stride
= strmout
->stride
[i
];
2187 struct ir3_instruction
*base
, *off
;
2189 base
= create_uniform(ctx
, regid(v
->constbase
.tfbo
, i
));
2191 /* 24-bit should be enough: */
2192 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
2193 create_immed(ctx
->block
, stride
* 4), 0);
2195 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
2198 /* Generate the per-output store instructions: */
2199 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
2200 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
2201 unsigned c
= j
+ strmout
->output
[i
].start_component
;
2202 struct ir3_instruction
*base
, *out
, *stg
;
2204 base
= bases
[strmout
->output
[i
].output_buffer
];
2205 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
2207 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
2208 create_immed(ctx
->block
, 1), 0);
2209 stg
->cat6
.type
= TYPE_U32
;
2210 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
2212 array_insert(ctx
->block
, ctx
->block
->keeps
, stg
);
2216 /* and finally switch to the new_end_block: */
2217 ctx
->block
= new_end_block
;
2221 emit_function(struct ir3_compile
*ctx
, nir_function_impl
*impl
)
2223 nir_metadata_require(impl
, nir_metadata_block_index
);
2225 emit_cf_list(ctx
, &impl
->body
);
2226 emit_block(ctx
, impl
->end_block
);
2228 /* at this point, we should have a single empty block,
2229 * into which we emit the 'end' instruction.
2231 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
2233 /* If stream-out (aka transform-feedback) enabled, emit the
2234 * stream-out instructions, followed by a new empty block (into
2235 * which the 'end' instruction lands).
2237 * NOTE: it is done in this order, rather than inserting before
2238 * we emit end_block, because NIR guarantees that all blocks
2239 * flow into end_block, and that end_block has no successors.
2240 * So by re-purposing end_block as the first block of stream-
2241 * out, we guarantee that all exit paths flow into the stream-
2244 if ((ctx
->compiler
->gpu_id
< 500) &&
2245 (ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
2246 !ctx
->so
->key
.binning_pass
) {
2247 debug_assert(ctx
->so
->type
== SHADER_VERTEX
);
2248 emit_stream_out(ctx
);
2251 ir3_END(ctx
->block
);
2255 setup_input(struct ir3_compile
*ctx
, nir_variable
*in
)
2257 struct ir3_shader_variant
*so
= ctx
->so
;
2258 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
2259 unsigned ncomp
= glsl_get_components(in
->type
);
2260 unsigned n
= in
->data
.driver_location
;
2261 unsigned slot
= in
->data
.location
;
2263 DBG("; in: slot=%u, len=%ux%u, drvloc=%u",
2264 slot
, array_len
, ncomp
, n
);
2266 /* let's pretend things other than vec4 don't exist: */
2267 ncomp
= MAX2(ncomp
, 4);
2268 compile_assert(ctx
, ncomp
== 4);
2270 so
->inputs
[n
].slot
= slot
;
2271 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
2272 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2273 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
2275 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2276 for (int i
= 0; i
< ncomp
; i
++) {
2277 struct ir3_instruction
*instr
= NULL
;
2278 unsigned idx
= (n
* 4) + i
;
2280 if (slot
== VARYING_SLOT_POS
) {
2281 so
->inputs
[n
].bary
= false;
2282 so
->frag_coord
= true;
2283 instr
= create_frag_coord(ctx
, i
);
2284 } else if (slot
== VARYING_SLOT_PNTC
) {
2285 /* see for example st_get_generic_varying_index().. this is
2286 * maybe a bit mesa/st specific. But we need things to line
2287 * up for this in fdN_program:
2288 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2289 * if (emit->sprite_coord_enable & texmask) {
2293 so
->inputs
[n
].slot
= VARYING_SLOT_VAR8
;
2294 so
->inputs
[n
].bary
= true;
2295 instr
= create_frag_input(ctx
, false);
2297 bool use_ldlv
= false;
2299 /* detect the special case for front/back colors where
2300 * we need to do flat vs smooth shading depending on
2303 if (in
->data
.interpolation
== INTERP_MODE_NONE
) {
2305 case VARYING_SLOT_COL0
:
2306 case VARYING_SLOT_COL1
:
2307 case VARYING_SLOT_BFC0
:
2308 case VARYING_SLOT_BFC1
:
2309 so
->inputs
[n
].rasterflat
= true;
2316 if (ctx
->flat_bypass
) {
2317 if ((so
->inputs
[n
].interpolate
== INTERP_MODE_FLAT
) ||
2318 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
2322 so
->inputs
[n
].bary
= true;
2324 instr
= create_frag_input(ctx
, use_ldlv
);
2327 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
2329 ctx
->ir
->inputs
[idx
] = instr
;
2331 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2332 for (int i
= 0; i
< ncomp
; i
++) {
2333 unsigned idx
= (n
* 4) + i
;
2334 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
2335 ctx
->ir
->inputs
[idx
] = create_input(ctx
->block
, idx
);
2338 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2341 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
2342 so
->total_in
+= ncomp
;
2347 setup_output(struct ir3_compile
*ctx
, nir_variable
*out
)
2349 struct ir3_shader_variant
*so
= ctx
->so
;
2350 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
2351 unsigned ncomp
= glsl_get_components(out
->type
);
2352 unsigned n
= out
->data
.driver_location
;
2353 unsigned slot
= out
->data
.location
;
2356 DBG("; out: slot=%u, len=%ux%u, drvloc=%u",
2357 slot
, array_len
, ncomp
, n
);
2359 /* let's pretend things other than vec4 don't exist: */
2360 ncomp
= MAX2(ncomp
, 4);
2361 compile_assert(ctx
, ncomp
== 4);
2363 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2365 case FRAG_RESULT_DEPTH
:
2366 comp
= 2; /* tgsi will write to .z component */
2367 so
->writes_pos
= true;
2369 case FRAG_RESULT_COLOR
:
2373 if (slot
>= FRAG_RESULT_DATA0
)
2375 compile_error(ctx
, "unknown FS output name: %s\n",
2376 gl_frag_result_name(slot
));
2378 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2380 case VARYING_SLOT_POS
:
2381 so
->writes_pos
= true;
2383 case VARYING_SLOT_PSIZ
:
2384 so
->writes_psize
= true;
2386 case VARYING_SLOT_COL0
:
2387 case VARYING_SLOT_COL1
:
2388 case VARYING_SLOT_BFC0
:
2389 case VARYING_SLOT_BFC1
:
2390 case VARYING_SLOT_FOGC
:
2391 case VARYING_SLOT_CLIP_DIST0
:
2392 case VARYING_SLOT_CLIP_DIST1
:
2393 case VARYING_SLOT_CLIP_VERTEX
:
2396 if (slot
>= VARYING_SLOT_VAR0
)
2398 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
2400 compile_error(ctx
, "unknown VS output name: %s\n",
2401 gl_varying_slot_name(slot
));
2404 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2407 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
2409 so
->outputs
[n
].slot
= slot
;
2410 so
->outputs
[n
].regid
= regid(n
, comp
);
2411 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
2413 for (int i
= 0; i
< ncomp
; i
++) {
2414 unsigned idx
= (n
* 4) + i
;
2415 compile_assert(ctx
, idx
< ctx
->ir
->noutputs
);
2416 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
2421 max_drvloc(struct exec_list
*vars
)
2424 nir_foreach_variable(var
, vars
) {
2425 drvloc
= MAX2(drvloc
, (int)var
->data
.driver_location
);
2430 static const unsigned max_sysvals
[SHADER_MAX
] = {
2431 [SHADER_VERTEX
] = 16,
2432 [SHADER_COMPUTE
] = 16, // TODO how many do we actually need?
2436 emit_instructions(struct ir3_compile
*ctx
)
2438 unsigned ninputs
, noutputs
;
2439 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
2441 ninputs
= (max_drvloc(&ctx
->s
->inputs
) + 1) * 4;
2442 noutputs
= (max_drvloc(&ctx
->s
->outputs
) + 1) * 4;
2444 /* we need to leave room for sysvals:
2446 ninputs
+= max_sysvals
[ctx
->so
->type
];
2448 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
2450 /* Create inputs in first block: */
2451 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
2452 ctx
->in_block
= ctx
->block
;
2453 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
2455 ninputs
-= max_sysvals
[ctx
->so
->type
];
2457 /* for fragment shader, we have a single input register (usually
2458 * r0.xy) which is used as the base for bary.f varying fetch instrs:
2460 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2461 // TODO maybe a helper for fi since we need it a few places..
2462 struct ir3_instruction
*instr
;
2463 instr
= ir3_instr_create(ctx
->block
, OPC_META_FI
);
2464 ir3_reg_create(instr
, 0, 0);
2465 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.x */
2466 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.y */
2467 ctx
->frag_pos
= instr
;
2471 nir_foreach_variable(var
, &ctx
->s
->inputs
) {
2472 setup_input(ctx
, var
);
2475 /* Setup outputs: */
2476 nir_foreach_variable(var
, &ctx
->s
->outputs
) {
2477 setup_output(ctx
, var
);
2480 /* Setup global variables (which should only be arrays): */
2481 nir_foreach_variable(var
, &ctx
->s
->globals
) {
2482 declare_var(ctx
, var
);
2485 /* Setup local variables (which should only be arrays): */
2486 /* NOTE: need to do something more clever when we support >1 fxn */
2487 nir_foreach_variable(var
, &fxn
->locals
) {
2488 declare_var(ctx
, var
);
2491 /* And emit the body: */
2493 emit_function(ctx
, fxn
);
2495 list_for_each_entry (struct ir3_block
, block
, &ctx
->ir
->block_list
, node
) {
2496 resolve_phis(ctx
, block
);
2500 /* from NIR perspective, we actually have inputs. But most of the "inputs"
2501 * for a fragment shader are just bary.f instructions. The *actual* inputs
2502 * from the hw perspective are the frag_pos and optionally frag_coord and
2506 fixup_frag_inputs(struct ir3_compile
*ctx
)
2508 struct ir3_shader_variant
*so
= ctx
->so
;
2509 struct ir3
*ir
= ctx
->ir
;
2510 struct ir3_instruction
**inputs
;
2511 struct ir3_instruction
*instr
;
2516 n
= 4; /* always have frag_pos */
2517 n
+= COND(so
->frag_face
, 4);
2518 n
+= COND(so
->frag_coord
, 4);
2520 inputs
= ir3_alloc(ctx
->ir
, n
* (sizeof(struct ir3_instruction
*)));
2522 if (so
->frag_face
) {
2523 /* this ultimately gets assigned to hr0.x so doesn't conflict
2524 * with frag_coord/frag_pos..
2526 inputs
[ir
->ninputs
++] = ctx
->frag_face
;
2527 ctx
->frag_face
->regs
[0]->num
= 0;
2529 /* remaining channels not used, but let's avoid confusing
2530 * other parts that expect inputs to come in groups of vec4
2532 inputs
[ir
->ninputs
++] = NULL
;
2533 inputs
[ir
->ninputs
++] = NULL
;
2534 inputs
[ir
->ninputs
++] = NULL
;
2537 /* since we don't know where to set the regid for frag_coord,
2538 * we have to use r0.x for it. But we don't want to *always*
2539 * use r1.x for frag_pos as that could increase the register
2540 * footprint on simple shaders:
2542 if (so
->frag_coord
) {
2543 ctx
->frag_coord
[0]->regs
[0]->num
= regid
++;
2544 ctx
->frag_coord
[1]->regs
[0]->num
= regid
++;
2545 ctx
->frag_coord
[2]->regs
[0]->num
= regid
++;
2546 ctx
->frag_coord
[3]->regs
[0]->num
= regid
++;
2548 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[0];
2549 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[1];
2550 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[2];
2551 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[3];
2554 /* we always have frag_pos: */
2555 so
->pos_regid
= regid
;
2558 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2559 instr
->regs
[0]->num
= regid
++;
2560 inputs
[ir
->ninputs
++] = instr
;
2561 ctx
->frag_pos
->regs
[1]->instr
= instr
;
2564 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2565 instr
->regs
[0]->num
= regid
++;
2566 inputs
[ir
->ninputs
++] = instr
;
2567 ctx
->frag_pos
->regs
[2]->instr
= instr
;
2569 ir
->inputs
= inputs
;
2572 /* Fixup tex sampler state for astc/srgb workaround instructions. We
2573 * need to assign the tex state indexes for these after we know the
2577 fixup_astc_srgb(struct ir3_compile
*ctx
)
2579 struct ir3_shader_variant
*so
= ctx
->so
;
2580 /* indexed by original tex idx, value is newly assigned alpha sampler
2581 * state tex idx. Zero is invalid since there is at least one sampler
2584 unsigned alt_tex_state
[16] = {0};
2585 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
2588 so
->astc_srgb
.base
= tex_idx
;
2590 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
2591 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
2593 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
2595 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
2596 /* assign new alternate/alpha tex state slot: */
2597 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
2598 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
2599 so
->astc_srgb
.count
++;
2602 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
2607 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
2608 struct ir3_shader_variant
*so
)
2610 struct ir3_compile
*ctx
;
2612 struct ir3_instruction
**inputs
;
2613 unsigned i
, j
, actual_in
, inloc
;
2614 int ret
= 0, max_bary
;
2618 ctx
= compile_init(compiler
, so
);
2620 DBG("INIT failed!");
2625 emit_instructions(ctx
);
2628 DBG("EMIT failed!");
2633 ir
= so
->ir
= ctx
->ir
;
2635 /* keep track of the inputs from TGSI perspective.. */
2636 inputs
= ir
->inputs
;
2638 /* but fixup actual inputs for frag shader: */
2639 if (so
->type
== SHADER_FRAGMENT
)
2640 fixup_frag_inputs(ctx
);
2642 /* at this point, for binning pass, throw away unneeded outputs: */
2643 if (so
->key
.binning_pass
) {
2644 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
2645 unsigned slot
= so
->outputs
[i
].slot
;
2647 /* throw away everything but first position/psize */
2648 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
2650 so
->outputs
[j
] = so
->outputs
[i
];
2651 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
2652 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
2653 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
2654 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
2659 so
->outputs_count
= j
;
2660 ir
->noutputs
= j
* 4;
2663 /* if we want half-precision outputs, mark the output registers
2666 if (so
->key
.half_precision
) {
2667 for (i
= 0; i
< ir
->noutputs
; i
++) {
2668 struct ir3_instruction
*out
= ir
->outputs
[i
];
2673 /* if frag shader writes z, that needs to be full precision: */
2674 if (so
->outputs
[i
/4].slot
== FRAG_RESULT_DEPTH
)
2677 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2678 /* output could be a fanout (ie. texture fetch output)
2679 * in which case we need to propagate the half-reg flag
2680 * up to the definer so that RA sees it:
2682 if (out
->opc
== OPC_META_FO
) {
2683 out
= out
->regs
[1]->instr
;
2684 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2687 if (out
->opc
== OPC_MOV
) {
2688 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
2693 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2694 printf("BEFORE CP:\n");
2700 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2701 printf("BEFORE GROUPING:\n");
2705 /* Group left/right neighbors, inserting mov's where needed to
2712 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2713 printf("AFTER DEPTH:\n");
2717 ret
= ir3_sched(ir
);
2719 DBG("SCHED failed!");
2723 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2724 printf("AFTER SCHED:\n");
2728 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
2734 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2735 printf("AFTER RA:\n");
2739 /* fixup input/outputs: */
2740 for (i
= 0; i
< so
->outputs_count
; i
++) {
2741 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
2744 /* Note that some or all channels of an input may be unused: */
2747 for (i
= 0; i
< so
->inputs_count
; i
++) {
2748 unsigned j
, regid
= ~0, compmask
= 0, maxcomp
= 0;
2749 so
->inputs
[i
].ncomp
= 0;
2750 so
->inputs
[i
].inloc
= inloc
;
2751 for (j
= 0; j
< 4; j
++) {
2752 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
2753 if (in
&& !(in
->flags
& IR3_INSTR_UNUSED
)) {
2754 compmask
|= (1 << j
);
2755 regid
= in
->regs
[0]->num
- j
;
2757 so
->inputs
[i
].ncomp
++;
2758 if ((so
->type
== SHADER_FRAGMENT
) && so
->inputs
[i
].bary
) {
2760 assert(in
->regs
[1]->flags
& IR3_REG_IMMED
);
2761 in
->regs
[1]->iim_val
= inloc
+ j
;
2766 if ((so
->type
== SHADER_FRAGMENT
) && compmask
&& so
->inputs
[i
].bary
) {
2768 so
->inputs
[i
].compmask
= (1 << maxcomp
) - 1;
2771 so
->inputs
[i
].compmask
= compmask
;
2773 so
->inputs
[i
].regid
= regid
;
2777 fixup_astc_srgb(ctx
);
2779 /* We need to do legalize after (for frag shader's) the "bary.f"
2780 * offsets (inloc) have been assigned.
2782 ir3_legalize(ir
, &so
->has_samp
, &so
->has_ssbo
, &max_bary
);
2784 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2785 printf("AFTER LEGALIZE:\n");
2789 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
2790 if (so
->type
== SHADER_VERTEX
)
2791 so
->total_in
= actual_in
;
2793 so
->total_in
= max_bary
+ 1;
2798 ir3_destroy(so
->ir
);