1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
36 #include "freedreno_util.h"
38 #include "ir3_compiler.h"
39 #include "ir3_shader.h"
42 #include "instr-a3xx.h"
47 struct ir3_compiler
*compiler
;
52 struct ir3_shader_variant
*so
;
54 struct ir3_block
*block
; /* the current block */
55 struct ir3_block
*in_block
; /* block created for shader inputs */
57 nir_function_impl
*impl
;
59 /* For fragment shaders, from the hw perspective the only
60 * actual input is r0.xy position register passed to bary.f.
61 * But TGSI doesn't know that, it still declares things as
62 * IN[] registers. So we do all the input tracking normally
63 * and fix things up after compile_instructions()
65 * NOTE that frag_pos is the hardware position (possibly it
66 * is actually an index or tag or some such.. it is *not*
67 * values that can be directly used for gl_FragCoord..)
69 struct ir3_instruction
*frag_pos
, *frag_face
, *frag_coord
[4];
71 /* For vertex shaders, keep track of the system values sources */
72 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
74 /* For fragment shaders: */
75 struct ir3_instruction
*samp_id
, *samp_mask_in
;
77 /* Compute shader inputs: */
78 struct ir3_instruction
*local_invocation_id
, *work_group_id
;
80 /* mapping from nir_register to defining instruction: */
81 struct hash_table
*def_ht
;
85 /* a common pattern for indirect addressing is to request the
86 * same address register multiple times. To avoid generating
87 * duplicate instruction sequences (which our backend does not
88 * try to clean up, since that should be done as the NIR stage)
89 * we cache the address value generated for a given src value:
91 * Note that we have to cache these per alignment, since same
92 * src used for an array of vec1 cannot be also used for an
95 struct hash_table
*addr_ht
[4];
97 /* last dst array, for indirect we need to insert a var-store.
99 struct ir3_instruction
**last_dst
;
102 /* maps nir_block to ir3_block, mostly for the purposes of
103 * figuring out the blocks successors
105 struct hash_table
*block_ht
;
107 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
108 * so we need to use ldlv.u32 to load the varying directly:
112 /* on a3xx, we need to add one to # of array levels:
116 /* on a3xx, we need to scale up integer coords for isaml based
119 bool unminify_coords
;
121 /* on a3xx do txf_ms w/ isaml and scaled coords: */
122 bool txf_ms_with_isaml
;
124 /* on a4xx, for array textures we need to add 0.5 to the array
127 bool array_index_add_half
;
129 /* on a4xx, bitmask of samplers which need astc+srgb workaround: */
132 unsigned samples
; /* bitmask of x,y sample shifts */
134 unsigned max_texture_index
;
136 /* set if we encounter something we can't handle yet, so we
137 * can bail cleanly and fallback to TGSI compiler f/e
142 /* gpu pointer size in units of 32bit registers/slots */
143 static unsigned pointer_size(struct ir3_context
*ctx
)
145 return (ctx
->compiler
->gpu_id
>= 500) ? 2 : 1;
148 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
149 static struct ir3_block
* get_block(struct ir3_context
*ctx
, const nir_block
*nblock
);
152 static struct ir3_context
*
153 compile_init(struct ir3_compiler
*compiler
,
154 struct ir3_shader_variant
*so
)
156 struct ir3_context
*ctx
= rzalloc(NULL
, struct ir3_context
);
158 if (compiler
->gpu_id
>= 400) {
159 /* need special handling for "flat" */
160 ctx
->flat_bypass
= true;
161 ctx
->levels_add_one
= false;
162 ctx
->unminify_coords
= false;
163 ctx
->txf_ms_with_isaml
= false;
164 ctx
->array_index_add_half
= true;
166 if (so
->type
== SHADER_VERTEX
) {
167 ctx
->astc_srgb
= so
->key
.vastc_srgb
;
168 } else if (so
->type
== SHADER_FRAGMENT
) {
169 ctx
->astc_srgb
= so
->key
.fastc_srgb
;
173 /* no special handling for "flat" */
174 ctx
->flat_bypass
= false;
175 ctx
->levels_add_one
= true;
176 ctx
->unminify_coords
= true;
177 ctx
->txf_ms_with_isaml
= true;
178 ctx
->array_index_add_half
= false;
180 if (so
->type
== SHADER_VERTEX
) {
181 ctx
->samples
= so
->key
.vsamples
;
182 } else if (so
->type
== SHADER_FRAGMENT
) {
183 ctx
->samples
= so
->key
.fsamples
;
187 ctx
->compiler
= compiler
;
189 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
190 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
191 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
192 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
194 /* TODO: maybe generate some sort of bitmask of what key
195 * lowers vs what shader has (ie. no need to lower
196 * texture clamp lowering if no texture sample instrs)..
197 * although should be done further up the stack to avoid
198 * creating duplicate variants..
201 if (ir3_key_lowers_nir(&so
->key
)) {
202 nir_shader
*s
= nir_shader_clone(ctx
, so
->shader
->nir
);
203 ctx
->s
= ir3_optimize_nir(so
->shader
, s
, &so
->key
);
205 /* fast-path for shader key that lowers nothing in NIR: */
206 ctx
->s
= so
->shader
->nir
;
209 /* this needs to be the last pass run, so do this here instead of
210 * in ir3_optimize_nir():
212 NIR_PASS_V(ctx
->s
, nir_lower_locals_to_regs
);
213 NIR_PASS_V(ctx
->s
, nir_convert_from_ssa
, true);
215 if (fd_mesa_debug
& FD_DBG_DISASM
) {
216 DBG("dump nir%dv%d: type=%d, k={bp=%u,cts=%u,hp=%u}",
217 so
->shader
->id
, so
->id
, so
->type
,
218 so
->key
.binning_pass
, so
->key
.color_two_side
,
219 so
->key
.half_precision
);
220 nir_print_shader(ctx
->s
, stdout
);
223 ir3_nir_scan_driver_consts(ctx
->s
, &so
->const_layout
);
225 so
->num_uniforms
= ctx
->s
->num_uniforms
;
226 so
->num_ubos
= ctx
->s
->info
.num_ubos
;
228 /* Layout of constant registers, each section aligned to vec4. Note
229 * that pointer size (ubo, etc) changes depending on generation.
234 * if (vertex shader) {
235 * driver params (IR3_DP_*)
236 * if (stream_output.num_outputs > 0)
237 * stream-out addresses
241 * Immediates go last mostly because they are inserted in the CP pass
242 * after the nir -> ir3 frontend.
244 unsigned constoff
= align(ctx
->s
->num_uniforms
, 4);
245 unsigned ptrsz
= pointer_size(ctx
);
247 memset(&so
->constbase
, ~0, sizeof(so
->constbase
));
249 if (so
->num_ubos
> 0) {
250 so
->constbase
.ubo
= constoff
;
251 constoff
+= align(ctx
->s
->info
.num_ubos
* ptrsz
, 4) / 4;
254 if (so
->const_layout
.ssbo_size
.count
> 0) {
255 unsigned cnt
= so
->const_layout
.ssbo_size
.count
;
256 so
->constbase
.ssbo_sizes
= constoff
;
257 constoff
+= align(cnt
, 4) / 4;
260 if (so
->const_layout
.image_dims
.count
> 0) {
261 unsigned cnt
= so
->const_layout
.image_dims
.count
;
262 so
->constbase
.image_dims
= constoff
;
263 constoff
+= align(cnt
, 4) / 4;
266 unsigned num_driver_params
= 0;
267 if (so
->type
== SHADER_VERTEX
) {
268 num_driver_params
= IR3_DP_VS_COUNT
;
269 } else if (so
->type
== SHADER_COMPUTE
) {
270 num_driver_params
= IR3_DP_CS_COUNT
;
273 so
->constbase
.driver_param
= constoff
;
274 constoff
+= align(num_driver_params
, 4) / 4;
276 if ((so
->type
== SHADER_VERTEX
) &&
277 (compiler
->gpu_id
< 500) &&
278 so
->shader
->stream_output
.num_outputs
> 0) {
279 so
->constbase
.tfbo
= constoff
;
280 constoff
+= align(PIPE_MAX_SO_BUFFERS
* ptrsz
, 4) / 4;
283 so
->constbase
.immediate
= constoff
;
289 compile_error(struct ir3_context
*ctx
, const char *format
, ...)
292 va_start(ap
, format
);
293 _debug_vprintf(format
, ap
);
295 nir_print_shader(ctx
->s
, stdout
);
300 #define compile_assert(ctx, cond) do { \
301 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
305 compile_free(struct ir3_context
*ctx
)
311 declare_array(struct ir3_context
*ctx
, nir_register
*reg
)
313 struct ir3_array
*arr
= rzalloc(ctx
, struct ir3_array
);
314 arr
->id
= ++ctx
->num_arrays
;
315 /* NOTE: sometimes we get non array regs, for example for arrays of
316 * length 1. See fs-const-array-of-struct-of-array.shader_test. So
317 * treat a non-array as if it was an array of length 1.
319 * It would be nice if there was a nir pass to convert arrays of
322 arr
->length
= reg
->num_components
* MAX2(1, reg
->num_array_elems
);
323 compile_assert(ctx
, arr
->length
> 0);
325 list_addtail(&arr
->node
, &ctx
->ir
->array_list
);
328 static struct ir3_array
*
329 get_array(struct ir3_context
*ctx
, nir_register
*reg
)
331 list_for_each_entry (struct ir3_array
, arr
, &ctx
->ir
->array_list
, node
) {
335 compile_error(ctx
, "bogus reg: %s\n", reg
->name
);
339 /* relative (indirect) if address!=NULL */
340 static struct ir3_instruction
*
341 create_array_load(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
342 struct ir3_instruction
*address
)
344 struct ir3_block
*block
= ctx
->block
;
345 struct ir3_instruction
*mov
;
346 struct ir3_register
*src
;
348 mov
= ir3_instr_create(block
, OPC_MOV
);
349 mov
->cat1
.src_type
= TYPE_U32
;
350 mov
->cat1
.dst_type
= TYPE_U32
;
351 mov
->barrier_class
= IR3_BARRIER_ARRAY_R
;
352 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_W
;
353 ir3_reg_create(mov
, 0, 0);
354 src
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
355 COND(address
, IR3_REG_RELATIV
));
356 src
->instr
= arr
->last_write
;
357 src
->size
= arr
->length
;
358 src
->array
.id
= arr
->id
;
359 src
->array
.offset
= n
;
362 ir3_instr_set_address(mov
, address
);
367 /* relative (indirect) if address!=NULL */
369 create_array_store(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
370 struct ir3_instruction
*src
, struct ir3_instruction
*address
)
372 struct ir3_block
*block
= ctx
->block
;
373 struct ir3_instruction
*mov
;
374 struct ir3_register
*dst
;
376 /* if not relative store, don't create an extra mov, since that
377 * ends up being difficult for cp to remove.
382 src
->barrier_class
|= IR3_BARRIER_ARRAY_W
;
383 src
->barrier_conflict
|= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
385 dst
->flags
|= IR3_REG_ARRAY
;
386 dst
->instr
= arr
->last_write
;
387 dst
->size
= arr
->length
;
388 dst
->array
.id
= arr
->id
;
389 dst
->array
.offset
= n
;
391 arr
->last_write
= src
;
393 array_insert(block
, block
->keeps
, src
);
398 mov
= ir3_instr_create(block
, OPC_MOV
);
399 mov
->cat1
.src_type
= TYPE_U32
;
400 mov
->cat1
.dst_type
= TYPE_U32
;
401 mov
->barrier_class
= IR3_BARRIER_ARRAY_W
;
402 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
403 dst
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
404 COND(address
, IR3_REG_RELATIV
));
405 dst
->instr
= arr
->last_write
;
406 dst
->size
= arr
->length
;
407 dst
->array
.id
= arr
->id
;
408 dst
->array
.offset
= n
;
409 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
412 ir3_instr_set_address(mov
, address
);
414 arr
->last_write
= mov
;
416 /* the array store may only matter to something in an earlier
417 * block (ie. loops), but since arrays are not in SSA, depth
418 * pass won't know this.. so keep all array stores:
420 array_insert(block
, block
->keeps
, mov
);
423 static inline type_t
utype_for_size(unsigned bit_size
)
426 case 32: return TYPE_U32
;
427 case 16: return TYPE_U16
;
428 case 8: return TYPE_U8
;
429 default: unreachable("bad bitsize"); return ~0;
433 static inline type_t
utype_src(nir_src src
)
434 { return utype_for_size(nir_src_bit_size(src
)); }
436 static inline type_t
utype_dst(nir_dest dst
)
437 { return utype_for_size(nir_dest_bit_size(dst
)); }
439 /* allocate a n element value array (to be populated by caller) and
442 static struct ir3_instruction
**
443 get_dst_ssa(struct ir3_context
*ctx
, nir_ssa_def
*dst
, unsigned n
)
445 struct ir3_instruction
**value
=
446 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
447 _mesa_hash_table_insert(ctx
->def_ht
, dst
, value
);
451 static struct ir3_instruction
**
452 get_dst(struct ir3_context
*ctx
, nir_dest
*dst
, unsigned n
)
454 struct ir3_instruction
**value
;
457 value
= get_dst_ssa(ctx
, &dst
->ssa
, n
);
459 value
= ralloc_array(ctx
, struct ir3_instruction
*, n
);
462 /* NOTE: in non-ssa case, we don't really need to store last_dst
463 * but this helps us catch cases where put_dst() call is forgotten
465 compile_assert(ctx
, !ctx
->last_dst
);
466 ctx
->last_dst
= value
;
472 static struct ir3_instruction
* get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
);
474 static struct ir3_instruction
* const *
475 get_src(struct ir3_context
*ctx
, nir_src
*src
)
478 struct hash_entry
*entry
;
479 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
480 compile_assert(ctx
, entry
);
483 nir_register
*reg
= src
->reg
.reg
;
484 struct ir3_array
*arr
= get_array(ctx
, reg
);
485 unsigned num_components
= arr
->r
->num_components
;
486 struct ir3_instruction
*addr
= NULL
;
487 struct ir3_instruction
**value
=
488 ralloc_array(ctx
, struct ir3_instruction
*, num_components
);
490 if (src
->reg
.indirect
)
491 addr
= get_addr(ctx
, get_src(ctx
, src
->reg
.indirect
)[0],
492 reg
->num_components
);
494 for (unsigned i
= 0; i
< num_components
; i
++) {
495 unsigned n
= src
->reg
.base_offset
* reg
->num_components
+ i
;
496 compile_assert(ctx
, n
< arr
->length
);
497 value
[i
] = create_array_load(ctx
, arr
, n
, addr
);
505 put_dst(struct ir3_context
*ctx
, nir_dest
*dst
)
507 unsigned bit_size
= nir_dest_bit_size(*dst
);
510 for (unsigned i
= 0; i
< ctx
->last_dst_n
; i
++) {
511 struct ir3_instruction
*dst
= ctx
->last_dst
[i
];
512 dst
->regs
[0]->flags
|= IR3_REG_HALF
;
513 if (ctx
->last_dst
[i
]->opc
== OPC_META_FO
)
514 dst
->regs
[1]->instr
->regs
[0]->flags
|= IR3_REG_HALF
;
519 nir_register
*reg
= dst
->reg
.reg
;
520 struct ir3_array
*arr
= get_array(ctx
, reg
);
521 unsigned num_components
= ctx
->last_dst_n
;
522 struct ir3_instruction
*addr
= NULL
;
524 if (dst
->reg
.indirect
)
525 addr
= get_addr(ctx
, get_src(ctx
, dst
->reg
.indirect
)[0],
526 reg
->num_components
);
528 for (unsigned i
= 0; i
< num_components
; i
++) {
529 unsigned n
= dst
->reg
.base_offset
* reg
->num_components
+ i
;
530 compile_assert(ctx
, n
< arr
->length
);
531 if (!ctx
->last_dst
[i
])
533 create_array_store(ctx
, arr
, n
, ctx
->last_dst
[i
], addr
);
536 ralloc_free(ctx
->last_dst
);
538 ctx
->last_dst
= NULL
;
542 static struct ir3_instruction
*
543 create_immed_typed(struct ir3_block
*block
, uint32_t val
, type_t type
)
545 struct ir3_instruction
*mov
;
546 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
548 mov
= ir3_instr_create(block
, OPC_MOV
);
549 mov
->cat1
.src_type
= type
;
550 mov
->cat1
.dst_type
= type
;
551 ir3_reg_create(mov
, 0, flags
);
552 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
557 static struct ir3_instruction
*
558 create_immed(struct ir3_block
*block
, uint32_t val
)
560 return create_immed_typed(block
, val
, TYPE_U32
);
563 static struct ir3_instruction
*
564 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
, int align
)
566 struct ir3_instruction
*instr
, *immed
;
568 /* TODO in at least some cases, the backend could probably be
569 * made clever enough to propagate IR3_REG_HALF..
571 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
572 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
579 /* src *= 2 => src <<= 1: */
580 immed
= create_immed(block
, 1);
581 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
583 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
584 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
585 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
589 immed
= create_immed(block
, 3);
590 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
592 instr
= ir3_MULL_U(block
, instr
, 0, immed
, 0);
593 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
594 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
597 /* src *= 4 => src <<= 2: */
598 immed
= create_immed(block
, 2);
599 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
601 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
602 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
603 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
606 unreachable("bad align");
610 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
611 instr
->regs
[0]->num
= regid(REG_A0
, 0);
612 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
613 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
618 /* caches addr values to avoid generating multiple cov/shl/mova
619 * sequences for each use of a given NIR level src as address
621 static struct ir3_instruction
*
622 get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
)
624 struct ir3_instruction
*addr
;
625 unsigned idx
= align
- 1;
627 compile_assert(ctx
, idx
< ARRAY_SIZE(ctx
->addr_ht
));
629 if (!ctx
->addr_ht
[idx
]) {
630 ctx
->addr_ht
[idx
] = _mesa_hash_table_create(ctx
,
631 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
633 struct hash_entry
*entry
;
634 entry
= _mesa_hash_table_search(ctx
->addr_ht
[idx
], src
);
639 addr
= create_addr(ctx
->block
, src
, align
);
640 _mesa_hash_table_insert(ctx
->addr_ht
[idx
], src
, addr
);
645 static struct ir3_instruction
*
646 get_predicate(struct ir3_context
*ctx
, struct ir3_instruction
*src
)
648 struct ir3_block
*b
= ctx
->block
;
649 struct ir3_instruction
*cond
;
651 /* NOTE: only cmps.*.* can write p0.x: */
652 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
653 cond
->cat2
.condition
= IR3_COND_NE
;
655 /* condition always goes in predicate register: */
656 cond
->regs
[0]->num
= regid(REG_P0
, 0);
661 static struct ir3_instruction
*
662 create_uniform(struct ir3_context
*ctx
, unsigned n
)
664 struct ir3_instruction
*mov
;
666 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
667 /* TODO get types right? */
668 mov
->cat1
.src_type
= TYPE_F32
;
669 mov
->cat1
.dst_type
= TYPE_F32
;
670 ir3_reg_create(mov
, 0, 0);
671 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
676 static struct ir3_instruction
*
677 create_uniform_indirect(struct ir3_context
*ctx
, int n
,
678 struct ir3_instruction
*address
)
680 struct ir3_instruction
*mov
;
682 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
683 mov
->cat1
.src_type
= TYPE_U32
;
684 mov
->cat1
.dst_type
= TYPE_U32
;
685 ir3_reg_create(mov
, 0, 0);
686 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
688 ir3_instr_set_address(mov
, address
);
693 static struct ir3_instruction
*
694 create_collect(struct ir3_context
*ctx
, struct ir3_instruction
*const *arr
,
697 struct ir3_block
*block
= ctx
->block
;
698 struct ir3_instruction
*collect
;
703 unsigned flags
= arr
[0]->regs
[0]->flags
& IR3_REG_HALF
;
705 collect
= ir3_instr_create2(block
, OPC_META_FI
, 1 + arrsz
);
706 ir3_reg_create(collect
, 0, flags
); /* dst */
707 for (unsigned i
= 0; i
< arrsz
; i
++) {
708 struct ir3_instruction
*elem
= arr
[i
];
710 /* Since arrays are pre-colored in RA, we can't assume that
711 * things will end up in the right place. (Ie. if a collect
712 * joins elements from two different arrays.) So insert an
715 * We could possibly skip this if all the collected elements
716 * are contiguous elements in a single array.. not sure how
717 * likely that is to happen.
719 * Fixes a problem with glamor shaders, that in effect do
726 * color = texture2D(tex, texcoord);
728 * In this case, texcoord will end up as nir registers (which
729 * translate to ir3 array's of length 1. And we can't assume
730 * the two (or more) arrays will get allocated in consecutive
734 if (elem
->regs
[0]->flags
& IR3_REG_ARRAY
) {
735 type_t type
= (flags
& IR3_REG_HALF
) ? TYPE_U16
: TYPE_U32
;
736 elem
= ir3_MOV(block
, elem
, type
);
739 compile_assert(ctx
, (elem
->regs
[0]->flags
& IR3_REG_HALF
) == flags
);
740 ir3_reg_create(collect
, 0, IR3_REG_SSA
| flags
)->instr
= elem
;
746 static struct ir3_instruction
*
747 create_indirect_load(struct ir3_context
*ctx
, unsigned arrsz
, int n
,
748 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
750 struct ir3_block
*block
= ctx
->block
;
751 struct ir3_instruction
*mov
;
752 struct ir3_register
*src
;
754 mov
= ir3_instr_create(block
, OPC_MOV
);
755 mov
->cat1
.src_type
= TYPE_U32
;
756 mov
->cat1
.dst_type
= TYPE_U32
;
757 ir3_reg_create(mov
, 0, 0);
758 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
759 src
->instr
= collect
;
761 src
->array
.offset
= n
;
763 ir3_instr_set_address(mov
, address
);
768 static struct ir3_instruction
*
769 create_input_compmask(struct ir3_block
*block
, unsigned n
, unsigned compmask
)
771 struct ir3_instruction
*in
;
773 in
= ir3_instr_create(block
, OPC_META_INPUT
);
774 in
->inout
.block
= block
;
775 ir3_reg_create(in
, n
, 0);
777 in
->regs
[0]->wrmask
= compmask
;
782 static struct ir3_instruction
*
783 create_input(struct ir3_block
*block
, unsigned n
)
785 return create_input_compmask(block
, n
, 0x1);
788 static struct ir3_instruction
*
789 create_frag_input(struct ir3_context
*ctx
, bool use_ldlv
)
791 struct ir3_block
*block
= ctx
->block
;
792 struct ir3_instruction
*instr
;
793 /* actual inloc is assigned and fixed up later: */
794 struct ir3_instruction
*inloc
= create_immed(block
, 0);
797 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
798 instr
->cat6
.type
= TYPE_U32
;
799 instr
->cat6
.iim_val
= 1;
801 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_pos
, 0);
802 instr
->regs
[2]->wrmask
= 0x3;
808 static struct ir3_instruction
*
809 create_frag_coord(struct ir3_context
*ctx
, unsigned comp
)
811 struct ir3_block
*block
= ctx
->block
;
812 struct ir3_instruction
*instr
;
814 compile_assert(ctx
, !ctx
->frag_coord
[comp
]);
816 ctx
->frag_coord
[comp
] = create_input(ctx
->block
, 0);
821 /* for frag_coord, we get unsigned values.. we need
822 * to subtract (integer) 8 and divide by 16 (right-
823 * shift by 4) then convert to float:
827 * mov.u32f32 dst, tmp
830 instr
= ir3_SUB_S(block
, ctx
->frag_coord
[comp
], 0,
831 create_immed(block
, 8), 0);
832 instr
= ir3_SHR_B(block
, instr
, 0,
833 create_immed(block
, 4), 0);
834 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
840 /* seems that we can use these as-is: */
841 return ctx
->frag_coord
[comp
];
845 static struct ir3_instruction
*
846 create_driver_param(struct ir3_context
*ctx
, enum ir3_driver_param dp
)
848 /* first four vec4 sysval's reserved for UBOs: */
849 /* NOTE: dp is in scalar, but there can be >4 dp components: */
850 unsigned n
= ctx
->so
->constbase
.driver_param
;
851 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
852 return create_uniform(ctx
, r
);
855 /* helper for instructions that produce multiple consecutive scalar
856 * outputs which need to have a split/fanout meta instruction inserted
859 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
860 struct ir3_instruction
*src
, unsigned base
, unsigned n
)
862 struct ir3_instruction
*prev
= NULL
;
864 if ((n
== 1) && (src
->regs
[0]->wrmask
== 0x1)) {
869 for (int i
= 0, j
= 0; i
< n
; i
++) {
870 struct ir3_instruction
*split
= ir3_instr_create(block
, OPC_META_FO
);
871 ir3_reg_create(split
, 0, IR3_REG_SSA
);
872 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
873 split
->fo
.off
= i
+ base
;
876 split
->cp
.left
= prev
;
877 split
->cp
.left_cnt
++;
878 prev
->cp
.right
= split
;
879 prev
->cp
.right_cnt
++;
883 if (src
->regs
[0]->wrmask
& (1 << (i
+ base
)))
889 * Adreno uses uint rather than having dedicated bool type,
890 * which (potentially) requires some conversion, in particular
891 * when using output of an bool instr to int input, or visa
895 * -------+---------+-------+-
899 * To convert from an adreno bool (uint) to nir, use:
901 * absneg.s dst, (neg)src
903 * To convert back in the other direction:
905 * absneg.s dst, (abs)arc
907 * The CP step can clean up the absneg.s that cancel each other
908 * out, and with a slight bit of extra cleverness (to recognize
909 * the instructions which produce either a 0 or 1) can eliminate
910 * the absneg.s's completely when an instruction that wants
911 * 0/1 consumes the result. For example, when a nir 'bcsel'
912 * consumes the result of 'feq'. So we should be able to get by
913 * without a boolean resolve step, and without incuring any
914 * extra penalty in instruction count.
917 /* NIR bool -> native (adreno): */
918 static struct ir3_instruction
*
919 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
921 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
924 /* native (adreno) -> NIR bool: */
925 static struct ir3_instruction
*
926 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
928 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
932 * alu/sfu instructions:
935 static struct ir3_instruction
*
936 create_cov(struct ir3_context
*ctx
, struct ir3_instruction
*src
,
937 unsigned src_bitsize
, nir_op op
)
939 type_t src_type
, dst_type
;
943 case nir_op_f2f16_rtne
:
944 case nir_op_f2f16_rtz
:
945 case nir_op_f2f16_undef
:
952 switch (src_bitsize
) {
960 compile_error(ctx
, "invalid src bit size: %u", src_bitsize
);
969 switch (src_bitsize
) {
980 compile_error(ctx
, "invalid src bit size: %u", src_bitsize
);
989 switch (src_bitsize
) {
1000 compile_error(ctx
, "invalid src bit size: %u", src_bitsize
);
1005 compile_error(ctx
, "invalid conversion op: %u", op
);
1012 dst_type
= TYPE_F32
;
1015 case nir_op_f2f16_rtne
:
1016 case nir_op_f2f16_rtz
:
1017 case nir_op_f2f16_undef
:
1018 /* TODO how to handle rounding mode? */
1021 dst_type
= TYPE_F16
;
1026 dst_type
= TYPE_S32
;
1031 dst_type
= TYPE_S16
;
1041 dst_type
= TYPE_U32
;
1046 dst_type
= TYPE_U16
;
1055 compile_error(ctx
, "invalid conversion op: %u", op
);
1058 return ir3_COV(ctx
->block
, src
, src_type
, dst_type
);
1062 emit_alu(struct ir3_context
*ctx
, nir_alu_instr
*alu
)
1064 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
1065 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
1066 unsigned bs
[info
->num_inputs
]; /* bit size */
1067 struct ir3_block
*b
= ctx
->block
;
1068 unsigned dst_sz
, wrmask
;
1070 if (alu
->dest
.dest
.is_ssa
) {
1071 dst_sz
= alu
->dest
.dest
.ssa
.num_components
;
1072 wrmask
= (1 << dst_sz
) - 1;
1074 dst_sz
= alu
->dest
.dest
.reg
.reg
->num_components
;
1075 wrmask
= alu
->dest
.write_mask
;
1078 dst
= get_dst(ctx
, &alu
->dest
.dest
, dst_sz
);
1080 /* Vectors are special in that they have non-scalarized writemasks,
1081 * and just take the first swizzle channel for each argument in
1082 * order into each writemask channel.
1084 if ((alu
->op
== nir_op_vec2
) ||
1085 (alu
->op
== nir_op_vec3
) ||
1086 (alu
->op
== nir_op_vec4
)) {
1088 for (int i
= 0; i
< info
->num_inputs
; i
++) {
1089 nir_alu_src
*asrc
= &alu
->src
[i
];
1091 compile_assert(ctx
, !asrc
->abs
);
1092 compile_assert(ctx
, !asrc
->negate
);
1094 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
1096 src
[i
] = create_immed(ctx
->block
, 0);
1097 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
1100 put_dst(ctx
, &alu
->dest
.dest
);
1104 /* We also get mov's with more than one component for mov's so
1105 * handle those specially:
1107 if ((alu
->op
== nir_op_imov
) || (alu
->op
== nir_op_fmov
)) {
1108 type_t type
= (alu
->op
== nir_op_imov
) ? TYPE_U32
: TYPE_F32
;
1109 nir_alu_src
*asrc
= &alu
->src
[0];
1110 struct ir3_instruction
*const *src0
= get_src(ctx
, &asrc
->src
);
1112 for (unsigned i
= 0; i
< dst_sz
; i
++) {
1113 if (wrmask
& (1 << i
)) {
1114 dst
[i
] = ir3_MOV(b
, src0
[asrc
->swizzle
[i
]], type
);
1120 put_dst(ctx
, &alu
->dest
.dest
);
1124 /* General case: We can just grab the one used channel per src. */
1125 for (int i
= 0; i
< info
->num_inputs
; i
++) {
1126 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
1127 nir_alu_src
*asrc
= &alu
->src
[i
];
1129 compile_assert(ctx
, !asrc
->abs
);
1130 compile_assert(ctx
, !asrc
->negate
);
1132 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
1133 bs
[i
] = nir_src_bit_size(asrc
->src
);
1135 compile_assert(ctx
, src
[i
]);
1140 case nir_op_f2f16_rtne
:
1141 case nir_op_f2f16_rtz
:
1142 case nir_op_f2f16_undef
:
1159 dst
[0] = create_cov(ctx
, src
[0], bs
[0], alu
->op
);
1162 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
1163 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1164 dst
[0] = ir3_n2b(b
, dst
[0]);
1167 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
1170 dst
[0] = ir3_b2n(b
, src
[0]);
1173 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1174 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1175 dst
[0] = ir3_n2b(b
, dst
[0]);
1179 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
1182 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
1185 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
1188 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
1191 /* if there is just a single use of the src, and it supports
1192 * (sat) bit, we can just fold the (sat) flag back to the
1193 * src instruction and create a mov. This is easier for cp
1196 * TODO probably opc_cat==4 is ok too
1198 if (alu
->src
[0].src
.is_ssa
&&
1199 (list_length(&alu
->src
[0].src
.ssa
->uses
) == 1) &&
1200 ((opc_cat(src
[0]->opc
) == 2) || (opc_cat(src
[0]->opc
) == 3))) {
1201 src
[0]->flags
|= IR3_INSTR_SAT
;
1202 dst
[0] = ir3_MOV(b
, src
[0], TYPE_U32
);
1204 /* otherwise generate a max.f that saturates.. blob does
1205 * similar (generating a cat2 mov using max.f)
1207 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[0], 0);
1208 dst
[0]->flags
|= IR3_INSTR_SAT
;
1212 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
1215 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
1218 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
1221 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
1224 dst
[0] = ir3_DSX(b
, src
[0], 0);
1225 dst
[0]->cat5
.type
= TYPE_F32
;
1228 dst
[0] = ir3_DSY(b
, src
[0], 0);
1229 dst
[0]->cat5
.type
= TYPE_F32
;
1233 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1234 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1235 dst
[0] = ir3_n2b(b
, dst
[0]);
1238 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1239 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1240 dst
[0] = ir3_n2b(b
, dst
[0]);
1243 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1244 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1245 dst
[0] = ir3_n2b(b
, dst
[0]);
1248 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1249 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1250 dst
[0] = ir3_n2b(b
, dst
[0]);
1253 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
1256 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
1259 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
1261 case nir_op_fround_even
:
1262 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
1265 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
1269 dst
[0] = ir3_SIN(b
, src
[0], 0);
1272 dst
[0] = ir3_COS(b
, src
[0], 0);
1275 dst
[0] = ir3_RSQ(b
, src
[0], 0);
1278 dst
[0] = ir3_RCP(b
, src
[0], 0);
1281 dst
[0] = ir3_LOG2(b
, src
[0], 0);
1284 dst
[0] = ir3_EXP2(b
, src
[0], 0);
1287 dst
[0] = ir3_SQRT(b
, src
[0], 0);
1291 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
1294 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
1297 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
1300 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
1303 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
1306 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
1309 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
1313 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
1314 * mull.u tmp0, a, b ; mul low, i.e. al * bl
1315 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
1316 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
1318 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
1319 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
1320 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
1323 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
1326 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
1329 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
1332 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
1335 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
1337 case nir_op_isign
: {
1338 /* maybe this would be sane to lower in nir.. */
1339 struct ir3_instruction
*neg
, *pos
;
1341 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1342 neg
->cat2
.condition
= IR3_COND_LT
;
1344 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1345 pos
->cat2
.condition
= IR3_COND_GT
;
1347 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
1352 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
1355 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
1358 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
1361 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1362 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1363 dst
[0] = ir3_n2b(b
, dst
[0]);
1366 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1367 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1368 dst
[0] = ir3_n2b(b
, dst
[0]);
1371 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1372 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1373 dst
[0] = ir3_n2b(b
, dst
[0]);
1376 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1377 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1378 dst
[0] = ir3_n2b(b
, dst
[0]);
1381 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1382 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1383 dst
[0] = ir3_n2b(b
, dst
[0]);
1386 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1387 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1388 dst
[0] = ir3_n2b(b
, dst
[0]);
1391 case nir_op_bcsel
: {
1392 struct ir3_instruction
*cond
= ir3_b2n(b
, src
[0]);
1393 compile_assert(ctx
, bs
[1] == bs
[2]);
1394 /* the boolean condition is 32b even if src[1] and src[2] are
1395 * half-precision, but sel.b16 wants all three src's to be the
1399 cond
= ir3_COV(b
, cond
, TYPE_U32
, TYPE_U16
);
1400 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, cond
, 0, src
[2], 0);
1403 case nir_op_bit_count
:
1404 dst
[0] = ir3_CBITS_B(b
, src
[0], 0);
1406 case nir_op_ifind_msb
: {
1407 struct ir3_instruction
*cmp
;
1408 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
1409 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
1410 cmp
->cat2
.condition
= IR3_COND_GE
;
1411 dst
[0] = ir3_SEL_B32(b
,
1412 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1416 case nir_op_ufind_msb
:
1417 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
1418 dst
[0] = ir3_SEL_B32(b
,
1419 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1420 src
[0], 0, dst
[0], 0);
1422 case nir_op_find_lsb
:
1423 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1424 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
1426 case nir_op_bitfield_reverse
:
1427 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1431 compile_error(ctx
, "Unhandled ALU op: %s\n",
1432 nir_op_infos
[alu
->op
].name
);
1436 put_dst(ctx
, &alu
->dest
.dest
);
1439 /* handles direct/indirect UBO reads: */
1441 emit_intrinsic_load_ubo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1442 struct ir3_instruction
**dst
)
1444 struct ir3_block
*b
= ctx
->block
;
1445 struct ir3_instruction
*base_lo
, *base_hi
, *addr
, *src0
, *src1
;
1446 nir_const_value
*const_offset
;
1447 /* UBO addresses are the first driver params: */
1448 unsigned ubo
= regid(ctx
->so
->constbase
.ubo
, 0);
1449 const unsigned ptrsz
= pointer_size(ctx
);
1453 /* First src is ubo index, which could either be an immed or not: */
1454 src0
= get_src(ctx
, &intr
->src
[0])[0];
1455 if (is_same_type_mov(src0
) &&
1456 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1457 base_lo
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
));
1458 base_hi
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
) + 1);
1460 base_lo
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
, 4));
1461 base_hi
= create_uniform_indirect(ctx
, ubo
+ 1, get_addr(ctx
, src0
, 4));
1464 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
1467 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1469 off
+= const_offset
->u32
[0];
1471 /* For load_ubo_indirect, second src is indirect offset: */
1472 src1
= get_src(ctx
, &intr
->src
[1])[0];
1474 /* and add offset to addr: */
1475 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1478 /* if offset is to large to encode in the ldg, split it out: */
1479 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1480 /* split out the minimal amount to improve the odds that
1481 * cp can fit the immediate in the add.s instruction:
1483 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1484 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1489 struct ir3_instruction
*carry
;
1491 /* handle 32b rollover, ie:
1492 * if (addr < base_lo)
1495 carry
= ir3_CMPS_U(b
, addr
, 0, base_lo
, 0);
1496 carry
->cat2
.condition
= IR3_COND_LT
;
1497 base_hi
= ir3_ADD_S(b
, base_hi
, 0, carry
, 0);
1499 addr
= create_collect(ctx
, (struct ir3_instruction
*[]){ addr
, base_hi
}, 2);
1502 for (int i
= 0; i
< intr
->num_components
; i
++) {
1503 struct ir3_instruction
*load
=
1504 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1505 load
->cat6
.type
= TYPE_U32
;
1506 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
1511 /* src[] = { buffer_index, offset }. No const_index */
1513 emit_intrinsic_load_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1514 struct ir3_instruction
**dst
)
1516 struct ir3_block
*b
= ctx
->block
;
1517 struct ir3_instruction
*ldgb
, *src0
, *src1
, *offset
;
1518 nir_const_value
*const_offset
;
1520 /* can this be non-const buffer_index? how do we handle that? */
1521 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1522 compile_assert(ctx
, const_offset
);
1524 offset
= get_src(ctx
, &intr
->src
[1])[0];
1526 /* src0 is uvec2(offset*4, 0), src1 is offset.. nir already *= 4: */
1527 src0
= create_collect(ctx
, (struct ir3_instruction
*[]){
1531 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1533 ldgb
= ir3_LDGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1535 ldgb
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1536 ldgb
->cat6
.iim_val
= intr
->num_components
;
1538 ldgb
->cat6
.type
= TYPE_U32
;
1539 ldgb
->barrier_class
= IR3_BARRIER_BUFFER_R
;
1540 ldgb
->barrier_conflict
= IR3_BARRIER_BUFFER_W
;
1542 split_dest(b
, dst
, ldgb
, 0, intr
->num_components
);
1545 /* src[] = { value, block_index, offset }. const_index[] = { write_mask } */
1547 emit_intrinsic_store_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1549 struct ir3_block
*b
= ctx
->block
;
1550 struct ir3_instruction
*stgb
, *src0
, *src1
, *src2
, *offset
;
1551 nir_const_value
*const_offset
;
1552 /* TODO handle wrmask properly, see _store_shared().. but I think
1553 * it is more a PITA than that, since blob ends up loading the
1554 * masked components and writing them back out.
1556 unsigned wrmask
= intr
->const_index
[0];
1557 unsigned ncomp
= ffs(~wrmask
) - 1;
1559 /* can this be non-const buffer_index? how do we handle that? */
1560 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1561 compile_assert(ctx
, const_offset
);
1563 offset
= get_src(ctx
, &intr
->src
[2])[0];
1565 /* src0 is value, src1 is offset, src2 is uvec2(offset*4, 0)..
1568 src0
= create_collect(ctx
, get_src(ctx
, &intr
->src
[0]), ncomp
);
1569 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1570 src2
= create_collect(ctx
, (struct ir3_instruction
*[]){
1575 stgb
= ir3_STGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1576 src0
, 0, src1
, 0, src2
, 0);
1577 stgb
->cat6
.iim_val
= ncomp
;
1579 stgb
->cat6
.type
= TYPE_U32
;
1580 stgb
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1581 stgb
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1583 array_insert(b
, b
->keeps
, stgb
);
1586 /* src[] = { block_index } */
1588 emit_intrinsic_ssbo_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1589 struct ir3_instruction
**dst
)
1591 /* SSBO size stored as a const starting at ssbo_sizes: */
1592 unsigned blk_idx
= nir_src_as_const_value(intr
->src
[0])->u32
[0];
1593 unsigned idx
= regid(ctx
->so
->constbase
.ssbo_sizes
, 0) +
1594 ctx
->so
->const_layout
.ssbo_size
.off
[blk_idx
];
1596 debug_assert(ctx
->so
->const_layout
.ssbo_size
.mask
& (1 << blk_idx
));
1598 dst
[0] = create_uniform(ctx
, idx
);
1602 * SSBO atomic intrinsics
1604 * All of the SSBO atomic memory operations read a value from memory,
1605 * compute a new value using one of the operations below, write the new
1606 * value to memory, and return the original value read.
1608 * All operations take 3 sources except CompSwap that takes 4. These
1609 * sources represent:
1611 * 0: The SSBO buffer index.
1612 * 1: The offset into the SSBO buffer of the variable that the atomic
1613 * operation will operate on.
1614 * 2: The data parameter to the atomic function (i.e. the value to add
1615 * in ssbo_atomic_add, etc).
1616 * 3: For CompSwap only: the second data parameter.
1618 static struct ir3_instruction
*
1619 emit_intrinsic_atomic_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1621 struct ir3_block
*b
= ctx
->block
;
1622 struct ir3_instruction
*atomic
, *ssbo
, *src0
, *src1
, *src2
, *offset
;
1623 nir_const_value
*const_offset
;
1624 type_t type
= TYPE_U32
;
1626 /* can this be non-const buffer_index? how do we handle that? */
1627 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1628 compile_assert(ctx
, const_offset
);
1629 ssbo
= create_immed(b
, const_offset
->u32
[0]);
1631 offset
= get_src(ctx
, &intr
->src
[1])[0];
1633 /* src0 is data (or uvec2(data, compare))
1635 * src2 is uvec2(offset*4, 0) (appears to be 64b byte offset)
1637 * Note that nir already multiplies the offset by four
1639 src0
= get_src(ctx
, &intr
->src
[2])[0];
1640 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1641 src2
= create_collect(ctx
, (struct ir3_instruction
*[]){
1646 switch (intr
->intrinsic
) {
1647 case nir_intrinsic_ssbo_atomic_add
:
1648 atomic
= ir3_ATOMIC_ADD_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1650 case nir_intrinsic_ssbo_atomic_imin
:
1651 atomic
= ir3_ATOMIC_MIN_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1654 case nir_intrinsic_ssbo_atomic_umin
:
1655 atomic
= ir3_ATOMIC_MIN_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1657 case nir_intrinsic_ssbo_atomic_imax
:
1658 atomic
= ir3_ATOMIC_MAX_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1661 case nir_intrinsic_ssbo_atomic_umax
:
1662 atomic
= ir3_ATOMIC_MAX_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1664 case nir_intrinsic_ssbo_atomic_and
:
1665 atomic
= ir3_ATOMIC_AND_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1667 case nir_intrinsic_ssbo_atomic_or
:
1668 atomic
= ir3_ATOMIC_OR_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1670 case nir_intrinsic_ssbo_atomic_xor
:
1671 atomic
= ir3_ATOMIC_XOR_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1673 case nir_intrinsic_ssbo_atomic_exchange
:
1674 atomic
= ir3_ATOMIC_XCHG_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1676 case nir_intrinsic_ssbo_atomic_comp_swap
:
1677 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
1678 src0
= create_collect(ctx
, (struct ir3_instruction
*[]){
1680 get_src(ctx
, &intr
->src
[3])[0],
1682 atomic
= ir3_ATOMIC_CMPXCHG_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1688 atomic
->cat6
.iim_val
= 1;
1690 atomic
->cat6
.type
= type
;
1691 atomic
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1692 atomic
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1694 /* even if nothing consume the result, we can't DCE the instruction: */
1695 array_insert(b
, b
->keeps
, atomic
);
1700 /* src[] = { offset }. const_index[] = { base } */
1702 emit_intrinsic_load_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1703 struct ir3_instruction
**dst
)
1705 struct ir3_block
*b
= ctx
->block
;
1706 struct ir3_instruction
*ldl
, *offset
;
1709 offset
= get_src(ctx
, &intr
->src
[0])[0];
1710 base
= nir_intrinsic_base(intr
);
1712 ldl
= ir3_LDL(b
, offset
, 0, create_immed(b
, intr
->num_components
), 0);
1713 ldl
->cat6
.src_offset
= base
;
1714 ldl
->cat6
.type
= utype_dst(intr
->dest
);
1715 ldl
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1717 ldl
->barrier_class
= IR3_BARRIER_SHARED_R
;
1718 ldl
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
1720 split_dest(b
, dst
, ldl
, 0, intr
->num_components
);
1723 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
1725 emit_intrinsic_store_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1727 struct ir3_block
*b
= ctx
->block
;
1728 struct ir3_instruction
*stl
, *offset
;
1729 struct ir3_instruction
* const *value
;
1730 unsigned base
, wrmask
;
1732 value
= get_src(ctx
, &intr
->src
[0]);
1733 offset
= get_src(ctx
, &intr
->src
[1])[0];
1735 base
= nir_intrinsic_base(intr
);
1736 wrmask
= nir_intrinsic_write_mask(intr
);
1738 /* Combine groups of consecutive enabled channels in one write
1739 * message. We use ffs to find the first enabled channel and then ffs on
1740 * the bit-inverse, down-shifted writemask to determine the length of
1741 * the block of enabled bits.
1743 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
1746 unsigned first_component
= ffs(wrmask
) - 1;
1747 unsigned length
= ffs(~(wrmask
>> first_component
)) - 1;
1749 stl
= ir3_STL(b
, offset
, 0,
1750 create_collect(ctx
, &value
[first_component
], length
), 0,
1751 create_immed(b
, length
), 0);
1752 stl
->cat6
.dst_offset
= first_component
+ base
;
1753 stl
->cat6
.type
= utype_src(intr
->src
[0]);
1754 stl
->barrier_class
= IR3_BARRIER_SHARED_W
;
1755 stl
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1757 array_insert(b
, b
->keeps
, stl
);
1759 /* Clear the bits in the writemask that we just wrote, then try
1760 * again to see if more channels are left.
1762 wrmask
&= (15 << (first_component
+ length
));
1767 * CS shared variable atomic intrinsics
1769 * All of the shared variable atomic memory operations read a value from
1770 * memory, compute a new value using one of the operations below, write the
1771 * new value to memory, and return the original value read.
1773 * All operations take 2 sources except CompSwap that takes 3. These
1774 * sources represent:
1776 * 0: The offset into the shared variable storage region that the atomic
1777 * operation will operate on.
1778 * 1: The data parameter to the atomic function (i.e. the value to add
1779 * in shared_atomic_add, etc).
1780 * 2: For CompSwap only: the second data parameter.
1782 static struct ir3_instruction
*
1783 emit_intrinsic_atomic_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1785 struct ir3_block
*b
= ctx
->block
;
1786 struct ir3_instruction
*atomic
, *src0
, *src1
;
1787 type_t type
= TYPE_U32
;
1789 src0
= get_src(ctx
, &intr
->src
[0])[0]; /* offset */
1790 src1
= get_src(ctx
, &intr
->src
[1])[0]; /* value */
1792 switch (intr
->intrinsic
) {
1793 case nir_intrinsic_shared_atomic_add
:
1794 atomic
= ir3_ATOMIC_ADD(b
, src0
, 0, src1
, 0);
1796 case nir_intrinsic_shared_atomic_imin
:
1797 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1800 case nir_intrinsic_shared_atomic_umin
:
1801 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1803 case nir_intrinsic_shared_atomic_imax
:
1804 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1807 case nir_intrinsic_shared_atomic_umax
:
1808 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1810 case nir_intrinsic_shared_atomic_and
:
1811 atomic
= ir3_ATOMIC_AND(b
, src0
, 0, src1
, 0);
1813 case nir_intrinsic_shared_atomic_or
:
1814 atomic
= ir3_ATOMIC_OR(b
, src0
, 0, src1
, 0);
1816 case nir_intrinsic_shared_atomic_xor
:
1817 atomic
= ir3_ATOMIC_XOR(b
, src0
, 0, src1
, 0);
1819 case nir_intrinsic_shared_atomic_exchange
:
1820 atomic
= ir3_ATOMIC_XCHG(b
, src0
, 0, src1
, 0);
1822 case nir_intrinsic_shared_atomic_comp_swap
:
1823 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1824 src1
= create_collect(ctx
, (struct ir3_instruction
*[]){
1825 get_src(ctx
, &intr
->src
[2])[0],
1828 atomic
= ir3_ATOMIC_CMPXCHG(b
, src0
, 0, src1
, 0);
1834 atomic
->cat6
.iim_val
= 1;
1836 atomic
->cat6
.type
= type
;
1837 atomic
->barrier_class
= IR3_BARRIER_SHARED_W
;
1838 atomic
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1840 /* even if nothing consume the result, we can't DCE the instruction: */
1841 array_insert(b
, b
->keeps
, atomic
);
1846 /* Images get mapped into SSBO/image state (for store/atomic) and texture
1847 * state block (for load). To simplify things, invert the image id and
1848 * map it from end of state block, ie. image 0 becomes num-1, image 1
1849 * becomes num-2, etc. This potentially avoids needing to re-emit texture
1850 * state when switching shaders.
1852 * TODO is max # of samplers and SSBOs the same. This shouldn't be hard-
1853 * coded. Also, since all the gl shader stages (ie. everything but CS)
1854 * share the same SSBO/image state block, this might require some more
1855 * logic if we supported images in anything other than FS..
1858 get_image_slot(struct ir3_context
*ctx
, nir_deref_instr
*deref
)
1860 unsigned int loc
= 0;
1861 unsigned inner_size
= 1;
1863 while (deref
->deref_type
!= nir_deref_type_var
) {
1864 assert(deref
->deref_type
== nir_deref_type_array
);
1865 nir_const_value
*const_index
= nir_src_as_const_value(deref
->arr
.index
);
1866 assert(const_index
);
1868 /* Go to the next instruction */
1869 deref
= nir_deref_instr_parent(deref
);
1871 assert(glsl_type_is_array(deref
->type
));
1872 const unsigned array_len
= glsl_get_length(deref
->type
);
1873 loc
+= MIN2(const_index
->u32
[0], array_len
- 1) * inner_size
;
1875 /* Update the inner size */
1876 inner_size
*= array_len
;
1879 loc
+= deref
->var
->data
.driver_location
;
1881 /* TODO figure out real limit per generation, and don't hardcode: */
1882 const unsigned max_samplers
= 16;
1883 return max_samplers
- loc
- 1;
1886 /* see tex_info() for equiv logic for texture instructions.. it would be
1887 * nice if this could be better unified..
1890 get_image_coords(const nir_variable
*var
, unsigned *flagsp
)
1892 const struct glsl_type
*type
= glsl_without_array(var
->type
);
1893 unsigned coords
, flags
= 0;
1895 switch (glsl_get_sampler_dim(type
)) {
1896 case GLSL_SAMPLER_DIM_1D
:
1897 case GLSL_SAMPLER_DIM_BUF
:
1900 case GLSL_SAMPLER_DIM_2D
:
1901 case GLSL_SAMPLER_DIM_RECT
:
1902 case GLSL_SAMPLER_DIM_EXTERNAL
:
1903 case GLSL_SAMPLER_DIM_MS
:
1906 case GLSL_SAMPLER_DIM_3D
:
1907 case GLSL_SAMPLER_DIM_CUBE
:
1908 flags
|= IR3_INSTR_3D
;
1912 unreachable("bad sampler dim");
1916 if (glsl_sampler_type_is_array(type
)) {
1917 /* note: unlike tex_info(), adjust # of coords to include array idx: */
1919 flags
|= IR3_INSTR_A
;
1929 get_image_type(const nir_variable
*var
)
1931 switch (glsl_get_sampler_result_type(glsl_without_array(var
->type
))) {
1932 case GLSL_TYPE_UINT
:
1936 case GLSL_TYPE_FLOAT
:
1939 unreachable("bad sampler type.");
1944 static struct ir3_instruction
*
1945 get_image_offset(struct ir3_context
*ctx
, const nir_variable
*var
,
1946 struct ir3_instruction
* const *coords
, bool byteoff
)
1948 struct ir3_block
*b
= ctx
->block
;
1949 struct ir3_instruction
*offset
;
1950 unsigned ncoords
= get_image_coords(var
, NULL
);
1952 /* to calculate the byte offset (yes, uggg) we need (up to) three
1953 * const values to know the bytes per pixel, and y and z stride:
1955 unsigned cb
= regid(ctx
->so
->constbase
.image_dims
, 0) +
1956 ctx
->so
->const_layout
.image_dims
.off
[var
->data
.driver_location
];
1958 debug_assert(ctx
->so
->const_layout
.image_dims
.mask
&
1959 (1 << var
->data
.driver_location
));
1961 /* offset = coords.x * bytes_per_pixel: */
1962 offset
= ir3_MUL_S(b
, coords
[0], 0, create_uniform(ctx
, cb
+ 0), 0);
1964 /* offset += coords.y * y_pitch: */
1965 offset
= ir3_MAD_S24(b
, create_uniform(ctx
, cb
+ 1), 0,
1966 coords
[1], 0, offset
, 0);
1969 /* offset += coords.z * z_pitch: */
1970 offset
= ir3_MAD_S24(b
, create_uniform(ctx
, cb
+ 2), 0,
1971 coords
[2], 0, offset
, 0);
1975 /* Some cases, like atomics, seem to use dword offset instead
1976 * of byte offsets.. blob just puts an extra shr.b in there
1979 offset
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1982 return create_collect(ctx
, (struct ir3_instruction
*[]){
1988 /* src[] = { coord, sample_index }. const_index[] = {} */
1990 emit_intrinsic_load_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1991 struct ir3_instruction
**dst
)
1993 struct ir3_block
*b
= ctx
->block
;
1994 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
1995 struct ir3_instruction
*sam
;
1996 struct ir3_instruction
* const *src0
= get_src(ctx
, &intr
->src
[0]);
1997 struct ir3_instruction
*coords
[4];
1998 unsigned flags
, ncoords
= get_image_coords(var
, &flags
);
1999 unsigned tex_idx
= get_image_slot(ctx
, var
);
2000 type_t type
= get_image_type(var
);
2002 /* hmm, this seems a bit odd, but it is what blob does and (at least
2003 * a5xx) just faults on bogus addresses otherwise:
2005 if (flags
& IR3_INSTR_3D
) {
2006 flags
&= ~IR3_INSTR_3D
;
2007 flags
|= IR3_INSTR_A
;
2010 for (unsigned i
= 0; i
< ncoords
; i
++)
2011 coords
[i
] = src0
[i
];
2014 coords
[ncoords
++] = create_immed(b
, 0);
2016 sam
= ir3_SAM(b
, OPC_ISAM
, type
, TGSI_WRITEMASK_XYZW
, flags
,
2017 tex_idx
, tex_idx
, create_collect(ctx
, coords
, ncoords
), NULL
);
2019 sam
->barrier_class
= IR3_BARRIER_IMAGE_R
;
2020 sam
->barrier_conflict
= IR3_BARRIER_IMAGE_W
;
2022 split_dest(b
, dst
, sam
, 0, 4);
2025 /* src[] = { coord, sample_index, value }. const_index[] = {} */
2027 emit_intrinsic_store_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
2029 struct ir3_block
*b
= ctx
->block
;
2030 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
2031 struct ir3_instruction
*stib
, *offset
;
2032 struct ir3_instruction
* const *value
= get_src(ctx
, &intr
->src
[2]);
2033 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[0]);
2034 unsigned ncoords
= get_image_coords(var
, NULL
);
2035 unsigned tex_idx
= get_image_slot(ctx
, var
);
2039 * src2 is 64b byte offset
2042 offset
= get_image_offset(ctx
, var
, coords
, true);
2044 /* NOTE: stib seems to take byte offset, but stgb.typed can be used
2045 * too and takes a dword offset.. not quite sure yet why blob uses
2046 * one over the other in various cases.
2049 stib
= ir3_STIB(b
, create_immed(b
, tex_idx
), 0,
2050 create_collect(ctx
, value
, 4), 0,
2051 create_collect(ctx
, coords
, ncoords
), 0,
2053 stib
->cat6
.iim_val
= 4;
2054 stib
->cat6
.d
= ncoords
;
2055 stib
->cat6
.type
= get_image_type(var
);
2056 stib
->cat6
.typed
= true;
2057 stib
->barrier_class
= IR3_BARRIER_IMAGE_W
;
2058 stib
->barrier_conflict
= IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
;
2060 array_insert(b
, b
->keeps
, stib
);
2064 emit_intrinsic_image_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
2065 struct ir3_instruction
**dst
)
2067 struct ir3_block
*b
= ctx
->block
;
2068 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
2069 unsigned tex_idx
= get_image_slot(ctx
, var
);
2070 struct ir3_instruction
*sam
, *lod
;
2071 unsigned flags
, ncoords
= get_image_coords(var
, &flags
);
2073 lod
= create_immed(b
, 0);
2074 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
2075 tex_idx
, tex_idx
, lod
, NULL
);
2077 /* Array size actually ends up in .w rather than .z. This doesn't
2078 * matter for miplevel 0, but for higher mips the value in z is
2079 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2080 * returned, which means that we have to add 1 to it for arrays for
2083 * Note use a temporary dst and then copy, since the size of the dst
2084 * array that is passed in is based on nir's understanding of the
2085 * result size, not the hardware's
2087 struct ir3_instruction
*tmp
[4];
2089 split_dest(b
, tmp
, sam
, 0, 4);
2091 for (unsigned i
= 0; i
< ncoords
; i
++)
2094 if (flags
& IR3_INSTR_A
) {
2095 if (ctx
->levels_add_one
) {
2096 dst
[ncoords
-1] = ir3_ADD_U(b
, tmp
[3], 0, create_immed(b
, 1), 0);
2098 dst
[ncoords
-1] = ir3_MOV(b
, tmp
[3], TYPE_U32
);
2103 /* src[] = { coord, sample_index, value, compare }. const_index[] = {} */
2104 static struct ir3_instruction
*
2105 emit_intrinsic_atomic_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
2107 struct ir3_block
*b
= ctx
->block
;
2108 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
2109 struct ir3_instruction
*atomic
, *image
, *src0
, *src1
, *src2
;
2110 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[0]);
2111 unsigned ncoords
= get_image_coords(var
, NULL
);
2113 image
= create_immed(b
, get_image_slot(ctx
, var
));
2115 /* src0 is value (or uvec2(value, compare))
2117 * src2 is 64b byte offset
2119 src0
= get_src(ctx
, &intr
->src
[2])[0];
2120 src1
= create_collect(ctx
, coords
, ncoords
);
2121 src2
= get_image_offset(ctx
, var
, coords
, false);
2123 switch (intr
->intrinsic
) {
2124 case nir_intrinsic_image_deref_atomic_add
:
2125 atomic
= ir3_ATOMIC_ADD_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2127 case nir_intrinsic_image_deref_atomic_min
:
2128 atomic
= ir3_ATOMIC_MIN_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2130 case nir_intrinsic_image_deref_atomic_max
:
2131 atomic
= ir3_ATOMIC_MAX_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2133 case nir_intrinsic_image_deref_atomic_and
:
2134 atomic
= ir3_ATOMIC_AND_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2136 case nir_intrinsic_image_deref_atomic_or
:
2137 atomic
= ir3_ATOMIC_OR_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2139 case nir_intrinsic_image_deref_atomic_xor
:
2140 atomic
= ir3_ATOMIC_XOR_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2142 case nir_intrinsic_image_deref_atomic_exchange
:
2143 atomic
= ir3_ATOMIC_XCHG_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2145 case nir_intrinsic_image_deref_atomic_comp_swap
:
2146 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
2147 src0
= create_collect(ctx
, (struct ir3_instruction
*[]){
2149 get_src(ctx
, &intr
->src
[3])[0],
2151 atomic
= ir3_ATOMIC_CMPXCHG_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2157 atomic
->cat6
.iim_val
= 1;
2158 atomic
->cat6
.d
= ncoords
;
2159 atomic
->cat6
.type
= get_image_type(var
);
2160 atomic
->cat6
.typed
= true;
2161 atomic
->barrier_class
= IR3_BARRIER_IMAGE_W
;
2162 atomic
->barrier_conflict
= IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
;
2164 /* even if nothing consume the result, we can't DCE the instruction: */
2165 array_insert(b
, b
->keeps
, atomic
);
2171 emit_intrinsic_barrier(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
2173 struct ir3_block
*b
= ctx
->block
;
2174 struct ir3_instruction
*barrier
;
2176 switch (intr
->intrinsic
) {
2177 case nir_intrinsic_barrier
:
2178 barrier
= ir3_BAR(b
);
2179 barrier
->cat7
.g
= true;
2180 barrier
->cat7
.l
= true;
2181 barrier
->flags
= IR3_INSTR_SS
| IR3_INSTR_SY
;
2182 barrier
->barrier_class
= IR3_BARRIER_EVERYTHING
;
2184 case nir_intrinsic_memory_barrier
:
2185 barrier
= ir3_FENCE(b
);
2186 barrier
->cat7
.g
= true;
2187 barrier
->cat7
.r
= true;
2188 barrier
->cat7
.w
= true;
2189 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
|
2190 IR3_BARRIER_BUFFER_W
;
2191 barrier
->barrier_conflict
=
2192 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
2193 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
2195 case nir_intrinsic_memory_barrier_atomic_counter
:
2196 case nir_intrinsic_memory_barrier_buffer
:
2197 barrier
= ir3_FENCE(b
);
2198 barrier
->cat7
.g
= true;
2199 barrier
->cat7
.r
= true;
2200 barrier
->cat7
.w
= true;
2201 barrier
->barrier_class
= IR3_BARRIER_BUFFER_W
;
2202 barrier
->barrier_conflict
= IR3_BARRIER_BUFFER_R
|
2203 IR3_BARRIER_BUFFER_W
;
2205 case nir_intrinsic_memory_barrier_image
:
2206 // TODO double check if this should have .g set
2207 barrier
= ir3_FENCE(b
);
2208 barrier
->cat7
.g
= true;
2209 barrier
->cat7
.r
= true;
2210 barrier
->cat7
.w
= true;
2211 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
;
2212 barrier
->barrier_conflict
= IR3_BARRIER_IMAGE_R
|
2213 IR3_BARRIER_IMAGE_W
;
2215 case nir_intrinsic_memory_barrier_shared
:
2216 barrier
= ir3_FENCE(b
);
2217 barrier
->cat7
.g
= true;
2218 barrier
->cat7
.l
= true;
2219 barrier
->cat7
.r
= true;
2220 barrier
->cat7
.w
= true;
2221 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
;
2222 barrier
->barrier_conflict
= IR3_BARRIER_SHARED_R
|
2223 IR3_BARRIER_SHARED_W
;
2225 case nir_intrinsic_group_memory_barrier
:
2226 barrier
= ir3_FENCE(b
);
2227 barrier
->cat7
.g
= true;
2228 barrier
->cat7
.l
= true;
2229 barrier
->cat7
.r
= true;
2230 barrier
->cat7
.w
= true;
2231 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
|
2232 IR3_BARRIER_IMAGE_W
|
2233 IR3_BARRIER_BUFFER_W
;
2234 barrier
->barrier_conflict
=
2235 IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
|
2236 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
2237 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
2243 /* make sure barrier doesn't get DCE'd */
2244 array_insert(b
, b
->keeps
, barrier
);
2247 static void add_sysval_input_compmask(struct ir3_context
*ctx
,
2248 gl_system_value slot
, unsigned compmask
,
2249 struct ir3_instruction
*instr
)
2251 struct ir3_shader_variant
*so
= ctx
->so
;
2252 unsigned r
= regid(so
->inputs_count
, 0);
2253 unsigned n
= so
->inputs_count
++;
2255 so
->inputs
[n
].sysval
= true;
2256 so
->inputs
[n
].slot
= slot
;
2257 so
->inputs
[n
].compmask
= compmask
;
2258 so
->inputs
[n
].regid
= r
;
2259 so
->inputs
[n
].interpolate
= INTERP_MODE_FLAT
;
2262 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
2263 ctx
->ir
->inputs
[r
] = instr
;
2266 static void add_sysval_input(struct ir3_context
*ctx
, gl_system_value slot
,
2267 struct ir3_instruction
*instr
)
2269 add_sysval_input_compmask(ctx
, slot
, 0x1, instr
);
2273 emit_intrinsic(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
2275 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
2276 struct ir3_instruction
**dst
;
2277 struct ir3_instruction
* const *src
;
2278 struct ir3_block
*b
= ctx
->block
;
2279 nir_const_value
*const_offset
;
2282 if (info
->has_dest
) {
2283 unsigned n
= nir_intrinsic_dest_components(intr
);
2284 dst
= get_dst(ctx
, &intr
->dest
, n
);
2289 switch (intr
->intrinsic
) {
2290 case nir_intrinsic_load_uniform
:
2291 idx
= nir_intrinsic_base(intr
);
2292 const_offset
= nir_src_as_const_value(intr
->src
[0]);
2294 idx
+= const_offset
->u32
[0];
2295 for (int i
= 0; i
< intr
->num_components
; i
++) {
2296 unsigned n
= idx
* 4 + i
;
2297 dst
[i
] = create_uniform(ctx
, n
);
2300 src
= get_src(ctx
, &intr
->src
[0]);
2301 for (int i
= 0; i
< intr
->num_components
; i
++) {
2302 int n
= idx
* 4 + i
;
2303 dst
[i
] = create_uniform_indirect(ctx
, n
,
2304 get_addr(ctx
, src
[0], 4));
2306 /* NOTE: if relative addressing is used, we set
2307 * constlen in the compiler (to worst-case value)
2308 * since we don't know in the assembler what the max
2309 * addr reg value can be:
2311 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
2314 case nir_intrinsic_load_ubo
:
2315 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
2317 case nir_intrinsic_load_input
:
2318 idx
= nir_intrinsic_base(intr
);
2319 comp
= nir_intrinsic_component(intr
);
2320 const_offset
= nir_src_as_const_value(intr
->src
[0]);
2322 idx
+= const_offset
->u32
[0];
2323 for (int i
= 0; i
< intr
->num_components
; i
++) {
2324 unsigned n
= idx
* 4 + i
+ comp
;
2325 dst
[i
] = ctx
->ir
->inputs
[n
];
2328 src
= get_src(ctx
, &intr
->src
[0]);
2329 struct ir3_instruction
*collect
=
2330 create_collect(ctx
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
2331 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0], 4);
2332 for (int i
= 0; i
< intr
->num_components
; i
++) {
2333 unsigned n
= idx
* 4 + i
+ comp
;
2334 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
2339 case nir_intrinsic_load_ssbo
:
2340 emit_intrinsic_load_ssbo(ctx
, intr
, dst
);
2342 case nir_intrinsic_store_ssbo
:
2343 emit_intrinsic_store_ssbo(ctx
, intr
);
2345 case nir_intrinsic_get_buffer_size
:
2346 emit_intrinsic_ssbo_size(ctx
, intr
, dst
);
2348 case nir_intrinsic_ssbo_atomic_add
:
2349 case nir_intrinsic_ssbo_atomic_imin
:
2350 case nir_intrinsic_ssbo_atomic_umin
:
2351 case nir_intrinsic_ssbo_atomic_imax
:
2352 case nir_intrinsic_ssbo_atomic_umax
:
2353 case nir_intrinsic_ssbo_atomic_and
:
2354 case nir_intrinsic_ssbo_atomic_or
:
2355 case nir_intrinsic_ssbo_atomic_xor
:
2356 case nir_intrinsic_ssbo_atomic_exchange
:
2357 case nir_intrinsic_ssbo_atomic_comp_swap
:
2358 dst
[0] = emit_intrinsic_atomic_ssbo(ctx
, intr
);
2360 case nir_intrinsic_load_shared
:
2361 emit_intrinsic_load_shared(ctx
, intr
, dst
);
2363 case nir_intrinsic_store_shared
:
2364 emit_intrinsic_store_shared(ctx
, intr
);
2366 case nir_intrinsic_shared_atomic_add
:
2367 case nir_intrinsic_shared_atomic_imin
:
2368 case nir_intrinsic_shared_atomic_umin
:
2369 case nir_intrinsic_shared_atomic_imax
:
2370 case nir_intrinsic_shared_atomic_umax
:
2371 case nir_intrinsic_shared_atomic_and
:
2372 case nir_intrinsic_shared_atomic_or
:
2373 case nir_intrinsic_shared_atomic_xor
:
2374 case nir_intrinsic_shared_atomic_exchange
:
2375 case nir_intrinsic_shared_atomic_comp_swap
:
2376 dst
[0] = emit_intrinsic_atomic_shared(ctx
, intr
);
2378 case nir_intrinsic_image_deref_load
:
2379 emit_intrinsic_load_image(ctx
, intr
, dst
);
2381 case nir_intrinsic_image_deref_store
:
2382 emit_intrinsic_store_image(ctx
, intr
);
2384 case nir_intrinsic_image_deref_size
:
2385 emit_intrinsic_image_size(ctx
, intr
, dst
);
2387 case nir_intrinsic_image_deref_atomic_add
:
2388 case nir_intrinsic_image_deref_atomic_min
:
2389 case nir_intrinsic_image_deref_atomic_max
:
2390 case nir_intrinsic_image_deref_atomic_and
:
2391 case nir_intrinsic_image_deref_atomic_or
:
2392 case nir_intrinsic_image_deref_atomic_xor
:
2393 case nir_intrinsic_image_deref_atomic_exchange
:
2394 case nir_intrinsic_image_deref_atomic_comp_swap
:
2395 dst
[0] = emit_intrinsic_atomic_image(ctx
, intr
);
2397 case nir_intrinsic_barrier
:
2398 case nir_intrinsic_memory_barrier
:
2399 case nir_intrinsic_group_memory_barrier
:
2400 case nir_intrinsic_memory_barrier_atomic_counter
:
2401 case nir_intrinsic_memory_barrier_buffer
:
2402 case nir_intrinsic_memory_barrier_image
:
2403 case nir_intrinsic_memory_barrier_shared
:
2404 emit_intrinsic_barrier(ctx
, intr
);
2405 /* note that blk ptr no longer valid, make that obvious: */
2408 case nir_intrinsic_store_output
:
2409 idx
= nir_intrinsic_base(intr
);
2410 comp
= nir_intrinsic_component(intr
);
2411 const_offset
= nir_src_as_const_value(intr
->src
[1]);
2412 compile_assert(ctx
, const_offset
!= NULL
);
2413 idx
+= const_offset
->u32
[0];
2415 src
= get_src(ctx
, &intr
->src
[0]);
2416 for (int i
= 0; i
< intr
->num_components
; i
++) {
2417 unsigned n
= idx
* 4 + i
+ comp
;
2418 ctx
->ir
->outputs
[n
] = src
[i
];
2421 case nir_intrinsic_load_base_vertex
:
2422 case nir_intrinsic_load_first_vertex
:
2423 if (!ctx
->basevertex
) {
2424 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
2425 add_sysval_input(ctx
, SYSTEM_VALUE_FIRST_VERTEX
, ctx
->basevertex
);
2427 dst
[0] = ctx
->basevertex
;
2429 case nir_intrinsic_load_vertex_id_zero_base
:
2430 case nir_intrinsic_load_vertex_id
:
2431 if (!ctx
->vertex_id
) {
2432 gl_system_value sv
= (intr
->intrinsic
== nir_intrinsic_load_vertex_id
) ?
2433 SYSTEM_VALUE_VERTEX_ID
: SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
;
2434 ctx
->vertex_id
= create_input(b
, 0);
2435 add_sysval_input(ctx
, sv
, ctx
->vertex_id
);
2437 dst
[0] = ctx
->vertex_id
;
2439 case nir_intrinsic_load_instance_id
:
2440 if (!ctx
->instance_id
) {
2441 ctx
->instance_id
= create_input(b
, 0);
2442 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
2445 dst
[0] = ctx
->instance_id
;
2447 case nir_intrinsic_load_sample_id
:
2448 if (!ctx
->samp_id
) {
2449 ctx
->samp_id
= create_input(b
, 0);
2450 ctx
->samp_id
->regs
[0]->flags
|= IR3_REG_HALF
;
2451 add_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_ID
,
2454 dst
[0] = ir3_COV(b
, ctx
->samp_id
, TYPE_U16
, TYPE_U32
);
2456 case nir_intrinsic_load_sample_mask_in
:
2457 if (!ctx
->samp_mask_in
) {
2458 ctx
->samp_mask_in
= create_input(b
, 0);
2459 add_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_MASK_IN
,
2462 dst
[0] = ctx
->samp_mask_in
;
2464 case nir_intrinsic_load_user_clip_plane
:
2465 idx
= nir_intrinsic_ucp_id(intr
);
2466 for (int i
= 0; i
< intr
->num_components
; i
++) {
2467 unsigned n
= idx
* 4 + i
;
2468 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
2471 case nir_intrinsic_load_front_face
:
2472 if (!ctx
->frag_face
) {
2473 ctx
->so
->frag_face
= true;
2474 ctx
->frag_face
= create_input(b
, 0);
2475 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
2477 /* for fragface, we get -1 for back and 0 for front. However this is
2478 * the inverse of what nir expects (where ~0 is true).
2480 dst
[0] = ir3_COV(b
, ctx
->frag_face
, TYPE_S16
, TYPE_S32
);
2481 dst
[0] = ir3_NOT_B(b
, dst
[0], 0);
2483 case nir_intrinsic_load_local_invocation_id
:
2484 if (!ctx
->local_invocation_id
) {
2485 ctx
->local_invocation_id
= create_input_compmask(b
, 0, 0x7);
2486 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
,
2487 0x7, ctx
->local_invocation_id
);
2489 split_dest(b
, dst
, ctx
->local_invocation_id
, 0, 3);
2491 case nir_intrinsic_load_work_group_id
:
2492 if (!ctx
->work_group_id
) {
2493 ctx
->work_group_id
= create_input_compmask(b
, 0, 0x7);
2494 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_WORK_GROUP_ID
,
2495 0x7, ctx
->work_group_id
);
2496 ctx
->work_group_id
->regs
[0]->flags
|= IR3_REG_HIGH
;
2498 split_dest(b
, dst
, ctx
->work_group_id
, 0, 3);
2500 case nir_intrinsic_load_num_work_groups
:
2501 for (int i
= 0; i
< intr
->num_components
; i
++) {
2502 dst
[i
] = create_driver_param(ctx
, IR3_DP_NUM_WORK_GROUPS_X
+ i
);
2505 case nir_intrinsic_load_local_group_size
:
2506 for (int i
= 0; i
< intr
->num_components
; i
++) {
2507 dst
[i
] = create_driver_param(ctx
, IR3_DP_LOCAL_GROUP_SIZE_X
+ i
);
2510 case nir_intrinsic_discard_if
:
2511 case nir_intrinsic_discard
: {
2512 struct ir3_instruction
*cond
, *kill
;
2514 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
2515 /* conditional discard: */
2516 src
= get_src(ctx
, &intr
->src
[0]);
2517 cond
= ir3_b2n(b
, src
[0]);
2519 /* unconditional discard: */
2520 cond
= create_immed(b
, 1);
2523 /* NOTE: only cmps.*.* can write p0.x: */
2524 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
2525 cond
->cat2
.condition
= IR3_COND_NE
;
2527 /* condition always goes in predicate register: */
2528 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2530 kill
= ir3_KILL(b
, cond
, 0);
2531 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
2533 array_insert(b
, b
->keeps
, kill
);
2534 ctx
->so
->has_kill
= true;
2539 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
2540 nir_intrinsic_infos
[intr
->intrinsic
].name
);
2545 put_dst(ctx
, &intr
->dest
);
2549 emit_load_const(struct ir3_context
*ctx
, nir_load_const_instr
*instr
)
2551 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
2552 instr
->def
.num_components
);
2553 type_t type
= (instr
->def
.bit_size
< 32) ? TYPE_U16
: TYPE_U32
;
2555 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
2556 dst
[i
] = create_immed_typed(ctx
->block
, instr
->value
.u32
[i
], type
);
2560 emit_undef(struct ir3_context
*ctx
, nir_ssa_undef_instr
*undef
)
2562 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
2563 undef
->def
.num_components
);
2564 type_t type
= (undef
->def
.bit_size
< 32) ? TYPE_U16
: TYPE_U32
;
2566 /* backend doesn't want undefined instructions, so just plug
2569 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
2570 dst
[i
] = create_immed_typed(ctx
->block
, fui(0.0), type
);
2574 * texture fetch/sample instructions:
2578 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
2580 unsigned coords
, flags
= 0;
2582 /* note: would use tex->coord_components.. except txs.. also,
2583 * since array index goes after shadow ref, we don't want to
2586 switch (tex
->sampler_dim
) {
2587 case GLSL_SAMPLER_DIM_1D
:
2588 case GLSL_SAMPLER_DIM_BUF
:
2591 case GLSL_SAMPLER_DIM_2D
:
2592 case GLSL_SAMPLER_DIM_RECT
:
2593 case GLSL_SAMPLER_DIM_EXTERNAL
:
2594 case GLSL_SAMPLER_DIM_MS
:
2597 case GLSL_SAMPLER_DIM_3D
:
2598 case GLSL_SAMPLER_DIM_CUBE
:
2600 flags
|= IR3_INSTR_3D
;
2603 unreachable("bad sampler_dim");
2606 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2607 flags
|= IR3_INSTR_S
;
2609 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
2610 flags
|= IR3_INSTR_A
;
2617 emit_tex(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2619 struct ir3_block
*b
= ctx
->block
;
2620 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
2621 struct ir3_instruction
* const *coord
, * const *off
, * const *ddx
, * const *ddy
;
2622 struct ir3_instruction
*lod
, *compare
, *proj
, *sample_index
;
2623 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
2624 unsigned i
, coords
, flags
;
2625 unsigned nsrc0
= 0, nsrc1
= 0;
2629 coord
= off
= ddx
= ddy
= NULL
;
2630 lod
= proj
= compare
= sample_index
= NULL
;
2632 /* TODO: might just be one component for gathers? */
2633 dst
= get_dst(ctx
, &tex
->dest
, 4);
2635 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
2636 switch (tex
->src
[i
].src_type
) {
2637 case nir_tex_src_coord
:
2638 coord
= get_src(ctx
, &tex
->src
[i
].src
);
2640 case nir_tex_src_bias
:
2641 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2644 case nir_tex_src_lod
:
2645 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2648 case nir_tex_src_comparator
: /* shadow comparator */
2649 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2651 case nir_tex_src_projector
:
2652 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2655 case nir_tex_src_offset
:
2656 off
= get_src(ctx
, &tex
->src
[i
].src
);
2659 case nir_tex_src_ddx
:
2660 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
2662 case nir_tex_src_ddy
:
2663 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
2665 case nir_tex_src_ms_index
:
2666 sample_index
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2669 compile_error(ctx
, "Unhandled NIR tex src type: %d\n",
2670 tex
->src
[i
].src_type
);
2676 case nir_texop_tex
: opc
= has_lod
? OPC_SAML
: OPC_SAM
; break;
2677 case nir_texop_txb
: opc
= OPC_SAMB
; break;
2678 case nir_texop_txl
: opc
= OPC_SAML
; break;
2679 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
2680 case nir_texop_txf
: opc
= OPC_ISAML
; break;
2681 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
2683 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2684 * what blob does, seems gather is broken?), and a3xx did
2685 * not support it (but probably could also emulate).
2687 switch (tex
->component
) {
2688 case 0: opc
= OPC_GATHER4R
; break;
2689 case 1: opc
= OPC_GATHER4G
; break;
2690 case 2: opc
= OPC_GATHER4B
; break;
2691 case 3: opc
= OPC_GATHER4A
; break;
2694 case nir_texop_txf_ms
: opc
= OPC_ISAMM
; break;
2696 case nir_texop_query_levels
:
2697 case nir_texop_texture_samples
:
2698 case nir_texop_samples_identical
:
2699 case nir_texop_txf_ms_mcs
:
2700 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
2704 tex_info(tex
, &flags
, &coords
);
2707 * lay out the first argument in the proper order:
2708 * - actual coordinates first
2709 * - shadow reference
2712 * - starting at offset 4, dpdx.xy, dpdy.xy
2714 * bias/lod go into the second arg
2717 /* insert tex coords: */
2718 for (i
= 0; i
< coords
; i
++)
2723 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2724 * with scaled x coord according to requested sample:
2726 if (tex
->op
== nir_texop_txf_ms
) {
2727 if (ctx
->txf_ms_with_isaml
) {
2728 /* the samples are laid out in x dimension as
2730 * x_ms = (x << ms) + sample_index;
2732 struct ir3_instruction
*ms
;
2733 ms
= create_immed(b
, (ctx
->samples
>> (2 * tex
->texture_index
)) & 3);
2735 src0
[0] = ir3_SHL_B(b
, src0
[0], 0, ms
, 0);
2736 src0
[0] = ir3_ADD_U(b
, src0
[0], 0, sample_index
, 0);
2740 src0
[nsrc0
++] = sample_index
;
2744 /* scale up integer coords for TXF based on the LOD */
2745 if (ctx
->unminify_coords
&& (opc
== OPC_ISAML
)) {
2747 for (i
= 0; i
< coords
; i
++)
2748 src0
[i
] = ir3_SHL_B(b
, src0
[i
], 0, lod
, 0);
2752 /* hw doesn't do 1d, so we treat it as 2d with
2753 * height of 1, and patch up the y coord.
2754 * TODO: y coord should be (int)0 in some cases..
2756 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
2759 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2760 src0
[nsrc0
++] = compare
;
2762 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
) {
2763 struct ir3_instruction
*idx
= coord
[coords
];
2765 /* the array coord for cube arrays needs 0.5 added to it */
2766 if (ctx
->array_index_add_half
&& (opc
!= OPC_ISAML
))
2767 idx
= ir3_ADD_F(b
, idx
, 0, create_immed(b
, fui(0.5)), 0);
2769 src0
[nsrc0
++] = idx
;
2773 src0
[nsrc0
++] = proj
;
2774 flags
|= IR3_INSTR_P
;
2777 /* pad to 4, then ddx/ddy: */
2778 if (tex
->op
== nir_texop_txd
) {
2780 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2781 for (i
= 0; i
< coords
; i
++)
2782 src0
[nsrc0
++] = ddx
[i
];
2784 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2785 for (i
= 0; i
< coords
; i
++)
2786 src0
[nsrc0
++] = ddy
[i
];
2788 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2792 * second argument (if applicable):
2797 if (has_off
| has_lod
| has_bias
) {
2799 unsigned off_coords
= coords
;
2800 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2802 for (i
= 0; i
< off_coords
; i
++)
2803 src1
[nsrc1
++] = off
[i
];
2805 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
2806 flags
|= IR3_INSTR_O
;
2809 if (has_lod
| has_bias
)
2810 src1
[nsrc1
++] = lod
;
2813 switch (tex
->dest_type
) {
2814 case nir_type_invalid
:
2815 case nir_type_float
:
2826 unreachable("bad dest_type");
2829 if (opc
== OPC_GETLOD
)
2832 unsigned tex_idx
= tex
->texture_index
;
2834 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex_idx
);
2836 struct ir3_instruction
*col0
= create_collect(ctx
, src0
, nsrc0
);
2837 struct ir3_instruction
*col1
= create_collect(ctx
, src1
, nsrc1
);
2839 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
, flags
,
2840 tex_idx
, tex_idx
, col0
, col1
);
2842 if ((ctx
->astc_srgb
& (1 << tex_idx
)) && !nir_tex_instr_is_query(tex
)) {
2843 /* only need first 3 components: */
2844 sam
->regs
[0]->wrmask
= 0x7;
2845 split_dest(b
, dst
, sam
, 0, 3);
2847 /* we need to sample the alpha separately with a non-ASTC
2850 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_W
, flags
,
2851 tex_idx
, tex_idx
, col0
, col1
);
2853 array_insert(ctx
->ir
, ctx
->ir
->astc_srgb
, sam
);
2855 /* fixup .w component: */
2856 split_dest(b
, &dst
[3], sam
, 3, 1);
2858 /* normal (non-workaround) case: */
2859 split_dest(b
, dst
, sam
, 0, 4);
2862 /* GETLOD returns results in 4.8 fixed point */
2863 if (opc
== OPC_GETLOD
) {
2864 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
2866 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
2867 for (i
= 0; i
< 2; i
++) {
2868 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_U32
, TYPE_F32
), 0,
2873 put_dst(ctx
, &tex
->dest
);
2877 emit_tex_query_levels(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2879 struct ir3_block
*b
= ctx
->block
;
2880 struct ir3_instruction
**dst
, *sam
;
2882 dst
= get_dst(ctx
, &tex
->dest
, 1);
2884 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
2885 tex
->texture_index
, tex
->texture_index
, NULL
, NULL
);
2887 /* even though there is only one component, since it ends
2888 * up in .z rather than .x, we need a split_dest()
2890 split_dest(b
, dst
, sam
, 0, 3);
2892 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2893 * the value in TEX_CONST_0 is zero-based.
2895 if (ctx
->levels_add_one
)
2896 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
2898 put_dst(ctx
, &tex
->dest
);
2902 emit_tex_txs(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2904 struct ir3_block
*b
= ctx
->block
;
2905 struct ir3_instruction
**dst
, *sam
;
2906 struct ir3_instruction
*lod
;
2907 unsigned flags
, coords
;
2909 tex_info(tex
, &flags
, &coords
);
2911 /* Actually we want the number of dimensions, not coordinates. This
2912 * distinction only matters for cubes.
2914 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2917 dst
= get_dst(ctx
, &tex
->dest
, 4);
2919 compile_assert(ctx
, tex
->num_srcs
== 1);
2920 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
2922 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
2924 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
2925 tex
->texture_index
, tex
->texture_index
, lod
, NULL
);
2927 split_dest(b
, dst
, sam
, 0, 4);
2929 /* Array size actually ends up in .w rather than .z. This doesn't
2930 * matter for miplevel 0, but for higher mips the value in z is
2931 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2932 * returned, which means that we have to add 1 to it for arrays.
2934 if (tex
->is_array
) {
2935 if (ctx
->levels_add_one
) {
2936 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
2938 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
2942 put_dst(ctx
, &tex
->dest
);
2946 emit_jump(struct ir3_context
*ctx
, nir_jump_instr
*jump
)
2948 switch (jump
->type
) {
2949 case nir_jump_break
:
2950 case nir_jump_continue
:
2951 case nir_jump_return
:
2952 /* I *think* we can simply just ignore this, and use the
2953 * successor block link to figure out where we need to
2954 * jump to for break/continue
2958 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
2964 emit_instr(struct ir3_context
*ctx
, nir_instr
*instr
)
2966 switch (instr
->type
) {
2967 case nir_instr_type_alu
:
2968 emit_alu(ctx
, nir_instr_as_alu(instr
));
2970 case nir_instr_type_deref
:
2971 /* ignored, handled as part of the intrinsic they are src to */
2973 case nir_instr_type_intrinsic
:
2974 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2976 case nir_instr_type_load_const
:
2977 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2979 case nir_instr_type_ssa_undef
:
2980 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
2982 case nir_instr_type_tex
: {
2983 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
2984 /* couple tex instructions get special-cased:
2988 emit_tex_txs(ctx
, tex
);
2990 case nir_texop_query_levels
:
2991 emit_tex_query_levels(ctx
, tex
);
2999 case nir_instr_type_jump
:
3000 emit_jump(ctx
, nir_instr_as_jump(instr
));
3002 case nir_instr_type_phi
:
3003 /* we have converted phi webs to regs in NIR by now */
3004 compile_error(ctx
, "Unexpected NIR instruction type: %d\n", instr
->type
);
3006 case nir_instr_type_call
:
3007 case nir_instr_type_parallel_copy
:
3008 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
3013 static struct ir3_block
*
3014 get_block(struct ir3_context
*ctx
, const nir_block
*nblock
)
3016 struct ir3_block
*block
;
3017 struct hash_entry
*hentry
;
3018 struct set_entry
*sentry
;
3021 hentry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
3023 return hentry
->data
;
3025 block
= ir3_block_create(ctx
->ir
);
3026 block
->nblock
= nblock
;
3027 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
3029 block
->predecessors_count
= nblock
->predecessors
->entries
;
3030 block
->predecessors
= ralloc_array_size(block
,
3031 sizeof(block
->predecessors
[0]), block
->predecessors_count
);
3033 set_foreach(nblock
->predecessors
, sentry
) {
3034 block
->predecessors
[i
++] = get_block(ctx
, sentry
->key
);
3041 emit_block(struct ir3_context
*ctx
, nir_block
*nblock
)
3043 struct ir3_block
*block
= get_block(ctx
, nblock
);
3045 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
3046 if (nblock
->successors
[i
]) {
3047 block
->successors
[i
] =
3048 get_block(ctx
, nblock
->successors
[i
]);
3053 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
3055 /* re-emit addr register in each block if needed: */
3056 for (int i
= 0; i
< ARRAY_SIZE(ctx
->addr_ht
); i
++) {
3057 _mesa_hash_table_destroy(ctx
->addr_ht
[i
], NULL
);
3058 ctx
->addr_ht
[i
] = NULL
;
3061 nir_foreach_instr(instr
, nblock
) {
3062 emit_instr(ctx
, instr
);
3068 static void emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
);
3071 emit_if(struct ir3_context
*ctx
, nir_if
*nif
)
3073 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
3075 ctx
->block
->condition
=
3076 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
3078 emit_cf_list(ctx
, &nif
->then_list
);
3079 emit_cf_list(ctx
, &nif
->else_list
);
3083 emit_loop(struct ir3_context
*ctx
, nir_loop
*nloop
)
3085 emit_cf_list(ctx
, &nloop
->body
);
3089 emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
)
3091 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
3092 switch (node
->type
) {
3093 case nir_cf_node_block
:
3094 emit_block(ctx
, nir_cf_node_as_block(node
));
3096 case nir_cf_node_if
:
3097 emit_if(ctx
, nir_cf_node_as_if(node
));
3099 case nir_cf_node_loop
:
3100 emit_loop(ctx
, nir_cf_node_as_loop(node
));
3102 case nir_cf_node_function
:
3103 compile_error(ctx
, "TODO\n");
3109 /* emit stream-out code. At this point, the current block is the original
3110 * (nir) end block, and nir ensures that all flow control paths terminate
3111 * into the end block. We re-purpose the original end block to generate
3112 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
3113 * block holding stream-out write instructions, followed by the new end
3117 * p0.x = (vtxcnt < maxvtxcnt)
3118 * // succs: blockStreamOut, blockNewEnd
3121 * ... stream-out instructions ...
3122 * // succs: blockNewEnd
3128 emit_stream_out(struct ir3_context
*ctx
)
3130 struct ir3_shader_variant
*v
= ctx
->so
;
3131 struct ir3
*ir
= ctx
->ir
;
3132 struct pipe_stream_output_info
*strmout
=
3133 &ctx
->so
->shader
->stream_output
;
3134 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
3135 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
3136 struct ir3_instruction
*bases
[PIPE_MAX_SO_BUFFERS
];
3138 /* create vtxcnt input in input block at top of shader,
3139 * so that it is seen as live over the entire duration
3142 vtxcnt
= create_input(ctx
->in_block
, 0);
3143 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
3145 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
3147 /* at this point, we are at the original 'end' block,
3148 * re-purpose this block to stream-out condition, then
3149 * append stream-out block and new-end block
3151 orig_end_block
= ctx
->block
;
3153 // TODO these blocks need to update predecessors..
3154 // maybe w/ store_global intrinsic, we could do this
3155 // stuff in nir->nir pass
3157 stream_out_block
= ir3_block_create(ir
);
3158 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
3160 new_end_block
= ir3_block_create(ir
);
3161 list_addtail(&new_end_block
->node
, &ir
->block_list
);
3163 orig_end_block
->successors
[0] = stream_out_block
;
3164 orig_end_block
->successors
[1] = new_end_block
;
3165 stream_out_block
->successors
[0] = new_end_block
;
3167 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
3168 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
3169 cond
->regs
[0]->num
= regid(REG_P0
, 0);
3170 cond
->cat2
.condition
= IR3_COND_LT
;
3172 /* condition goes on previous block to the conditional,
3173 * since it is used to pick which of the two successor
3176 orig_end_block
->condition
= cond
;
3178 /* switch to stream_out_block to generate the stream-out
3181 ctx
->block
= stream_out_block
;
3183 /* Calculate base addresses based on vtxcnt. Instructions
3184 * generated for bases not used in following loop will be
3185 * stripped out in the backend.
3187 for (unsigned i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
3188 unsigned stride
= strmout
->stride
[i
];
3189 struct ir3_instruction
*base
, *off
;
3191 base
= create_uniform(ctx
, regid(v
->constbase
.tfbo
, i
));
3193 /* 24-bit should be enough: */
3194 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
3195 create_immed(ctx
->block
, stride
* 4), 0);
3197 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
3200 /* Generate the per-output store instructions: */
3201 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
3202 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
3203 unsigned c
= j
+ strmout
->output
[i
].start_component
;
3204 struct ir3_instruction
*base
, *out
, *stg
;
3206 base
= bases
[strmout
->output
[i
].output_buffer
];
3207 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
3209 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
3210 create_immed(ctx
->block
, 1), 0);
3211 stg
->cat6
.type
= TYPE_U32
;
3212 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
3214 array_insert(ctx
->block
, ctx
->block
->keeps
, stg
);
3218 /* and finally switch to the new_end_block: */
3219 ctx
->block
= new_end_block
;
3223 emit_function(struct ir3_context
*ctx
, nir_function_impl
*impl
)
3225 nir_metadata_require(impl
, nir_metadata_block_index
);
3227 emit_cf_list(ctx
, &impl
->body
);
3228 emit_block(ctx
, impl
->end_block
);
3230 /* at this point, we should have a single empty block,
3231 * into which we emit the 'end' instruction.
3233 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
3235 /* If stream-out (aka transform-feedback) enabled, emit the
3236 * stream-out instructions, followed by a new empty block (into
3237 * which the 'end' instruction lands).
3239 * NOTE: it is done in this order, rather than inserting before
3240 * we emit end_block, because NIR guarantees that all blocks
3241 * flow into end_block, and that end_block has no successors.
3242 * So by re-purposing end_block as the first block of stream-
3243 * out, we guarantee that all exit paths flow into the stream-
3246 if ((ctx
->compiler
->gpu_id
< 500) &&
3247 (ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
3248 !ctx
->so
->key
.binning_pass
) {
3249 debug_assert(ctx
->so
->type
== SHADER_VERTEX
);
3250 emit_stream_out(ctx
);
3253 ir3_END(ctx
->block
);
3257 setup_input(struct ir3_context
*ctx
, nir_variable
*in
)
3259 struct ir3_shader_variant
*so
= ctx
->so
;
3260 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
3261 unsigned ncomp
= glsl_get_components(in
->type
);
3262 unsigned n
= in
->data
.driver_location
;
3263 unsigned slot
= in
->data
.location
;
3265 DBG("; in: slot=%u, len=%ux%u, drvloc=%u",
3266 slot
, array_len
, ncomp
, n
);
3268 /* let's pretend things other than vec4 don't exist: */
3269 ncomp
= MAX2(ncomp
, 4);
3270 compile_assert(ctx
, ncomp
== 4);
3272 so
->inputs
[n
].slot
= slot
;
3273 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
3274 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
3275 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
3277 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3278 for (int i
= 0; i
< ncomp
; i
++) {
3279 struct ir3_instruction
*instr
= NULL
;
3280 unsigned idx
= (n
* 4) + i
;
3282 if (slot
== VARYING_SLOT_POS
) {
3283 so
->inputs
[n
].bary
= false;
3284 so
->frag_coord
= true;
3285 instr
= create_frag_coord(ctx
, i
);
3286 } else if (slot
== VARYING_SLOT_PNTC
) {
3287 /* see for example st_get_generic_varying_index().. this is
3288 * maybe a bit mesa/st specific. But we need things to line
3289 * up for this in fdN_program:
3290 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
3291 * if (emit->sprite_coord_enable & texmask) {
3295 so
->inputs
[n
].slot
= VARYING_SLOT_VAR8
;
3296 so
->inputs
[n
].bary
= true;
3297 instr
= create_frag_input(ctx
, false);
3299 bool use_ldlv
= false;
3301 /* detect the special case for front/back colors where
3302 * we need to do flat vs smooth shading depending on
3305 if (in
->data
.interpolation
== INTERP_MODE_NONE
) {
3307 case VARYING_SLOT_COL0
:
3308 case VARYING_SLOT_COL1
:
3309 case VARYING_SLOT_BFC0
:
3310 case VARYING_SLOT_BFC1
:
3311 so
->inputs
[n
].rasterflat
= true;
3318 if (ctx
->flat_bypass
) {
3319 if ((so
->inputs
[n
].interpolate
== INTERP_MODE_FLAT
) ||
3320 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
3324 so
->inputs
[n
].bary
= true;
3326 instr
= create_frag_input(ctx
, use_ldlv
);
3329 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
3331 ctx
->ir
->inputs
[idx
] = instr
;
3333 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
3334 for (int i
= 0; i
< ncomp
; i
++) {
3335 unsigned idx
= (n
* 4) + i
;
3336 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
3337 ctx
->ir
->inputs
[idx
] = create_input(ctx
->block
, idx
);
3340 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3343 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
3344 so
->total_in
+= ncomp
;
3349 setup_output(struct ir3_context
*ctx
, nir_variable
*out
)
3351 struct ir3_shader_variant
*so
= ctx
->so
;
3352 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
3353 unsigned ncomp
= glsl_get_components(out
->type
);
3354 unsigned n
= out
->data
.driver_location
;
3355 unsigned slot
= out
->data
.location
;
3358 DBG("; out: slot=%u, len=%ux%u, drvloc=%u",
3359 slot
, array_len
, ncomp
, n
);
3361 /* let's pretend things other than vec4 don't exist: */
3362 ncomp
= MAX2(ncomp
, 4);
3363 compile_assert(ctx
, ncomp
== 4);
3365 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3367 case FRAG_RESULT_DEPTH
:
3368 comp
= 2; /* tgsi will write to .z component */
3369 so
->writes_pos
= true;
3371 case FRAG_RESULT_COLOR
:
3375 if (slot
>= FRAG_RESULT_DATA0
)
3377 compile_error(ctx
, "unknown FS output name: %s\n",
3378 gl_frag_result_name(slot
));
3380 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
3382 case VARYING_SLOT_POS
:
3383 so
->writes_pos
= true;
3385 case VARYING_SLOT_PSIZ
:
3386 so
->writes_psize
= true;
3388 case VARYING_SLOT_COL0
:
3389 case VARYING_SLOT_COL1
:
3390 case VARYING_SLOT_BFC0
:
3391 case VARYING_SLOT_BFC1
:
3392 case VARYING_SLOT_FOGC
:
3393 case VARYING_SLOT_CLIP_DIST0
:
3394 case VARYING_SLOT_CLIP_DIST1
:
3395 case VARYING_SLOT_CLIP_VERTEX
:
3398 if (slot
>= VARYING_SLOT_VAR0
)
3400 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
3402 compile_error(ctx
, "unknown VS output name: %s\n",
3403 gl_varying_slot_name(slot
));
3406 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3409 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
3411 so
->outputs
[n
].slot
= slot
;
3412 so
->outputs
[n
].regid
= regid(n
, comp
);
3413 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
3415 for (int i
= 0; i
< ncomp
; i
++) {
3416 unsigned idx
= (n
* 4) + i
;
3417 compile_assert(ctx
, idx
< ctx
->ir
->noutputs
);
3418 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
3423 max_drvloc(struct exec_list
*vars
)
3426 nir_foreach_variable(var
, vars
) {
3427 drvloc
= MAX2(drvloc
, (int)var
->data
.driver_location
);
3432 static const unsigned max_sysvals
[SHADER_MAX
] = {
3433 [SHADER_FRAGMENT
] = 8,
3434 [SHADER_VERTEX
] = 16,
3435 [SHADER_COMPUTE
] = 16, // TODO how many do we actually need?
3439 emit_instructions(struct ir3_context
*ctx
)
3441 unsigned ninputs
, noutputs
;
3442 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
3444 ninputs
= (max_drvloc(&ctx
->s
->inputs
) + 1) * 4;
3445 noutputs
= (max_drvloc(&ctx
->s
->outputs
) + 1) * 4;
3447 /* we need to leave room for sysvals:
3449 ninputs
+= max_sysvals
[ctx
->so
->type
];
3451 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
3453 /* Create inputs in first block: */
3454 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
3455 ctx
->in_block
= ctx
->block
;
3456 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
3458 ninputs
-= max_sysvals
[ctx
->so
->type
];
3460 /* for fragment shader, we have a single input register (usually
3461 * r0.xy) which is used as the base for bary.f varying fetch instrs:
3463 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3464 // TODO maybe a helper for fi since we need it a few places..
3465 struct ir3_instruction
*instr
;
3466 instr
= ir3_instr_create(ctx
->block
, OPC_META_FI
);
3467 ir3_reg_create(instr
, 0, 0);
3468 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.x */
3469 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.y */
3470 ctx
->frag_pos
= instr
;
3474 nir_foreach_variable(var
, &ctx
->s
->inputs
) {
3475 setup_input(ctx
, var
);
3478 /* Setup outputs: */
3479 nir_foreach_variable(var
, &ctx
->s
->outputs
) {
3480 setup_output(ctx
, var
);
3483 /* Setup registers (which should only be arrays): */
3484 nir_foreach_register(reg
, &ctx
->s
->registers
) {
3485 declare_array(ctx
, reg
);
3488 /* NOTE: need to do something more clever when we support >1 fxn */
3489 nir_foreach_register(reg
, &fxn
->registers
) {
3490 declare_array(ctx
, reg
);
3492 /* And emit the body: */
3494 emit_function(ctx
, fxn
);
3497 /* from NIR perspective, we actually have inputs. But most of the "inputs"
3498 * for a fragment shader are just bary.f instructions. The *actual* inputs
3499 * from the hw perspective are the frag_pos and optionally frag_coord and
3503 fixup_frag_inputs(struct ir3_context
*ctx
)
3505 struct ir3_shader_variant
*so
= ctx
->so
;
3506 struct ir3
*ir
= ctx
->ir
;
3507 struct ir3_instruction
**inputs
;
3508 struct ir3_instruction
*instr
;
3513 n
= 4; /* always have frag_pos */
3514 n
+= COND(so
->frag_face
, 4);
3515 n
+= COND(so
->frag_coord
, 4);
3517 inputs
= ir3_alloc(ctx
->ir
, n
* (sizeof(struct ir3_instruction
*)));
3519 if (so
->frag_face
) {
3520 /* this ultimately gets assigned to hr0.x so doesn't conflict
3521 * with frag_coord/frag_pos..
3523 inputs
[ir
->ninputs
++] = ctx
->frag_face
;
3524 ctx
->frag_face
->regs
[0]->num
= 0;
3526 /* remaining channels not used, but let's avoid confusing
3527 * other parts that expect inputs to come in groups of vec4
3529 inputs
[ir
->ninputs
++] = NULL
;
3530 inputs
[ir
->ninputs
++] = NULL
;
3531 inputs
[ir
->ninputs
++] = NULL
;
3534 /* since we don't know where to set the regid for frag_coord,
3535 * we have to use r0.x for it. But we don't want to *always*
3536 * use r1.x for frag_pos as that could increase the register
3537 * footprint on simple shaders:
3539 if (so
->frag_coord
) {
3540 ctx
->frag_coord
[0]->regs
[0]->num
= regid
++;
3541 ctx
->frag_coord
[1]->regs
[0]->num
= regid
++;
3542 ctx
->frag_coord
[2]->regs
[0]->num
= regid
++;
3543 ctx
->frag_coord
[3]->regs
[0]->num
= regid
++;
3545 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[0];
3546 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[1];
3547 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[2];
3548 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[3];
3551 /* we always have frag_pos: */
3552 so
->pos_regid
= regid
;
3555 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
3556 instr
->regs
[0]->num
= regid
++;
3557 inputs
[ir
->ninputs
++] = instr
;
3558 ctx
->frag_pos
->regs
[1]->instr
= instr
;
3561 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
3562 instr
->regs
[0]->num
= regid
++;
3563 inputs
[ir
->ninputs
++] = instr
;
3564 ctx
->frag_pos
->regs
[2]->instr
= instr
;
3566 ir
->inputs
= inputs
;
3569 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3570 * need to assign the tex state indexes for these after we know the
3574 fixup_astc_srgb(struct ir3_context
*ctx
)
3576 struct ir3_shader_variant
*so
= ctx
->so
;
3577 /* indexed by original tex idx, value is newly assigned alpha sampler
3578 * state tex idx. Zero is invalid since there is at least one sampler
3581 unsigned alt_tex_state
[16] = {0};
3582 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
3585 so
->astc_srgb
.base
= tex_idx
;
3587 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
3588 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
3590 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
3592 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
3593 /* assign new alternate/alpha tex state slot: */
3594 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
3595 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
3596 so
->astc_srgb
.count
++;
3599 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
3604 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
3605 struct ir3_shader_variant
*so
)
3607 struct ir3_context
*ctx
;
3609 struct ir3_instruction
**inputs
;
3610 unsigned i
, j
, actual_in
, inloc
;
3611 int ret
= 0, max_bary
;
3615 ctx
= compile_init(compiler
, so
);
3617 DBG("INIT failed!");
3622 emit_instructions(ctx
);
3625 DBG("EMIT failed!");
3630 ir
= so
->ir
= ctx
->ir
;
3632 /* keep track of the inputs from TGSI perspective.. */
3633 inputs
= ir
->inputs
;
3635 /* but fixup actual inputs for frag shader: */
3636 if (so
->type
== SHADER_FRAGMENT
)
3637 fixup_frag_inputs(ctx
);
3639 /* at this point, for binning pass, throw away unneeded outputs: */
3640 if (so
->key
.binning_pass
) {
3641 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
3642 unsigned slot
= so
->outputs
[i
].slot
;
3644 /* throw away everything but first position/psize */
3645 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
3647 so
->outputs
[j
] = so
->outputs
[i
];
3648 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
3649 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
3650 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
3651 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
3656 so
->outputs_count
= j
;
3657 ir
->noutputs
= j
* 4;
3660 /* if we want half-precision outputs, mark the output registers
3663 if (so
->key
.half_precision
) {
3664 for (i
= 0; i
< ir
->noutputs
; i
++) {
3665 struct ir3_instruction
*out
= ir
->outputs
[i
];
3670 /* if frag shader writes z, that needs to be full precision: */
3671 if (so
->outputs
[i
/4].slot
== FRAG_RESULT_DEPTH
)
3674 out
->regs
[0]->flags
|= IR3_REG_HALF
;
3675 /* output could be a fanout (ie. texture fetch output)
3676 * in which case we need to propagate the half-reg flag
3677 * up to the definer so that RA sees it:
3679 if (out
->opc
== OPC_META_FO
) {
3680 out
= out
->regs
[1]->instr
;
3681 out
->regs
[0]->flags
|= IR3_REG_HALF
;
3684 if (out
->opc
== OPC_MOV
) {
3685 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
3690 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3691 printf("BEFORE CP:\n");
3697 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3698 printf("BEFORE GROUPING:\n");
3702 ir3_sched_add_deps(ir
);
3704 /* Group left/right neighbors, inserting mov's where needed to
3709 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3710 printf("AFTER GROUPING:\n");
3716 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3717 printf("AFTER DEPTH:\n");
3721 ret
= ir3_sched(ir
);
3723 DBG("SCHED failed!");
3727 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3728 printf("AFTER SCHED:\n");
3732 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
3738 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3739 printf("AFTER RA:\n");
3743 /* fixup input/outputs: */
3744 for (i
= 0; i
< so
->outputs_count
; i
++) {
3745 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
3748 /* Note that some or all channels of an input may be unused: */
3751 for (i
= 0; i
< so
->inputs_count
; i
++) {
3752 unsigned j
, regid
= ~0, compmask
= 0, maxcomp
= 0;
3753 so
->inputs
[i
].ncomp
= 0;
3754 so
->inputs
[i
].inloc
= inloc
;
3755 for (j
= 0; j
< 4; j
++) {
3756 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
3757 if (in
&& !(in
->flags
& IR3_INSTR_UNUSED
)) {
3758 compmask
|= (1 << j
);
3759 regid
= in
->regs
[0]->num
- j
;
3761 so
->inputs
[i
].ncomp
++;
3762 if ((so
->type
== SHADER_FRAGMENT
) && so
->inputs
[i
].bary
) {
3764 assert(in
->regs
[1]->flags
& IR3_REG_IMMED
);
3765 in
->regs
[1]->iim_val
= inloc
+ j
;
3770 if ((so
->type
== SHADER_FRAGMENT
) && compmask
&& so
->inputs
[i
].bary
) {
3772 so
->inputs
[i
].compmask
= (1 << maxcomp
) - 1;
3774 } else if (!so
->inputs
[i
].sysval
) {
3775 so
->inputs
[i
].compmask
= compmask
;
3777 so
->inputs
[i
].regid
= regid
;
3781 fixup_astc_srgb(ctx
);
3783 /* We need to do legalize after (for frag shader's) the "bary.f"
3784 * offsets (inloc) have been assigned.
3786 ir3_legalize(ir
, &so
->has_samp
, &so
->has_ssbo
, &max_bary
);
3788 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3789 printf("AFTER LEGALIZE:\n");
3793 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3794 if (so
->type
== SHADER_VERTEX
)
3795 so
->total_in
= actual_in
;
3797 so
->total_in
= max_bary
+ 1;
3802 ir3_destroy(so
->ir
);