projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
freedreno/ir3: block reshuffling and loops!
[mesa.git] / src / gallium / drivers / freedreno / ir3 / ir3_compiler_nir.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include <stdarg.h>
30
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
35 #include "tgsi/tgsi_lowering.h"
36 #include "tgsi/tgsi_strings.h"
37
38 #include "nir/tgsi_to_nir.h"
39 #include "glsl/shader_enums.h"
40
41 #include "freedreno_util.h"
42
43 #include "ir3_compiler.h"
44 #include "ir3_shader.h"
45 #include "ir3_nir.h"
46
47 #include "instr-a3xx.h"
48 #include "ir3.h"
49
50
51 struct ir3_compile {
52 struct ir3_compiler *compiler;
53
54 const struct tgsi_token *tokens;
55 struct nir_shader *s;
56
57 struct ir3 *ir;
58 struct ir3_shader_variant *so;
59
60 /* bitmask of which samplers are integer: */
61 uint16_t integer_s;
62
63 struct ir3_block *block; /* the current block */
64 struct ir3_block *in_block; /* block created for shader inputs */
65
66 nir_function_impl *impl;
67
68 /* For fragment shaders, from the hw perspective the only
69 * actual input is r0.xy position register passed to bary.f.
70 * But TGSI doesn't know that, it still declares things as
71 * IN[] registers. So we do all the input tracking normally
72 * and fix things up after compile_instructions()
73 *
74 * NOTE that frag_pos is the hardware position (possibly it
75 * is actually an index or tag or some such.. it is *not*
76 * values that can be directly used for gl_FragCoord..)
77 */
78 struct ir3_instruction *frag_pos, *frag_face, *frag_coord[4];
79
80 /* For vertex shaders, keep track of the system values sources */
81 struct ir3_instruction *vertex_id, *basevertex, *instance_id;
82
83 /* mapping from nir_register to defining instruction: */
84 struct hash_table *def_ht;
85
86 /* mapping from nir_variable to ir3_array: */
87 struct hash_table *var_ht;
88 unsigned num_arrays;
89
90 /* a common pattern for indirect addressing is to request the
91 * same address register multiple times. To avoid generating
92 * duplicate instruction sequences (which our backend does not
93 * try to clean up, since that should be done as the NIR stage)
94 * we cache the address value generated for a given src value:
95 */
96 struct hash_table *addr_ht;
97
98 /* maps nir_block to ir3_block, mostly for the purposes of
99 * figuring out the blocks successors
100 */
101 struct hash_table *block_ht;
102
103 /* for calculating input/output positions/linkages: */
104 unsigned next_inloc;
105
106 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
107 * so we need to use ldlv.u32 to load the varying directly:
108 */
109 bool flat_bypass;
110
111 /* on a3xx, we need to add one to # of array levels:
112 */
113 bool levels_add_one;
114
115 /* for looking up which system value is which */
116 unsigned sysval_semantics[8];
117
118 /* list of kill instructions: */
119 struct ir3_instruction *kill[16];
120 unsigned int kill_count;
121
122 /* set if we encounter something we can't handle yet, so we
123 * can bail cleanly and fallback to TGSI compiler f/e
124 */
125 bool error;
126 };
127
128
129 static struct ir3_instruction * create_immed(struct ir3_block *block, uint32_t val);
130 static struct ir3_block * get_block(struct ir3_compile *ctx, nir_block *nblock);
131
132 static struct nir_shader *to_nir(const struct tgsi_token *tokens)
133 {
134 struct nir_shader_compiler_options options = {
135 .lower_fpow = true,
136 .lower_fsat = true,
137 .lower_scmp = true,
138 .lower_flrp = true,
139 .native_integers = true,
140 };
141 bool progress;
142
143 struct nir_shader *s = tgsi_to_nir(tokens, &options);
144
145 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
146 debug_printf("----------------------\n");
147 nir_print_shader(s, stdout);
148 debug_printf("----------------------\n");
149 }
150
151 nir_opt_global_to_local(s);
152 nir_convert_to_ssa(s);
153 nir_lower_idiv(s);
154
155 do {
156 progress = false;
157
158 nir_lower_vars_to_ssa(s);
159 nir_lower_alu_to_scalar(s);
160 nir_lower_phis_to_scalar(s);
161
162 progress |= nir_copy_prop(s);
163 progress |= nir_opt_dce(s);
164 progress |= nir_opt_cse(s);
165 progress |= ir3_nir_lower_if_else(s);
166 progress |= nir_opt_algebraic(s);
167 progress |= nir_opt_constant_folding(s);
168
169 } while (progress);
170
171 nir_remove_dead_variables(s);
172 nir_validate_shader(s);
173
174 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
175 debug_printf("----------------------\n");
176 nir_print_shader(s, stdout);
177 debug_printf("----------------------\n");
178 }
179
180 return s;
181 }
182
183 /* TODO nir doesn't lower everything for us yet, but ideally it would: */
184 static const struct tgsi_token *
185 lower_tgsi(struct ir3_compile *ctx, const struct tgsi_token *tokens,
186 struct ir3_shader_variant *so)
187 {
188 struct tgsi_shader_info info;
189 struct tgsi_lowering_config lconfig = {
190 .color_two_side = so->key.color_two_side,
191 .lower_FRC = true,
192 };
193
194 switch (so->type) {
195 case SHADER_FRAGMENT:
196 case SHADER_COMPUTE:
197 lconfig.saturate_s = so->key.fsaturate_s;
198 lconfig.saturate_t = so->key.fsaturate_t;
199 lconfig.saturate_r = so->key.fsaturate_r;
200 break;
201 case SHADER_VERTEX:
202 lconfig.saturate_s = so->key.vsaturate_s;
203 lconfig.saturate_t = so->key.vsaturate_t;
204 lconfig.saturate_r = so->key.vsaturate_r;
205 break;
206 }
207
208 if (ctx->compiler->gpu_id >= 400) {
209 /* a4xx seems to have *no* sam.p */
210 lconfig.lower_TXP = ~0; /* lower all txp */
211 } else {
212 /* a3xx just needs to avoid sam.p for 3d tex */
213 lconfig.lower_TXP = (1 << TGSI_TEXTURE_3D);
214 }
215
216 return tgsi_transform_lowering(&lconfig, tokens, &info);
217 }
218
219 static struct ir3_compile *
220 compile_init(struct ir3_compiler *compiler,
221 struct ir3_shader_variant *so,
222 const struct tgsi_token *tokens)
223 {
224 struct ir3_compile *ctx = rzalloc(NULL, struct ir3_compile);
225 const struct tgsi_token *lowered_tokens;
226
227 if (compiler->gpu_id >= 400) {
228 /* need special handling for "flat" */
229 ctx->flat_bypass = true;
230 ctx->levels_add_one = false;
231 } else {
232 /* no special handling for "flat" */
233 ctx->flat_bypass = false;
234 ctx->levels_add_one = true;
235 }
236
237 switch (so->type) {
238 case SHADER_FRAGMENT:
239 case SHADER_COMPUTE:
240 ctx->integer_s = so->key.finteger_s;
241 break;
242 case SHADER_VERTEX:
243 ctx->integer_s = so->key.vinteger_s;
244 break;
245 }
246
247 ctx->compiler = compiler;
248 ctx->ir = so->ir;
249 ctx->so = so;
250 ctx->next_inloc = 8;
251 ctx->def_ht = _mesa_hash_table_create(ctx,
252 _mesa_hash_pointer, _mesa_key_pointer_equal);
253 ctx->var_ht = _mesa_hash_table_create(ctx,
254 _mesa_hash_pointer, _mesa_key_pointer_equal);
255 ctx->addr_ht = _mesa_hash_table_create(ctx,
256 _mesa_hash_pointer, _mesa_key_pointer_equal);
257 ctx->block_ht = _mesa_hash_table_create(ctx,
258 _mesa_hash_pointer, _mesa_key_pointer_equal);
259
260 lowered_tokens = lower_tgsi(ctx, tokens, so);
261 if (!lowered_tokens)
262 lowered_tokens = tokens;
263 ctx->s = to_nir(lowered_tokens);
264
265 if (lowered_tokens != tokens)
266 free((void *)lowered_tokens);
267
268 so->first_driver_param = so->first_immediate = ctx->s->num_uniforms;
269
270 /* one (vec4) slot for vertex id base: */
271 if (so->type == SHADER_VERTEX)
272 so->first_immediate++;
273
274 /* reserve 4 (vec4) slots for ubo base addresses: */
275 so->first_immediate += 4;
276
277 return ctx;
278 }
279
280 static void
281 compile_error(struct ir3_compile *ctx, const char *format, ...)
282 {
283 va_list ap;
284 va_start(ap, format);
285 _debug_vprintf(format, ap);
286 va_end(ap);
287 nir_print_shader(ctx->s, stdout);
288 ctx->error = true;
289 debug_assert(0);
290 }
291
292 #define compile_assert(ctx, cond) do { \
293 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
294 } while (0)
295
296 static void
297 compile_free(struct ir3_compile *ctx)
298 {
299 ralloc_free(ctx);
300 }
301
302 /* global per-array information: */
303 struct ir3_array {
304 unsigned length, aid;
305 };
306
307 /* per-block array state: */
308 struct ir3_array_value {
309 /* TODO drop length/aid, and just have ptr back to ir3_array */
310 unsigned length, aid;
311 /* initial array element values are phi's, other than for the
312 * entry block. The phi src's get added later in a resolve step
313 * after we have visited all the blocks, to account for back
314 * edges in the cfg.
315 */
316 struct ir3_instruction **phis;
317 /* current array element values (as block is processed). When
318 * the array phi's are resolved, it will contain the array state
319 * at exit of block, so successor blocks can use it to add their
320 * phi srcs.
321 */
322 struct ir3_instruction *arr[];
323 };
324
325 /* track array assignments per basic block. When an array is read
326 * outside of the same basic block, we can use NIR's dominance-frontier
327 * information to figure out where phi nodes are needed.
328 */
329 struct ir3_nir_block_data {
330 unsigned foo;
331 /* indexed by array-id (aid): */
332 struct ir3_array_value *arrs[];
333 };
334
335 static struct ir3_nir_block_data *
336 get_block_data(struct ir3_compile *ctx, struct ir3_block *block)
337 {
338 if (!block->bd) {
339 struct ir3_nir_block_data *bd = ralloc_size(ctx, sizeof(*bd) +
340 ((ctx->num_arrays + 1) * sizeof(bd->arrs[0])));
341 block->bd = bd;
342 }
343 return block->bd;
344 }
345
346 static void
347 declare_var(struct ir3_compile *ctx, nir_variable *var)
348 {
349 unsigned length = glsl_get_length(var->type) * 4; /* always vec4, at least with ttn */
350 struct ir3_array *arr = ralloc(ctx, struct ir3_array);
351 arr->length = length;
352 arr->aid = ++ctx->num_arrays;
353 _mesa_hash_table_insert(ctx->var_ht, var, arr);
354 }
355
356 static nir_block *
357 nir_block_pred(nir_block *block)
358 {
359 assert(block->predecessors->entries < 2);
360 if (block->predecessors->entries == 0)
361 return NULL;
362 return (nir_block *)_mesa_set_next_entry(block->predecessors, NULL)->key;
363 }
364
365 static struct ir3_array_value *
366 get_var(struct ir3_compile *ctx, nir_variable *var)
367 {
368 struct hash_entry *entry = _mesa_hash_table_search(ctx->var_ht, var);
369 struct ir3_block *block = ctx->block;
370 struct ir3_nir_block_data *bd = get_block_data(ctx, block);
371 struct ir3_array *arr = entry->data;
372
373 if (!bd->arrs[arr->aid]) {
374 struct ir3_array_value *av = ralloc_size(bd, sizeof(*av) +
375 (arr->length * sizeof(av->arr[0])));
376 struct ir3_array_value *defn = NULL;
377 nir_block *pred_block;
378
379 av->length = arr->length;
380 av->aid = arr->aid;
381
382 /* For loops, we have to consider that we have not visited some
383 * of the blocks who should feed into the phi (ie. back-edges in
384 * the cfg).. for example:
385 *
386 * loop {
387 * block { load_var; ... }
388 * if then block {} else block {}
389 * block { store_var; ... }
390 * if then block {} else block {}
391 * block {...}
392 * }
393 *
394 * We can skip the phi if we can chase the block predecessors
395 * until finding the block previously defining the array without
396 * crossing a block that has more than one predecessor.
397 *
398 * Otherwise create phi's and resolve them as a post-pass after
399 * all the blocks have been visited (to handle back-edges).
400 */
401
402 for (pred_block = block->nblock;
403 pred_block && (pred_block->predecessors->entries < 2) && !defn;
404 pred_block = nir_block_pred(pred_block)) {
405 struct ir3_block *pblock = get_block(ctx, pred_block);
406 struct ir3_nir_block_data *pbd = pblock->bd;
407 if (!pbd)
408 continue;
409 defn = pbd->arrs[arr->aid];
410 }
411
412 if (defn) {
413 /* only one possible definer: */
414 for (unsigned i = 0; i < arr->length; i++)
415 av->arr[i] = defn->arr[i];
416 } else if (pred_block) {
417 /* not the first block, and multiple potential definers: */
418 av->phis = ralloc_size(av, arr->length * sizeof(av->phis[0]));
419
420 for (unsigned i = 0; i < arr->length; i++) {
421 struct ir3_instruction *phi;
422
423 phi = ir3_instr_create2(block, -1, OPC_META_PHI,
424 1 + ctx->impl->num_blocks);
425 ir3_reg_create(phi, 0, 0); /* dst */
426
427 /* phi's should go at head of block: */
428 list_delinit(&phi->node);
429 list_add(&phi->node, &block->instr_list);
430
431 av->phis[i] = av->arr[i] = phi;
432 }
433 } else {
434 /* Some shaders end up reading array elements without
435 * first writing.. so initialize things to prevent null
436 * instr ptrs later:
437 */
438 for (unsigned i = 0; i < arr->length; i++)
439 av->arr[i] = create_immed(block, 0);
440 }
441
442 bd->arrs[arr->aid] = av;
443 }
444
445 return bd->arrs[arr->aid];
446 }
447
448 static void
449 add_array_phi_srcs(struct ir3_compile *ctx, nir_block *nblock,
450 struct ir3_array_value *av, BITSET_WORD *visited)
451 {
452 struct ir3_block *block;
453 struct ir3_nir_block_data *bd;
454
455 if (BITSET_TEST(visited, nblock->index))
456 return;
457
458 BITSET_SET(visited, nblock->index);
459
460 block = get_block(ctx, nblock);
461 bd = block->bd;
462
463 if (bd && bd->arrs[av->aid]) {
464 struct ir3_array_value *dav = bd->arrs[av->aid];
465 for (unsigned i = 0; i < av->length; i++) {
466 ir3_reg_create(av->phis[i], 0, IR3_REG_SSA)->instr =
467 dav->arr[i];
468 }
469 } else {
470 /* didn't find defn, recurse predecessors: */
471 struct set_entry *entry;
472 set_foreach(nblock->predecessors, entry) {
473 add_array_phi_srcs(ctx, (nir_block *)entry->key, av, visited);
474 }
475 }
476 }
477
478 static void
479 resolve_array_phis(struct ir3_compile *ctx, struct ir3_block *block)
480 {
481 struct ir3_nir_block_data *bd = block->bd;
482 unsigned bitset_words = BITSET_WORDS(ctx->impl->num_blocks);
483
484 if (!bd)
485 return;
486
487 /* TODO use nir dom_frontier to help us with this? */
488
489 for (unsigned i = 1; i <= ctx->num_arrays; i++) {
490 struct ir3_array_value *av = bd->arrs[i];
491 BITSET_WORD visited[bitset_words];
492 struct set_entry *entry;
493
494 if (!(av && av->phis))
495 continue;
496
497 memset(visited, 0, sizeof(visited));
498 set_foreach(block->nblock->predecessors, entry) {
499 add_array_phi_srcs(ctx, (nir_block *)entry->key, av, visited);
500 }
501 }
502 }
503
504 /* allocate a n element value array (to be populated by caller) and
505 * insert in def_ht
506 */
507 static struct ir3_instruction **
508 __get_dst(struct ir3_compile *ctx, void *key, unsigned n)
509 {
510 struct ir3_instruction **value =
511 ralloc_array(ctx->def_ht, struct ir3_instruction *, n);
512 _mesa_hash_table_insert(ctx->def_ht, key, value);
513 return value;
514 }
515
516 static struct ir3_instruction **
517 get_dst(struct ir3_compile *ctx, nir_dest *dst, unsigned n)
518 {
519 if (dst->is_ssa) {
520 return __get_dst(ctx, &dst->ssa, n);
521 } else {
522 return __get_dst(ctx, dst->reg.reg, n);
523 }
524 }
525
526 static struct ir3_instruction **
527 get_dst_ssa(struct ir3_compile *ctx, nir_ssa_def *dst, unsigned n)
528 {
529 return __get_dst(ctx, dst, n);
530 }
531
532 static struct ir3_instruction **
533 get_src(struct ir3_compile *ctx, nir_src *src)
534 {
535 struct hash_entry *entry;
536 if (src->is_ssa) {
537 entry = _mesa_hash_table_search(ctx->def_ht, src->ssa);
538 } else {
539 entry = _mesa_hash_table_search(ctx->def_ht, src->reg.reg);
540 }
541 compile_assert(ctx, entry);
542 return entry->data;
543 }
544
545 static struct ir3_instruction *
546 create_immed(struct ir3_block *block, uint32_t val)
547 {
548 struct ir3_instruction *mov;
549
550 mov = ir3_instr_create(block, 1, 0);
551 mov->cat1.src_type = TYPE_U32;
552 mov->cat1.dst_type = TYPE_U32;
553 ir3_reg_create(mov, 0, 0);
554 ir3_reg_create(mov, 0, IR3_REG_IMMED)->uim_val = val;
555
556 return mov;
557 }
558
559 static struct ir3_instruction *
560 create_addr(struct ir3_block *block, struct ir3_instruction *src)
561 {
562 struct ir3_instruction *instr, *immed;
563
564 /* TODO in at least some cases, the backend could probably be
565 * made clever enough to propagate IR3_REG_HALF..
566 */
567 instr = ir3_COV(block, src, TYPE_U32, TYPE_S16);
568 instr->regs[0]->flags |= IR3_REG_HALF;
569
570 immed = create_immed(block, 2);
571 immed->regs[0]->flags |= IR3_REG_HALF;
572
573 instr = ir3_SHL_B(block, instr, 0, immed, 0);
574 instr->regs[0]->flags |= IR3_REG_HALF;
575 instr->regs[1]->flags |= IR3_REG_HALF;
576
577 instr = ir3_MOV(block, instr, TYPE_S16);
578 instr->regs[0]->num = regid(REG_A0, 0);
579 instr->regs[0]->flags |= IR3_REG_HALF;
580 instr->regs[1]->flags |= IR3_REG_HALF;
581
582 return instr;
583 }
584
585 /* caches addr values to avoid generating multiple cov/shl/mova
586 * sequences for each use of a given NIR level src as address
587 */
588 static struct ir3_instruction *
589 get_addr(struct ir3_compile *ctx, struct ir3_instruction *src)
590 {
591 struct ir3_instruction *addr;
592 struct hash_entry *entry;
593 entry = _mesa_hash_table_search(ctx->addr_ht, src);
594 if (entry)
595 return entry->data;
596
597 /* TODO do we need to cache per block? */
598 addr = create_addr(ctx->block, src);
599 _mesa_hash_table_insert(ctx->addr_ht, src, addr);
600
601 return addr;
602 }
603
604 static struct ir3_instruction *
605 get_predicate(struct ir3_compile *ctx, struct ir3_instruction *src)
606 {
607 struct ir3_block *b = ctx->block;
608 struct ir3_instruction *cond;
609
610 /* NOTE: only cmps.*.* can write p0.x: */
611 cond = ir3_CMPS_S(b, src, 0, create_immed(b, 0), 0);
612 cond->cat2.condition = IR3_COND_NE;
613
614 /* condition always goes in predicate register: */
615 cond->regs[0]->num = regid(REG_P0, 0);
616
617 return cond;
618 }
619
620 static struct ir3_instruction *
621 create_uniform(struct ir3_compile *ctx, unsigned n)
622 {
623 struct ir3_instruction *mov;
624
625 mov = ir3_instr_create(ctx->block, 1, 0);
626 /* TODO get types right? */
627 mov->cat1.src_type = TYPE_F32;
628 mov->cat1.dst_type = TYPE_F32;
629 ir3_reg_create(mov, 0, 0);
630 ir3_reg_create(mov, n, IR3_REG_CONST);
631
632 return mov;
633 }
634
635 static struct ir3_instruction *
636 create_uniform_indirect(struct ir3_compile *ctx, unsigned n,
637 struct ir3_instruction *address)
638 {
639 struct ir3_instruction *mov;
640
641 mov = ir3_instr_create(ctx->block, 1, 0);
642 mov->cat1.src_type = TYPE_U32;
643 mov->cat1.dst_type = TYPE_U32;
644 ir3_reg_create(mov, 0, 0);
645 ir3_reg_create(mov, n, IR3_REG_CONST | IR3_REG_RELATIV);
646 mov->address = address;
647
648 array_insert(ctx->ir->indirects, mov);
649
650 return mov;
651 }
652
653 static struct ir3_instruction *
654 create_collect(struct ir3_block *block, struct ir3_instruction **arr,
655 unsigned arrsz)
656 {
657 struct ir3_instruction *collect;
658
659 if (arrsz == 0)
660 return NULL;
661
662 collect = ir3_instr_create2(block, -1, OPC_META_FI, 1 + arrsz);
663 ir3_reg_create(collect, 0, 0); /* dst */
664 for (unsigned i = 0; i < arrsz; i++)
665 ir3_reg_create(collect, 0, IR3_REG_SSA)->instr = arr[i];
666
667 return collect;
668 }
669
670 static struct ir3_instruction *
671 create_indirect_load(struct ir3_compile *ctx, unsigned arrsz, unsigned n,
672 struct ir3_instruction *address, struct ir3_instruction *collect)
673 {
674 struct ir3_block *block = ctx->block;
675 struct ir3_instruction *mov;
676 struct ir3_register *src;
677
678 mov = ir3_instr_create(block, 1, 0);
679 mov->cat1.src_type = TYPE_U32;
680 mov->cat1.dst_type = TYPE_U32;
681 ir3_reg_create(mov, 0, 0);
682 src = ir3_reg_create(mov, 0, IR3_REG_SSA | IR3_REG_RELATIV);
683 src->instr = collect;
684 src->size = arrsz;
685 src->offset = n;
686 mov->address = address;
687
688 array_insert(ctx->ir->indirects, mov);
689
690 return mov;
691 }
692
693 static struct ir3_instruction *
694 create_indirect_store(struct ir3_compile *ctx, unsigned arrsz, unsigned n,
695 struct ir3_instruction *src, struct ir3_instruction *address,
696 struct ir3_instruction *collect)
697 {
698 struct ir3_block *block = ctx->block;
699 struct ir3_instruction *mov;
700 struct ir3_register *dst;
701
702 mov = ir3_instr_create(block, 1, 0);
703 mov->cat1.src_type = TYPE_U32;
704 mov->cat1.dst_type = TYPE_U32;
705 dst = ir3_reg_create(mov, 0, IR3_REG_RELATIV);
706 dst->size = arrsz;
707 dst->offset = n;
708 ir3_reg_create(mov, 0, IR3_REG_SSA)->instr = src;
709 mov->address = address;
710 mov->fanin = collect;
711
712 array_insert(ctx->ir->indirects, mov);
713
714 return mov;
715 }
716
717 static struct ir3_instruction *
718 create_input(struct ir3_block *block, struct ir3_instruction *instr,
719 unsigned n)
720 {
721 struct ir3_instruction *in;
722
723 in = ir3_instr_create(block, -1, OPC_META_INPUT);
724 in->inout.block = block;
725 ir3_reg_create(in, n, 0);
726 if (instr)
727 ir3_reg_create(in, 0, IR3_REG_SSA)->instr = instr;
728
729 return in;
730 }
731
732 static struct ir3_instruction *
733 create_frag_input(struct ir3_compile *ctx, unsigned n, bool use_ldlv)
734 {
735 struct ir3_block *block = ctx->block;
736 struct ir3_instruction *instr;
737 struct ir3_instruction *inloc = create_immed(block, n);
738
739 if (use_ldlv) {
740 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
741 instr->cat6.type = TYPE_U32;
742 instr->cat6.iim_val = 1;
743 } else {
744 instr = ir3_BARY_F(block, inloc, 0, ctx->frag_pos, 0);
745 instr->regs[2]->wrmask = 0x3;
746 }
747
748 return instr;
749 }
750
751 static struct ir3_instruction *
752 create_frag_coord(struct ir3_compile *ctx, unsigned comp)
753 {
754 struct ir3_block *block = ctx->block;
755 struct ir3_instruction *instr;
756
757 compile_assert(ctx, !ctx->frag_coord[comp]);
758
759 ctx->frag_coord[comp] = create_input(ctx->block, NULL, 0);
760
761 switch (comp) {
762 case 0: /* .x */
763 case 1: /* .y */
764 /* for frag_coord, we get unsigned values.. we need
765 * to subtract (integer) 8 and divide by 16 (right-
766 * shift by 4) then convert to float:
767 *
768 * sub.s tmp, src, 8
769 * shr.b tmp, tmp, 4
770 * mov.u32f32 dst, tmp
771 *
772 */
773 instr = ir3_SUB_S(block, ctx->frag_coord[comp], 0,
774 create_immed(block, 8), 0);
775 instr = ir3_SHR_B(block, instr, 0,
776 create_immed(block, 4), 0);
777 instr = ir3_COV(block, instr, TYPE_U32, TYPE_F32);
778
779 return instr;
780 case 2: /* .z */
781 case 3: /* .w */
782 default:
783 /* seems that we can use these as-is: */
784 return ctx->frag_coord[comp];
785 }
786 }
787
788 static struct ir3_instruction *
789 create_frag_face(struct ir3_compile *ctx, unsigned comp)
790 {
791 struct ir3_block *block = ctx->block;
792 struct ir3_instruction *instr;
793
794 switch (comp) {
795 case 0: /* .x */
796 compile_assert(ctx, !ctx->frag_face);
797
798 ctx->frag_face = create_input(block, NULL, 0);
799 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
800
801 /* for faceness, we always get -1 or 0 (int).. but TGSI expects
802 * positive vs negative float.. and piglit further seems to
803 * expect -1.0 or 1.0:
804 *
805 * mul.s tmp, hr0.x, 2
806 * add.s tmp, tmp, 1
807 * mov.s32f32, dst, tmp
808 *
809 */
810 instr = ir3_MUL_S(block, ctx->frag_face, 0,
811 create_immed(block, 2), 0);
812 instr = ir3_ADD_S(block, instr, 0,
813 create_immed(block, 1), 0);
814 instr = ir3_COV(block, instr, TYPE_S32, TYPE_F32);
815
816 return instr;
817 case 1: /* .y */
818 case 2: /* .z */
819 return create_immed(block, fui(0.0));
820 default:
821 case 3: /* .w */
822 return create_immed(block, fui(1.0));
823 }
824 }
825
826 /* helper for instructions that produce multiple consecutive scalar
827 * outputs which need to have a split/fanout meta instruction inserted
828 */
829 static void
830 split_dest(struct ir3_block *block, struct ir3_instruction **dst,
831 struct ir3_instruction *src)
832 {
833 struct ir3_instruction *prev = NULL;
834 for (int i = 0, j = 0; i < 4; i++) {
835 struct ir3_instruction *split =
836 ir3_instr_create(block, -1, OPC_META_FO);
837 ir3_reg_create(split, 0, IR3_REG_SSA);
838 ir3_reg_create(split, 0, IR3_REG_SSA)->instr = src;
839 split->fo.off = i;
840
841 if (prev) {
842 split->cp.left = prev;
843 split->cp.left_cnt++;
844 prev->cp.right = split;
845 prev->cp.right_cnt++;
846 }
847 prev = split;
848
849 if (src->regs[0]->wrmask & (1 << i))
850 dst[j++] = split;
851 }
852 }
853
854 /*
855 * Adreno uses uint rather than having dedicated bool type,
856 * which (potentially) requires some conversion, in particular
857 * when using output of an bool instr to int input, or visa
858 * versa.
859 *
860 * | Adreno | NIR |
861 * -------+---------+-------+-
862 * true | 1 | ~0 |
863 * false | 0 | 0 |
864 *
865 * To convert from an adreno bool (uint) to nir, use:
866 *
867 * absneg.s dst, (neg)src
868 *
869 * To convert back in the other direction:
870 *
871 * absneg.s dst, (abs)arc
872 *
873 * The CP step can clean up the absneg.s that cancel each other
874 * out, and with a slight bit of extra cleverness (to recognize
875 * the instructions which produce either a 0 or 1) can eliminate
876 * the absneg.s's completely when an instruction that wants
877 * 0/1 consumes the result. For example, when a nir 'bcsel'
878 * consumes the result of 'feq'. So we should be able to get by
879 * without a boolean resolve step, and without incuring any
880 * extra penalty in instruction count.
881 */
882
883 /* NIR bool -> native (adreno): */
884 static struct ir3_instruction *
885 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
886 {
887 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
888 }
889
890 /* native (adreno) -> NIR bool: */
891 static struct ir3_instruction *
892 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
893 {
894 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
895 }
896
897 /*
898 * alu/sfu instructions:
899 */
900
901 static void
902 emit_alu(struct ir3_compile *ctx, nir_alu_instr *alu)
903 {
904 const nir_op_info *info = &nir_op_infos[alu->op];
905 struct ir3_instruction **dst, *src[info->num_inputs];
906 struct ir3_block *b = ctx->block;
907
908 dst = get_dst(ctx, &alu->dest.dest, MAX2(info->output_size, 1));
909
910 /* Vectors are special in that they have non-scalarized writemasks,
911 * and just take the first swizzle channel for each argument in
912 * order into each writemask channel.
913 */
914 if ((alu->op == nir_op_vec2) ||
915 (alu->op == nir_op_vec3) ||
916 (alu->op == nir_op_vec4)) {
917
918 for (int i = 0; i < info->num_inputs; i++) {
919 nir_alu_src *asrc = &alu->src[i];
920
921 compile_assert(ctx, !asrc->abs);
922 compile_assert(ctx, !asrc->negate);
923
924 src[i] = get_src(ctx, &asrc->src)[asrc->swizzle[0]];
925 if (!src[i])
926 src[i] = create_immed(ctx->block, 0);
927 dst[i] = ir3_MOV(b, src[i], TYPE_U32);
928 }
929
930 return;
931 }
932
933 /* General case: We can just grab the one used channel per src. */
934 for (int i = 0; i < info->num_inputs; i++) {
935 unsigned chan = ffs(alu->dest.write_mask) - 1;
936 nir_alu_src *asrc = &alu->src[i];
937
938 compile_assert(ctx, !asrc->abs);
939 compile_assert(ctx, !asrc->negate);
940
941 src[i] = get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
942
943 compile_assert(ctx, src[i]);
944 }
945
946 switch (alu->op) {
947 case nir_op_f2i:
948 dst[0] = ir3_COV(b, src[0], TYPE_F32, TYPE_S32);
949 break;
950 case nir_op_f2u:
951 dst[0] = ir3_COV(b, src[0], TYPE_F32, TYPE_U32);
952 break;
953 case nir_op_i2f:
954 dst[0] = ir3_COV(b, src[0], TYPE_S32, TYPE_F32);
955 break;
956 case nir_op_u2f:
957 dst[0] = ir3_COV(b, src[0], TYPE_U32, TYPE_F32);
958 break;
959 case nir_op_imov:
960 dst[0] = ir3_MOV(b, src[0], TYPE_S32);
961 break;
962 case nir_op_fmov:
963 dst[0] = ir3_MOV(b, src[0], TYPE_F32);
964 break;
965 case nir_op_f2b:
966 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
967 dst[0]->cat2.condition = IR3_COND_NE;
968 dst[0] = ir3_n2b(b, dst[0]);
969 break;
970 case nir_op_b2f:
971 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
972 break;
973 case nir_op_b2i:
974 dst[0] = ir3_b2n(b, src[0]);
975 break;
976 case nir_op_i2b:
977 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
978 dst[0]->cat2.condition = IR3_COND_NE;
979 dst[0] = ir3_n2b(b, dst[0]);
980 break;
981
982 case nir_op_fneg:
983 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
984 break;
985 case nir_op_fabs:
986 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
987 break;
988 case nir_op_fmax:
989 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
990 break;
991 case nir_op_fmin:
992 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
993 break;
994 case nir_op_fmul:
995 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
996 break;
997 case nir_op_fadd:
998 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
999 break;
1000 case nir_op_fsub:
1001 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
1002 break;
1003 case nir_op_ffma:
1004 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
1005 break;
1006 case nir_op_fddx:
1007 dst[0] = ir3_DSX(b, src[0], 0);
1008 dst[0]->cat5.type = TYPE_F32;
1009 break;
1010 case nir_op_fddy:
1011 dst[0] = ir3_DSY(b, src[0], 0);
1012 dst[0]->cat5.type = TYPE_F32;
1013 break;
1014 break;
1015 case nir_op_flt:
1016 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
1017 dst[0]->cat2.condition = IR3_COND_LT;
1018 dst[0] = ir3_n2b(b, dst[0]);
1019 break;
1020 case nir_op_fge:
1021 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
1022 dst[0]->cat2.condition = IR3_COND_GE;
1023 dst[0] = ir3_n2b(b, dst[0]);
1024 break;
1025 case nir_op_feq:
1026 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
1027 dst[0]->cat2.condition = IR3_COND_EQ;
1028 dst[0] = ir3_n2b(b, dst[0]);
1029 break;
1030 case nir_op_fne:
1031 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
1032 dst[0]->cat2.condition = IR3_COND_NE;
1033 dst[0] = ir3_n2b(b, dst[0]);
1034 break;
1035 case nir_op_fceil:
1036 dst[0] = ir3_CEIL_F(b, src[0], 0);
1037 break;
1038 case nir_op_ffloor:
1039 dst[0] = ir3_FLOOR_F(b, src[0], 0);
1040 break;
1041 case nir_op_ftrunc:
1042 dst[0] = ir3_TRUNC_F(b, src[0], 0);
1043 break;
1044 case nir_op_fround_even:
1045 dst[0] = ir3_RNDNE_F(b, src[0], 0);
1046 break;
1047 case nir_op_fsign:
1048 dst[0] = ir3_SIGN_F(b, src[0], 0);
1049 break;
1050
1051 case nir_op_fsin:
1052 dst[0] = ir3_SIN(b, src[0], 0);
1053 break;
1054 case nir_op_fcos:
1055 dst[0] = ir3_COS(b, src[0], 0);
1056 break;
1057 case nir_op_frsq:
1058 dst[0] = ir3_RSQ(b, src[0], 0);
1059 break;
1060 case nir_op_frcp:
1061 dst[0] = ir3_RCP(b, src[0], 0);
1062 break;
1063 case nir_op_flog2:
1064 dst[0] = ir3_LOG2(b, src[0], 0);
1065 break;
1066 case nir_op_fexp2:
1067 dst[0] = ir3_EXP2(b, src[0], 0);
1068 break;
1069 case nir_op_fsqrt:
1070 dst[0] = ir3_SQRT(b, src[0], 0);
1071 break;
1072
1073 case nir_op_iabs:
1074 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
1075 break;
1076 case nir_op_iadd:
1077 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
1078 break;
1079 case nir_op_iand:
1080 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
1081 break;
1082 case nir_op_imax:
1083 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
1084 break;
1085 case nir_op_imin:
1086 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
1087 break;
1088 case nir_op_imul:
1089 /*
1090 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
1091 * mull.u tmp0, a, b ; mul low, i.e. al * bl
1092 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
1093 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
1094 */
1095 dst[0] = ir3_MADSH_M16(b, src[1], 0, src[0], 0,
1096 ir3_MADSH_M16(b, src[0], 0, src[1], 0,
1097 ir3_MULL_U(b, src[0], 0, src[1], 0), 0), 0);
1098 break;
1099 case nir_op_ineg:
1100 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
1101 break;
1102 case nir_op_inot:
1103 dst[0] = ir3_NOT_B(b, src[0], 0);
1104 break;
1105 case nir_op_ior:
1106 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
1107 break;
1108 case nir_op_ishl:
1109 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
1110 break;
1111 case nir_op_ishr:
1112 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
1113 break;
1114 case nir_op_isign: {
1115 /* maybe this would be sane to lower in nir.. */
1116 struct ir3_instruction *neg, *pos;
1117
1118 neg = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
1119 neg->cat2.condition = IR3_COND_LT;
1120
1121 pos = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
1122 pos->cat2.condition = IR3_COND_GT;
1123
1124 dst[0] = ir3_SUB_U(b, pos, 0, neg, 0);
1125
1126 break;
1127 }
1128 case nir_op_isub:
1129 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
1130 break;
1131 case nir_op_ixor:
1132 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
1133 break;
1134 case nir_op_ushr:
1135 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
1136 break;
1137 case nir_op_ilt:
1138 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
1139 dst[0]->cat2.condition = IR3_COND_LT;
1140 dst[0] = ir3_n2b(b, dst[0]);
1141 break;
1142 case nir_op_ige:
1143 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
1144 dst[0]->cat2.condition = IR3_COND_GE;
1145 dst[0] = ir3_n2b(b, dst[0]);
1146 break;
1147 case nir_op_ieq:
1148 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
1149 dst[0]->cat2.condition = IR3_COND_EQ;
1150 dst[0] = ir3_n2b(b, dst[0]);
1151 break;
1152 case nir_op_ine:
1153 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
1154 dst[0]->cat2.condition = IR3_COND_NE;
1155 dst[0] = ir3_n2b(b, dst[0]);
1156 break;
1157 case nir_op_ult:
1158 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
1159 dst[0]->cat2.condition = IR3_COND_LT;
1160 dst[0] = ir3_n2b(b, dst[0]);
1161 break;
1162 case nir_op_uge:
1163 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
1164 dst[0]->cat2.condition = IR3_COND_GE;
1165 dst[0] = ir3_n2b(b, dst[0]);
1166 break;
1167
1168 case nir_op_bcsel:
1169 dst[0] = ir3_SEL_B32(b, src[1], 0, ir3_b2n(b, src[0]), 0, src[2], 0);
1170 break;
1171
1172 default:
1173 compile_error(ctx, "Unhandled ALU op: %s\n",
1174 nir_op_infos[alu->op].name);
1175 break;
1176 }
1177 }
1178
1179 /* handles direct/indirect UBO reads: */
1180 static void
1181 emit_intrinsic_load_ubo(struct ir3_compile *ctx, nir_intrinsic_instr *intr,
1182 struct ir3_instruction **dst)
1183 {
1184 struct ir3_block *b = ctx->block;
1185 struct ir3_instruction *addr, *src0, *src1;
1186 /* UBO addresses are the first driver params: */
1187 unsigned ubo = regid(ctx->so->first_driver_param, 0);
1188 unsigned off = intr->const_index[0];
1189
1190 /* First src is ubo index, which could either be an immed or not: */
1191 src0 = get_src(ctx, &intr->src[0])[0];
1192 if (is_same_type_mov(src0) &&
1193 (src0->regs[1]->flags & IR3_REG_IMMED)) {
1194 addr = create_uniform(ctx, ubo + src0->regs[1]->iim_val);
1195 } else {
1196 addr = create_uniform_indirect(ctx, ubo, get_addr(ctx, src0));
1197 }
1198
1199 if (intr->intrinsic == nir_intrinsic_load_ubo_indirect) {
1200 /* For load_ubo_indirect, second src is indirect offset: */
1201 src1 = get_src(ctx, &intr->src[1])[0];
1202
1203 /* and add offset to addr: */
1204 addr = ir3_ADD_S(b, addr, 0, src1, 0);
1205 }
1206
1207 /* if offset is to large to encode in the ldg, split it out: */
1208 if ((off + (intr->num_components * 4)) > 1024) {
1209 /* split out the minimal amount to improve the odds that
1210 * cp can fit the immediate in the add.s instruction:
1211 */
1212 unsigned off2 = off + (intr->num_components * 4) - 1024;
1213 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
1214 off -= off2;
1215 }
1216
1217 for (int i = 0; i < intr->num_components; i++) {
1218 struct ir3_instruction *load =
1219 ir3_LDG(b, addr, 0, create_immed(b, 1), 0);
1220 load->cat6.type = TYPE_U32;
1221 load->cat6.offset = off + i * 4; /* byte offset */
1222 dst[i] = load;
1223 }
1224 }
1225
1226 /* handles array reads: */
1227 static void
1228 emit_intrinisic_load_var(struct ir3_compile *ctx, nir_intrinsic_instr *intr,
1229 struct ir3_instruction **dst)
1230 {
1231 nir_deref_var *dvar = intr->variables[0];
1232 nir_deref_array *darr = nir_deref_as_array(dvar->deref.child);
1233 struct ir3_array_value *arr = get_var(ctx, dvar->var);
1234
1235 compile_assert(ctx, dvar->deref.child &&
1236 (dvar->deref.child->deref_type == nir_deref_type_array));
1237
1238 switch (darr->deref_array_type) {
1239 case nir_deref_array_type_direct:
1240 /* direct access does not require anything special: */
1241 for (int i = 0; i < intr->num_components; i++) {
1242 unsigned n = darr->base_offset * 4 + i;
1243 compile_assert(ctx, n < arr->length);
1244 dst[i] = arr->arr[n];
1245 }
1246 break;
1247 case nir_deref_array_type_indirect: {
1248 /* for indirect, we need to collect all the array elements: */
1249 struct ir3_instruction *collect =
1250 create_collect(ctx->block, arr->arr, arr->length);
1251 struct ir3_instruction *addr =
1252 get_addr(ctx, get_src(ctx, &darr->indirect)[0]);
1253 for (int i = 0; i < intr->num_components; i++) {
1254 unsigned n = darr->base_offset * 4 + i;
1255 compile_assert(ctx, n < arr->length);
1256 dst[i] = create_indirect_load(ctx, arr->length, n, addr, collect);
1257 }
1258 break;
1259 }
1260 default:
1261 compile_error(ctx, "Unhandled load deref type: %u\n",
1262 darr->deref_array_type);
1263 break;
1264 }
1265 }
1266
1267 /* handles array writes: */
1268 static void
1269 emit_intrinisic_store_var(struct ir3_compile *ctx, nir_intrinsic_instr *intr)
1270 {
1271 nir_deref_var *dvar = intr->variables[0];
1272 nir_deref_array *darr = nir_deref_as_array(dvar->deref.child);
1273 struct ir3_array_value *arr = get_var(ctx, dvar->var);
1274 struct ir3_instruction **src;
1275
1276 compile_assert(ctx, dvar->deref.child &&
1277 (dvar->deref.child->deref_type == nir_deref_type_array));
1278
1279 src = get_src(ctx, &intr->src[0]);
1280
1281 switch (darr->deref_array_type) {
1282 case nir_deref_array_type_direct:
1283 /* direct access does not require anything special: */
1284 for (int i = 0; i < intr->num_components; i++) {
1285 unsigned n = darr->base_offset * 4 + i;
1286 compile_assert(ctx, n < arr->length);
1287 arr->arr[n] = src[i];
1288 }
1289 break;
1290 case nir_deref_array_type_indirect: {
1291 /* for indirect, create indirect-store and fan that out: */
1292 struct ir3_instruction *collect =
1293 create_collect(ctx->block, arr->arr, arr->length);
1294 struct ir3_instruction *addr =
1295 get_addr(ctx, get_src(ctx, &darr->indirect)[0]);
1296 for (int i = 0; i < intr->num_components; i++) {
1297 struct ir3_instruction *store;
1298 unsigned n = darr->base_offset * 4 + i;
1299 compile_assert(ctx, n < arr->length);
1300
1301 store = create_indirect_store(ctx, arr->length,
1302 n, src[i], addr, collect);
1303
1304 store->fanin->fi.aid = arr->aid;
1305
1306 /* TODO: probably split this out to be used for
1307 * store_output_indirect? or move this into
1308 * create_indirect_store()?
1309 */
1310 for (int j = i; j < arr->length; j += 4) {
1311 struct ir3_instruction *split;
1312
1313 split = ir3_instr_create(ctx->block, -1, OPC_META_FO);
1314 split->fo.off = j;
1315 ir3_reg_create(split, 0, 0);
1316 ir3_reg_create(split, 0, IR3_REG_SSA)->instr = store;
1317
1318 arr->arr[j] = split;
1319 }
1320 }
1321 break;
1322 }
1323 default:
1324 compile_error(ctx, "Unhandled store deref type: %u\n",
1325 darr->deref_array_type);
1326 break;
1327 }
1328 }
1329
1330 static void add_sysval_input(struct ir3_compile *ctx, unsigned name,
1331 struct ir3_instruction *instr)
1332 {
1333 struct ir3_shader_variant *so = ctx->so;
1334 unsigned r = regid(so->inputs_count, 0);
1335 unsigned n = so->inputs_count++;
1336
1337 so->inputs[n].semantic = ir3_semantic_name(name, 0);
1338 so->inputs[n].compmask = 1;
1339 so->inputs[n].regid = r;
1340 so->inputs[n].interpolate = TGSI_INTERPOLATE_CONSTANT;
1341 so->total_in++;
1342
1343 ctx->ir->ninputs = MAX2(ctx->ir->ninputs, r + 1);
1344 ctx->ir->inputs[r] = instr;
1345 }
1346
1347 static void
1348 emit_intrinisic(struct ir3_compile *ctx, nir_intrinsic_instr *intr)
1349 {
1350 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1351 struct ir3_instruction **dst, **src;
1352 struct ir3_block *b = ctx->block;
1353 unsigned idx = intr->const_index[0];
1354
1355 if (info->has_dest) {
1356 dst = get_dst(ctx, &intr->dest, intr->num_components);
1357 } else {
1358 dst = NULL;
1359 }
1360
1361 switch (intr->intrinsic) {
1362 case nir_intrinsic_load_uniform:
1363 for (int i = 0; i < intr->num_components; i++) {
1364 unsigned n = idx * 4 + i;
1365 dst[i] = create_uniform(ctx, n);
1366 }
1367 break;
1368 case nir_intrinsic_load_uniform_indirect:
1369 src = get_src(ctx, &intr->src[0]);
1370 for (int i = 0; i < intr->num_components; i++) {
1371 unsigned n = idx * 4 + i;
1372 dst[i] = create_uniform_indirect(ctx, n,
1373 get_addr(ctx, src[0]));
1374 }
1375 break;
1376 case nir_intrinsic_load_ubo:
1377 case nir_intrinsic_load_ubo_indirect:
1378 emit_intrinsic_load_ubo(ctx, intr, dst);
1379 break;
1380 case nir_intrinsic_load_input:
1381 for (int i = 0; i < intr->num_components; i++) {
1382 unsigned n = idx * 4 + i;
1383 dst[i] = ctx->ir->inputs[n];
1384 }
1385 break;
1386 case nir_intrinsic_load_input_indirect:
1387 src = get_src(ctx, &intr->src[0]);
1388 struct ir3_instruction *collect =
1389 create_collect(b, ctx->ir->inputs, ctx->ir->ninputs);
1390 struct ir3_instruction *addr = get_addr(ctx, src[0]);
1391 for (int i = 0; i < intr->num_components; i++) {
1392 unsigned n = idx * 4 + i;
1393 dst[i] = create_indirect_load(ctx, ctx->ir->ninputs,
1394 n, addr, collect);
1395 }
1396 break;
1397 case nir_intrinsic_load_var:
1398 emit_intrinisic_load_var(ctx, intr, dst);
1399 break;
1400 case nir_intrinsic_store_var:
1401 emit_intrinisic_store_var(ctx, intr);
1402 break;
1403 case nir_intrinsic_store_output:
1404 src = get_src(ctx, &intr->src[0]);
1405 for (int i = 0; i < intr->num_components; i++) {
1406 unsigned n = idx * 4 + i;
1407 ctx->ir->outputs[n] = src[i];
1408 }
1409 break;
1410 case nir_intrinsic_load_base_vertex:
1411 if (!ctx->basevertex) {
1412 /* first four vec4 sysval's reserved for UBOs: */
1413 unsigned r = regid(ctx->so->first_driver_param + 4, 0);
1414 ctx->basevertex = create_uniform(ctx, r);
1415 add_sysval_input(ctx, TGSI_SEMANTIC_BASEVERTEX,
1416 ctx->basevertex);
1417 }
1418 dst[0] = ctx->basevertex;
1419 break;
1420 case nir_intrinsic_load_vertex_id_zero_base:
1421 if (!ctx->vertex_id) {
1422 ctx->vertex_id = create_input(ctx->block, NULL, 0);
1423 add_sysval_input(ctx, TGSI_SEMANTIC_VERTEXID_NOBASE,
1424 ctx->vertex_id);
1425 }
1426 dst[0] = ctx->vertex_id;
1427 break;
1428 case nir_intrinsic_load_instance_id:
1429 if (!ctx->instance_id) {
1430 ctx->instance_id = create_input(ctx->block, NULL, 0);
1431 add_sysval_input(ctx, TGSI_SEMANTIC_INSTANCEID,
1432 ctx->instance_id);
1433 }
1434 dst[0] = ctx->instance_id;
1435 break;
1436 case nir_intrinsic_discard_if:
1437 case nir_intrinsic_discard: {
1438 struct ir3_instruction *cond, *kill;
1439
1440 if (intr->intrinsic == nir_intrinsic_discard_if) {
1441 /* conditional discard: */
1442 src = get_src(ctx, &intr->src[0]);
1443 cond = ir3_b2n(b, src[0]);
1444 } else {
1445 /* unconditional discard: */
1446 cond = create_immed(b, 1);
1447 }
1448
1449 /* NOTE: only cmps.*.* can write p0.x: */
1450 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1451 cond->cat2.condition = IR3_COND_NE;
1452
1453 /* condition always goes in predicate register: */
1454 cond->regs[0]->num = regid(REG_P0, 0);
1455
1456 kill = ir3_KILL(b, cond, 0);
1457 array_insert(ctx->ir->predicates, kill);
1458
1459 ctx->kill[ctx->kill_count++] = kill;
1460 ctx->so->has_kill = true;
1461
1462 break;
1463 }
1464 default:
1465 compile_error(ctx, "Unhandled intrinsic type: %s\n",
1466 nir_intrinsic_infos[intr->intrinsic].name);
1467 break;
1468 }
1469 }
1470
1471 static void
1472 emit_load_const(struct ir3_compile *ctx, nir_load_const_instr *instr)
1473 {
1474 struct ir3_instruction **dst = get_dst_ssa(ctx, &instr->def,
1475 instr->def.num_components);
1476 for (int i = 0; i < instr->def.num_components; i++)
1477 dst[i] = create_immed(ctx->block, instr->value.u[i]);
1478 }
1479
1480 static void
1481 emit_undef(struct ir3_compile *ctx, nir_ssa_undef_instr *undef)
1482 {
1483 struct ir3_instruction **dst = get_dst_ssa(ctx, &undef->def,
1484 undef->def.num_components);
1485 /* backend doesn't want undefined instructions, so just plug
1486 * in 0.0..
1487 */
1488 for (int i = 0; i < undef->def.num_components; i++)
1489 dst[i] = create_immed(ctx->block, fui(0.0));
1490 }
1491
1492 /*
1493 * texture fetch/sample instructions:
1494 */
1495
1496 static void
1497 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1498 {
1499 unsigned coords, flags = 0;
1500
1501 /* note: would use tex->coord_components.. except txs.. also,
1502 * since array index goes after shadow ref, we don't want to
1503 * count it:
1504 */
1505 switch (tex->sampler_dim) {
1506 case GLSL_SAMPLER_DIM_1D:
1507 case GLSL_SAMPLER_DIM_BUF:
1508 coords = 1;
1509 break;
1510 case GLSL_SAMPLER_DIM_2D:
1511 case GLSL_SAMPLER_DIM_RECT:
1512 case GLSL_SAMPLER_DIM_EXTERNAL:
1513 case GLSL_SAMPLER_DIM_MS:
1514 coords = 2;
1515 break;
1516 case GLSL_SAMPLER_DIM_3D:
1517 case GLSL_SAMPLER_DIM_CUBE:
1518 coords = 3;
1519 flags |= IR3_INSTR_3D;
1520 break;
1521 default:
1522 unreachable("bad sampler_dim");
1523 }
1524
1525 if (tex->is_shadow)
1526 flags |= IR3_INSTR_S;
1527
1528 if (tex->is_array)
1529 flags |= IR3_INSTR_A;
1530
1531 *flagsp = flags;
1532 *coordsp = coords;
1533 }
1534
1535 static void
1536 emit_tex(struct ir3_compile *ctx, nir_tex_instr *tex)
1537 {
1538 struct ir3_block *b = ctx->block;
1539 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1540 struct ir3_instruction **coord, *lod, *compare, *proj, **off, **ddx, **ddy;
1541 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1542 unsigned i, coords, flags;
1543 unsigned nsrc0 = 0, nsrc1 = 0;
1544 type_t type;
1545 opc_t opc = 0;
1546
1547 coord = off = ddx = ddy = NULL;
1548 lod = proj = compare = NULL;
1549
1550 /* TODO: might just be one component for gathers? */
1551 dst = get_dst(ctx, &tex->dest, 4);
1552
1553 for (unsigned i = 0; i < tex->num_srcs; i++) {
1554 switch (tex->src[i].src_type) {
1555 case nir_tex_src_coord:
1556 coord = get_src(ctx, &tex->src[i].src);
1557 break;
1558 case nir_tex_src_bias:
1559 lod = get_src(ctx, &tex->src[i].src)[0];
1560 has_bias = true;
1561 break;
1562 case nir_tex_src_lod:
1563 lod = get_src(ctx, &tex->src[i].src)[0];
1564 has_lod = true;
1565 break;
1566 case nir_tex_src_comparitor: /* shadow comparator */
1567 compare = get_src(ctx, &tex->src[i].src)[0];
1568 break;
1569 case nir_tex_src_projector:
1570 proj = get_src(ctx, &tex->src[i].src)[0];
1571 has_proj = true;
1572 break;
1573 case nir_tex_src_offset:
1574 off = get_src(ctx, &tex->src[i].src);
1575 has_off = true;
1576 break;
1577 case nir_tex_src_ddx:
1578 ddx = get_src(ctx, &tex->src[i].src);
1579 break;
1580 case nir_tex_src_ddy:
1581 ddy = get_src(ctx, &tex->src[i].src);
1582 break;
1583 default:
1584 compile_error(ctx, "Unhandled NIR tex serc type: %d\n",
1585 tex->src[i].src_type);
1586 return;
1587 }
1588 }
1589
1590 switch (tex->op) {
1591 case nir_texop_tex: opc = OPC_SAM; break;
1592 case nir_texop_txb: opc = OPC_SAMB; break;
1593 case nir_texop_txl: opc = OPC_SAML; break;
1594 case nir_texop_txd: opc = OPC_SAMGQ; break;
1595 case nir_texop_txf: opc = OPC_ISAML; break;
1596 case nir_texop_txf_ms:
1597 case nir_texop_txs:
1598 case nir_texop_lod:
1599 case nir_texop_tg4:
1600 case nir_texop_query_levels:
1601 compile_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
1602 return;
1603 }
1604
1605 tex_info(tex, &flags, &coords);
1606
1607 /* scale up integer coords for TXF based on the LOD */
1608 if (opc == OPC_ISAML) {
1609 assert(has_lod);
1610 for (i = 0; i < coords; i++)
1611 coord[i] = ir3_SHL_B(b, coord[i], 0, lod, 0);
1612 }
1613 /*
1614 * lay out the first argument in the proper order:
1615 * - actual coordinates first
1616 * - shadow reference
1617 * - array index
1618 * - projection w
1619 * - starting at offset 4, dpdx.xy, dpdy.xy
1620 *
1621 * bias/lod go into the second arg
1622 */
1623
1624 /* insert tex coords: */
1625 for (i = 0; i < coords; i++)
1626 src0[nsrc0++] = coord[i];
1627
1628 if (coords == 1) {
1629 /* hw doesn't do 1d, so we treat it as 2d with
1630 * height of 1, and patch up the y coord.
1631 * TODO: y coord should be (int)0 in some cases..
1632 */
1633 src0[nsrc0++] = create_immed(b, fui(0.5));
1634 }
1635
1636 if (tex->is_shadow)
1637 src0[nsrc0++] = compare;
1638
1639 if (tex->is_array)
1640 src0[nsrc0++] = coord[coords];
1641
1642 if (has_proj) {
1643 src0[nsrc0++] = proj;
1644 flags |= IR3_INSTR_P;
1645 }
1646
1647 /* pad to 4, then ddx/ddy: */
1648 if (tex->op == nir_texop_txd) {
1649 while (nsrc0 < 4)
1650 src0[nsrc0++] = create_immed(b, fui(0.0));
1651 for (i = 0; i < coords; i++)
1652 src0[nsrc0++] = ddx[i];
1653 if (coords < 2)
1654 src0[nsrc0++] = create_immed(b, fui(0.0));
1655 for (i = 0; i < coords; i++)
1656 src0[nsrc0++] = ddy[i];
1657 if (coords < 2)
1658 src0[nsrc0++] = create_immed(b, fui(0.0));
1659 }
1660
1661 /*
1662 * second argument (if applicable):
1663 * - offsets
1664 * - lod
1665 * - bias
1666 */
1667 if (has_off | has_lod | has_bias) {
1668 if (has_off) {
1669 for (i = 0; i < coords; i++)
1670 src1[nsrc1++] = off[i];
1671 if (coords < 2)
1672 src1[nsrc1++] = create_immed(b, fui(0.0));
1673 flags |= IR3_INSTR_O;
1674 }
1675
1676 if (has_lod | has_bias)
1677 src1[nsrc1++] = lod;
1678 }
1679
1680 switch (tex->dest_type) {
1681 case nir_type_invalid:
1682 case nir_type_float:
1683 type = TYPE_F32;
1684 break;
1685 case nir_type_int:
1686 type = TYPE_S32;
1687 break;
1688 case nir_type_unsigned:
1689 case nir_type_bool:
1690 type = TYPE_U32;
1691 break;
1692 default:
1693 unreachable("bad dest_type");
1694 }
1695
1696 sam = ir3_SAM(b, opc, type, TGSI_WRITEMASK_XYZW,
1697 flags, tex->sampler_index, tex->sampler_index,
1698 create_collect(b, src0, nsrc0),
1699 create_collect(b, src1, nsrc1));
1700
1701 split_dest(b, dst, sam);
1702 }
1703
1704 static void
1705 emit_tex_query_levels(struct ir3_compile *ctx, nir_tex_instr *tex)
1706 {
1707 struct ir3_block *b = ctx->block;
1708 struct ir3_instruction **dst, *sam;
1709
1710 dst = get_dst(ctx, &tex->dest, 1);
1711
1712 sam = ir3_SAM(b, OPC_GETINFO, TYPE_U32, TGSI_WRITEMASK_Z, 0,
1713 tex->sampler_index, tex->sampler_index, NULL, NULL);
1714
1715 /* even though there is only one component, since it ends
1716 * up in .z rather than .x, we need a split_dest()
1717 */
1718 split_dest(b, dst, sam);
1719
1720 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1721 * the value in TEX_CONST_0 is zero-based.
1722 */
1723 if (ctx->levels_add_one)
1724 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
1725 }
1726
1727 static void
1728 emit_tex_txs(struct ir3_compile *ctx, nir_tex_instr *tex)
1729 {
1730 struct ir3_block *b = ctx->block;
1731 struct ir3_instruction **dst, *sam, *lod;
1732 unsigned flags, coords;
1733
1734 tex_info(tex, &flags, &coords);
1735
1736 dst = get_dst(ctx, &tex->dest, 4);
1737
1738 compile_assert(ctx, tex->num_srcs == 1);
1739 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod);
1740
1741 lod = get_src(ctx, &tex->src[0].src)[0];
1742
1743 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, TGSI_WRITEMASK_XYZW, flags,
1744 tex->sampler_index, tex->sampler_index, lod, NULL);
1745
1746 split_dest(b, dst, sam);
1747
1748 /* Array size actually ends up in .w rather than .z. This doesn't
1749 * matter for miplevel 0, but for higher mips the value in z is
1750 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1751 * returned, which means that we have to add 1 to it for arrays.
1752 */
1753 if (tex->is_array) {
1754 if (ctx->levels_add_one) {
1755 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
1756 } else {
1757 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
1758 }
1759 }
1760 }
1761
1762 static void
1763 emit_phi(struct ir3_compile *ctx, nir_phi_instr *nphi)
1764 {
1765 struct ir3_instruction *phi, **dst;
1766
1767 /* NOTE: phi's should be lowered to scalar at this point */
1768 compile_assert(ctx, nphi->dest.ssa.num_components == 1);
1769
1770 dst = get_dst(ctx, &nphi->dest, 1);
1771
1772 phi = ir3_instr_create2(ctx->block, -1, OPC_META_PHI,
1773 1 + exec_list_length(&nphi->srcs));
1774 ir3_reg_create(phi, 0, 0); /* dst */
1775 phi->phi.nphi = nphi;
1776
1777 dst[0] = phi;
1778 }
1779
1780 /* phi instructions are left partially constructed. We don't resolve
1781 * their srcs until the end of the block, since (eg. loops) one of
1782 * the phi's srcs might be defined after the phi due to back edges in
1783 * the CFG.
1784 */
1785 static void
1786 resolve_phis(struct ir3_compile *ctx, struct ir3_block *block)
1787 {
1788 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
1789 nir_phi_instr *nphi;
1790
1791 /* phi's only come at start of block: */
1792 if (!(is_meta(instr) && (instr->opc == OPC_META_PHI)))
1793 break;
1794
1795 if (!instr->phi.nphi)
1796 break;
1797
1798 nphi = instr->phi.nphi;
1799 instr->phi.nphi = NULL;
1800
1801 foreach_list_typed(nir_phi_src, nsrc, node, &nphi->srcs) {
1802 struct ir3_instruction *src = get_src(ctx, &nsrc->src)[0];
1803 ir3_reg_create(instr, 0, IR3_REG_SSA)->instr = src;
1804 }
1805 }
1806
1807 resolve_array_phis(ctx, block);
1808 }
1809
1810 static void
1811 emit_jump(struct ir3_compile *ctx, nir_jump_instr *jump)
1812 {
1813 switch (jump->type) {
1814 case nir_jump_break:
1815 case nir_jump_continue:
1816 /* I *think* we can simply just ignore this, and use the
1817 * successor block link to figure out where we need to
1818 * jump to for break/continue
1819 */
1820 break;
1821 default:
1822 compile_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
1823 break;
1824 }
1825 }
1826
1827 static void
1828 emit_instr(struct ir3_compile *ctx, nir_instr *instr)
1829 {
1830 switch (instr->type) {
1831 case nir_instr_type_alu:
1832 emit_alu(ctx, nir_instr_as_alu(instr));
1833 break;
1834 case nir_instr_type_intrinsic:
1835 emit_intrinisic(ctx, nir_instr_as_intrinsic(instr));
1836 break;
1837 case nir_instr_type_load_const:
1838 emit_load_const(ctx, nir_instr_as_load_const(instr));
1839 break;
1840 case nir_instr_type_ssa_undef:
1841 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
1842 break;
1843 case nir_instr_type_tex: {
1844 nir_tex_instr *tex = nir_instr_as_tex(instr);
1845 /* couple tex instructions get special-cased:
1846 */
1847 switch (tex->op) {
1848 case nir_texop_txs:
1849 emit_tex_txs(ctx, tex);
1850 break;
1851 case nir_texop_query_levels:
1852 emit_tex_query_levels(ctx, tex);
1853 break;
1854 default:
1855 emit_tex(ctx, tex);
1856 break;
1857 }
1858 break;
1859 }
1860 case nir_instr_type_phi:
1861 emit_phi(ctx, nir_instr_as_phi(instr));
1862 break;
1863 case nir_instr_type_jump:
1864 emit_jump(ctx, nir_instr_as_jump(instr));
1865 break;
1866 case nir_instr_type_call:
1867 case nir_instr_type_parallel_copy:
1868 compile_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
1869 break;
1870 }
1871 }
1872
1873 static struct ir3_block *
1874 get_block(struct ir3_compile *ctx, nir_block *nblock)
1875 {
1876 struct ir3_block *block;
1877 struct hash_entry *entry;
1878 entry = _mesa_hash_table_search(ctx->block_ht, nblock);
1879 if (entry)
1880 return entry->data;
1881
1882 block = ir3_block_create(ctx->ir);
1883 block->nblock = nblock;
1884 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
1885
1886 return block;
1887 }
1888
1889 static void
1890 emit_block(struct ir3_compile *ctx, nir_block *nblock)
1891 {
1892 struct ir3_block *block = get_block(ctx, nblock);
1893
1894 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
1895 if (nblock->successors[i]) {
1896 block->successors[i] =
1897 get_block(ctx, nblock->successors[i]);
1898 }
1899 }
1900
1901 ctx->block = block;
1902 list_addtail(&block->node, &ctx->ir->block_list);
1903
1904 nir_foreach_instr(nblock, instr) {
1905 emit_instr(ctx, instr);
1906 if (ctx->error)
1907 return;
1908 }
1909 }
1910
1911 static void emit_cf_list(struct ir3_compile *ctx, struct exec_list *list);
1912
1913 static void
1914 emit_if(struct ir3_compile *ctx, nir_if *nif)
1915 {
1916 struct ir3_instruction *condition = get_src(ctx, &nif->condition)[0];
1917
1918 ctx->block->condition =
1919 get_predicate(ctx, ir3_b2n(condition->block, condition));
1920
1921 emit_cf_list(ctx, &nif->then_list);
1922 emit_cf_list(ctx, &nif->else_list);
1923 }
1924
1925 static void
1926 emit_loop(struct ir3_compile *ctx, nir_loop *nloop)
1927 {
1928 emit_cf_list(ctx, &nloop->body);
1929 }
1930
1931 static void
1932 emit_cf_list(struct ir3_compile *ctx, struct exec_list *list)
1933 {
1934 foreach_list_typed(nir_cf_node, node, node, list) {
1935 switch (node->type) {
1936 case nir_cf_node_block:
1937 emit_block(ctx, nir_cf_node_as_block(node));
1938 break;
1939 case nir_cf_node_if:
1940 emit_if(ctx, nir_cf_node_as_if(node));
1941 break;
1942 case nir_cf_node_loop:
1943 emit_loop(ctx, nir_cf_node_as_loop(node));
1944 break;
1945 case nir_cf_node_function:
1946 compile_error(ctx, "TODO\n");
1947 break;
1948 }
1949 }
1950 }
1951
1952 static void
1953 emit_function(struct ir3_compile *ctx, nir_function_impl *impl)
1954 {
1955 emit_cf_list(ctx, &impl->body);
1956 emit_block(ctx, impl->end_block);
1957
1958 /* at this point, we should have a single empty block,
1959 * into which we emit the 'end' instruction.
1960 */
1961 compile_assert(ctx, list_empty(&ctx->block->instr_list));
1962 ir3_END(ctx->block);
1963 }
1964
1965 static void
1966 setup_input(struct ir3_compile *ctx, nir_variable *in)
1967 {
1968 struct ir3_shader_variant *so = ctx->so;
1969 unsigned array_len = MAX2(glsl_get_length(in->type), 1);
1970 unsigned ncomp = glsl_get_components(in->type);
1971 /* XXX: map loc slots to semantics */
1972 unsigned semantic_name = in->data.location;
1973 unsigned semantic_index = in->data.index;
1974 unsigned n = in->data.driver_location;
1975
1976 DBG("; in: %u:%u, len=%ux%u, loc=%u\n",
1977 semantic_name, semantic_index, array_len,
1978 ncomp, n);
1979
1980 so->inputs[n].semantic =
1981 ir3_semantic_name(semantic_name, semantic_index);
1982 so->inputs[n].compmask = (1 << ncomp) - 1;
1983 so->inputs[n].inloc = ctx->next_inloc;
1984 so->inputs[n].interpolate = 0;
1985 so->inputs_count = MAX2(so->inputs_count, n + 1);
1986
1987 /* the fdN_program_emit() code expects tgsi consts here, so map
1988 * things back to tgsi for now:
1989 */
1990 switch (in->data.interpolation) {
1991 case INTERP_QUALIFIER_FLAT:
1992 so->inputs[n].interpolate = TGSI_INTERPOLATE_CONSTANT;
1993 break;
1994 case INTERP_QUALIFIER_NOPERSPECTIVE:
1995 so->inputs[n].interpolate = TGSI_INTERPOLATE_LINEAR;
1996 break;
1997 case INTERP_QUALIFIER_SMOOTH:
1998 so->inputs[n].interpolate = TGSI_INTERPOLATE_PERSPECTIVE;
1999 break;
2000 }
2001
2002 for (int i = 0; i < ncomp; i++) {
2003 struct ir3_instruction *instr = NULL;
2004 unsigned idx = (n * 4) + i;
2005
2006 if (ctx->so->type == SHADER_FRAGMENT) {
2007 if (semantic_name == TGSI_SEMANTIC_POSITION) {
2008 so->inputs[n].bary = false;
2009 so->frag_coord = true;
2010 instr = create_frag_coord(ctx, i);
2011 } else if (semantic_name == TGSI_SEMANTIC_FACE) {
2012 so->inputs[n].bary = false;
2013 so->frag_face = true;
2014 instr = create_frag_face(ctx, i);
2015 } else {
2016 bool use_ldlv = false;
2017
2018 /* with NIR, we need to infer TGSI_INTERPOLATE_COLOR
2019 * from the semantic name:
2020 */
2021 if ((in->data.interpolation == INTERP_QUALIFIER_NONE) &&
2022 ((semantic_name == TGSI_SEMANTIC_COLOR) ||
2023 (semantic_name == TGSI_SEMANTIC_BCOLOR)))
2024 so->inputs[n].interpolate = TGSI_INTERPOLATE_COLOR;
2025
2026 if (ctx->flat_bypass) {
2027 /* with NIR, we need to infer TGSI_INTERPOLATE_COLOR
2028 * from the semantic name:
2029 */
2030 switch (so->inputs[n].interpolate) {
2031 case TGSI_INTERPOLATE_COLOR:
2032 if (!ctx->so->key.rasterflat)
2033 break;
2034 /* fallthrough */
2035 case TGSI_INTERPOLATE_CONSTANT:
2036 use_ldlv = true;
2037 break;
2038 }
2039 }
2040
2041 so->inputs[n].bary = true;
2042
2043 instr = create_frag_input(ctx,
2044 so->inputs[n].inloc + i - 8, use_ldlv);
2045 }
2046 } else {
2047 instr = create_input(ctx->block, NULL, idx);
2048 }
2049
2050 ctx->ir->inputs[idx] = instr;
2051 }
2052
2053 if (so->inputs[n].bary || (ctx->so->type == SHADER_VERTEX)) {
2054 ctx->next_inloc += ncomp;
2055 so->total_in += ncomp;
2056 }
2057 }
2058
2059 static void
2060 setup_output(struct ir3_compile *ctx, nir_variable *out)
2061 {
2062 struct ir3_shader_variant *so = ctx->so;
2063 unsigned array_len = MAX2(glsl_get_length(out->type), 1);
2064 unsigned ncomp = glsl_get_components(out->type);
2065 /* XXX: map loc slots to semantics */
2066 unsigned semantic_name = out->data.location;
2067 unsigned semantic_index = out->data.index;
2068 unsigned n = out->data.driver_location;
2069 unsigned comp = 0;
2070
2071 DBG("; out: %u:%u, len=%ux%u, loc=%u\n",
2072 semantic_name, semantic_index, array_len,
2073 ncomp, n);
2074
2075 if (ctx->so->type == SHADER_VERTEX) {
2076 switch (semantic_name) {
2077 case TGSI_SEMANTIC_POSITION:
2078 so->writes_pos = true;
2079 break;
2080 case TGSI_SEMANTIC_PSIZE:
2081 so->writes_psize = true;
2082 break;
2083 case TGSI_SEMANTIC_COLOR:
2084 case TGSI_SEMANTIC_BCOLOR:
2085 case TGSI_SEMANTIC_GENERIC:
2086 case TGSI_SEMANTIC_FOG:
2087 case TGSI_SEMANTIC_TEXCOORD:
2088 break;
2089 default:
2090 compile_error(ctx, "unknown VS semantic name: %s\n",
2091 tgsi_semantic_names[semantic_name]);
2092 }
2093 } else {
2094 switch (semantic_name) {
2095 case TGSI_SEMANTIC_POSITION:
2096 comp = 2; /* tgsi will write to .z component */
2097 so->writes_pos = true;
2098 break;
2099 case TGSI_SEMANTIC_COLOR:
2100 break;
2101 default:
2102 compile_error(ctx, "unknown FS semantic name: %s\n",
2103 tgsi_semantic_names[semantic_name]);
2104 }
2105 }
2106
2107 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
2108
2109 so->outputs[n].semantic =
2110 ir3_semantic_name(semantic_name, semantic_index);
2111 so->outputs[n].regid = regid(n, comp);
2112 so->outputs_count = MAX2(so->outputs_count, n + 1);
2113
2114 for (int i = 0; i < ncomp; i++) {
2115 unsigned idx = (n * 4) + i;
2116
2117 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2118 }
2119 }
2120
2121 static void
2122 emit_instructions(struct ir3_compile *ctx)
2123 {
2124 unsigned ninputs, noutputs;
2125 nir_function_impl *fxn = NULL;
2126
2127 /* Find the main function: */
2128 nir_foreach_overload(ctx->s, overload) {
2129 compile_assert(ctx, strcmp(overload->function->name, "main") == 0);
2130 compile_assert(ctx, overload->impl);
2131 fxn = overload->impl;
2132 break;
2133 }
2134
2135 ninputs = exec_list_length(&ctx->s->inputs) * 4;
2136 noutputs = exec_list_length(&ctx->s->outputs) * 4;
2137
2138 /* we need to allocate big enough outputs array so that
2139 * we can stuff the kill's at the end. Likewise for vtx
2140 * shaders, we need to leave room for sysvals:
2141 */
2142 if (ctx->so->type == SHADER_FRAGMENT) {
2143 noutputs += ARRAY_SIZE(ctx->kill);
2144 } else if (ctx->so->type == SHADER_VERTEX) {
2145 ninputs += 8;
2146 }
2147
2148 ctx->ir = ir3_create(ctx->compiler, ninputs, noutputs);
2149
2150 /* Create inputs in first block: */
2151 ctx->block = get_block(ctx, fxn->start_block);
2152 ctx->in_block = ctx->block;
2153 list_addtail(&ctx->block->node, &ctx->ir->block_list);
2154
2155 if (ctx->so->type == SHADER_FRAGMENT) {
2156 ctx->ir->noutputs -= ARRAY_SIZE(ctx->kill);
2157 } else if (ctx->so->type == SHADER_VERTEX) {
2158 ctx->ir->ninputs -= 8;
2159 }
2160
2161 /* for fragment shader, we have a single input register (usually
2162 * r0.xy) which is used as the base for bary.f varying fetch instrs:
2163 */
2164 if (ctx->so->type == SHADER_FRAGMENT) {
2165 // TODO maybe a helper for fi since we need it a few places..
2166 struct ir3_instruction *instr;
2167 instr = ir3_instr_create(ctx->block, -1, OPC_META_FI);
2168 ir3_reg_create(instr, 0, 0);
2169 ir3_reg_create(instr, 0, IR3_REG_SSA); /* r0.x */
2170 ir3_reg_create(instr, 0, IR3_REG_SSA); /* r0.y */
2171 ctx->frag_pos = instr;
2172 }
2173
2174 /* Setup inputs: */
2175 foreach_list_typed(nir_variable, var, node, &ctx->s->inputs) {
2176 setup_input(ctx, var);
2177 }
2178
2179 /* Setup outputs: */
2180 foreach_list_typed(nir_variable, var, node, &ctx->s->outputs) {
2181 setup_output(ctx, var);
2182 }
2183
2184 /* Setup variables (which should only be arrays): */
2185 foreach_list_typed(nir_variable, var, node, &ctx->s->globals) {
2186 declare_var(ctx, var);
2187 }
2188
2189 /* And emit the body: */
2190 ctx->impl = fxn;
2191 emit_function(ctx, fxn);
2192
2193 list_for_each_entry (struct ir3_block, block, &ctx->ir->block_list, node) {
2194 resolve_phis(ctx, block);
2195 }
2196 }
2197
2198 /* from NIR perspective, we actually have inputs. But most of the "inputs"
2199 * for a fragment shader are just bary.f instructions. The *actual* inputs
2200 * from the hw perspective are the frag_pos and optionally frag_coord and
2201 * frag_face.
2202 */
2203 static void
2204 fixup_frag_inputs(struct ir3_compile *ctx)
2205 {
2206 struct ir3_shader_variant *so = ctx->so;
2207 struct ir3 *ir = ctx->ir;
2208 struct ir3_instruction **inputs;
2209 struct ir3_instruction *instr;
2210 int n, regid = 0;
2211
2212 ir->ninputs = 0;
2213
2214 n = 4; /* always have frag_pos */
2215 n += COND(so->frag_face, 4);
2216 n += COND(so->frag_coord, 4);
2217
2218 inputs = ir3_alloc(ctx->ir, n * (sizeof(struct ir3_instruction *)));
2219
2220 if (so->frag_face) {
2221 /* this ultimately gets assigned to hr0.x so doesn't conflict
2222 * with frag_coord/frag_pos..
2223 */
2224 inputs[ir->ninputs++] = ctx->frag_face;
2225 ctx->frag_face->regs[0]->num = 0;
2226
2227 /* remaining channels not used, but let's avoid confusing
2228 * other parts that expect inputs to come in groups of vec4
2229 */
2230 inputs[ir->ninputs++] = NULL;
2231 inputs[ir->ninputs++] = NULL;
2232 inputs[ir->ninputs++] = NULL;
2233 }
2234
2235 /* since we don't know where to set the regid for frag_coord,
2236 * we have to use r0.x for it. But we don't want to *always*
2237 * use r1.x for frag_pos as that could increase the register
2238 * footprint on simple shaders:
2239 */
2240 if (so->frag_coord) {
2241 ctx->frag_coord[0]->regs[0]->num = regid++;
2242 ctx->frag_coord[1]->regs[0]->num = regid++;
2243 ctx->frag_coord[2]->regs[0]->num = regid++;
2244 ctx->frag_coord[3]->regs[0]->num = regid++;
2245
2246 inputs[ir->ninputs++] = ctx->frag_coord[0];
2247 inputs[ir->ninputs++] = ctx->frag_coord[1];
2248 inputs[ir->ninputs++] = ctx->frag_coord[2];
2249 inputs[ir->ninputs++] = ctx->frag_coord[3];
2250 }
2251
2252 /* we always have frag_pos: */
2253 so->pos_regid = regid;
2254
2255 /* r0.x */
2256 instr = create_input(ctx->in_block, NULL, ir->ninputs);
2257 instr->regs[0]->num = regid++;
2258 inputs[ir->ninputs++] = instr;
2259 ctx->frag_pos->regs[1]->instr = instr;
2260
2261 /* r0.y */
2262 instr = create_input(ctx->in_block, NULL, ir->ninputs);
2263 instr->regs[0]->num = regid++;
2264 inputs[ir->ninputs++] = instr;
2265 ctx->frag_pos->regs[2]->instr = instr;
2266
2267 ir->inputs = inputs;
2268 }
2269
2270 int
2271 ir3_compile_shader_nir(struct ir3_compiler *compiler,
2272 struct ir3_shader_variant *so,
2273 const struct tgsi_token *tokens,
2274 struct ir3_shader_key key)
2275 {
2276 struct ir3_compile *ctx;
2277 struct ir3 *ir;
2278 struct ir3_instruction **inputs;
2279 unsigned i, j, actual_in;
2280 int ret = 0, max_bary;
2281
2282 assert(!so->ir);
2283
2284 ctx = compile_init(compiler, so, tokens);
2285 if (!ctx) {
2286 DBG("INIT failed!");
2287 ret = -1;
2288 goto out;
2289 }
2290
2291 emit_instructions(ctx);
2292
2293 if (ctx->error) {
2294 DBG("EMIT failed!");
2295 ret = -1;
2296 goto out;
2297 }
2298
2299 ir = so->ir = ctx->ir;
2300
2301 /* keep track of the inputs from TGSI perspective.. */
2302 inputs = ir->inputs;
2303
2304 /* but fixup actual inputs for frag shader: */
2305 if (so->type == SHADER_FRAGMENT)
2306 fixup_frag_inputs(ctx);
2307
2308 /* at this point, for binning pass, throw away unneeded outputs: */
2309 if (key.binning_pass) {
2310 for (i = 0, j = 0; i < so->outputs_count; i++) {
2311 unsigned name = sem2name(so->outputs[i].semantic);
2312 unsigned idx = sem2idx(so->outputs[i].semantic);
2313
2314 /* throw away everything but first position/psize */
2315 if ((idx == 0) && ((name == TGSI_SEMANTIC_POSITION) ||
2316 (name == TGSI_SEMANTIC_PSIZE))) {
2317 if (i != j) {
2318 so->outputs[j] = so->outputs[i];
2319 ir->outputs[(j*4)+0] = ir->outputs[(i*4)+0];
2320 ir->outputs[(j*4)+1] = ir->outputs[(i*4)+1];
2321 ir->outputs[(j*4)+2] = ir->outputs[(i*4)+2];
2322 ir->outputs[(j*4)+3] = ir->outputs[(i*4)+3];
2323 }
2324 j++;
2325 }
2326 }
2327 so->outputs_count = j;
2328 ir->noutputs = j * 4;
2329 }
2330
2331 /* if we want half-precision outputs, mark the output registers
2332 * as half:
2333 */
2334 if (key.half_precision) {
2335 for (i = 0; i < ir->noutputs; i++) {
2336 struct ir3_instruction *out = ir->outputs[i];
2337 if (!out)
2338 continue;
2339 out->regs[0]->flags |= IR3_REG_HALF;
2340 /* output could be a fanout (ie. texture fetch output)
2341 * in which case we need to propagate the half-reg flag
2342 * up to the definer so that RA sees it:
2343 */
2344 if (is_meta(out) && (out->opc == OPC_META_FO)) {
2345 out = out->regs[1]->instr;
2346 out->regs[0]->flags |= IR3_REG_HALF;
2347 }
2348
2349 if (out->category == 1) {
2350 out->cat1.dst_type = half_type(out->cat1.dst_type);
2351 }
2352 }
2353 }
2354
2355 /* at this point, we want the kill's in the outputs array too,
2356 * so that they get scheduled (since they have no dst).. we've
2357 * already ensured that the array is big enough in push_block():
2358 */
2359 if (so->type == SHADER_FRAGMENT) {
2360 for (i = 0; i < ctx->kill_count; i++)
2361 ir->outputs[ir->noutputs++] = ctx->kill[i];
2362 }
2363
2364 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
2365 printf("BEFORE CP:\n");
2366 ir3_print(ir);
2367 }
2368
2369 ir3_cp(ir);
2370
2371 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
2372 printf("BEFORE GROUPING:\n");
2373 ir3_print(ir);
2374 }
2375
2376 /* Group left/right neighbors, inserting mov's where needed to
2377 * solve conflicts:
2378 */
2379 ir3_group(ir);
2380
2381 ir3_depth(ir);
2382
2383 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
2384 printf("AFTER DEPTH:\n");
2385 ir3_print(ir);
2386 }
2387
2388 ret = ir3_sched(ir);
2389 if (ret) {
2390 DBG("SCHED failed!");
2391 goto out;
2392 }
2393
2394 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
2395 printf("AFTER SCHED:\n");
2396 ir3_print(ir);
2397 }
2398
2399 ret = ir3_ra(ir, so->type, so->frag_coord, so->frag_face);
2400 if (ret) {
2401 DBG("RA failed!");
2402 goto out;
2403 }
2404
2405 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
2406 printf("AFTER RA:\n");
2407 ir3_print(ir);
2408 }
2409
2410 ir3_legalize(ir, &so->has_samp, &max_bary);
2411
2412 if (fd_mesa_debug & FD_DBG_OPTMSGS) {
2413 printf("AFTER LEGALIZE:\n");
2414 ir3_print(ir);
2415 }
2416
2417 /* fixup input/outputs: */
2418 for (i = 0; i < so->outputs_count; i++) {
2419 so->outputs[i].regid = ir->outputs[i*4]->regs[0]->num;
2420 /* preserve hack for depth output.. tgsi writes depth to .z,
2421 * but what we give the hw is the scalar register:
2422 */
2423 if ((so->type == SHADER_FRAGMENT) &&
2424 (sem2name(so->outputs[i].semantic) == TGSI_SEMANTIC_POSITION))
2425 so->outputs[i].regid += 2;
2426 }
2427
2428 /* Note that some or all channels of an input may be unused: */
2429 actual_in = 0;
2430 for (i = 0; i < so->inputs_count; i++) {
2431 unsigned j, regid = ~0, compmask = 0;
2432 so->inputs[i].ncomp = 0;
2433 for (j = 0; j < 4; j++) {
2434 struct ir3_instruction *in = inputs[(i*4) + j];
2435 if (in) {
2436 compmask |= (1 << j);
2437 regid = in->regs[0]->num - j;
2438 actual_in++;
2439 so->inputs[i].ncomp++;
2440 }
2441 }
2442 so->inputs[i].regid = regid;
2443 so->inputs[i].compmask = compmask;
2444 }
2445
2446 /* fragment shader always gets full vec4's even if it doesn't
2447 * fetch all components, but vertex shader we need to update
2448 * with the actual number of components fetch, otherwise thing
2449 * will hang due to mismaptch between VFD_DECODE's and
2450 * TOTALATTRTOVS
2451 */
2452 if (so->type == SHADER_VERTEX)
2453 so->total_in = actual_in;
2454 else
2455 so->total_in = align(max_bary + 1, 4);
2456
2457 out:
2458 if (ret) {
2459 ir3_destroy(so->ir);
2460 so->ir = NULL;
2461 }
2462 compile_free(ctx);
2463
2464 return ret;
2465 }